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actlib_dataflow_neuro
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4 Commits
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M. Mastella
c8ac3cf37d
started register_v2 with reading and writing abilities
2022-03-09 13:05:08 +01:00
M. Mastella
e49866323c
register_write works
2022-03-07 16:36:01 +01:00
Michele
aa67bd6168
register simulates correctly up to the fake clock generation
2022-03-05 20:28:50 +01:00
Michele
7fe31f0ed8
started testing the register_w (doesn't compile)
2022-03-04 21:17:30 +01:00