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  • ae4e63d634 removed weird sigbuf 1output dev alexmadison 2023-12-01 13:46:21 +0100
  • bf81cfefee added note to get rid of unsued sigbuf1output alexmadison 2023-12-01 13:44:07 +0100
  • 76e0e22356 removed unused cells alexmadison 2023-12-01 13:21:46 +0100
  • 51327289a7 removed sadc handshake because why would anyone instantiate sadc hs when we have a lovely neuron handshake alexmadison 2023-12-01 12:13:06 +0100
  • b2de1a45d7 removed std and acell instantiate tests in wrong folder, and they are old, acells do not have x1 etc alexmadison 2023-12-01 12:09:44 +0100
  • a0480b0369 removed texel_singlecore: is never used, and is a simplification of dualcore alexmadison 2023-12-01 12:06:10 +0100
  • d0717fbea8 removed texel chip tests with write-only registers alexmadison 2023-12-01 12:05:30 +0100
  • 1c4206b7d4 added note alexmadison 2023-12-01 11:52:55 +0100
  • dbad8816a9 renamed decoder dly test to be include dly alexmadison 2023-12-01 11:40:11 +0100
  • 9e7b1cd120 fixed std instaitate test by just copying the async instantiate test alexmadison 2023-12-01 11:22:34 +0100
  • ca3a56572d got rid of flip flop reg tests alexmadison 2023-12-01 11:05:31 +0100
  • 627caf1aed removed texel small, super old alexmadison 2023-12-01 11:01:18 +0100
  • 7e2ae21098 removed texel slim registers, is literally same as texel glue but with less registers, test.prs targets regs that dont exist?? alexmadison 2023-12-01 10:58:38 +0100
  • 8cc3c14f83 removed unused texel_in30 instantaitions alexmadison 2023-12-01 10:55:32 +0100
  • e4fbc508af removed unused test and object alexmadison 2023-11-21 16:17:58 +0100
  • 99b1d8caaf fixed test alexmadison 2023-11-21 16:07:52 +0100
  • c336e37377 fixed unit tests alexmadison 2023-11-21 15:59:00 +0100
  • bd56ac71e1 fixed register wr array tests alexmadison 2023-11-21 15:55:15 +0100
  • e7158ca2a9 fixed unit test alexmadison 2023-11-21 15:54:35 +0100
  • 51010a6095 removed tests of non-A-cell registers alexmadison 2023-11-21 15:54:11 +0100
  • 5eb77108ab fixed test alexmadison 2023-11-21 15:41:57 +0100
  • 96042d3bea fixed test alexmadison 2023-11-21 14:49:07 +0100
  • 023da63c73 removed test because its a stupid component alexmadison 2023-11-21 14:33:12 +0100
  • aa299fb45f fixed unit tests with new handshake blocks alexmadison 2023-11-21 14:22:41 +0100
  • 9411dde4aa fixed test, changed to simple encoder alexmadison 2023-11-21 13:35:36 +0100
  • c1e26267e2 fixed test by using encoder_simple alexmadison 2023-11-21 13:28:38 +0100
  • 1aeb37f976 fixed test, bits were flipped alexmadison 2023-11-21 12:24:15 +0100
  • a130ca59ea deleted fifo3 test because it doesnt actually use the fifo object alexmadison 2023-11-21 12:17:04 +0100
  • 0a91459073 removed old decoder, only simple now, fixed 8x8 test, deleted other 2 alexmadison 2023-11-21 11:26:04 +0100
  • db39324593 fixed encoder2d tests, just changed labels, lowercase d alexmadison 2023-11-21 10:19:21 +0100
  • 73acbcbc4f fixed demux_td_sign test and unfucked the sign flipping which shoudl have broken the other version tbh alexmadison 2023-11-21 10:14:54 +0100
  • 8b37b91891 removed texel dualcore mapper, never used alexmadison 2023-11-21 09:54:18 +0100
  • 200088fb0a removed mapper test, never tested irl alexmadison 2023-11-21 09:52:18 +0100
  • e412faf459 fixed demux td 2 unit test and added note to prims alexmadison 2023-11-21 09:46:56 +0100
  • 6eb91b72e0 fixed demux bit 7 test and added note to primitives alexmadison 2023-11-21 09:35:28 +0100
  • 822cb58d2c fixed demux_7 test and added comment on demux alexmadison 2023-11-21 09:25:53 +0100
  • 1d542e8a15 added todo about line end pullups alexmadison 2023-11-17 13:18:58 +0100
  • 1c4160092d fixed decoder_2d_hybrid unit test alexmadison 2023-11-17 13:18:17 +0100
  • 25e0b4b1a2 fixing tests, started cleaning M. Mastella 2023-11-17 11:13:19 +0100
  • ff077c5169 regenned with cores having new names TexelTapeout alexmadison 2022-07-06 18:25:23 +0200
  • 1cd1b1d054 wiping split modules alexmadison 2022-07-06 18:24:32 +0200
  • 72dab29f5c regennmed tdc no read to have the same number of reg bits as normal tdcg alexmadison 2022-07-06 17:43:21 +0200
  • 502d35b000 added slice before registers, so register sizes can be reduced alexmadison 2022-07-06 17:26:26 +0200
  • 27a0d34153 genned texel dualcore glue noread netlist clean alexmadison 2022-07-06 16:04:34 +0200
  • b21b84e78d added some watches alexmadison 2022-07-06 15:46:41 +0200
  • 194a7ad196 created version of tdc_g without register read functionality alexmadison 2022-07-06 15:35:20 +0200
  • 2ddbeac978 generated a tdc_glue with only 8 registers alexmadison 2022-07-06 14:06:19 +0200
  • 7896e0de24 added tests for dynapse sadc hs alexmadison 2022-07-05 10:53:17 +0200
  • 8753540b33 removed inverted inputs from sadc encoder, regenned with proper reset sigs I hope alexmadison 2022-07-01 17:26:55 +0200
  • a70c9a1b6d removed extra supply vss lines from tiehi/lows alexmadison 2022-06-29 18:25:44 +0200
  • 9a7a34c02f please god let this be the last regen of the act. Tiehi/lo's have been given fake PRs alexmadison 2022-06-29 16:24:00 +0200
  • 8e38a0fb01 put fake PRs in tiehi/los lol alexmadison 2022-06-29 15:58:58 +0200
  • f488e5dc81 renamed to sadc_encoder alexmadison 2022-06-29 13:36:14 +0200
  • 836e19a72d added sadc encoder with inputs low active for dynapse sadcs alexmadison 2022-06-29 13:18:42 +0200
  • ba7ae68651 lmao forgot to remove top.vdd/vss alexmadison 2022-06-28 18:20:57 +0200
  • cd978118b5 dindo nuffin alexmadison 2022-06-28 18:04:40 +0200
  • 1a7c6121a0 don't think i regenned netlist.v but just to be safe lol alexmadison 2022-06-28 14:46:43 +0200
  • df3bb4022c regenned netlist with sigbufs fixed lol alexmadison 2022-06-27 15:57:02 +0200
  • 14ba815112 fixed treegate buff issue lol alexmadison 2022-06-27 11:56:12 +0200
  • 79c3d9ed98 tdc glue small for testing alexmadison 2022-06-23 17:54:10 +0200
  • 905adaad48 added a buffer to the reset pd on req lines alexmadison 2022-06-23 17:53:07 +0200
  • 6b0eff672c removed split modules folder from git alexmadison 2022-06-23 17:51:50 +0200
  • 4e01e252b8 final final generation of tdc_glue i swear alexmadison 2022-06-23 17:51:16 +0200
  • 144d89fb90 moved _y_a_B away from the out req lines to avoid more parasitic capacitance in neuron hs alexmadison 2022-06-22 20:34:59 +0200
  • 4d4183f714 altered pull downs and ups in the encoder and neuron handshake to minimise parasitic capacitances when ack switches alexmadison 2022-06-22 19:22:27 +0200
  • 6c1e079fd4 did some sram shit, doesnt matter alexmadison 2022-06-22 19:16:04 +0200
  • 6daea1ef02 updated dummy neurons to have Buf X12 to avoid slow in acks alexmadison 2022-06-22 19:14:39 +0200
  • c972419199 regenned with delays in encoder alexmadison 2022-06-21 14:00:04 +0200
  • dde782d7c0 updated 2d encoder simple to include delays after the arbiter alexmadison 2022-06-21 13:39:34 +0200
  • 7ca41040a3 beta idea to have slow falling edge delays on ack from arbiter. bad idea, gonna revert lol alexmadison 2022-06-21 12:06:15 +0200
  • 17d9d3da41 regenned without pulldown delays alexmadison 2022-06-20 16:10:35 +0200
  • 8953fdafe6 removed PRs from keeps, again... alexmadison 2022-06-20 15:43:56 +0200
  • 6a7da77a92 removed line pulldown delays oops alexmadison 2022-06-20 15:43:22 +0200
  • ce4e6dc23c regenned modules with synapses and neurons removed from top level alexmadison 2022-06-17 12:29:45 +0200
  • 21d6982763 removed synapses and neurons from top level outputs: alexmadison 2022-06-17 12:10:25 +0200
  • c790e73e69 regenned without name change stuff alexmadison 2022-06-17 11:56:01 +0200
  • bfffdb7e97 deleted heretical files alexmadison 2022-06-16 18:45:35 +0200
  • 2cd1a4b91a genned alexmadison 2022-06-16 18:06:06 +0200
  • 3d0e36fbfb genned verilog netlist alexmadison 2022-06-16 17:48:13 +0200
  • 0cdc01c279 regenned texel dualcore glue with new registers and neuron req keep fix alexmadison 2022-06-16 17:40:33 +0200
  • 75f79705c6 fixed bug in neuron handshake array where keeps were connected to post-buffered reqs rather than pre-buffered reqs... alexmadison 2022-06-16 16:56:38 +0200
  • 97dacbfd08 commented out old registers alexmadison 2022-06-15 18:08:33 +0200
  • 87577268e5 added improved registers alexmadison 2022-06-15 17:58:34 +0200
  • 2ea83f3472 test merge of sram rw output working alexmadison 2022-05-10 15:34:04 +0200
  • 016f634ac6 test of spike from sram workin alexmadison 2022-05-10 15:22:19 +0200
  • 9ee41dc390 spikes out to sram working alexmadison 2022-05-10 14:53:26 +0200
  • 7735cf8cba made note of demux td to fixgit add ../dataflow_neuro/primitives.act alexmadison 2022-05-10 14:53:00 +0200
  • 4c208bc18a packets to sram rw working alexmadison 2022-05-10 14:07:51 +0200
  • 9ceaa10eeb minor change in demux_td alexmadison 2022-05-09 19:29:37 +0200
  • af2c6c665d adding mapper io to chip wip alexmadison 2022-05-09 19:29:18 +0200
  • 03851e19b7 mapper test init alexmadison 2022-05-09 18:04:49 +0200
  • 1586adc0e1 started adding mapper alexmadison 2022-05-09 18:04:17 +0200
  • f3a9f2f44c minor changes alexmadison 2022-05-09 16:50:26 +0200
  • 0d7b82a0dd altered amzo targettting tests to avoid instabilities alexmadison 2022-05-09 16:48:58 +0200
  • b1e24fa93c added more monitoring tests alexmadison 2022-05-08 19:05:52 +0200
  • b994b60690 inverted TBUFs alexmadison 2022-05-08 17:03:38 +0200
  • 6ed0c4bfed beefed up prsim to include AMZIOs alexmadison 2022-05-08 17:03:02 +0200
  • 04a7a108d5 added reset signals in and out alexmadison 2022-05-06 14:17:15 +0200
  • f4c6ce3112 minor indentation fix alexmadison 2022-05-05 15:02:56 +0200
  • 71a2192427 texel dualcore with glue passed tests alexmadison 2022-05-05 14:57:38 +0200