commented out old registers
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alexmadison
parent
87577268e5
commit
97dacbfd08
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@ -48,65 +48,65 @@ namespace tmpl {
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* Also, in.a does not wait for out.v to go low to go to low.
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* Means have a buffer that completes its Right handshake as soon as out data is valid.
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*/
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export template<pint N>
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defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
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reset_B; power supply) {
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// export template<pint N>
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// defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
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// reset_B; power supply) {
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//control
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bool _en, _reset_BX[N];
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bool _in_aB;
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// //control
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// bool _en, _reset_BX[N];
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// bool _in_aB;
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bool _reset;
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bool _resetX[N];
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// bool _reset;
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// bool _resetX[N];
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// Reset sigs
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INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
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sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
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// // Reset sigs
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// INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
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// sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
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// sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
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A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
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.pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
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// A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
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// .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
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INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
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// INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
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// Flush sigs
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bool _flushB, _flushBX[N*2];
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INV_X1 flush_inv(.a = flush, .y = _flushB);
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sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
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_en = _in_aB;
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// // Flush sigs
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// bool _flushB, _flushBX[N*2];
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// INV_X1 flush_inv(.a = flush, .y = _flushB);
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// sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
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// _en = _in_aB;
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//validity
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bool _in_v;
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vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
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BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
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// //validity
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// bool _in_v;
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// vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
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// BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
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//function
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bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
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A_1C2N_SB_X4 f_buf_func[N];
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A_1C2N_RB_X4 t_buf_func[N];
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sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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(i:N:
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f_buf_func[i].y=out.d[i].f;
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t_buf_func[i].y=out.d[i].t;
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// //function
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// bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
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// A_1C2N_SB_X4 f_buf_func[N];
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// A_1C2N_RB_X4 t_buf_func[N];
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// sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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// (i:N:
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// f_buf_func[i].y=out.d[i].f;
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// t_buf_func[i].y=out.d[i].t;
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f_buf_func[i].c1=_flushBX[i];
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t_buf_func[i].c1=_flushBX[i+N];
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// f_buf_func[i].c1=_flushBX[i];
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// t_buf_func[i].c1=_flushBX[i+N];
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f_buf_func[i].n2=en_buf.out[i];
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t_buf_func[i].n2=en_buf.out[i+N];
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f_buf_func[i].n1=in.d.d[i].f;
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t_buf_func[i].n1=in.d.d[i].t;
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f_buf_func[i].vdd=supply.vdd;
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t_buf_func[i].vdd=supply.vdd;
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f_buf_func[i].vss=supply.vss;
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t_buf_func[i].vss=supply.vss;
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f_buf_func[i].pr = _resetX[i];
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f_buf_func[i].sr = _resetX[i];
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t_buf_func[i].pr_B = _reset_BX[i];
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t_buf_func[i].sr_B = _reset_BX[i];
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)
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}
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// f_buf_func[i].n2=en_buf.out[i];
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// t_buf_func[i].n2=en_buf.out[i+N];
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// f_buf_func[i].n1=in.d.d[i].f;
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// t_buf_func[i].n1=in.d.d[i].t;
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// f_buf_func[i].vdd=supply.vdd;
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// t_buf_func[i].vdd=supply.vdd;
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// f_buf_func[i].vss=supply.vss;
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// t_buf_func[i].vss=supply.vss;
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// f_buf_func[i].pr = _resetX[i];
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// f_buf_func[i].sr = _resetX[i];
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// t_buf_func[i].pr_B = _reset_BX[i];
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// t_buf_func[i].sr_B = _reset_BX[i];
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// )
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// }
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/**
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@ -114,63 +114,63 @@ sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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* MSB is whether to read or write.
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* Currently only handles writing.
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*/
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export template<pint N>
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defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
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bool? reset_B; power supply) {
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// export template<pint N>
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// defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
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// bool? reset_B; power supply) {
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bool _en2;
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bool _w;
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bool _out_v, _out_vB;
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bool _flush, _flushB;
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// bool _en2;
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// bool _w;
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// bool _out_v, _out_vB;
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// bool _flush, _flushB;
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_w = in.d.d[N].t;
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// _w = in.d.d[N].t;
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// Buffer
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buffer_register<N> buf(.out = out, .out_v = _out_v, .flush = _flush,
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.supply = supply, .reset_B = reset_B);
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buf.in.v = in.v;
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// // Buffer
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// buffer_register<N> buf(.out = out, .out_v = _out_v, .flush = _flush,
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// .supply = supply, .reset_B = reset_B);
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// buf.in.v = in.v;
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// In ack stuff
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INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
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// To stop in ack going low before en2 has been reset.
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A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a,
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.vdd = supply.vdd, .vss = supply.vss);
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// // In ack stuff
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// INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
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// // To stop in ack going low before en2 has been reset.
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// A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a,
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// .vdd = supply.vdd, .vss = supply.vss);
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// Out valid tree
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vtree<N> out_valid(.in = buf.out, .out = _out_v, .supply = supply);
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INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss);
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// // Out valid tree
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// vtree<N> out_valid(.in = buf.out, .out = _out_v, .supply = supply);
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// INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss);
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// Control
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A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush,
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.vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B);
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INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss);
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// // Control
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// A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush,
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// .vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B);
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// INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss);
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A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
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.pr_B = reset_B, .sr_B = reset_B);
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// A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
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// .pr_B = reset_B, .sr_B = reset_B);
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// Pass to let data into the buffer
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NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
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sigbuf<N*2> passX(.in = pass.y, .supply = supply);
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AND2_X1 gandalf_t[N];
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AND2_X1 gandalf_f[N];
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(i:0..N-1:
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gandalf_t[i].a = in.d.d[i].t;
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gandalf_f[i].a = in.d.d[i].f;
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gandalf_t[i].b = passX.out[i];
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gandalf_f[i].b = passX.out[i+N];
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gandalf_t[i].y = buf.in.d.d[i].t;
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gandalf_f[i].y = buf.in.d.d[i].f;
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// // Pass to let data into the buffer
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// NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
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// sigbuf<N*2> passX(.in = pass.y, .supply = supply);
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// AND2_X1 gandalf_t[N];
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// AND2_X1 gandalf_f[N];
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// (i:0..N-1:
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// gandalf_t[i].a = in.d.d[i].t;
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// gandalf_f[i].a = in.d.d[i].f;
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// gandalf_t[i].b = passX.out[i];
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// gandalf_f[i].b = passX.out[i+N];
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// gandalf_t[i].y = buf.in.d.d[i].t;
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// gandalf_f[i].y = buf.in.d.d[i].f;
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gandalf_t[i].vdd = supply.vdd;
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gandalf_f[i].vdd = supply.vdd;
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gandalf_t[i].vss = supply.vss;
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gandalf_f[i].vss = supply.vss;
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// gandalf_t[i].vdd = supply.vdd;
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// gandalf_f[i].vdd = supply.vdd;
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// gandalf_t[i].vss = supply.vss;
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// gandalf_f[i].vss = supply.vss;
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)
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// )
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}
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// }
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/**
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* A single register made out of A cells.
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