regenned with cores having new names

wiping split modules
regennmed tdc no read to have the same number of reg bits as normal tdcg
2022-07-06 18:25:23 +02:00 · 2022-07-06 18:24:32 +02:00 · 2022-07-06 17:43:21 +02:00 · 2022-07-06 17:26:26 +02:00 · 2022-07-06 16:04:34 +02:00 · 2022-07-06 15:46:41 +02:00
825 changed files with 1301214 additions and 174690 deletions
--- a/dataflow_neuro/cell_lib_std.act
+++ b/dataflow_neuro/cell_lib_std.act
@@ -27,14 +27,29 @@
 namespace tmpl {
  namespace dataflow_neuro {

+
+    // We have to add a pretend buffer in here
+    // to ensure that act2v doesn't simplify things
+    // and just connect y to vss/vdd lol
    export defproc TIELO_X1(bool! y; bool vdd, vss)
    {
-      y = vss;
+      bool _y, a;
+      a = vss;
+      prs {
+        a => _y-
+        _y => y-
+      }
+
    }

    export defproc TIEHI_X1(bool! y; bool vdd, vss)
    {
-      y = vdd;
+      bool _y, a;
+      a = vdd;
+      prs {
+        a => _y-
+        _y => y-
+      }      
    }

    /*-- inverters --*/
--- a/dataflow_neuro/chips_noread.act
+++ b/dataflow_neuro/chips_noread.act
@@ -0,0 +1,467 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_core (avMx1of2<N_IN> in, out;
+    Mx1of2<REG_NCW> reg_data[REG_M];
+
+    // Dummy synapses and neurons in the handshake blocks
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
+    reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+    // Onwards
+    fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Register
+    slice_data<N_IN-1, 0,REG_NCW+REG_NCA> slice_pre_reg(.in = _demux.out2, .supply = supply);
+    fifo<REG_NCW+REG_NCA,N_BUFFERS> fifo_dmx2reg(.in = slice_pre_reg.out, .reset_B = _reset_BX, .supply = supply);
+    register_w_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
+        .supply = supply, .reset_B = reset_reg_B);
+
+
+    // Spike Decoder
+    pint NC_SYN;
+    NC_SYN = NC_SYN_X + NC_SYN_Y;
+    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
+    fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
+    decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
+        .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
+        .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
+        .supply = supply, .reset_B = _reset_BX);
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    )
+
+    // Synapse handshake circuits, to be removed for innovus
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    //     .synapses = synapses,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
+    //     .to_pu = syn_pu,
+    //     .out_ackB_decoder = dec_ackB,
+    //     .supply = supply);
+
+    // Neurons + encoder
+    pint NC_NRN;
+    NC_NRN = NC_NRN_X + NC_NRN_Y;
+    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
+    fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Neuron handshake circuits, to be removed for innovus
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    //     .outx = enc_inx, .outy = enc_iny,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
+    //     .supply = supply, .reset_B = _reset_BX);
+
+
+
+    // Merge
+    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
+
+    // Output
+    fifo<N_IN, N_BUFFERS> fifo_out(.in = append_enc.out, .out = out,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // Neuron/synapse monitor targeters
+    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
+    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
+    pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
+    pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
+
+    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
+    nrn_mon_dec_x.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_X:
+        nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
+    )
+    sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
+    nrn_mon_dec_y.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_Y:
+        nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
+    )
+    sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
+        .supply = supply);
+    syn_mon_dec_x.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_X:
+        syn_mon_dec_x.in.d[i] = register.data[3].d[i];
+    )
+    sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
+    syn_mon_dec_y.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_Y:
+        syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
+    )
+    sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
+
+    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
+    // Stops the possibility of dev_mon being high while some other sig is high.
+    // Otherwise boom.
+    // Also the 4th monitor line to each synapse is active LOW, needs inverter.
+    bool DEV_DEBUG;
+    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
+    sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+        .supply = supply);
+    DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    INV_X1 syn_targ_set_high_inv[NSMX4];
+    [NSMX4 >= 1 ->
+        AND2_X1 ands_devmon[NSMX4];
+        (i:NSMX4:
+            ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
+            ands_devmon[i].b = DEV_DEBUG;
+            ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
+            ands_devmon[i].vdd = supply.vdd;
+            ands_devmon[i].vss = supply.vss;
+
+            syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
+            syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
+            syn_targ_set_high_inv[i].vdd = supply.vdd;
+            syn_targ_set_high_inv[i].vss = supply.vss;
+
+        )
+        // Wire up the remaining lines.
+        (i:N_SYN_MON_X:
+            [(~(i%4 = 1)) & (~(i%4=3))->
+                syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
+            ]
+        )
+    ]
+
+    // Create TBUFs for each synapse column,
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
+    KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
+    sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
+    (j:N_MON_AMZO_PER_SYN:
+        (i:N_SYN_X:
+            index = i*N_MON_AMZO_PER_SYN + j;
+            syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
+            syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
+            syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
+        )
+
+        syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
+        syn_AMZO_keeps[j].vdd = supply.vdd;
+        syn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+
+    // Create TBUFs for each neuron column, and add keeps.
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
+    KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
+    sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply); 
+    (j:N_MON_AMZO_PER_NRN:
+        (i:N_NRN_X:
+            index = i*N_MON_AMZO_PER_NRN + j;
+            nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
+            nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
+            nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
+        )
+
+        nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
+        nrn_AMZO_keeps[j].vdd = supply.vdd;
+        nrn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+    // Create buffered signals from register to nrns.
+    sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
+    (i:N_FLAGS_PER_NRN:
+        sb_nrn_EFO.in[i] = register.data[5].d[i].t;
+    )
+
+    // Create  buffered signals from register to synapses.
+    // Includes safety on the first 3 flags with dev mon.
+    sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
+    (i:3..N_FLAGS_PER_SYN-1:
+        sb_syn_EFO.in[i] = register.data[4].d[i].t;
+    )  
+    AND2_X1 syn_flags_dev_safety[3];
+    (i:0..2:
+        syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
+        syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
+
+        syn_flags_dev_safety[i].vdd = supply.vdd;
+        syn_flags_dev_safety[i].vss = supply.vss;
+    )
+
+    // Create non-buffered reset signals for the neuron/syn handshakes
+    // Since sigs are buffered before each neuron.
+    sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
+    sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
+    sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
+    INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
+    sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
+
+}
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+   
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+    // Merge cores and loopback
+    merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+}
+}
+
--- a/dataflow_neuro/coders.act
+++ b/dataflow_neuro/coders.act
@@ -1080,6 +1080,31 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
 				.reset_B = _reset_BX, .supply = supply);
 		}

+		/**
+	   * Same as encoder1d_bd above but with inverters on in.a/r bc sadc neuron handshake
+	   * signals are backwards lol.
+	   */
+		export template<pint Nc, N, N_BUFFERS, N_BD_DLY_CFG>
+		defproc encoder1d_bd_sadc(a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG], reset_B; power supply) {
+			
+
+			encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.out = out, .dly_cfg = dly_cfg,
+				.reset_B = reset_B, .supply = supply);
+
+			INV_X1 req_invs[N];
+			INV_X1 ack_invs[N];
+			(i:N:
+				req_invs[i](.a = in[i].r, .y = c.in[i].r, .vdd = supply.vdd, .vss = supply.vss);
+				ack_invs[i](.a = c.in[i].a, .y = in[i].a, .vdd = supply.vdd, .vss = supply.vss);
+
+			)
+			
+
+		}
+
+
+
+

 		/**
 	   * Neuron handshaking.
--- a/dataflow_neuro/dynapse.act
+++ b/dataflow_neuro/dynapse.act
@@ -0,0 +1,66 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export
+defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
+	bool _en;
+	bool _out_a_B;
+
+	INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
+
+	A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_1C1P_X1 A_en(.c1 = in.a, .p1 =  out.r, .y = _en,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+}
+
+}
+}
+
--- a/dataflow_neuro/primitives.act
+++ b/dataflow_neuro/primitives.act
@@ -841,17 +841,22 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
    _N1 = std::min(N1,N);
    _N0 = std::max(N0,0);

+    [_N0 = 0 & _N1 = N ->
+      in = out;
+    [] _N0 != 0 | _N1 != N ->

-    // BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
+      vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
+      (i:_N1-_N0:
+          in.d.d[i + _N0] = out.d.d[i];
+      )

-    vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
-    (i:_N1-_N0:
-        in.d.d[i + _N0] = out.d.d[i];
-    )
+      // in.a = out.a;
+
+      A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
+
+    ]

-    // in.a = out.a;

-    A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);

 }

--- a/dataflow_neuro/registers.act
+++ b/dataflow_neuro/registers.act
@@ -41,137 +41,6 @@ namespace tmpl {
    namespace dataflow_neuro {


-/**
- * Buffer for use in an A-cell register.
- * Basically the same as a normal buffer, except that when out.v goes high,
- * in.a goes high too.
- * Also, in.a does not wait for out.v to go low to go to low.
- * Means have a buffer that completes its Right handshake as soon as out data is valid.
- */
-// export template<pint N>
-// defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
-//     reset_B; power supply) {
-
-
-// //control
-// bool _en, _reset_BX[N];
-// bool _in_aB;
-
-// bool _reset;
-// bool _resetX[N];
-
-// // Reset sigs
-// INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
-// sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
-// sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
-
-// A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
-//     .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
-
-// INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
-
-// // Flush sigs 
-// bool _flushB, _flushBX[N*2];
-// INV_X1 flush_inv(.a = flush, .y = _flushB);
-// sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
-// _en = _in_aB;
-
-// //validity
-// bool _in_v;
-// vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
-// BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
-
-// //function
-// bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
-// A_1C2N_SB_X4 f_buf_func[N];
-// A_1C2N_RB_X4 t_buf_func[N];
-// sigbuf<N*2> en_buf(.in=_en, .supply=supply);
-// (i:N: 
-//     f_buf_func[i].y=out.d[i].f;
-//     t_buf_func[i].y=out.d[i].t;
-
-//     f_buf_func[i].c1=_flushBX[i];
-//     t_buf_func[i].c1=_flushBX[i+N];
-
-//     f_buf_func[i].n2=en_buf.out[i];
-//     t_buf_func[i].n2=en_buf.out[i+N];
-//     f_buf_func[i].n1=in.d.d[i].f;
-//     t_buf_func[i].n1=in.d.d[i].t;
-//     f_buf_func[i].vdd=supply.vdd;
-//     t_buf_func[i].vdd=supply.vdd;
-//     f_buf_func[i].vss=supply.vss;
-//     t_buf_func[i].vss=supply.vss;
-//     f_buf_func[i].pr = _resetX[i];
-//     f_buf_func[i].sr = _resetX[i];
-//     t_buf_func[i].pr_B = _reset_BX[i];
-//     t_buf_func[i].sr_B = _reset_BX[i];
-// )
-// }
-
-
-/**
- * A single register made out of A cells.
- * MSB is whether to read or write.
- * Currently only handles writing.
- */
-// export template<pint N>
-// defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
-//     bool? reset_B; power supply) {
-
-
-// bool _en2;
-// bool _w; 
-// bool _out_v, _out_vB;
-// bool _flush, _flushB;
-
-// _w = in.d.d[N].t;
-
-// // Buffer
-// buffer_register<N> buf(.out = out, .out_v = _out_v, .flush = _flush,
-//     .supply = supply, .reset_B = reset_B);
-// buf.in.v = in.v;
-
-// // In ack stuff
-// INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
-// // To stop in ack going low before en2 has been reset.
-// A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a,
-//     .vdd = supply.vdd, .vss = supply.vss);
-
-// // Out valid tree
-// vtree<N> out_valid(.in = buf.out, .out = _out_v, .supply = supply);
-// INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss);
-
-// // Control
-// A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush,
-//     .vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B);
-// INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss);
-
-// A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
-//     .pr_B = reset_B, .sr_B = reset_B);
-
-// // Pass to let data into the buffer
-// NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
-// sigbuf<N*2> passX(.in = pass.y, .supply = supply);
-// AND2_X1 gandalf_t[N];
-// AND2_X1 gandalf_f[N];
-// (i:0..N-1:
-//     gandalf_t[i].a = in.d.d[i].t;
-//     gandalf_f[i].a = in.d.d[i].f;
-//     gandalf_t[i].b = passX.out[i]; 
-//     gandalf_f[i].b = passX.out[i+N];
-//     gandalf_t[i].y = buf.in.d.d[i].t;
-//     gandalf_f[i].y = buf.in.d.d[i].f; 
-
-//     gandalf_t[i].vdd = supply.vdd;
-//     gandalf_f[i].vdd = supply.vdd;
-//     gandalf_t[i].vss = supply.vss;
-//     gandalf_f[i].vss = supply.vss;
-
-
-// )
-
-// }
-
 /**
 * A single register made out of A cells.
 * MSB is whether to read or write.
@@ -407,5 +276,75 @@ A_2C_B_X1 addr_read_f[NcA];



+
+
+/** 
+ * Array of registers made out of A-cells.
+ * !!!Registers ONLY have write functionality!!!
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * LSB [-addr-][-word-] MSB
+ */
+export template<pint NcA, NcW, M>
+defproc register_w_array(avMx1of2<NcA + NcW> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
+    bool? reset_B; power supply) {
+
+
+// Input valid tree
+vtree<NcA + NcW> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+bool _write_ack;
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+A_2C_B_X1 ack_safety(.c1 = _write_ack, .c2 = in.v, .y = in.a);
+
+
+// Registers
+register_acells_improved<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
+    )
+
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcW].t = decoder.out[i];
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
+
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
+
+    // Connect outputs
+    data[i] = registers[i].out;
+
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+
+}
+
+
+
+
 }}

--- a/test/unit_tests/sadc_encoder/netlist.v
+++ b/test/unit_tests/sadc_encoder/netlist.v
--- a/test/unit_tests/sadc_encoder/netlist_clean.v
+++ b/test/unit_tests/sadc_encoder/netlist_clean.v
--- a/test/unit_tests/sadc_encoder/split_modules/sadc__encoder/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/sadc__encoder/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/sadc__encoder/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/sadc__encoder/netlist/verilog.v
@@ -0,0 +1,129 @@
+module sadc__encoder(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iin15_d_d0 , Iin15_a , Iin16_d_d0 , Iin16_a , Iin17_d_d0 , Iin17_a , Iin18_d_d0 , Iin18_a , Iin19_d_d0 , Iin19_a , Iin20_d_d0 , Iin20_a , Iin21_d_d0 , Iin21_a , Iin22_d_d0 , Iin22_a , Iin23_d_d0 , Iin23_a , Iout_d0 , Iout_d1 , Iout_d2 , Iout_d3 , Iout_d4 , Iout_r , Iout_a , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0_d_d0 ;
+   
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   input Iin3_d_d0 ;
+   
+   input Iin4_d_d0 ;
+   
+   input Iin5_d_d0 ;
+   
+   input Iin6_d_d0 ;
+   
+   input Iin7_d_d0 ;
+   
+   input Iin8_d_d0 ;
+   
+   input Iin9_d_d0 ;
+   
+   input Iin10_d_d0 ;
+   
+   input Iin11_d_d0 ;
+   
+   input Iin12_d_d0 ;
+   
+   input Iin13_d_d0 ;
+   
+   input Iin14_d_d0 ;
+   
+   input Iin15_d_d0 ;
+   
+   input Iin16_d_d0 ;
+   
+   input Iin17_d_d0 ;
+   
+   input Iin18_d_d0 ;
+   
+   input Iin19_d_d0 ;
+   
+   input Iin20_d_d0 ;
+   
+   input Iin21_d_d0 ;
+   
+   input Iin22_d_d0 ;
+   
+   input Iin23_d_d0 ;
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Idly_cfg0 ;
+   input Idly_cfg1 ;
+   input Idly_cfg2 ;
+   input Idly_cfg3 ;
+   input reset_B;
+
+// -- signals ---
+   wire Iin14_d_d0 ;
+   wire Iout_a ;
+   output Iout_d0 ;
+   wire Iin6_d_d0 ;
+   output Iout_d4 ;
+   output Iin19_a ;
+   output Iin17_a ;
+   output Iin13_a ;
+   output Iin21_a ;
+   wire Iin20_d_d0 ;
+   wire Iin15_d_d0 ;
+   wire Iin4_d_d0 ;
+   wire Iin21_d_d0 ;
+   wire Iin16_d_d0 ;
+   wire Idly_cfg2 ;
+   wire Iin13_d_d0 ;
+   output Iin9_a ;
+   wire Iin5_d_d0 ;
+   wire Iin3_d_d0 ;
+   output Iin10_a ;
+   output Iin2_a ;
+   output Iout_r ;
+   output Iin20_a ;
+   output Iin3_a ;
+   output Iin8_a ;
+   wire Iin23_d_d0 ;
+   wire Iin18_d_d0 ;
+   output Iin15_a ;
+   output Iin22_a ;
+   wire Iin2_d_d0 ;
+   wire Iin11_d_d0 ;
+   wire Iin22_d_d0 ;
+   wire Iin12_d_d0 ;
+   output Iin11_a ;
+   wire Iin8_d_d0 ;
+   output Iout_d2 ;
+   output Iin16_a ;
+   output Iin23_a ;
+   wire Iin7_d_d0 ;
+   wire Iin0_d_d0 ;
+   wire Idly_cfg3 ;
+   wire Idly_cfg1 ;
+   output Iout_d1 ;
+   output Iin1_a ;
+   output Iin7_a ;
+   output Iin6_a ;
+   output Iin0_a ;
+   output Iin12_a ;
+   output Iin4_a ;
+   wire Iin19_d_d0 ;
+   wire Iin9_d_d0 ;
+   output Iout_d3 ;
+   output Iin14_a ;
+   wire Iin1_d_d0 ;
+   wire Idly_cfg0 ;
+   output Iin18_a ;
+   wire Iin10_d_d0 ;
+   output Iin5_a ;
+   wire reset_B;
+   wire Iin17_d_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0encoder1d__bd_35_724_75_74_4 Ic  (.Iin0_d_d0 (Iin0_d_d0 ), .Iin0_a (Iin0_a ), .Iin1_d_d0 (Iin1_d_d0 ), .Iin1_a (Iin1_a ), .Iin2_d_d0 (Iin2_d_d0 ), .Iin2_a (Iin2_a ), .Iin3_d_d0 (Iin3_d_d0 ), .Iin3_a (Iin3_a ), .Iin4_d_d0 (Iin4_d_d0 ), .Iin4_a (Iin4_a ), .Iin5_d_d0 (Iin5_d_d0 ), .Iin5_a (Iin5_a ), .Iin6_d_d0 (Iin6_d_d0 ), .Iin6_a (Iin6_a ), .Iin7_d_d0 (Iin7_d_d0 ), .Iin7_a (Iin7_a ), .Iin8_d_d0 (Iin8_d_d0 ), .Iin8_a (Iin8_a ), .Iin9_d_d0 (Iin9_d_d0 ), .Iin9_a (Iin9_a ), .Iin10_d_d0 (Iin10_d_d0 ), .Iin10_a (Iin10_a ), .Iin11_d_d0 (Iin11_d_d0 ), .Iin11_a (Iin11_a ), .Iin12_d_d0 (Iin12_d_d0 ), .Iin12_a (Iin12_a ), .Iin13_d_d0 (Iin13_d_d0 ), .Iin13_a (Iin13_a ), .Iin14_d_d0 (Iin14_d_d0 ), .Iin14_a (Iin14_a ), .Iin15_d_d0 (Iin15_d_d0 ), .Iin15_a (Iin15_a ), .Iin16_d_d0 (Iin16_d_d0 ), .Iin16_a (Iin16_a ), .Iin17_d_d0 (Iin17_d_d0 ), .Iin17_a (Iin17_a ), .Iin18_d_d0 (Iin18_d_d0 ), .Iin18_a (Iin18_a ), .Iin19_d_d0 (Iin19_d_d0 ), .Iin19_a (Iin19_a ), .Iin20_d_d0 (Iin20_d_d0 ), .Iin20_a (Iin20_a ), .Iin21_d_d0 (Iin21_d_d0 ), .Iin21_a (Iin21_a ), .Iin22_d_d0 (Iin22_d_d0 ), .Iin22_a (Iin22_a ), .Iin23_d_d0 (Iin23_d_d0 ), .Iin23_a (Iin23_a ), .Iout_d0 (Iout_d0 ), .Iout_d1 (Iout_d1 ), .Iout_d2 (Iout_d2 ), .Iout_d3 (Iout_d3 ), .Iout_d4 (Iout_d4 ), .Iout_r (Iout_r ), .Iout_a (Iout_a ), .Idly_cfg0 (Idly_cfg0 ), .Idly_cfg1 (Idly_cfg1 ), .Idly_cfg2 (Idly_cfg2 ), .Idly_cfg3 (Idly_cfg3 ), .reset_B(reset_B), .Isupply_vss (vss), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/verilog.v
@@ -0,0 +1,26 @@
+module tmpl_0_0dataflow__neuro_0_0arbiter__handshake(Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iout_d_d0 , Iout_a , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   
+   input Iout_a ;
+
+// -- signals ---
+   wire _y1_arb ;
+   wire Iout_a ;
+   wire Iin1_d_d0 ;
+   wire Iin2_d_d0 ;
+   output Iin1_a ;
+   output Iin2_a ;
+   output Iout_d_d0 ;
+   wire _y2_arb ;
+
+// --- instances
+A_2C_B_X1 Iack_cell1  (.y(Iin1_a ), .c1(Iout_a ), .c2(_y1_arb), .vdd(vdd), .vss(vss));
+ARBITER Iarbiter  (.a(Iin1_d_d0 ), .b(Iin2_d_d0 ), .c(Iin2_a ), .d(Iin1_a ), .y1(_y1_arb), .y2(_y2_arb), .vdd(vdd), .vss(vss));
+A_2C_B_X1 Iack_cell2  (.y(Iin2_a ), .c1(Iout_a ), .c2(_y2_arb), .vdd(vdd), .vss(vss));
+OR2_X1 Ior_cell  (.y(Iout_d_d0 ), .a(_y1_arb), .b(_y2_arb), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_324_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_324_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_324_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_324_4/netlist/verilog.v
@@ -0,0 +1,175 @@
+module tmpl_0_0dataflow__neuro_0_0arbtree_324_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iin15_d_d0 , Iin15_a , Iin16_d_d0 , Iin16_a , Iin17_d_d0 , Iin17_a , Iin18_d_d0 , Iin18_a , Iin19_d_d0 , Iin19_a , Iin20_d_d0 , Iin20_a , Iin21_d_d0 , Iin21_a , Iin22_d_d0 , Iin22_a , Iin23_d_d0 , Iin23_a , Iout_d_d0 , Iout_a , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0_d_d0 ;
+   
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   input Iin3_d_d0 ;
+   
+   input Iin4_d_d0 ;
+   
+   input Iin5_d_d0 ;
+   
+   input Iin6_d_d0 ;
+   
+   input Iin7_d_d0 ;
+   
+   input Iin8_d_d0 ;
+   
+   input Iin9_d_d0 ;
+   
+   input Iin10_d_d0 ;
+   
+   input Iin11_d_d0 ;
+   
+   input Iin12_d_d0 ;
+   
+   input Iin13_d_d0 ;
+   
+   input Iin14_d_d0 ;
+   
+   input Iin15_d_d0 ;
+   
+   input Iin16_d_d0 ;
+   
+   input Iin17_d_d0 ;
+   
+   input Iin18_d_d0 ;
+   
+   input Iin19_d_d0 ;
+   
+   input Iin20_d_d0 ;
+   
+   input Iin21_d_d0 ;
+   
+   input Iin22_d_d0 ;
+   
+   input Iin23_d_d0 ;
+   
+   
+   input Iout_a ;
+
+// -- signals ---
+   wire Iin9_d_d0 ;
+   wire Itmp43_a ;
+   wire Itmp40_a ;
+   wire Itmp34_a ;
+   wire Itmp32_a ;
+   wire Iin10_d_d0 ;
+   output Iin23_a ;
+   wire Itmp41_a ;
+   wire Itmp35_a ;
+   wire Itmp32_d_d0 ;
+   output Iin11_a ;
+   wire Itmp42_d_d0 ;
+   wire Itmp40_d_d0 ;
+   output Iin22_a ;
+   output Iin16_a ;
+   wire Iin3_d_d0 ;
+   wire Itmp38_a ;
+   wire Itmp37_d_d0 ;
+   wire Iin20_d_d0 ;
+   wire Itmp29_d_d0 ;
+   wire Iin4_d_d0 ;
+   wire Iin19_d_d0 ;
+   output Iin8_a ;
+   wire Iin23_d_d0 ;
+   output Iin19_a ;
+   wire Iin8_d_d0 ;
+   wire Itmp36_d_d0 ;
+   wire Itmp29_a ;
+   output Iin4_a ;
+   wire Itmp24_d_d0 ;
+   wire Itmp31_a ;
+   wire Iin7_d_d0 ;
+   output Iin0_a ;
+   output Iin15_a ;
+   output Iin6_a ;
+   wire Itmp25_a ;
+   output Iin12_a ;
+   wire Itmp25_d_d0 ;
+   wire Itmp24_a ;
+   wire Itmp46_a ;
+   wire Itmp39_a ;
+   wire Iin21_d_d0 ;
+   wire Iin15_d_d0 ;
+   wire Itmp34_d_d0 ;
+   output Iin14_a ;
+   output Iin9_a ;
+   wire Itmp26_a ;
+   output Iin5_a ;
+   wire Iin22_d_d0 ;
+   output Iin2_a ;
+   wire Itmp36_a ;
+   wire Itmp27_a ;
+   wire Itmp30_d_d0 ;
+   output Iin18_a ;
+   wire Itmp45_a ;
+   wire Itmp43_d_d0 ;
+   wire Itmp41_d_d0 ;
+   wire Itmp35_d_d0 ;
+   wire Itmp33_a ;
+   wire Itmp31_d_d0 ;
+   wire Iin0_d_d0 ;
+   wire Itmp38_d_d0 ;
+   wire Iin12_d_d0 ;
+   output Iin10_a ;
+   output Iin1_a ;
+   wire Iin1_d_d0 ;
+   wire Itmp30_a ;
+   output Iin13_a ;
+   wire Iin13_d_d0 ;
+   output Iin7_a ;
+   wire Iin2_d_d0 ;
+   wire Iin16_d_d0 ;
+   wire Iin14_d_d0 ;
+   output Iout_d_d0 ;
+   wire Itmp28_a ;
+   wire Itmp45_d_d0 ;
+   wire Itmp46_d_d0 ;
+   wire Itmp26_d_d0 ;
+   wire Itmp37_a ;
+   output Iin20_a ;
+   wire Itmp33_d_d0 ;
+   wire Iin18_d_d0 ;
+   wire Iin5_d_d0 ;
+   output Iin3_a ;
+   wire Itmp42_a ;
+   output Iin21_a ;
+   output Iin17_a ;
+   wire Iin17_d_d0 ;
+   wire Iin11_d_d0 ;
+   wire Itmp28_d_d0 ;
+   wire Iout_a ;
+   wire Itmp39_d_d0 ;
+   wire Itmp27_d_d0 ;
+   wire Iin6_d_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0  (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp24_d_d0 ), .Iout_a (Itmp24_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1  (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp25_d_d0 ), .Iout_a (Itmp25_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2  (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp26_d_d0 ), .Iout_a (Itmp26_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3  (.Iin1_d_d0 (Iin6_d_d0 ), .Iin1_a (Iin6_a ), .Iin2_d_d0 (Iin7_d_d0 ), .Iin2_a (Iin7_a ), .Iout_d_d0 (Itmp27_d_d0 ), .Iout_a (Itmp27_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4  (.Iin1_d_d0 (Iin8_d_d0 ), .Iin1_a (Iin8_a ), .Iin2_d_d0 (Iin9_d_d0 ), .Iin2_a (Iin9_a ), .Iout_d_d0 (Itmp28_d_d0 ), .Iout_a (Itmp28_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs5  (.Iin1_d_d0 (Iin10_d_d0 ), .Iin1_a (Iin10_a ), .Iin2_d_d0 (Iin11_d_d0 ), .Iin2_a (Iin11_a ), .Iout_d_d0 (Itmp29_d_d0 ), .Iout_a (Itmp29_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs6  (.Iin1_d_d0 (Iin12_d_d0 ), .Iin1_a (Iin12_a ), .Iin2_d_d0 (Iin13_d_d0 ), .Iin2_a (Iin13_a ), .Iout_d_d0 (Itmp30_d_d0 ), .Iout_a (Itmp30_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs7  (.Iin1_d_d0 (Iin14_d_d0 ), .Iin1_a (Iin14_a ), .Iin2_d_d0 (Iin15_d_d0 ), .Iin2_a (Iin15_a ), .Iout_d_d0 (Itmp31_d_d0 ), .Iout_a (Itmp31_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs8  (.Iin1_d_d0 (Iin16_d_d0 ), .Iin1_a (Iin16_a ), .Iin2_d_d0 (Iin17_d_d0 ), .Iin2_a (Iin17_a ), .Iout_d_d0 (Itmp32_d_d0 ), .Iout_a (Itmp32_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs9  (.Iin1_d_d0 (Iin18_d_d0 ), .Iin1_a (Iin18_a ), .Iin2_d_d0 (Iin19_d_d0 ), .Iin2_a (Iin19_a ), .Iout_d_d0 (Itmp33_d_d0 ), .Iout_a (Itmp33_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs10  (.Iin1_d_d0 (Iin20_d_d0 ), .Iin1_a (Iin20_a ), .Iin2_d_d0 (Iin21_d_d0 ), .Iin2_a (Iin21_a ), .Iout_d_d0 (Itmp34_d_d0 ), .Iout_a (Itmp34_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs11  (.Iin1_d_d0 (Iin22_d_d0 ), .Iin1_a (Iin22_a ), .Iin2_d_d0 (Iin23_d_d0 ), .Iin2_a (Iin23_a ), .Iout_d_d0 (Itmp35_d_d0 ), .Iout_a (Itmp35_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs12  (.Iin1_d_d0 (Itmp24_d_d0 ), .Iin1_a (Itmp24_a ), .Iin2_d_d0 (Itmp25_d_d0 ), .Iin2_a (Itmp25_a ), .Iout_d_d0 (Itmp36_d_d0 ), .Iout_a (Itmp36_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs13  (.Iin1_d_d0 (Itmp26_d_d0 ), .Iin1_a (Itmp26_a ), .Iin2_d_d0 (Itmp27_d_d0 ), .Iin2_a (Itmp27_a ), .Iout_d_d0 (Itmp37_d_d0 ), .Iout_a (Itmp37_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs14  (.Iin1_d_d0 (Itmp28_d_d0 ), .Iin1_a (Itmp28_a ), .Iin2_d_d0 (Itmp29_d_d0 ), .Iin2_a (Itmp29_a ), .Iout_d_d0 (Itmp38_d_d0 ), .Iout_a (Itmp38_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs15  (.Iin1_d_d0 (Itmp30_d_d0 ), .Iin1_a (Itmp30_a ), .Iin2_d_d0 (Itmp31_d_d0 ), .Iin2_a (Itmp31_a ), .Iout_d_d0 (Itmp39_d_d0 ), .Iout_a (Itmp39_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs16  (.Iin1_d_d0 (Itmp32_d_d0 ), .Iin1_a (Itmp32_a ), .Iin2_d_d0 (Itmp33_d_d0 ), .Iin2_a (Itmp33_a ), .Iout_d_d0 (Itmp40_d_d0 ), .Iout_a (Itmp40_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs17  (.Iin1_d_d0 (Itmp34_d_d0 ), .Iin1_a (Itmp34_a ), .Iin2_d_d0 (Itmp35_d_d0 ), .Iin2_a (Itmp35_a ), .Iout_d_d0 (Itmp41_d_d0 ), .Iout_a (Itmp41_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs18  (.Iin1_d_d0 (Itmp36_d_d0 ), .Iin1_a (Itmp36_a ), .Iin2_d_d0 (Itmp37_d_d0 ), .Iin2_a (Itmp37_a ), .Iout_d_d0 (Itmp42_d_d0 ), .Iout_a (Itmp42_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs19  (.Iin1_d_d0 (Itmp38_d_d0 ), .Iin1_a (Itmp38_a ), .Iin2_d_d0 (Itmp39_d_d0 ), .Iin2_a (Itmp39_a ), .Iout_d_d0 (Itmp43_d_d0 ), .Iout_a (Itmp43_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs20  (.Iin1_d_d0 (Itmp40_d_d0 ), .Iin1_a (Itmp40_a ), .Iin2_d_d0 (Itmp41_d_d0 ), .Iin2_a (Itmp41_a ), .Iout_d_d0 (Itmp46_d_d0 ), .Iout_a (Itmp46_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs21  (.Iin1_d_d0 (Itmp42_d_d0 ), .Iin1_a (Itmp42_a ), .Iin2_d_d0 (Itmp43_d_d0 ), .Iin2_a (Itmp43_a ), .Iout_d_d0 (Itmp45_d_d0 ), .Iout_a (Itmp45_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs22  (.Iin1_d_d0 (Itmp45_d_d0 ), .Iin1_a (Itmp45_a ), .Iin2_d_d0 (Itmp46_d_d0 ), .Iin2_a (Itmp46_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_35_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_35_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_35_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_35_4/netlist/verilog.v
@@ -0,0 +1,84 @@
+module tmpl_0_0dataflow__neuro_0_0buffer_35_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   output Iout_d_d3_d1 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d1_d0 ;
+   output Iout_d_d3_d0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iout_v ;
+   wire I_out_a_BX0 ;
+   wire Iin_d_d3_d0 ;
+   wire Ien_buf_out0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d4_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire _in_v ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire _reset_BX ;
+   wire Iin_d_d0_d1 ;
+   wire Iout_a ;
+   output Iin_a ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d4_d0 ;
+   output Iin_v ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d0_d1 ;
+   wire _out_a_B ;
+   output Iout_d_d0_d0 ;
+   wire reset_B;
+   wire Iin_d_d3_d1 ;
+   wire _en ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d2_d1 ;
+   wire I_reset_BXX0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_310_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_310_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_35_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_310_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_35_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_35_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_35_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_35_4/netlist/verilog.v
@@ -0,0 +1,25 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   output out;
+
+// -- signals ---
+   wire Itmp5 ;
+   wire Iin3 ;
+   wire Iin0 ;
+   wire Iin2 ;
+   wire Iin4 ;
+   wire out ;
+   wire Itmp6 ;
+   wire Iin1 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp5 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(out), .c1(Itmp5 ), .c2(Itmp6 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp6 ), .c1(Iin2 ), .c2(Iin3 ), .c3(Iin4 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist/verilog.v
@@ -0,0 +1,65 @@
+module tmpl_0_0dataflow__neuro_0_0delayprog_34_4(out, in, Is0 , Is1 , Is2 , Is3 , vdd, vss); 
+   input vdd;
+   input vss;
+   output out;
+   input in;
+   input Is0 ;
+   input Is1 ;
+   input Is2 ;
+   input Is3 ;
+
+// -- signals ---
+   wire Idly5_a ;
+   wire Idly7_a ;
+   wire Is2 ;
+   wire Idly0_a ;
+   wire Is1 ;
+   wire Is3 ;
+   wire I_a3 ;
+   wire Idly1_a ;
+   wire in;
+   wire Idly6_a ;
+   wire Idly14_y ;
+   wire I_a2 ;
+   wire Is0 ;
+   wire out ;
+   wire Idly14_a ;
+   wire Idly4_a ;
+   wire I_a1 ;
+   wire Idly2_a ;
+   wire Idly10_a ;
+   wire Idly2_y ;
+   wire Idly12_a ;
+   wire Idly9_a ;
+   wire Idly6_y ;
+   wire Idly0_y ;
+   wire Idly3_a ;
+   wire Idly11_a ;
+   wire Idly13_a ;
+   wire Idly8_a ;
+
+// --- instances
+AND2_X1 Iand20  (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand21  (.y(Idly1_a ), .a(I_a1 ), .b(Is1 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand22  (.y(Idly3_a ), .a(I_a2 ), .b(Is2 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand23  (.y(Idly7_a ), .a(I_a3 ), .b(Is3 ), .vdd(vdd), .vss(vss));
+MUX2_X1 Imu20  (.y(I_a1 ), .a(in), .b(Idly0_y ), .s(Is0 ), .vdd(vdd), .vss(vss));
+MUX2_X1 Imu21  (.y(I_a2 ), .a(I_a1 ), .b(Idly2_y ), .s(Is1 ), .vdd(vdd), .vss(vss));
+MUX2_X1 Imu22  (.y(I_a3 ), .a(I_a2 ), .b(Idly6_y ), .s(Is2 ), .vdd(vdd), .vss(vss));
+MUX2_X1 Imu23  (.y(out), .a(I_a3 ), .b(Idly14_y ), .s(Is3 ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly0  (.y(Idly0_y ), .a(Idly0_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly1  (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly2  (.y(Idly2_y ), .a(Idly2_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly3  (.y(Idly4_a ), .a(Idly3_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly4  (.y(Idly5_a ), .a(Idly4_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly5  (.y(Idly6_a ), .a(Idly5_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly6  (.y(Idly6_y ), .a(Idly6_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly7  (.y(Idly8_a ), .a(Idly7_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly8  (.y(Idly9_a ), .a(Idly8_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly9  (.y(Idly10_a ), .a(Idly9_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly10  (.y(Idly11_a ), .a(Idly10_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly11  (.y(Idly12_a ), .a(Idly11_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly12  (.y(Idly13_a ), .a(Idly12_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly13  (.y(Idly14_a ), .a(Idly13_a ), .vdd(vdd), .vss(vss));
+DLY4_X1 Idly14  (.y(Idly14_y ), .a(Idly14_a ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_35_724_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_35_724_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_35_724_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_35_724_4/netlist/verilog.v
@@ -0,0 +1,123 @@
+module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_35_724_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iout_d0_d0 , Iout_d0_d1 , Iout_d1_d0 , Iout_d1_d1 , Iout_d2_d0 , Iout_d2_d1 , Iout_d3_d0 , Iout_d3_d1 , Iout_d4_d0 , Iout_d4_d1 , Isupply_vss , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   input Iin23 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Isupply_vss ;
+
+// -- signals ---
+   wire Iin23 ;
+   wire Iin22 ;
+   wire Iin6 ;
+   wire I_inX5 ;
+   wire Iin21 ;
+   wire Iin4 ;
+   wire I_inX10 ;
+   wire I_inX19 ;
+   wire Iin13 ;
+   wire Iin16 ;
+   wire I_inX21 ;
+   wire Iin11 ;
+   wire I_inX8 ;
+   wire Itielo2_y ;
+   wire Isupply_vss ;
+   wire I_inX6 ;
+   output Iout_d0_d1 ;
+   wire Iin5 ;
+   wire I_inX13 ;
+   wire I_inX3 ;
+   wire I_inX22 ;
+   wire I_inX18 ;
+   wire Itielo4_y ;
+   output Iout_d0_d0 ;
+   output Iout_d2_d1 ;
+   wire Iin0 ;
+   wire Iin8 ;
+   wire I_inX16 ;
+   output Iout_d1_d1 ;
+   wire Iin17 ;
+   wire I_inX17 ;
+   wire Iin20 ;
+   wire Iin12 ;
+   wire I_inX14 ;
+   output Iout_d4_d0 ;
+   output Iout_d1_d0 ;
+   wire I_inX7 ;
+   output Iout_d2_d0 ;
+   wire Iin3 ;
+   output Iout_d3_d1 ;
+   wire Iin15 ;
+   wire I_inX0 ;
+   wire Iin19 ;
+   wire I_inX12 ;
+   wire Iin14 ;
+   wire Itielo1_y ;
+   wire Iin2 ;
+   wire I_inX1 ;
+   wire I_inX9 ;
+   wire Iin18 ;
+   wire Iin1 ;
+   output Iout_d4_d1 ;
+   wire Itielo3_y ;
+   wire Iin7 ;
+   wire I_inX11 ;
+   wire I_inX20 ;
+   wire Iin10 ;
+   wire Iin9 ;
+   wire I_inX2 ;
+   wire Itielo0_y ;
+   wire I_inX4 ;
+   output Iout_d3_d0 ;
+   wire I_inX23 ;
+   wire I_inX15 ;
+
+// --- instances
+TIELO_X1 Itielo0  (.y(Itielo0_y ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielo1  (.y(Itielo1_y ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielo2  (.y(Itielo2_y ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielo3  (.y(Itielo3_y ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielo4  (.y(Itielo4_y ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_t0  (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (I_inX7 ), .Iin4 (I_inX9 ), .Iin5 (I_inX11 ), .Iin6 (I_inX13 ), .Iin7 (I_inX15 ), .Iin8 (I_inX17 ), .Iin9 (I_inX19 ), .Iin10 (I_inX21 ), .Iin11 (I_inX23 ), .Iin12 (Itielo0_y ), .Iin13 (Itielo0_y ), .Iin14 (Itielo0_y ), .Iin15 (Itielo0_y ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_t1  (.Iin0 (I_inX2 ), .Iin1 (I_inX3 ), .Iin2 (I_inX6 ), .Iin3 (I_inX7 ), .Iin4 (I_inX10 ), .Iin5 (I_inX11 ), .Iin6 (I_inX14 ), .Iin7 (I_inX15 ), .Iin8 (I_inX18 ), .Iin9 (I_inX19 ), .Iin10 (I_inX22 ), .Iin11 (I_inX23 ), .Iin12 (Itielo1_y ), .Iin13 (Itielo1_y ), .Iin14 (Itielo1_y ), .Iin15 (Itielo1_y ), .out(Iout_d1_d1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_t2  (.Iin0 (I_inX4 ), .Iin1 (I_inX5 ), .Iin2 (I_inX6 ), .Iin3 (I_inX7 ), .Iin4 (I_inX12 ), .Iin5 (I_inX13 ), .Iin6 (I_inX14 ), .Iin7 (I_inX15 ), .Iin8 (I_inX20 ), .Iin9 (I_inX21 ), .Iin10 (I_inX22 ), .Iin11 (I_inX23 ), .Iin12 (Itielo2_y ), .Iin13 (Itielo2_y ), .Iin14 (Itielo2_y ), .Iin15 (Itielo2_y ), .out(Iout_d2_d1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_t3  (.Iin0 (I_inX8 ), .Iin1 (I_inX9 ), .Iin2 (I_inX10 ), .Iin3 (I_inX11 ), .Iin4 (I_inX12 ), .Iin5 (I_inX13 ), .Iin6 (I_inX14 ), .Iin7 (I_inX15 ), .Iin8 (Itielo3_y ), .Iin9 (Itielo3_y ), .Iin10 (Itielo3_y ), .Iin11 (Itielo3_y ), .Iin12 (Itielo3_y ), .Iin13 (Itielo3_y ), .Iin14 (Itielo3_y ), .Iin15 (Itielo3_y ), .out(Iout_d3_d1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_t4  (.Iin0 (I_inX16 ), .Iin1 (I_inX17 ), .Iin2 (I_inX18 ), .Iin3 (I_inX19 ), .Iin4 (I_inX20 ), .Iin5 (I_inX21 ), .Iin6 (I_inX22 ), .Iin7 (I_inX23 ), .Iin8 (Itielo4_y ), .Iin9 (Itielo4_y ), .Iin10 (Itielo4_y ), .Iin11 (Itielo4_y ), .Iin12 (Itielo4_y ), .Iin13 (Itielo4_y ), .Iin14 (Itielo4_y ), .Iin15 (Itielo4_y ), .out(Iout_d4_d1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_f0  (.Iin0 (I_inX0 ), .Iin1 (I_inX2 ), .Iin2 (I_inX4 ), .Iin3 (I_inX6 ), .Iin4 (I_inX8 ), .Iin5 (I_inX10 ), .Iin6 (I_inX12 ), .Iin7 (I_inX14 ), .Iin8 (I_inX16 ), .Iin9 (I_inX18 ), .Iin10 (I_inX20 ), .Iin11 (I_inX22 ), .Iin12 (Itielo0_y ), .Iin13 (Itielo0_y ), .Iin14 (Itielo0_y ), .Iin15 (Itielo0_y ), .out(Iout_d0_d0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_f1  (.Iin0 (I_inX0 ), .Iin1 (I_inX1 ), .Iin2 (I_inX4 ), .Iin3 (I_inX5 ), .Iin4 (I_inX8 ), .Iin5 (I_inX9 ), .Iin6 (I_inX12 ), .Iin7 (I_inX13 ), .Iin8 (I_inX16 ), .Iin9 (I_inX17 ), .Iin10 (I_inX20 ), .Iin11 (I_inX21 ), .Iin12 (Itielo1_y ), .Iin13 (Itielo1_y ), .Iin14 (Itielo1_y ), .Iin15 (Itielo1_y ), .out(Iout_d1_d0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_f2  (.Iin0 (I_inX0 ), .Iin1 (I_inX1 ), .Iin2 (I_inX2 ), .Iin3 (I_inX3 ), .Iin4 (I_inX8 ), .Iin5 (I_inX9 ), .Iin6 (I_inX10 ), .Iin7 (I_inX11 ), .Iin8 (I_inX16 ), .Iin9 (I_inX17 ), .Iin10 (I_inX18 ), .Iin11 (I_inX19 ), .Iin12 (Itielo2_y ), .Iin13 (Itielo2_y ), .Iin14 (Itielo2_y ), .Iin15 (Itielo2_y ), .out(Iout_d2_d0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_f3  (.Iin0 (I_inX0 ), .Iin1 (I_inX1 ), .Iin2 (I_inX2 ), .Iin3 (I_inX3 ), .Iin4 (I_inX4 ), .Iin5 (I_inX5 ), .Iin6 (I_inX6 ), .Iin7 (I_inX7 ), .Iin8 (I_inX16 ), .Iin9 (I_inX17 ), .Iin10 (I_inX18 ), .Iin11 (I_inX19 ), .Iin12 (I_inX20 ), .Iin13 (I_inX21 ), .Iin14 (I_inX22 ), .Iin15 (I_inX23 ), .out(Iout_d3_d0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0ortree_316_4 Iors_f4  (.Iin0 (I_inX0 ), .Iin1 (I_inX1 ), .Iin2 (I_inX2 ), .Iin3 (I_inX3 ), .Iin4 (I_inX4 ), .Iin5 (I_inX5 ), .Iin6 (I_inX6 ), .Iin7 (I_inX7 ), .Iin8 (I_inX8 ), .Iin9 (I_inX9 ), .Iin10 (I_inX10 ), .Iin11 (I_inX11 ), .Iin12 (I_inX12 ), .Iin13 (I_inX13 ), .Iin14 (I_inX14 ), .Iin15 (I_inX15 ), .out(Iout_d4_d0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_324_75_4 Isb_in  (.Iin0 (Iin0 ), .Iin1 (Iin1 ), .Iin2 (Iin2 ), .Iin3 (Iin3 ), .Iin4 (Iin4 ), .Iin5 (Iin5 ), .Iin6 (Iin6 ), .Iin7 (Iin7 ), .Iin8 (Iin8 ), .Iin9 (Iin9 ), .Iin10 (Iin10 ), .Iin11 (Iin11 ), .Iin12 (Iin12 ), .Iin13 (Iin13 ), .Iin14 (Iin14 ), .Iin15 (Iin15 ), .Iin16 (Iin16 ), .Iin17 (Iin17 ), .Iin18 (Iin18 ), .Iin19 (Iin19 ), .Iin20 (Iin20 ), .Iin21 (Iin21 ), .Iin22 (Iin22 ), .Iin23 (Iin23 ), .Iout0 (I_inX0 ), .Iout1 (I_inX1 ), .Iout2 (I_inX2 ), .Iout3 (I_inX3 ), .Iout4 (I_inX4 ), .Iout5 (I_inX5 ), .Iout6 (I_inX6 ), .Iout7 (I_inX7 ), .Iout8 (I_inX8 ), .Iout9 (I_inX9 ), .Iout10 (I_inX10 ), .Iout11 (I_inX11 ), .Iout12 (I_inX12 ), .Iout13 (I_inX13 ), .Iout14 (I_inX14 ), .Iout15 (I_inX15 ), .Iout16 (I_inX16 ), .Iout17 (I_inX17 ), .Iout18 (I_inX18 ), .Iout19 (I_inX19 ), .Iout20 (I_inX20 ), .Iout21 (I_inX21 ), .Iout22 (I_inX22 ), .Iout23 (I_inX23 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__bd_35_724_75_74_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__bd_35_724_75_74_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__bd_35_724_75_74_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__bd_35_724_75_74_4/netlist/verilog.v
@@ -0,0 +1,159 @@
+module tmpl_0_0dataflow__neuro_0_0encoder1d__bd_35_724_75_74_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iin15_d_d0 , Iin15_a , Iin16_d_d0 , Iin16_a , Iin17_d_d0 , Iin17_a , Iin18_d_d0 , Iin18_a , Iin19_d_d0 , Iin19_a , Iin20_d_d0 , Iin20_a , Iin21_d_d0 , Iin21_a , Iin22_d_d0 , Iin22_a , Iin23_d_d0 , Iin23_a , Iout_d0 , Iout_d1 , Iout_d2 , Iout_d3 , Iout_d4 , Iout_r , Iout_a , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , reset_B, Isupply_vss , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0_d_d0 ;
+   
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   input Iin3_d_d0 ;
+   
+   input Iin4_d_d0 ;
+   
+   input Iin5_d_d0 ;
+   
+   input Iin6_d_d0 ;
+   
+   input Iin7_d_d0 ;
+   
+   input Iin8_d_d0 ;
+   
+   input Iin9_d_d0 ;
+   
+   input Iin10_d_d0 ;
+   
+   input Iin11_d_d0 ;
+   
+   input Iin12_d_d0 ;
+   
+   input Iin13_d_d0 ;
+   
+   input Iin14_d_d0 ;
+   
+   input Iin15_d_d0 ;
+   
+   input Iin16_d_d0 ;
+   
+   input Iin17_d_d0 ;
+   
+   input Iin18_d_d0 ;
+   
+   input Iin19_d_d0 ;
+   
+   input Iin20_d_d0 ;
+   
+   input Iin21_d_d0 ;
+   
+   input Iin22_d_d0 ;
+   
+   input Iin23_d_d0 ;
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Idly_cfg0 ;
+   input Idly_cfg1 ;
+   input Idly_cfg2 ;
+   input Idly_cfg3 ;
+   input reset_B;
+   input Isupply_vss ;
+
+// -- signals ---
+   wire Iin9_d_d0 ;
+   wire Iin20_d_d0 ;
+   output Iin11_a ;
+   wire Iin4_d_d0 ;
+   wire I_fifo_out_d_d0_d1 ;
+   wire Iin19_d_d0 ;
+   output Iin10_a ;
+   wire Iin10_d_d0 ;
+   output Iout_d3 ;
+   wire I_fifo_out_d_d1_d1 ;
+   wire Iin21_d_d0 ;
+   wire Iin6_d_d0 ;
+   output Iin15_a ;
+   wire I_enc_out_d_d2_d0 ;
+   wire I_enc_out_d_d0_d0 ;
+   output Iin8_a ;
+   output Iin6_a ;
+   wire Iin3_d_d0 ;
+   output Iin2_a ;
+   wire I_enc_out_d_d3_d1 ;
+   wire I_fifo_out_d_d1_d0 ;
+   wire Iin12_d_d0 ;
+   wire I_enc_out_d_d4_d1 ;
+   wire I_fifo_out_d_d0_d0 ;
+   wire I_enc_out_v ;
+   wire I_fifo_out_d_d3_d0 ;
+   wire I_enc_out_d_d3_d0 ;
+   output Iout_d4 ;
+   output Iin22_a ;
+   wire _reset_BX ;
+   wire Iout_a ;
+   wire I_fifo_out_v ;
+   wire Iin5_d_d0 ;
+   output Iin1_a ;
+   wire Idly_cfg1 ;
+   wire I_fifo_out_d_d2_d0 ;
+   wire Iin14_d_d0 ;
+   output Iin7_a ;
+   output Iin5_a ;
+   wire I_enc_out_d_d4_d0 ;
+   output Iin21_a ;
+   output Iin9_a ;
+   wire I_fifo_out_d_d4_d0 ;
+   output Iin13_a ;
+   output Iin4_a ;
+   wire I_enc_out_d_d2_d1 ;
+   wire I_enc_out_d_d0_d1 ;
+   output Iout_d1 ;
+   wire Idly_cfg0 ;
+   wire Iin18_d_d0 ;
+   wire Iin16_d_d0 ;
+   output Iin12_a ;
+   wire Iin2_d_d0 ;
+   wire I_enc_out_d_d1_d0 ;
+   output Iin0_a ;
+   wire I_fifo_out_a ;
+   wire Iin15_d_d0 ;
+   output Iin14_a ;
+   wire Iin8_d_d0 ;
+   wire Iin7_d_d0 ;
+   wire Iin23_d_d0 ;
+   output Iin20_a ;
+   wire Isupply_vss ;
+   wire I_fifo_out_d_d2_d1 ;
+   wire reset_B;
+   output Iin18_a ;
+   wire I_enc_out_d_d1_d1 ;
+   wire Iin22_d_d0 ;
+   output Iin16_a ;
+   wire Iin1_d_d0 ;
+   wire Idly_cfg3 ;
+   wire I_enc_out_a ;
+   wire Idly_cfg2 ;
+   output Iin3_a ;
+   output Iin23_a ;
+   output Iout_d2 ;
+   output Iout_d0 ;
+   output Iin17_a ;
+   wire Iin0_d_d0 ;
+   output Iout_r ;
+   output Iin19_a ;
+   wire I_fifo_out_d_d3_d1 ;
+   wire I_fifo_out_d_d4_d1 ;
+   wire Iin17_d_d0 ;
+   wire Iin13_d_d0 ;
+   wire Iin11_d_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4 I_qdi2bd  (.Iin_d_d0_d0 (I_fifo_out_d_d0_d0 ), .Iin_d_d0_d1 (I_fifo_out_d_d0_d1 ), .Iin_d_d1_d0 (I_fifo_out_d_d1_d0 ), .Iin_d_d1_d1 (I_fifo_out_d_d1_d1 ), .Iin_d_d2_d0 (I_fifo_out_d_d2_d0 ), .Iin_d_d2_d1 (I_fifo_out_d_d2_d1 ), .Iin_d_d3_d0 (I_fifo_out_d_d3_d0 ), .Iin_d_d3_d1 (I_fifo_out_d_d3_d1 ), .Iin_d_d4_d0 (I_fifo_out_d_d4_d0 ), .Iin_d_d4_d1 (I_fifo_out_d_d4_d1 ), .Iin_a (I_fifo_out_a ), .Iin_v (I_fifo_out_v ), .Iout_d0 (Iout_d0 ), .Iout_d1 (Iout_d1 ), .Iout_d2 (Iout_d2 ), .Iout_d3 (Iout_d3 ), .Iout_d4 (Iout_d4 ), .Iout_r (Iout_r ), .Iout_a (Iout_a ), .Idly_cfg0 (Idly_cfg0 ), .Idly_cfg1 (Idly_cfg1 ), .Idly_cfg2 (Idly_cfg2 ), .Idly_cfg3 (Idly_cfg3 ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0fifo_35_75_4 I_fifo  (.Iin_d_d0_d0 (I_enc_out_d_d0_d0 ), .Iin_d_d0_d1 (I_enc_out_d_d0_d1 ), .Iin_d_d1_d0 (I_enc_out_d_d1_d0 ), .Iin_d_d1_d1 (I_enc_out_d_d1_d1 ), .Iin_d_d2_d0 (I_enc_out_d_d2_d0 ), .Iin_d_d2_d1 (I_enc_out_d_d2_d1 ), .Iin_d_d3_d0 (I_enc_out_d_d3_d0 ), .Iin_d_d3_d1 (I_enc_out_d_d3_d1 ), .Iin_d_d4_d0 (I_enc_out_d_d4_d0 ), .Iin_d_d4_d1 (I_enc_out_d_d4_d1 ), .Iin_a (I_enc_out_a ), .Iin_v (I_enc_out_v ), .Iout_d_d0_d0 (I_fifo_out_d_d0_d0 ), .Iout_d_d0_d1 (I_fifo_out_d_d0_d1 ), .Iout_d_d1_d0 (I_fifo_out_d_d1_d0 ), .Iout_d_d1_d1 (I_fifo_out_d_d1_d1 ), .Iout_d_d2_d0 (I_fifo_out_d_d2_d0 ), .Iout_d_d2_d1 (I_fifo_out_d_d2_d1 ), .Iout_d_d3_d0 (I_fifo_out_d_d3_d0 ), .Iout_d_d3_d1 (I_fifo_out_d_d3_d1 ), .Iout_d_d4_d0 (I_fifo_out_d_d4_d0 ), .Iout_d_d4_d1 (I_fifo_out_d_d4_d1 ), .Iout_a (I_fifo_out_a ), .Iout_v (I_fifo_out_v ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0encoder1d__simple_35_724_4 I_enc  (.Iin0_d_d0 (Iin0_d_d0 ), .Iin0_a (Iin0_a ), .Iin1_d_d0 (Iin1_d_d0 ), .Iin1_a (Iin1_a ), .Iin2_d_d0 (Iin2_d_d0 ), .Iin2_a (Iin2_a ), .Iin3_d_d0 (Iin3_d_d0 ), .Iin3_a (Iin3_a ), .Iin4_d_d0 (Iin4_d_d0 ), .Iin4_a (Iin4_a ), .Iin5_d_d0 (Iin5_d_d0 ), .Iin5_a (Iin5_a ), .Iin6_d_d0 (Iin6_d_d0 ), .Iin6_a (Iin6_a ), .Iin7_d_d0 (Iin7_d_d0 ), .Iin7_a (Iin7_a ), .Iin8_d_d0 (Iin8_d_d0 ), .Iin8_a (Iin8_a ), .Iin9_d_d0 (Iin9_d_d0 ), .Iin9_a (Iin9_a ), .Iin10_d_d0 (Iin10_d_d0 ), .Iin10_a (Iin10_a ), .Iin11_d_d0 (Iin11_d_d0 ), .Iin11_a (Iin11_a ), .Iin12_d_d0 (Iin12_d_d0 ), .Iin12_a (Iin12_a ), .Iin13_d_d0 (Iin13_d_d0 ), .Iin13_a (Iin13_a ), .Iin14_d_d0 (Iin14_d_d0 ), .Iin14_a (Iin14_a ), .Iin15_d_d0 (Iin15_d_d0 ), .Iin15_a (Iin15_a ), .Iin16_d_d0 (Iin16_d_d0 ), .Iin16_a (Iin16_a ), .Iin17_d_d0 (Iin17_d_d0 ), .Iin17_a (Iin17_a ), .Iin18_d_d0 (Iin18_d_d0 ), .Iin18_a (Iin18_a ), .Iin19_d_d0 (Iin19_d_d0 ), .Iin19_a (Iin19_a ), .Iin20_d_d0 (Iin20_d_d0 ), .Iin20_a (Iin20_a ), .Iin21_d_d0 (Iin21_d_d0 ), .Iin21_a (Iin21_a ), .Iin22_d_d0 (Iin22_d_d0 ), .Iin22_a (Iin22_a ), .Iin23_d_d0 (Iin23_d_d0 ), .Iin23_a (Iin23_a ), .Iout_d_d0_d0 (I_enc_out_d_d0_d0 ), .Iout_d_d0_d1 (I_enc_out_d_d0_d1 ), .Iout_d_d1_d0 (I_enc_out_d_d1_d0 ), .Iout_d_d1_d1 (I_enc_out_d_d1_d1 ), .Iout_d_d2_d0 (I_enc_out_d_d2_d0 ), .Iout_d_d2_d1 (I_enc_out_d_d2_d1 ), .Iout_d_d3_d0 (I_enc_out_d_d3_d0 ), .Iout_d_d3_d1 (I_enc_out_d_d3_d1 ), .Iout_d_d4_d0 (I_enc_out_d_d4_d0 ), .Iout_d_d4_d1 (I_enc_out_d_d4_d1 ), .Iout_a (I_enc_out_a ), .Iout_v (I_enc_out_v ), .Isupply_vss (Isupply_vss ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
+BUF_X4 Irsb  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__simple_35_724_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__simple_35_724_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__simple_35_724_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0encoder1d__simple_35_724_4/netlist/verilog.v
@@ -0,0 +1,152 @@
+module tmpl_0_0dataflow__neuro_0_0encoder1d__simple_35_724_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iin15_d_d0 , Iin15_a , Iin16_d_d0 , Iin16_a , Iin17_d_d0 , Iin17_a , Iin18_d_d0 , Iin18_a , Iin19_d_d0 , Iin19_a , Iin20_d_d0 , Iin20_a , Iin21_d_d0 , Iin21_a , Iin22_d_d0 , Iin22_a , Iin23_d_d0 , Iin23_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_a , Iout_v , Isupply_vss , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0_d_d0 ;
+   
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   input Iin3_d_d0 ;
+   
+   input Iin4_d_d0 ;
+   
+   input Iin5_d_d0 ;
+   
+   input Iin6_d_d0 ;
+   
+   input Iin7_d_d0 ;
+   
+   input Iin8_d_d0 ;
+   
+   input Iin9_d_d0 ;
+   
+   input Iin10_d_d0 ;
+   
+   input Iin11_d_d0 ;
+   
+   input Iin12_d_d0 ;
+   
+   input Iin13_d_d0 ;
+   
+   input Iin14_d_d0 ;
+   
+   input Iin15_d_d0 ;
+   
+   input Iin16_d_d0 ;
+   
+   input Iin17_d_d0 ;
+   
+   input Iin18_d_d0 ;
+   
+   input Iin19_d_d0 ;
+   
+   input Iin20_d_d0 ;
+   
+   input Iin21_d_d0 ;
+   
+   input Iin22_d_d0 ;
+   
+   input Iin23_d_d0 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input Isupply_vss ;
+   input reset_B;
+
+// -- signals ---
+   wire Iout_a ;
+   output Iout_d_d0_d0 ;
+   wire IXenc_out_d3_d1 ;
+   wire _r_x ;
+   output Iin4_a ;
+   output Iout_d_d3_d0 ;
+   output Iin16_a ;
+   wire Iin11_d_d0 ;
+   output Iout_d_d1_d0 ;
+   output Iin10_a ;
+   wire Iin10_d_d0 ;
+   wire Iin4_d_d0 ;
+   output Iin0_a ;
+   output Iin18_a ;
+   wire Iin8_d_d0 ;
+   output Iout_d_d1_d1 ;
+   wire Iin19_d_d0 ;
+   output Iin15_a ;
+   wire Iin9_d_d0 ;
+   output Iout_d_d2_d0 ;
+   wire IXenc_out_d2_d1 ;
+   output Iin13_a ;
+   output Iin22_a ;
+   wire Iin12_d_d0 ;
+   output Iin6_a ;
+   output Iin1_a ;
+   output Iout_d_d3_d1 ;
+   output Iin23_a ;
+   wire Iin16_d_d0 ;
+   wire IXenc_out_d0_d0 ;
+   wire Iin17_d_d0 ;
+   wire Iin13_d_d0 ;
+   output Iin7_a ;
+   output Iin14_a ;
+   output Iin11_a ;
+   wire IXenc_out_d2_d0 ;
+   wire Iin5_d_d0 ;
+   wire Iin20_d_d0 ;
+   wire Iin18_d_d0 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d2_d1 ;
+   wire reset_B;
+   wire IXenc_out_d3_d0 ;
+   wire Iin23_d_d0 ;
+   output Iout_d_d4_d1 ;
+   wire Ibuf_in_v ;
+   wire IXenc_out_d0_d1 ;
+   wire Iin2_d_d0 ;
+   output Iin17_a ;
+   wire Iin15_d_d0 ;
+   wire Iin7_d_d0 ;
+   wire Iin6_d_d0 ;
+   output Iin2_a ;
+   output Iin19_a ;
+   output Iin5_a ;
+   wire Iin1_d_d0 ;
+   wire IXenc_out_d1_d1 ;
+   output Iin9_a ;
+   output Iin8_a ;
+   output Iin3_a ;
+   wire Ia_x_Cel_c1 ;
+   output Iout_d_d0_d1 ;
+   wire IXenc_out_d4_d1 ;
+   wire _a_x ;
+   wire Iin22_d_d0 ;
+   output Iin21_a ;
+   output Iin12_a ;
+   wire Iin14_d_d0 ;
+   wire Iin3_d_d0 ;
+   wire Isupply_vss ;
+   wire IXenc_out_d4_d0 ;
+   wire Iout_v ;
+   wire Iin21_d_d0 ;
+   output Iin20_a ;
+   wire Iin0_d_d0 ;
+   wire Iinv_buf_a ;
+   wire IXenc_out_d1_d0 ;
+
+// --- instances
+INV_X2 Iinv_buf  (.y(Ia_x_Cel_c1 ), .a(Iinv_buf_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbtree_324_4 IXarb  (.Iin0_d_d0 (Iin0_d_d0 ), .Iin0_a (Iin0_a ), .Iin1_d_d0 (Iin1_d_d0 ), .Iin1_a (Iin1_a ), .Iin2_d_d0 (Iin2_d_d0 ), .Iin2_a (Iin2_a ), .Iin3_d_d0 (Iin3_d_d0 ), .Iin3_a (Iin3_a ), .Iin4_d_d0 (Iin4_d_d0 ), .Iin4_a (Iin4_a ), .Iin5_d_d0 (Iin5_d_d0 ), .Iin5_a (Iin5_a ), .Iin6_d_d0 (Iin6_d_d0 ), .Iin6_a (Iin6_a ), .Iin7_d_d0 (Iin7_d_d0 ), .Iin7_a (Iin7_a ), .Iin8_d_d0 (Iin8_d_d0 ), .Iin8_a (Iin8_a ), .Iin9_d_d0 (Iin9_d_d0 ), .Iin9_a (Iin9_a ), .Iin10_d_d0 (Iin10_d_d0 ), .Iin10_a (Iin10_a ), .Iin11_d_d0 (Iin11_d_d0 ), .Iin11_a (Iin11_a ), .Iin12_d_d0 (Iin12_d_d0 ), .Iin12_a (Iin12_a ), .Iin13_d_d0 (Iin13_d_d0 ), .Iin13_a (Iin13_a ), .Iin14_d_d0 (Iin14_d_d0 ), .Iin14_a (Iin14_a ), .Iin15_d_d0 (Iin15_d_d0 ), .Iin15_a (Iin15_a ), .Iin16_d_d0 (Iin16_d_d0 ), .Iin16_a (Iin16_a ), .Iin17_d_d0 (Iin17_d_d0 ), .Iin17_a (Iin17_a ), .Iin18_d_d0 (Iin18_d_d0 ), .Iin18_a (Iin18_a ), .Iin19_d_d0 (Iin19_d_d0 ), .Iin19_a (Iin19_a ), .Iin20_d_d0 (Iin20_d_d0 ), .Iin20_a (Iin20_a ), .Iin21_d_d0 (Iin21_d_d0 ), .Iin21_a (Iin21_a ), .Iin22_d_d0 (Iin22_d_d0 ), .Iin22_a (Iin22_a ), .Iin23_d_d0 (Iin23_d_d0 ), .Iin23_a (Iin23_a ), .Iout_d_d0 (_r_x), .Iout_a (_a_x), .vdd(vdd), .vss(vss));
+A_2C_RB_X1 Ia_x_Cel  (.y(_a_x), .c1(Ia_x_Cel_c1 ), .c2(_r_x), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0dualrail__encoder_35_724_4 IXenc  (.Iin0 (Iin0_a ), .Iin1 (Iin1_a ), .Iin2 (Iin2_a ), .Iin3 (Iin3_a ), .Iin4 (Iin4_a ), .Iin5 (Iin5_a ), .Iin6 (Iin6_a ), .Iin7 (Iin7_a ), .Iin8 (Iin8_a ), .Iin9 (Iin9_a ), .Iin10 (Iin10_a ), .Iin11 (Iin11_a ), .Iin12 (Iin12_a ), .Iin13 (Iin13_a ), .Iin14 (Iin14_a ), .Iin15 (Iin15_a ), .Iin16 (Iin16_a ), .Iin17 (Iin17_a ), .Iin18 (Iin18_a ), .Iin19 (Iin19_a ), .Iin20 (Iin20_a ), .Iin21 (Iin21_a ), .Iin22 (Iin22_a ), .Iin23 (Iin23_a ), .Iout_d0_d0 (IXenc_out_d0_d0 ), .Iout_d0_d1 (IXenc_out_d0_d1 ), .Iout_d1_d0 (IXenc_out_d1_d0 ), .Iout_d1_d1 (IXenc_out_d1_d1 ), .Iout_d2_d0 (IXenc_out_d2_d0 ), .Iout_d2_d1 (IXenc_out_d2_d1 ), .Iout_d3_d0 (IXenc_out_d3_d0 ), .Iout_d3_d1 (IXenc_out_d3_d1 ), .Iout_d4_d0 (IXenc_out_d4_d0 ), .Iout_d4_d1 (IXenc_out_d4_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ibuf  (.Iin_d_d0_d0 (IXenc_out_d0_d0 ), .Iin_d_d0_d1 (IXenc_out_d0_d1 ), .Iin_d_d1_d0 (IXenc_out_d1_d0 ), .Iin_d_d1_d1 (IXenc_out_d1_d1 ), .Iin_d_d2_d0 (IXenc_out_d2_d0 ), .Iin_d_d2_d1 (IXenc_out_d2_d1 ), .Iin_d_d3_d0 (IXenc_out_d3_d0 ), .Iin_d_d3_d1 (IXenc_out_d3_d1 ), .Iin_d_d4_d0 (IXenc_out_d4_d0 ), .Iin_d_d4_d1 (IXenc_out_d4_d1 ), .Iin_a (Iinv_buf_a ), .Iin_v (Ibuf_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_35_75_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_35_75_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_35_75_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_35_75_4/netlist/verilog.v
@@ -0,0 +1,115 @@
+module tmpl_0_0dataflow__neuro_0_0fifo_35_75_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   wire Ififo_element1_in_d_d1_d0 ;
+   wire Ififo_element4_in_d_d4_d1 ;
+   wire Ififo_element4_in_d_d1_d1 ;
+   wire Ififo_element2_in_d_d4_d1 ;
+   wire Ififo_element2_in_d_d2_d0 ;
+   output Iin_a ;
+   wire Iout_a ;
+   output Iout_d_d2_d1 ;
+   wire Ififo_element4_in_d_d2_d0 ;
+   wire Ififo_element4_in_d_d0_d1 ;
+   wire Ififo_element1_in_d_d3_d1 ;
+   wire Ififo_element4_in_d_d3_d0 ;
+   wire Ififo_element2_in_d_d0_d1 ;
+   wire Ififo_element3_in_d_d4_d1 ;
+   wire Ififo_element2_in_v ;
+   wire Ififo_element2_in_d_d1_d0 ;
+   wire Ififo_element1_in_d_d4_d0 ;
+   wire Iin_d_d4_d1 ;
+   wire reset_B;
+   wire Ififo_element4_in_d_d2_d1 ;
+   output Iout_d_d3_d1 ;
+   wire Ififo_element2_in_d_d0_d0 ;
+   output Iout_d_d4_d1 ;
+   wire Ififo_element2_in_d_d3_d1 ;
+   wire Iin_d_d1_d1 ;
+   wire _reset_BX ;
+   output Iout_d_d1_d1 ;
+   wire Ififo_element2_in_a ;
+   wire Ififo_element1_in_v ;
+   wire Iin_d_d2_d0 ;
+   wire Ififo_element3_in_d_d4_d0 ;
+   wire Ififo_element2_in_d_d4_d0 ;
+   wire Ififo_element3_in_d_d0_d1 ;
+   wire Ififo_element2_in_d_d2_d1 ;
+   wire Ififo_element1_in_a ;
+   wire Iin_d_d2_d1 ;
+   wire Ififo_element1_in_d_d3_d0 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d4_d0 ;
+   wire Ififo_element3_in_d_d3_d1 ;
+   wire Ififo_element3_in_d_d1_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Ififo_element3_in_a ;
+   wire Ififo_element2_in_d_d3_d0 ;
+   output Iout_d_d0_d0 ;
+   wire Ififo_element4_in_d_d4_d0 ;
+   wire Iout_v ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d1_d0 ;
+   wire Ififo_element4_in_d_d0_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire I_reset_BXX4 ;
+   wire Ififo_element3_in_d_d2_d0 ;
+   wire Ififo_element3_in_d_d1_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Ififo_element4_in_v ;
+   wire Ififo_element3_in_d_d3_d0 ;
+   wire Ififo_element1_in_d_d2_d1 ;
+   wire Ififo_element1_in_d_d2_d0 ;
+   wire Ififo_element1_in_d_d0_d1 ;
+   output Iin_v ;
+   wire Ififo_element4_in_d_d1_d0 ;
+   wire Ififo_element2_in_d_d1_d1 ;
+   wire Ififo_element1_in_d_d0_d0 ;
+   wire Ififo_element3_in_v ;
+   wire Ififo_element1_in_d_d4_d1 ;
+   wire Ififo_element3_in_d_d2_d1 ;
+   wire Ififo_element3_in_d_d0_d0 ;
+   output Iout_d_d3_d0 ;
+   wire Ififo_element4_in_a ;
+   output Iout_d_d0_d1 ;
+   wire Ififo_element4_in_d_d3_d1 ;
+   wire Ififo_element1_in_d_d1_d1 ;
+   wire Iin_d_d1_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX4 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element0  (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iout_a (Ififo_element1_in_a ), .Iout_v (Ififo_element1_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element1  (.Iin_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iin_a (Ififo_element1_in_a ), .Iin_v (Ififo_element1_in_v ), .Iout_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iout_a (Ififo_element2_in_a ), .Iout_v (Ififo_element2_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element2  (.Iin_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iin_a (Ififo_element2_in_a ), .Iin_v (Ififo_element2_in_v ), .Iout_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iout_a (Ififo_element3_in_a ), .Iout_v (Ififo_element3_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element3  (.Iin_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iin_a (Ififo_element3_in_a ), .Iin_v (Ififo_element3_in_v ), .Iout_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iout_a (Ififo_element4_in_a ), .Iout_v (Ififo_element4_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element4  (.Iin_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iin_a (Ififo_element4_in_a ), .Iin_v (Ififo_element4_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_316_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_316_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_316_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_316_4/netlist/verilog.v
@@ -0,0 +1,71 @@
+module tmpl_0_0dataflow__neuro_0_0ortree_316_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   output out;
+
+// -- signals ---
+   wire Itmp19 ;
+   wire Iin15 ;
+   wire Iin4 ;
+   wire Itmp18 ;
+   wire Itmp21 ;
+   wire Iin1 ;
+   wire Itmp29 ;
+   wire Itmp26 ;
+   wire Iin11 ;
+   wire Iin6 ;
+   wire Iin14 ;
+   wire Iin9 ;
+   wire Itmp22 ;
+   wire Itmp25 ;
+   wire Itmp23 ;
+   wire Iin13 ;
+   wire Iin10 ;
+   wire Iin5 ;
+   wire Itmp28 ;
+   wire out ;
+   wire Iin0 ;
+   wire Iin3 ;
+   wire Itmp20 ;
+   wire Itmp16 ;
+   wire Iin12 ;
+   wire Itmp17 ;
+   wire Itmp27 ;
+   wire Iin2 ;
+   wire Iin8 ;
+   wire Itmp24 ;
+   wire Iin7 ;
+
+// --- instances
+OR2_X1 Ior2s0  (.y(Itmp16 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s1  (.y(Itmp17 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s2  (.y(Itmp18 ), .a(Iin4 ), .b(Iin5 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s3  (.y(Itmp19 ), .a(Iin6 ), .b(Iin7 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s4  (.y(Itmp20 ), .a(Iin8 ), .b(Iin9 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s5  (.y(Itmp21 ), .a(Iin10 ), .b(Iin11 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s6  (.y(Itmp22 ), .a(Iin12 ), .b(Iin13 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s7  (.y(Itmp23 ), .a(Iin14 ), .b(Iin15 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s8  (.y(Itmp24 ), .a(Itmp16 ), .b(Itmp17 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s9  (.y(Itmp25 ), .a(Itmp18 ), .b(Itmp19 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s10  (.y(Itmp26 ), .a(Itmp20 ), .b(Itmp21 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s11  (.y(Itmp27 ), .a(Itmp22 ), .b(Itmp23 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s12  (.y(Itmp28 ), .a(Itmp24 ), .b(Itmp25 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s13  (.y(Itmp29 ), .a(Itmp26 ), .b(Itmp27 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ior2s14  (.y(out), .a(Itmp28 ), .b(Itmp29 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4/netlist/verilog.v
@@ -0,0 +1,65 @@
+module tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_a , Iin_v , Iout_d0 , Iout_d1 , Iout_d2 , Iout_d3 , Iout_d4 , Iout_r , Iout_a , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Idly_cfg0 ;
+   input Idly_cfg1 ;
+   input Idly_cfg2 ;
+   input Idly_cfg3 ;
+   input reset_B;
+
+// -- signals ---
+   wire Iin_d_d0_d0 ;
+   output Iout_d4 ;
+   wire Iout_vtree_in_d3_d0 ;
+   output Iin_a ;
+   output Iin_v ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d1_d1 ;
+   wire reset_B;
+   wire Iout_vtree_in_d1_d0 ;
+   wire Idly_cfg3 ;
+   output Iout_d2 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d1_d0 ;
+   output Iout_r ;
+   wire Iout_a ;
+   wire Idly_cfg0 ;
+   wire Idly_cfg1 ;
+   wire Iout_vtree_in_d2_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Idly_in ;
+   wire Iin_d_d4_d1 ;
+   wire Iout_vtree_in_d4_d0 ;
+   output Iout_d0 ;
+   wire Iin_d_d0_d1 ;
+   output Iout_d3 ;
+   wire Iout_vtree_in_d0_d0 ;
+   wire Idly_cfg2 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly  (.out(Iout_r ), .in(Idly_in ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ibuf  (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Iout_vtree_in_d0_d0 ), .Iout_d_d0_d1 (Iout_d0 ), .Iout_d_d1_d0 (Iout_vtree_in_d1_d0 ), .Iout_d_d1_d1 (Iout_d1 ), .Iout_d_d2_d0 (Iout_vtree_in_d2_d0 ), .Iout_d_d2_d1 (Iout_d2 ), .Iout_d_d3_d0 (Iout_vtree_in_d3_d0 ), .Iout_d_d3_d1 (Iout_d3 ), .Iout_d_d4_d0 (Iout_vtree_in_d4_d0 ), .Iout_d_d4_d1 (Iout_d4 ), .Iout_a (Iout_a ), .Iout_v (Idly_in ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_35_4 Iout_vtree  (.Iin_d0_d0 (Iout_vtree_in_d0_d0 ), .Iin_d0_d1 (Iout_d0 ), .Iin_d1_d0 (Iout_vtree_in_d1_d0 ), .Iin_d1_d1 (Iout_d1 ), .Iin_d2_d0 (Iout_vtree_in_d2_d0 ), .Iin_d2_d1 (Iout_d2 ), .Iin_d3_d0 (Iout_vtree_in_d3_d0 ), .Iin_d3_d1 (Iout_d3 ), .Iin_d4_d0 (Iout_vtree_in_d4_d0 ), .Iin_d4_d1 (Iout_d4 ), .out(Idly_in ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_310_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_310_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_310_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_310_4/netlist/verilog.v
@@ -0,0 +1,13 @@
+module tmpl_0_0dataflow__neuro_0_0sigbuf_310_4(in, Iout0 , vdd, vss); 
+   input vdd;
+   input vss;
+   input in;
+   
+
+// -- signals ---
+   wire in;
+   output Iout0 ;
+
+// --- instances
+BUF_X3 Ibuf3  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_35_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_35_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_35_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_35_4/netlist/verilog.v
@@ -0,0 +1,13 @@
+module tmpl_0_0dataflow__neuro_0_0sigbuf_35_4(in, Iout0 , vdd, vss); 
+   input vdd;
+   input vss;
+   input in;
+   
+
+// -- signals ---
+   output Iout0 ;
+   wire in;
+
+// --- instances
+BUF_X2 Ibuf2  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_324_75_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_324_75_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_324_75_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_324_75_4/netlist/verilog.v
@@ -0,0 +1,128 @@
+module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_324_75_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   input Iin23 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+// -- signals ---
+   output Iout5 ;
+   wire Iin11 ;
+   output Iout1 ;
+   wire Iin22 ;
+   output Iout6 ;
+   wire Iin20 ;
+   wire Iin17 ;
+   wire Iin5 ;
+   wire Iin18 ;
+   wire Iin2 ;
+   wire Iin0 ;
+   output Iout17 ;
+   output Iout16 ;
+   output Iout9 ;
+   output Iout23 ;
+   wire Iin4 ;
+   output Iout8 ;
+   wire Iin8 ;
+   output Iout7 ;
+   output Iout14 ;
+   wire Iin14 ;
+   output Iout22 ;
+   wire Iin16 ;
+   output Iout0 ;
+   wire Iin10 ;
+   output Iout19 ;
+   wire Iin13 ;
+   wire Iin19 ;
+   output Iout2 ;
+   output Iout20 ;
+   wire Iin6 ;
+   wire Iin23 ;
+   output Iout21 ;
+   output Iout13 ;
+   output Iout3 ;
+   output Iout18 ;
+   wire Iin7 ;
+   output Iout15 ;
+   output Iout12 ;
+   output Iout10 ;
+   wire Iin1 ;
+   wire Iin21 ;
+   wire Iin9 ;
+   wire Iin3 ;
+   output Iout11 ;
+   output Iout4 ;
+   wire Iin15 ;
+   wire Iin12 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb0  (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb1  (.in(Iin1 ), .Iout0 (Iout1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb2  (.in(Iin2 ), .Iout0 (Iout2 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb3  (.in(Iin3 ), .Iout0 (Iout3 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb4  (.in(Iin4 ), .Iout0 (Iout4 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb5  (.in(Iin5 ), .Iout0 (Iout5 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb6  (.in(Iin6 ), .Iout0 (Iout6 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb7  (.in(Iin7 ), .Iout0 (Iout7 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb8  (.in(Iin8 ), .Iout0 (Iout8 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb9  (.in(Iin9 ), .Iout0 (Iout9 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb10  (.in(Iin10 ), .Iout0 (Iout10 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb11  (.in(Iin11 ), .Iout0 (Iout11 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb12  (.in(Iin12 ), .Iout0 (Iout12 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb13  (.in(Iin13 ), .Iout0 (Iout13 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb14  (.in(Iin14 ), .Iout0 (Iout14 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb15  (.in(Iin15 ), .Iout0 (Iout15 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb16  (.in(Iin16 ), .Iout0 (Iout16 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb17  (.in(Iin17 ), .Iout0 (Iout17 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb18  (.in(Iin18 ), .Iout0 (Iout18 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb19  (.in(Iin19 ), .Iout0 (Iout19 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb20  (.in(Iin20 ), .Iout0 (Iout20 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb21  (.in(Iin21 ), .Iout0 (Iout21 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb22  (.in(Iin22 ), .Iout0 (Iout22 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Isb23  (.in(Iin23 ), .Iout0 (Iout23 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0vtree_35_4/netlist/master.tag
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0vtree_35_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0vtree_35_4/netlist/verilog.v
+++ b/test/unit_tests/sadc_encoder/split_modules/tmpl_0_0dataflow__neuro_0_0vtree_35_4/netlist/verilog.v
@@ -0,0 +1,41 @@
+module tmpl_0_0dataflow__neuro_0_0vtree_35_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d0_d0 ;
+   input Iin_d0_d1 ;
+   input Iin_d1_d0 ;
+   input Iin_d1_d1 ;
+   input Iin_d2_d0 ;
+   input Iin_d2_d1 ;
+   input Iin_d3_d0 ;
+   input Iin_d3_d1 ;
+   input Iin_d4_d0 ;
+   input Iin_d4_d1 ;
+   output out;
+
+// -- signals ---
+   wire Ict_in0 ;
+   wire Iin_d3_d0 ;
+   wire Iin_d0_d1 ;
+   wire Iin_d3_d1 ;
+   wire Iin_d4_d1 ;
+   wire Iin_d1_d1 ;
+   wire Ict_in1 ;
+   wire out ;
+   wire Ict_in2 ;
+   wire Ict_in3 ;
+   wire Iin_d1_d0 ;
+   wire Ict_in4 ;
+   wire Iin_d2_d1 ;
+   wire Iin_d0_d0 ;
+   wire Iin_d2_d0 ;
+   wire Iin_d4_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0ctree_35_4 Ict  (.Iin0 (Ict_in0 ), .Iin1 (Ict_in1 ), .Iin2 (Ict_in2 ), .Iin3 (Ict_in3 ), .Iin4 (Ict_in4 ), .out(out), .vdd(vdd), .vss(vss));
+OR2_X1 IOR2_tf0  (.y(Ict_in0 ), .a(Iin_d0_d1 ), .b(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
+OR2_X1 IOR2_tf1  (.y(Ict_in1 ), .a(Iin_d1_d1 ), .b(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
+OR2_X1 IOR2_tf2  (.y(Ict_in2 ), .a(Iin_d2_d1 ), .b(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
+OR2_X1 IOR2_tf3  (.y(Ict_in3 ), .a(Iin_d3_d1 ), .b(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
+OR2_X1 IOR2_tf4  (.y(Ict_in4 ), .a(Iin_d4_d1 ), .b(Iin_d4_d0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/sadc_encoder/test.act
+++ b/test/unit_tests/sadc_encoder/test.act
@@ -0,0 +1,61 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+pint N = 24;
+pint Nc = std::ceil_log2(N);
+pint N_BUFFERS = 5;
+pint N_BD_DLY_CFG = 4;
+
+defproc sadc_encoder (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]; bool? reset_B) {
+
+    // bool _reset_B;
+    // prs {
+    //    Reset => _reset_B-
+    // }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+    encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
+        .reset_B = reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+sadc_encoder c; 
--- a/test/unit_tests/sadc_encoder/test.prsim
+++ b/test/unit_tests/sadc_encoder/test.prsim
@@ -0,0 +1,102 @@
+watchall
+
+set c.reset_B 0
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+set c.in[4].r 0
+set c.in[5].r 0
+set c.in[6].r 0
+set c.in[7].r 0
+set c.in[8].r 0
+set c.in[9].r 0
+set c.in[10].r 0
+set c.in[11].r 0
+set c.in[12].r 0
+set c.in[13].r 0
+set c.in[14].r 0
+set c.in[15].r 0
+set c.in[16].r 0
+set c.in[17].r 0
+set c.in[18].r 0 
+set c.in[19].r 0
+set c.in[20].r 0
+set c.in[21].r 0
+set c.in[22].r 0
+set c.in[23].r 0
+
+
+set c.out.a 0
+
+# set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+# set Reset 0
+set c.reset_B 1
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 5
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+assert c.in[4].a 0
+assert c.in[5].a 0
+assert c.in[6].a 0
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 5 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 5
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 5 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 5
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+
--- a/test/unit_tests/sadc_hs/test.act
+++ b/test/unit_tests/sadc_hs/test.act
@@ -0,0 +1,67 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/dynapse.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+defproc _sadc_hs (a1of1 in[4], out; bool? reset_B) {
+
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    // pipe loads of inputs into the sadc handshake
+    // to simulate a neuron going nuts
+    fifo_t<3> in_fifos[4];
+    arbtree<4> in_arbtree(.supply = supply);
+
+    (i:4:
+        in_fifos[i].in = in[i];
+        in_fifos[i].reset_B = reset_B;
+        in_fifos[i].out = in_arbtree.in[i];
+        in_fifos[i].supply = supply;
+    )
+
+    sadc_hs c(.in = in_arbtree.out,
+        .reset_B = reset_B, .supply = supply);
+
+    fifo_t<8> out_fifo(.in = c.out, .out = out,
+        .supply = supply, .reset_B = reset_B);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+_sadc_hs c; 
--- a/test/unit_tests/sadc_hs/test.prsim
+++ b/test/unit_tests/sadc_hs/test.prsim
@@ -0,0 +1,72 @@
+watchall
+
+set c.reset_B 0
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+
+set c.out.a 0
+
+
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set c.reset_B 1
+cycle
+system "echo '[] Reset finished'"
+status X
+
+
+system "echo '[] Setting all in reqs high'"
+set c.in[0].r 1
+set c.in[1].r 1
+set c.in[2].r 1
+set c.in[3].r 1
+cycle
+
+assert c.in[0].a 1
+assert c.in[1].a 1
+assert c.in[2].a 1
+assert c.in[3].a 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+cycle
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle
--- a/test/unit_tests/texel_dualcore_glue/netlist.v
+++ b/test/unit_tests/texel_dualcore_glue/netlist.v
--- a/test/unit_tests/texel_dualcore_glue/netlist_clean.v
+++ b/test/unit_tests/texel_dualcore_glue/netlist_clean.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/texeldualcoreglue/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/texeldualcoreglue/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/texeldualcoreglue/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/texeldualcoreglue/netlist/verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist/verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist/verilog.v
@@ -0,0 +1,17 @@
+module tmpl_0_0dataflow__neuro_0_0andtree_33_4(Iin0 , Iin1 , Iin2 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   output out;
+
+// -- signals ---
+   wire Iin2 ;
+   wire Iin0 ;
+   wire Iin1 ;
+   wire out ;
+
+// --- instances
+AND3_X1 Iand3s0  (.y(out), .a(Iin0 ), .b(Iin1 ), .c(Iin2 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist/verilog.v
@@ -0,0 +1,23 @@
+module tmpl_0_0dataflow__neuro_0_0andtree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   output out;
+
+// -- signals ---
+   wire Iin1 ;
+   wire Itmp4 ;
+   wire Iin0 ;
+   wire Iin3 ;
+   wire out ;
+   wire Itmp5 ;
+   wire Iin2 ;
+
+// --- instances
+AND2_X1 Iand2s0  (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s1  (.y(Itmp5 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s2  (.y(out), .a(Itmp4 ), .b(Itmp5 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist/verilog.v
@@ -0,0 +1,25 @@
+module tmpl_0_0dataflow__neuro_0_0andtree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   output out;
+
+// -- signals ---
+   wire Itmp5 ;
+   wire Iin2 ;
+   wire Itmp6 ;
+   wire Iin0 ;
+   wire Iin3 ;
+   wire out ;
+   wire Iin1 ;
+   wire Iin4 ;
+
+// --- instances
+AND3_X1 Iand3s0  (.y(Itmp6 ), .a(Iin2 ), .b(Iin3 ), .c(Iin4 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s0  (.y(Itmp5 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s1  (.y(out), .a(Itmp5 ), .b(Itmp6 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist/verilog.v
@@ -0,0 +1,29 @@
+module tmpl_0_0dataflow__neuro_0_0andtree_36_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   output out;
+
+// -- signals ---
+   wire Iin3 ;
+   wire Itmp6 ;
+   wire Iin2 ;
+   wire Itmp8 ;
+   wire Iin5 ;
+   wire Iin4 ;
+   wire Itmp7 ;
+   wire out ;
+   wire Iin1 ;
+   wire Iin0 ;
+
+// --- instances
+AND3_X1 Iand3s0  (.y(out), .a(Itmp6 ), .b(Itmp7 ), .c(Itmp8 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s0  (.y(Itmp6 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s1  (.y(Itmp7 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s2  (.y(Itmp8 ), .a(Iin4 ), .b(Iin5 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist/verilog.v
@@ -0,0 +1,41 @@
+module tmpl_0_0dataflow__neuro_0_0andtree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   output out;
+
+// -- signals ---
+   wire Itmp12 ;
+   wire Iin0 ;
+   wire Iin1 ;
+   wire Iin7 ;
+   wire Iin3 ;
+   wire Iin8 ;
+   wire Itmp9 ;
+   wire Iin4 ;
+   wire Itmp14 ;
+   wire Itmp13 ;
+   wire out ;
+   wire Itmp11 ;
+   wire Iin6 ;
+   wire Iin5 ;
+   wire Iin2 ;
+   wire Itmp10 ;
+
+// --- instances
+AND3_X1 Iand3s0  (.y(Itmp12 ), .a(Iin6 ), .b(Iin7 ), .c(Iin8 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s0  (.y(Itmp9 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s1  (.y(Itmp10 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s2  (.y(Itmp11 ), .a(Iin4 ), .b(Iin5 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s3  (.y(Itmp13 ), .a(Itmp9 ), .b(Itmp10 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s4  (.y(Itmp14 ), .a(Itmp11 ), .b(Itmp12 ), .vdd(vdd), .vss(vss));
+AND2_X1 Iand2s5  (.y(out), .a(Itmp13 ), .b(Itmp14 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/verilog.v
@@ -0,0 +1,137 @@
+module tmpl_0_0dataflow__neuro_0_0append_329_72_72_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Isupply_vss , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   input Iin_d_d13_d0 ;
+   input Iin_d_d13_d1 ;
+   input Iin_d_d14_d0 ;
+   input Iin_d_d14_d1 ;
+   input Iin_d_d15_d0 ;
+   input Iin_d_d15_d1 ;
+   input Iin_d_d16_d0 ;
+   input Iin_d_d16_d1 ;
+   input Iin_d_d17_d0 ;
+   input Iin_d_d17_d1 ;
+   input Iin_d_d18_d0 ;
+   input Iin_d_d18_d1 ;
+   input Iin_d_d19_d0 ;
+   input Iin_d_d19_d1 ;
+   input Iin_d_d20_d0 ;
+   input Iin_d_d20_d1 ;
+   input Iin_d_d21_d0 ;
+   input Iin_d_d21_d1 ;
+   input Iin_d_d22_d0 ;
+   input Iin_d_d22_d1 ;
+   input Iin_d_d23_d0 ;
+   input Iin_d_d23_d1 ;
+   input Iin_d_d24_d0 ;
+   input Iin_d_d24_d1 ;
+   input Iin_d_d25_d0 ;
+   input Iin_d_d25_d1 ;
+   input Iin_d_d26_d0 ;
+   input Iin_d_d26_d1 ;
+   input Iin_d_d27_d0 ;
+   input Iin_d_d27_d1 ;
+   input Iin_d_d28_d0 ;
+   input Iin_d_d28_d1 ;
+   
+   
+   
+   input Isupply_vss ;
+
+// -- signals ---
+   output Iout_d_d29_d0 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d26_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d13_d1 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d16_d1 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d30_d0 ;
+   wire Iin_d_d25_d0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d5_d0 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d7_d0 ;
+   wire Isupply_vss ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d12_d1 ;
+   wire Isb_in ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d7_d1 ;
+
+// --- instances
+TIELO_X1 Itielows0  (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows1  (.y(Iout_d_d30_d0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_329_4 Iin_val  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_32_4 Isb  (.in(Isb_in ), .Iout0 (Iout_d_d29_d0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/verilog.v
@@ -0,0 +1,142 @@
+module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Isupply_vss , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   input Iin_d_d13_d0 ;
+   input Iin_d_d13_d1 ;
+   input Iin_d_d14_d0 ;
+   input Iin_d_d14_d1 ;
+   input Iin_d_d15_d0 ;
+   input Iin_d_d15_d1 ;
+   input Iin_d_d16_d0 ;
+   input Iin_d_d16_d1 ;
+   input Iin_d_d17_d0 ;
+   input Iin_d_d17_d1 ;
+   input Iin_d_d18_d0 ;
+   input Iin_d_d18_d1 ;
+   input Iin_d_d19_d0 ;
+   input Iin_d_d19_d1 ;
+   input Iin_d_d20_d0 ;
+   input Iin_d_d20_d1 ;
+   input Iin_d_d21_d0 ;
+   input Iin_d_d21_d1 ;
+   input Iin_d_d22_d0 ;
+   input Iin_d_d22_d1 ;
+   input Iin_d_d23_d0 ;
+   input Iin_d_d23_d1 ;
+   input Iin_d_d24_d0 ;
+   input Iin_d_d24_d1 ;
+   input Iin_d_d25_d0 ;
+   input Iin_d_d25_d1 ;
+   input Iin_d_d26_d0 ;
+   input Iin_d_d26_d1 ;
+   input Iin_d_d27_d0 ;
+   input Iin_d_d27_d1 ;
+   input Iin_d_d28_d0 ;
+   input Iin_d_d28_d1 ;
+   input Iin_d_d29_d0 ;
+   input Iin_d_d29_d1 ;
+   input Iin_d_d30_d0 ;
+   input Iin_d_d30_d1 ;
+   
+   
+   input Isupply_vss ;
+
+// -- signals ---
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d5_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d25_d0 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d4_d1 ;
+   wire Isb_in ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d30_d0 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d26_d1 ;
+   output Iout_d_d31_d1 ;
+   wire Iin_d_d29_d1 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d12_d1 ;
+   output Iout_d_d31_d0 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d16_d1 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d13_d1 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d15_d0 ;
+   wire Isupply_vss ;
+
+// --- instances
+TIELO_X1 Itielows0  (.y(Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb  (.in(Isb_in ), .Iout0 (Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/verilog.v
@@ -0,0 +1,142 @@
+module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Isupply_vss , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   input Iin_d_d13_d0 ;
+   input Iin_d_d13_d1 ;
+   input Iin_d_d14_d0 ;
+   input Iin_d_d14_d1 ;
+   input Iin_d_d15_d0 ;
+   input Iin_d_d15_d1 ;
+   input Iin_d_d16_d0 ;
+   input Iin_d_d16_d1 ;
+   input Iin_d_d17_d0 ;
+   input Iin_d_d17_d1 ;
+   input Iin_d_d18_d0 ;
+   input Iin_d_d18_d1 ;
+   input Iin_d_d19_d0 ;
+   input Iin_d_d19_d1 ;
+   input Iin_d_d20_d0 ;
+   input Iin_d_d20_d1 ;
+   input Iin_d_d21_d0 ;
+   input Iin_d_d21_d1 ;
+   input Iin_d_d22_d0 ;
+   input Iin_d_d22_d1 ;
+   input Iin_d_d23_d0 ;
+   input Iin_d_d23_d1 ;
+   input Iin_d_d24_d0 ;
+   input Iin_d_d24_d1 ;
+   input Iin_d_d25_d0 ;
+   input Iin_d_d25_d1 ;
+   input Iin_d_d26_d0 ;
+   input Iin_d_d26_d1 ;
+   input Iin_d_d27_d0 ;
+   input Iin_d_d27_d1 ;
+   input Iin_d_d28_d0 ;
+   input Iin_d_d28_d1 ;
+   input Iin_d_d29_d0 ;
+   input Iin_d_d29_d1 ;
+   input Iin_d_d30_d0 ;
+   input Iin_d_d30_d1 ;
+   
+   
+   input Isupply_vss ;
+
+// -- signals ---
+   wire Iin_d_d29_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d13_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d6_d1 ;
+   wire Isupply_vss ;
+   output Iout_d_d31_d0 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d5_d1 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d16_d1 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d26_d1 ;
+   wire Iin_d_d25_d0 ;
+   wire Iin_d_d30_d0 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d31_d1 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d3_d0 ;
+   wire Isb_in ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d10_d1 ;
+
+// --- instances
+TIELO_X1 Itielows0  (.y(Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb  (.in(Isb_in ), .Iout0 (Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v
@@ -0,0 +1,115 @@
+module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d1 , Iout_d_d9_d1 , Iout_d_d10_d1 , Iout_d_d11_d1 , Iout_d_d12_d1 , Iout_d_d13_d1 , Iout_d_d14_d1 , Iout_d_d15_d1 , Iout_d_d16_d1 , Iout_d_d17_d1 , Iout_d_d18_d1 , Iout_d_d19_d1 , Iout_d_d20_d1 , Iout_d_d21_d1 , Iout_d_d22_d1 , Iout_d_d23_d1 , Iout_d_d24_d1 , Iout_d_d25_d1 , Iout_d_d26_d1 , Iout_d_d27_d1 , Iout_d_d28_d1 , Iout_d_d29_d1 , Iout_d_d30_d1 , Isupply_vss , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Isupply_vss ;
+
+// -- signals ---
+   output Iout_d_d27_d1 ;
+   output Iout_d_d16_d1 ;
+   output Iout_d_d11_d1 ;
+   output Iout_d_d14_d1 ;
+   output Iout_d_d30_d1 ;
+   output Iout_d_d19_d1 ;
+   wire Iin_d_d5_d0 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d15_d1 ;
+   output Iout_d_d29_d1 ;
+   output Iout_d_d28_d1 ;
+   output Iout_d_d25_d1 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d9_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Isupply_vss ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d7_d1 ;
+   wire Iin_d_d6_d0 ;
+   output Iout_d_d21_d1 ;
+   wire Isb_in ;
+   output Iout_d_d10_d1 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d_d20_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d1_d0 ;
+   output Iout_d_d18_d1 ;
+   output Iout_d_d7_d0 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d13_d1 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d12_d1 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d8_d1 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d23_d1 ;
+
+// --- instances
+TIELO_X1 Itielows0  (.y(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows1  (.y(Iout_d_d8_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows2  (.y(Iout_d_d9_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows3  (.y(Iout_d_d10_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows4  (.y(Iout_d_d11_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows5  (.y(Iout_d_d12_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows6  (.y(Iout_d_d13_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows7  (.y(Iout_d_d14_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows8  (.y(Iout_d_d15_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows9  (.y(Iout_d_d16_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows10  (.y(Iout_d_d17_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows11  (.y(Iout_d_d18_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows12  (.y(Iout_d_d19_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows13  (.y(Iout_d_d20_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows14  (.y(Iout_d_d21_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows15  (.y(Iout_d_d22_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows16  (.y(Iout_d_d23_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows17  (.y(Iout_d_d24_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows18  (.y(Iout_d_d25_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows19  (.y(Iout_d_d26_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows20  (.y(Iout_d_d27_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows21  (.y(Iout_d_d28_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows22  (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
+TIELO_X1 Itielows23  (.y(Iout_d_d30_d1 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Isb  (.in(Isb_in ), .Iout0 (Iout_d_d7_d0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/verilog.v
@@ -0,0 +1,26 @@
+module tmpl_0_0dataflow__neuro_0_0arbiter__handshake(Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iout_d_d0 , Iout_a , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   
+   input Iout_a ;
+
+// -- signals ---
+   output Iout_d_d0 ;
+   wire Iin1_d_d0 ;
+   wire Iout_a ;
+   wire _y1_arb ;
+   wire _y2_arb ;
+   output Iin2_a ;
+   wire Iin2_d_d0 ;
+   output Iin1_a ;
+
+// --- instances
+A_2C_B_X1 Iack_cell1  (.y(Iin1_a ), .c1(Iout_a ), .c2(_y1_arb), .vdd(vdd), .vss(vss));
+ARBITER Iarbiter  (.a(Iin1_d_d0 ), .b(Iin2_d_d0 ), .c(Iin2_a ), .d(Iin1_a ), .y1(_y1_arb), .y2(_y2_arb), .vdd(vdd), .vss(vss));
+A_2C_B_X1 Iack_cell2  (.y(Iin2_a ), .c1(Iout_a ), .c2(_y2_arb), .vdd(vdd), .vss(vss));
+OR2_X1 Ior_cell  (.y(Iout_d_d0 ), .a(_y1_arb), .b(_y2_arb), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist/verilog.v
@@ -0,0 +1,112 @@
+module tmpl_0_0dataflow__neuro_0_0arbtree_315_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iout_d_d0 , Iout_a , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0_d_d0 ;
+   
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   input Iin3_d_d0 ;
+   
+   input Iin4_d_d0 ;
+   
+   input Iin5_d_d0 ;
+   
+   input Iin6_d_d0 ;
+   
+   input Iin7_d_d0 ;
+   
+   input Iin8_d_d0 ;
+   
+   input Iin9_d_d0 ;
+   
+   input Iin10_d_d0 ;
+   
+   input Iin11_d_d0 ;
+   
+   input Iin12_d_d0 ;
+   
+   input Iin13_d_d0 ;
+   
+   input Iin14_d_d0 ;
+   
+   
+   input Iout_a ;
+
+// -- signals ---
+   wire Iout_a ;
+   wire Iin13_d_d0 ;
+   wire Iin3_d_d0 ;
+   wire Itmp15_a ;
+   wire Itmp25_a ;
+   wire Itmp23_a ;
+   output Iin8_a ;
+   wire Iin2_d_d0 ;
+   wire Itmp28_a ;
+   wire Itmp26_a ;
+   wire Iin14_d_d0 ;
+   wire Itmp27_d_d0 ;
+   output Iin13_a ;
+   wire Itmp15_d_d0 ;
+   wire Iin1_d_d0 ;
+   wire Itmp19_a ;
+   output Iout_d_d0 ;
+   wire Itmp24_d_d0 ;
+   output Iin11_a ;
+   wire Itmp16_d_d0 ;
+   wire Itmp17_a ;
+   wire Itmp23_d_d0 ;
+   wire Itmp21_d_d0 ;
+   output Iin4_a ;
+   output Iin14_a ;
+   wire Itmp20_a ;
+   wire Itmp19_d_d0 ;
+   wire Iin6_d_d0 ;
+   wire Itmp24_a ;
+   wire Itmp18_d_d0 ;
+   wire Iin4_d_d0 ;
+   output Iin9_a ;
+   wire Iin5_d_d0 ;
+   wire Iin12_d_d0 ;
+   output Iin3_a ;
+   output Iin2_a ;
+   wire Itmp21_a ;
+   output Iin1_a ;
+   wire Itmp28_d_d0 ;
+   wire Itmp27_a ;
+   wire Itmp17_d_d0 ;
+   output Iin0_a ;
+   output Iin5_a ;
+   wire Iin10_d_d0 ;
+   output Iin7_a ;
+   wire Iin0_d_d0 ;
+   output Iin10_a ;
+   wire Iin11_d_d0 ;
+   output Iin6_a ;
+   wire Itmp18_a ;
+   wire Itmp25_d_d0 ;
+   wire Itmp20_d_d0 ;
+   wire Iin7_d_d0 ;
+   wire Itmp16_a ;
+   output Iin12_a ;
+   wire Iin9_d_d0 ;
+   wire Iin8_d_d0 ;
+   wire Itmp26_d_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0  (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp15_d_d0 ), .Iout_a (Itmp15_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1  (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp16_d_d0 ), .Iout_a (Itmp16_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2  (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp17_d_d0 ), .Iout_a (Itmp17_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3  (.Iin1_d_d0 (Iin6_d_d0 ), .Iin1_a (Iin6_a ), .Iin2_d_d0 (Iin7_d_d0 ), .Iin2_a (Iin7_a ), .Iout_d_d0 (Itmp18_d_d0 ), .Iout_a (Itmp18_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4  (.Iin1_d_d0 (Iin8_d_d0 ), .Iin1_a (Iin8_a ), .Iin2_d_d0 (Iin9_d_d0 ), .Iin2_a (Iin9_a ), .Iout_d_d0 (Itmp19_d_d0 ), .Iout_a (Itmp19_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs5  (.Iin1_d_d0 (Iin10_d_d0 ), .Iin1_a (Iin10_a ), .Iin2_d_d0 (Iin11_d_d0 ), .Iin2_a (Iin11_a ), .Iout_d_d0 (Itmp20_d_d0 ), .Iout_a (Itmp20_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs6  (.Iin1_d_d0 (Iin12_d_d0 ), .Iin1_a (Iin12_a ), .Iin2_d_d0 (Iin13_d_d0 ), .Iin2_a (Iin13_a ), .Iout_d_d0 (Itmp21_d_d0 ), .Iout_a (Itmp21_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs7  (.Iin1_d_d0 (Itmp15_d_d0 ), .Iin1_a (Itmp15_a ), .Iin2_d_d0 (Itmp16_d_d0 ), .Iin2_a (Itmp16_a ), .Iout_d_d0 (Itmp23_d_d0 ), .Iout_a (Itmp23_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs8  (.Iin1_d_d0 (Itmp17_d_d0 ), .Iin1_a (Itmp17_a ), .Iin2_d_d0 (Itmp18_d_d0 ), .Iin2_a (Itmp18_a ), .Iout_d_d0 (Itmp24_d_d0 ), .Iout_a (Itmp24_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs9  (.Iin1_d_d0 (Itmp19_d_d0 ), .Iin1_a (Itmp19_a ), .Iin2_d_d0 (Itmp20_d_d0 ), .Iin2_a (Itmp20_a ), .Iout_d_d0 (Itmp25_d_d0 ), .Iout_a (Itmp25_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs10  (.Iin1_d_d0 (Itmp21_d_d0 ), .Iin1_a (Itmp21_a ), .Iin2_d_d0 (Iin14_d_d0 ), .Iin2_a (Iin14_a ), .Iout_d_d0 (Itmp26_d_d0 ), .Iout_a (Itmp26_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs11  (.Iin1_d_d0 (Itmp23_d_d0 ), .Iin1_a (Itmp23_a ), .Iin2_d_d0 (Itmp24_d_d0 ), .Iin2_a (Itmp24_a ), .Iout_d_d0 (Itmp27_d_d0 ), .Iout_a (Itmp27_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs12  (.Iin1_d_d0 (Itmp25_d_d0 ), .Iin1_a (Itmp25_a ), .Iin2_d_d0 (Itmp26_d_d0 ), .Iin2_a (Itmp26_a ), .Iout_d_d0 (Itmp28_d_d0 ), .Iout_a (Itmp28_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs13  (.Iin1_d_d0 (Itmp27_d_d0 ), .Iin1_a (Itmp27_a ), .Iin2_d_d0 (Itmp28_d_d0 ), .Iin2_a (Itmp28_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist/verilog.v
@@ -0,0 +1,49 @@
+module tmpl_0_0dataflow__neuro_0_0arbtree_36_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iout_d_d0 , Iout_a , vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0_d_d0 ;
+   
+   input Iin1_d_d0 ;
+   
+   input Iin2_d_d0 ;
+   
+   input Iin3_d_d0 ;
+   
+   input Iin4_d_d0 ;
+   
+   input Iin5_d_d0 ;
+   
+   
+   input Iout_a ;
+
+// -- signals ---
+   wire Iin1_d_d0 ;
+   wire Iin2_d_d0 ;
+   wire Iin0_d_d0 ;
+   output Iin0_a ;
+   wire Iin3_d_d0 ;
+   output Iin4_a ;
+   wire Itmp7_d_d0 ;
+   wire Iout_a ;
+   wire Itmp10_a ;
+   wire Itmp9_d_d0 ;
+   output Iin3_a ;
+   wire Itmp6_a ;
+   wire Itmp9_a ;
+   wire Iin5_d_d0 ;
+   wire Itmp7_a ;
+   output Iout_d_d0 ;
+   output Iin5_a ;
+   output Iin1_a ;
+   wire Itmp10_d_d0 ;
+   output Iin2_a ;
+   wire Iin4_d_d0 ;
+   wire Itmp6_d_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0  (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp6_d_d0 ), .Iout_a (Itmp6_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1  (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp7_d_d0 ), .Iout_a (Itmp7_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2  (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp10_d_d0 ), .Iout_a (Itmp10_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3  (.Iin1_d_d0 (Itmp6_d_d0 ), .Iin1_a (Itmp6_a ), .Iin2_d_d0 (Itmp7_d_d0 ), .Iin2_a (Itmp7_a ), .Iout_d_d0 (Itmp9_d_d0 ), .Iout_a (Itmp9_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4  (.Iin1_d_d0 (Itmp9_d_d0 ), .Iin1_a (Itmp9_a ), .Iin2_d_d0 (Itmp10_d_d0 ), .Iin2_a (Itmp10_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist/verilog.v
@@ -0,0 +1,373 @@
+module tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4(Iin_d0 , Iin_d1 , Iin_d2 , Iin_d3 , Iin_d4 , Iin_d5 , Iin_d6 , Iin_d7 , Iin_d8 , Iin_d9 , Iin_d10 , Iin_d11 , Iin_d12 , Iin_d13 , Iin_d14 , Iin_d15 , Iin_d16 , Iin_d17 , Iin_d18 , Iin_d19 , Iin_d20 , Iin_d21 , Iin_d22 , Iin_d23 , Iin_d24 , Iin_d25 , Iin_d26 , Iin_d27 , Iin_d28 , Iin_d29 , Iin_d30 , Iin_d31 , Iin_r , Iin_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Iout_a , Iout_v , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , Idly_cfg20 , Idly_cfg21 , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d0 ;
+   input Iin_d1 ;
+   input Iin_d2 ;
+   input Iin_d3 ;
+   input Iin_d4 ;
+   input Iin_d5 ;
+   input Iin_d6 ;
+   input Iin_d7 ;
+   input Iin_d8 ;
+   input Iin_d9 ;
+   input Iin_d10 ;
+   input Iin_d11 ;
+   input Iin_d12 ;
+   input Iin_d13 ;
+   input Iin_d14 ;
+   input Iin_d15 ;
+   input Iin_d16 ;
+   input Iin_d17 ;
+   input Iin_d18 ;
+   input Iin_d19 ;
+   input Iin_d20 ;
+   input Iin_d21 ;
+   input Iin_d22 ;
+   input Iin_d23 ;
+   input Iin_d24 ;
+   input Iin_d25 ;
+   input Iin_d26 ;
+   input Iin_d27 ;
+   input Iin_d28 ;
+   input Iin_d29 ;
+   input Iin_d30 ;
+   input Iin_d31 ;
+   input Iin_r ;
+   
+   
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+   
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+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input Idly_cfg0 ;
+   input Idly_cfg1 ;
+   input Idly_cfg2 ;
+   input Idly_cfg3 ;
+   input Idly_cfg20 ;
+   input Idly_cfg21 ;
+   input reset_B;
+
+// -- signals ---
+   output Iout_d_d14_d1 ;
+   wire Iin_d4 ;
+   wire I_inB11 ;
+   wire Iin_d25 ;
+   wire _en ;
+   wire I_inB9 ;
+   wire Iin_d13 ;
+   output Iout_d_d23_d1 ;
+   wire I_inB21 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d21_d1 ;
+   output Iout_d_d0_d0 ;
+   wire Iin_d22 ;
+   output Iout_d_d14_d0 ;
+   output Iout_d_d26_d0 ;
+   output Iout_d_d28_d1 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d12_d1 ;
+   wire Idly_cfg21 ;
+   wire Iin_d3 ;
+   wire Iin_d9 ;
+   wire I_inB19 ;
+   output Iout_d_d2_d1 ;
+   wire I_inB18 ;
+   wire I_inB24 ;
+   wire Iin_d10 ;
+   output Iout_d_d19_d0 ;
+   output Iin_a ;
+   wire Iin_d8 ;
+   wire I_inB14 ;
+   wire I_inB15 ;
+   wire Iin_d2 ;
+   output Iout_d_d30_d1 ;
+   output Iout_d_d16_d1 ;
+   wire Idly_cfg3 ;
+   wire Iin_d14 ;
+   wire Iin_d0 ;
+   output Iout_d_d22_d0 ;
+   output Iout_d_d23_d0 ;
+   wire I_inB17 ;
+   wire I_inB22 ;
+   wire Iin_d20 ;
+   output Iout_d_d22_d1 ;
+   wire reset_B;
+   wire I_inB13 ;
+   output Iout_d_d18_d1 ;
+   wire _reqX ;
+   wire I_inB25 ;
+   wire I_inB27 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d12_d0 ;
+   wire Idly_cfg2 ;
+   wire I_inB7 ;
+   wire Iin_d23 ;
+   output Iout_d_d13_d0 ;
+   wire I_inB16 ;
+   output Iout_d_d25_d0 ;
+   output Iout_d_d20_d1 ;
+   wire Idly_cfg1 ;
+   wire I_inB26 ;
+   wire Iin_d17 ;
+   wire Iin_d19 ;
+   wire I_inB30 ;
+   output Iout_d_d29_d0 ;
+   output Iout_d_d8_d1 ;
+   wire Idly_cfg0 ;
+   wire Idly_cfg20 ;
+   wire I_inB20 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d13_d1 ;
+   wire _out_a_B ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d0_d1 ;
+   wire Iout_v ;
+   output Iout_d_d4_d0 ;
+   wire I_reqXX0 ;
+   wire Iin_r ;
+   wire Iin_d21 ;
+   output Iout_d_d1_d0 ;
+   wire Idly2_out ;
+   wire I_inB28 ;
+   output Iout_d_d31_d0 ;
+   output Iout_d_d4_d1 ;
+   output Iout_d_d11_d1 ;
+   output Iout_d_d25_d1 ;
+   wire I_inB5 ;
+   wire I_reset_BXX0 ;
+   wire _req_slowfall ;
+   wire Iin_d26 ;
+   wire I_inB8 ;
+   wire Iin_d24 ;
+   output Iout_d_d16_d0 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d17_d1 ;
+   wire Iin_d5 ;
+   wire Iin_d11 ;
+   wire _req ;
+   wire Iin_d1 ;
+   wire I_inB4 ;
+   wire Iin_d27 ;
+   output Iout_d_d30_d0 ;
+   wire Iin_d18 ;
+   output Iout_d_d7_d1 ;
+   wire If_buf_func31_c2 ;
+   output Iout_d_d10_d1 ;
+   wire I_inB29 ;
+   wire _reset_BX ;
+   output Iout_d_d24_d0 ;
+   wire I_inB2 ;
+   wire I_inB31 ;
+   output Iout_d_d20_d0 ;
+   wire I_inB1 ;
+   output Iout_d_d27_d1 ;
+   wire I_inB12 ;
+   wire Iin_d31 ;
+   output Iout_d_d5_d1 ;
+   wire Iin_d15 ;
+   wire I_inB6 ;
+   wire I_inB10 ;
+   output Iout_d_d9_d0 ;
+   wire Iin_d29 ;
+   output Iout_d_d28_d0 ;
+   output Iout_d_d31_d1 ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d15_d0 ;
+   output Iout_d_d27_d0 ;
+   output Iout_d_d6_d1 ;
+   wire Iin_d6 ;
+   output Iout_d_d10_d0 ;
+   output Iout_d_d21_d0 ;
+   wire I_inB3 ;
+   output Iout_d_d8_d0 ;
+   wire Ien_buf_out0 ;
+   wire Iin_d7 ;
+   wire I_inB23 ;
+   output Iout_d_d19_d1 ;
+   wire I_inB0 ;
+   output Iout_d_d18_d0 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d12 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d15_d1 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d1_d1 ;
+   wire Iout_a ;
+   wire Iin_d16 ;
+   wire Iin_d28 ;
+   wire Iin_d30 ;
+   output Iout_d_d17_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(_req_slowfall), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly  (.out(_req), .in(Iin_r ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0delayprog_32_4 Idly2  (.out(Idly2_out ), .in(_reqX), .Is0 (Idly_cfg20 ), .Is1 (Idly_cfg21 ), .vdd(vdd), .vss(vss));
+BUF_X4 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs0  (.y(I_inB0 ), .a(Iin_d0 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs1  (.y(I_inB1 ), .a(Iin_d1 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs2  (.y(I_inB2 ), .a(Iin_d2 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs3  (.y(I_inB3 ), .a(Iin_d3 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs4  (.y(I_inB4 ), .a(Iin_d4 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs5  (.y(I_inB5 ), .a(Iin_d5 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs6  (.y(I_inB6 ), .a(Iin_d6 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs7  (.y(I_inB7 ), .a(Iin_d7 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs8  (.y(I_inB8 ), .a(Iin_d8 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs9  (.y(I_inB9 ), .a(Iin_d9 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs10  (.y(I_inB10 ), .a(Iin_d10 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs11  (.y(I_inB11 ), .a(Iin_d11 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs12  (.y(I_inB12 ), .a(Iin_d12 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs13  (.y(I_inB13 ), .a(Iin_d13 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs14  (.y(I_inB14 ), .a(Iin_d14 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs15  (.y(I_inB15 ), .a(Iin_d15 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs16  (.y(I_inB16 ), .a(Iin_d16 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs17  (.y(I_inB17 ), .a(Iin_d17 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs18  (.y(I_inB18 ), .a(Iin_d18 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs19  (.y(I_inB19 ), .a(Iin_d19 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs20  (.y(I_inB20 ), .a(Iin_d20 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs21  (.y(I_inB21 ), .a(Iin_d21 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs22  (.y(I_inB22 ), .a(Iin_d22 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs23  (.y(I_inB23 ), .a(Iin_d23 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs24  (.y(I_inB24 ), .a(Iin_d24 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs25  (.y(I_inB25 ), .a(Iin_d25 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs26  (.y(I_inB26 ), .a(Iin_d26 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs27  (.y(I_inB27 ), .a(Iin_d27 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs28  (.y(I_inB28 ), .a(Iin_d28 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs29  (.y(I_inB29 ), .a(Iin_d29 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs30  (.y(I_inB30 ), .a(Iin_d30 ), .vdd(vdd), .vss(vss));
+INV_X1 Iinput_invs31  (.y(I_inB31 ), .a(Iin_d31 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (If_buf_func31_c2 ), .vdd(vdd), .vss(vss));
+OR2_X1 Ireq_dly_or  (.y(_req_slowfall), .a(_reqX), .b(Idly2_out ), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireq_bufarray  (.in(_reqX), .Iout0 (I_reqXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Ireq_buf  (.y(_reqX), .a(_req), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB0 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB1 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB2 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB3 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB4 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB5 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB6 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func7  (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB7 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func8  (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB8 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func9  (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB9 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func10  (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB10 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func11  (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB11 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func12  (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB12 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func13  (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB13 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func14  (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB14 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func15  (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB15 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func16  (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB16 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func17  (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB17 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func18  (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB18 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func19  (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB19 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func20  (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB20 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func21  (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB21 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func22  (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB22 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func23  (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB23 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func24  (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB24 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func25  (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB25 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func26  (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB26 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func27  (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB27 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func28  (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB28 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func29  (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB29 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func30  (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB30 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 If_buf_func31  (.y(Iout_d_d31_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB31 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d0 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d1 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d2 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d3 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d4 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d5 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d6 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func7  (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d7 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func8  (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d8 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func9  (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d9 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func10  (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d10 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func11  (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d11 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func12  (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d12 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func13  (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d13 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func14  (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d14 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func15  (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d15 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func16  (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d16 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func17  (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d17 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func18  (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d18 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func19  (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d19 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func20  (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d20 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func21  (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d21 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func22  (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d22 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func23  (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d23 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func24  (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d24 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func25  (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d25 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func26  (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d26 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func27  (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d27 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func28  (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d28 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func29  (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d29 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func30  (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d30 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C2N_RB_X4 It_buf_func31  (.y(Iout_d_d31_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d31 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/verilog.v
@@ -0,0 +1,164 @@
+module tmpl_0_0dataflow__neuro_0_0buffer_313_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   output Iout_d_d2_d1 ;
+   output Iout_d_d7_d1 ;
+   output Iin_v ;
+   wire Ien_buf_out0 ;
+   wire Iin_d_d0_d0 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d6_d1 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d4_d1 ;
+   output Iout_d_d0_d1 ;
+   wire Iout_a ;
+   output Iout_d_d2_d0 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d9_d1 ;
+   wire _in_v ;
+   wire I_reset_BXX0 ;
+   output Iout_d_d8_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d3_d0 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d12_d0 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d6_d0 ;
+   wire reset_B;
+   output Iout_d_d1_d0 ;
+   output Iout_d_d0_d0 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d4_d1 ;
+   wire Iin_d_d9_d0 ;
+   output Iout_d_d10_d1 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d5_d1 ;
+   wire _out_a_B ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d1_d0 ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d10_d0 ;
+   output Iout_d_d4_d0 ;
+   wire Iin_d_d6_d1 ;
+   output Iin_a ;
+   output Iout_d_d8_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire _reset_BX ;
+   wire Iin_d_d11_d0 ;
+   wire Iout_v ;
+   output Iout_d_d11_d1 ;
+   wire Iin_d_d0_d1 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d1_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d6_d0 ;
+   wire _en ;
+   wire Iin_d_d5_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_313_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func7  (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func8  (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func9  (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func10  (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func11  (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func12  (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func7  (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func8  (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func9  (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func10  (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func11  (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func12  (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/verilog.v
@@ -0,0 +1,324 @@
+module tmpl_0_0dataflow__neuro_0_0buffer_329_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   input Iin_d_d13_d0 ;
+   input Iin_d_d13_d1 ;
+   input Iin_d_d14_d0 ;
+   input Iin_d_d14_d1 ;
+   input Iin_d_d15_d0 ;
+   input Iin_d_d15_d1 ;
+   input Iin_d_d16_d0 ;
+   input Iin_d_d16_d1 ;
+   input Iin_d_d17_d0 ;
+   input Iin_d_d17_d1 ;
+   input Iin_d_d18_d0 ;
+   input Iin_d_d18_d1 ;
+   input Iin_d_d19_d0 ;
+   input Iin_d_d19_d1 ;
+   input Iin_d_d20_d0 ;
+   input Iin_d_d20_d1 ;
+   input Iin_d_d21_d0 ;
+   input Iin_d_d21_d1 ;
+   input Iin_d_d22_d0 ;
+   input Iin_d_d22_d1 ;
+   input Iin_d_d23_d0 ;
+   input Iin_d_d23_d1 ;
+   input Iin_d_d24_d0 ;
+   input Iin_d_d24_d1 ;
+   input Iin_d_d25_d0 ;
+   input Iin_d_d25_d1 ;
+   input Iin_d_d26_d0 ;
+   input Iin_d_d26_d1 ;
+   input Iin_d_d27_d0 ;
+   input Iin_d_d27_d1 ;
+   input Iin_d_d28_d0 ;
+   input Iin_d_d28_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   output Iout_d_d18_d0 ;
+   output Iout_d_d19_d1 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d15_d1 ;
+   output Iout_d_d15_d1 ;
+   output Iout_d_d2_d1 ;
+   wire Iin_d_d26_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d17_d1 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d0_d0 ;
+   output Iin_v ;
+   output Iout_d_d27_d0 ;
+   output Iout_d_d16_d0 ;
+   output Iout_d_d0_d0 ;
+   output Iout_d_d9_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d15_d0 ;
+   output Iin_a ;
+   output Iout_d_d1_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d7_d0 ;
+   wire Iin_d_d13_d1 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d16_d0 ;
+   output Iout_d_d11_d1 ;
+   output Iout_d_d16_d1 ;
+   wire Ien_buf_out0 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d12_d0 ;
+   output Iout_d_d6_d1 ;
+   wire I_reset_BXX0 ;
+   wire _out_a_B ;
+   output Iout_d_d26_d1 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d22_d0 ;
+   output Iout_d_d10_d0 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d19_d1 ;
+   output Iout_d_d8_d1 ;
+   output Iout_d_d4_d1 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d1_d0 ;
+   wire _in_v ;
+   wire _en ;
+   output Iout_d_d20_d0 ;
+   output Iout_d_d14_d0 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d0_d1 ;
+   wire Iin_d_d16_d1 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d13_d1 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d10_d0 ;
+   wire Iout_a ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d26_d0 ;
+   output Iout_d_d11_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d23_d0 ;
+   output Iout_d_d23_d0 ;
+   output Iout_d_d17_d0 ;
+   wire Iout_v ;
+   output Iout_d_d15_d0 ;
+   output Iout_d_d18_d1 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d4_d1 ;
+   output Iout_d_d24_d0 ;
+   output Iout_d_d23_d1 ;
+   output Iout_d_d7_d1 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d5_d0 ;
+   output Iout_d_d19_d0 ;
+   output Iout_d_d14_d1 ;
+   wire Iin_d_d25_d0 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire _reset_BX ;
+   output Iout_d_d28_d0 ;
+   output Iout_d_d27_d1 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d5_d1 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d2_d0 ;
+   output Iout_d_d25_d0 ;
+   output Iout_d_d25_d1 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d21_d1 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d6_d0 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d3_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d9_d0 ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d22_d1 ;
+   wire reset_B;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d17_d1 ;
+   output Iout_d_d21_d0 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d7_d0 ;
+   output Iout_d_d28_d1 ;
+   output Iout_d_d20_d1 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d1_d1 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_329_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func7  (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func8  (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func9  (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func10  (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func11  (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func12  (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func13  (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func14  (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func15  (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func16  (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func17  (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func18  (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func19  (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func20  (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func21  (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func22  (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func23  (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func24  (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func25  (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func26  (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func27  (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func28  (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func7  (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func8  (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func9  (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func10  (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func11  (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func12  (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func13  (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func14  (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func15  (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func16  (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func17  (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func18  (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func19  (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func20  (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func21  (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func22  (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func23  (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func24  (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func25  (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func26  (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func27  (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func28  (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist/verilog.v
@@ -0,0 +1,334 @@
+module tmpl_0_0dataflow__neuro_0_0buffer_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   input Iin_d_d13_d0 ;
+   input Iin_d_d13_d1 ;
+   input Iin_d_d14_d0 ;
+   input Iin_d_d14_d1 ;
+   input Iin_d_d15_d0 ;
+   input Iin_d_d15_d1 ;
+   input Iin_d_d16_d0 ;
+   input Iin_d_d16_d1 ;
+   input Iin_d_d17_d0 ;
+   input Iin_d_d17_d1 ;
+   input Iin_d_d18_d0 ;
+   input Iin_d_d18_d1 ;
+   input Iin_d_d19_d0 ;
+   input Iin_d_d19_d1 ;
+   input Iin_d_d20_d0 ;
+   input Iin_d_d20_d1 ;
+   input Iin_d_d21_d0 ;
+   input Iin_d_d21_d1 ;
+   input Iin_d_d22_d0 ;
+   input Iin_d_d22_d1 ;
+   input Iin_d_d23_d0 ;
+   input Iin_d_d23_d1 ;
+   input Iin_d_d24_d0 ;
+   input Iin_d_d24_d1 ;
+   input Iin_d_d25_d0 ;
+   input Iin_d_d25_d1 ;
+   input Iin_d_d26_d0 ;
+   input Iin_d_d26_d1 ;
+   input Iin_d_d27_d0 ;
+   input Iin_d_d27_d1 ;
+   input Iin_d_d28_d0 ;
+   input Iin_d_d28_d1 ;
+   input Iin_d_d29_d0 ;
+   input Iin_d_d29_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   wire Iin_d_d15_d1 ;
+   output Iout_d_d14_d1 ;
+   output Iout_d_d0_d0 ;
+   output Iout_d_d17_d0 ;
+   output Iout_d_d24_d0 ;
+   output Iout_d_d27_d0 ;
+   output Iout_d_d29_d0 ;
+   output Iout_d_d2_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d21_d0 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d19_d0 ;
+   wire Iin_d_d12_d0 ;
+   output Iout_d_d18_d1 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d14_d1 ;
+   wire reset_B;
+   output Iout_d_d5_d0 ;
+   wire Iin_d_d16_d1 ;
+   wire Iin_d_d26_d1 ;
+   output Iout_d_d16_d1 ;
+   output Iout_d_d28_d1 ;
+   output Iout_d_d15_d0 ;
+   output Iout_d_d13_d1 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d28_d0 ;
+   output Iout_d_d15_d1 ;
+   output Iout_d_d21_d1 ;
+   output Iout_d_d22_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d9_d0 ;
+   output Iout_d_d20_d1 ;
+   wire Iin_d_d23_d1 ;
+   output Iout_d_d9_d0 ;
+   wire _reset_BX ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d12_d1 ;
+   output Iout_d_d23_d0 ;
+   wire Iout_a ;
+   wire Iin_d_d25_d0 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d25_d0 ;
+   wire Iout_v ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d13_d1 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d28_d1 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d14_d0 ;
+   output Iout_d_d20_d0 ;
+   output Iout_d_d21_d0 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d26_d0 ;
+   output Iout_d_d28_d0 ;
+   wire Iin_d_d18_d1 ;
+   wire _out_a_B ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d13_d0 ;
+   output Iout_d_d23_d1 ;
+   output Iout_d_d6_d0 ;
+   wire Iin_d_d7_d1 ;
+   wire _in_v ;
+   wire Iin_d_d22_d1 ;
+   output Iout_d_d1_d0 ;
+   output Iout_d_d10_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d16_d0 ;
+   output Iout_d_d4_d1 ;
+   output Iout_d_d11_d1 ;
+   output Iout_d_d16_d0 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d17_d0 ;
+   output Iout_d_d12_d1 ;
+   output Iin_v ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d22_d0 ;
+   output Iin_a ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d24_d0 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d4_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d19_d0 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d18_d0 ;
+   wire _en ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d20_d1 ;
+   output Iout_d_d10_d0 ;
+   wire Iin_d_d14_d0 ;
+   output Iout_d_d26_d0 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d7_d1 ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d0_d1 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d8_d0 ;
+   wire I_reset_BXX0 ;
+   output Iout_d_d27_d1 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d29_d1 ;
+   output Iout_d_d25_d1 ;
+   wire I_out_a_BX0 ;
+   wire Iin_d_d23_d0 ;
+   output Iout_d_d11_d0 ;
+   wire Ien_buf_out0 ;
+   output Iout_d_d8_d1 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d12_d0 ;
+   output Iout_d_d13_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_330_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func7  (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func8  (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func9  (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func10  (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func11  (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func12  (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func13  (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func14  (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func15  (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func16  (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func17  (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func18  (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func19  (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func20  (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func21  (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func22  (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func23  (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func24  (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func25  (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func26  (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func27  (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func28  (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func29  (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func7  (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func8  (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func9  (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func10  (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func11  (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func12  (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func13  (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func14  (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func15  (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func16  (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func17  (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func18  (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func19  (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func20  (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func21  (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func22  (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func23  (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func24  (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func25  (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func26  (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func27  (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func28  (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func29  (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/verilog.v
@@ -0,0 +1,344 @@
+module tmpl_0_0dataflow__neuro_0_0buffer_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   input Iin_d_d13_d0 ;
+   input Iin_d_d13_d1 ;
+   input Iin_d_d14_d0 ;
+   input Iin_d_d14_d1 ;
+   input Iin_d_d15_d0 ;
+   input Iin_d_d15_d1 ;
+   input Iin_d_d16_d0 ;
+   input Iin_d_d16_d1 ;
+   input Iin_d_d17_d0 ;
+   input Iin_d_d17_d1 ;
+   input Iin_d_d18_d0 ;
+   input Iin_d_d18_d1 ;
+   input Iin_d_d19_d0 ;
+   input Iin_d_d19_d1 ;
+   input Iin_d_d20_d0 ;
+   input Iin_d_d20_d1 ;
+   input Iin_d_d21_d0 ;
+   input Iin_d_d21_d1 ;
+   input Iin_d_d22_d0 ;
+   input Iin_d_d22_d1 ;
+   input Iin_d_d23_d0 ;
+   input Iin_d_d23_d1 ;
+   input Iin_d_d24_d0 ;
+   input Iin_d_d24_d1 ;
+   input Iin_d_d25_d0 ;
+   input Iin_d_d25_d1 ;
+   input Iin_d_d26_d0 ;
+   input Iin_d_d26_d1 ;
+   input Iin_d_d27_d0 ;
+   input Iin_d_d27_d1 ;
+   input Iin_d_d28_d0 ;
+   input Iin_d_d28_d1 ;
+   input Iin_d_d29_d0 ;
+   input Iin_d_d29_d1 ;
+   input Iin_d_d30_d0 ;
+   input Iin_d_d30_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   wire _reset_BX ;
+   wire Iin_d_d0_d1 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d18_d1 ;
+   output Iout_d_d25_d0 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d24_d1 ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d1_d0 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d23_d0 ;
+   wire Iin_d_d20_d1 ;
+   output Iin_v ;
+   wire _in_v ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d0_d0 ;
+   output Iout_d_d15_d0 ;
+   output Iout_d_d16_d0 ;
+   output Iout_d_d30_d0 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d26_d1 ;
+   wire Ien_buf_out0 ;
+   wire Iin_d_d21_d0 ;
+   output Iout_d_d28_d0 ;
+   wire Iin_d_d29_d0 ;
+   output Iout_d_d11_d1 ;
+   output Iout_d_d27_d1 ;
+   output Iout_d_d21_d0 ;
+   output Iout_d_d26_d0 ;
+   wire Iin_d_d27_d0 ;
+   output Iout_d_d15_d1 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d14_d0 ;
+   wire Iin_d_d1_d0 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d28_d1 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d30_d0 ;
+   output Iout_d_d2_d1 ;
+   wire Iout_a ;
+   wire Iin_d_d14_d1 ;
+   output Iout_d_d0_d1 ;
+   output Iout_d_d20_d0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d30_d1 ;
+   output Iout_d_d20_d1 ;
+   wire Iin_d_d19_d1 ;
+   output Iout_d_d30_d1 ;
+   output Iout_d_d10_d0 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d8_d0 ;
+   wire _en ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d24_d0 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d22_d0 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d11_d0 ;
+   output Iout_d_d29_d0 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d8_d1 ;
+   wire I_reset_BXX0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d13_d1 ;
+   wire Iin_d_d29_d1 ;
+   wire Iin_d_d11_d1 ;
+   output Iout_d_d12_d0 ;
+   wire Iin_d_d28_d1 ;
+   output Iout_d_d13_d1 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d20_d0 ;
+   output Iout_d_d7_d1 ;
+   output Iin_a ;
+   wire Iin_d_d4_d1 ;
+   wire reset_B;
+   wire Iin_d_d25_d0 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d25_d1 ;
+   output Iout_d_d24_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d8_d1 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d17_d0 ;
+   wire Iin_d_d9_d0 ;
+   output Iout_d_d27_d0 ;
+   wire Iin_d_d27_d1 ;
+   output Iout_d_d16_d1 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d11_d0 ;
+   wire _out_a_B ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d19_d0 ;
+   output Iout_d_d23_d1 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d4_d1 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d18_d0 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d16_d1 ;
+   wire Iout_v ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d9_d1 ;
+   output Iout_d_d21_d1 ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d6_d0 ;
+   wire Iin_d_d18_d1 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d14_d1 ;
+   output Iout_d_d19_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_331_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func7  (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func8  (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func9  (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func10  (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func11  (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func12  (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func13  (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func14  (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func15  (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func16  (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func17  (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func18  (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func19  (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func20  (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func21  (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func22  (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func23  (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func24  (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func25  (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func26  (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func27  (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func28  (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func29  (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func30  (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func7  (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func8  (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func9  (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func10  (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func11  (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func12  (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func13  (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func14  (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func15  (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func16  (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func17  (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func18  (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func19  (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func20  (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func21  (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func22  (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func23  (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func24  (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func25  (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func26  (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func27  (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func28  (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func29  (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func30  (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/verilog.v
@@ -0,0 +1,354 @@
+module tmpl_0_0dataflow__neuro_0_0buffer_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_d_d31_d0 , Iin_d_d31_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   input Iin_d_d7_d0 ;
+   input Iin_d_d7_d1 ;
+   input Iin_d_d8_d0 ;
+   input Iin_d_d8_d1 ;
+   input Iin_d_d9_d0 ;
+   input Iin_d_d9_d1 ;
+   input Iin_d_d10_d0 ;
+   input Iin_d_d10_d1 ;
+   input Iin_d_d11_d0 ;
+   input Iin_d_d11_d1 ;
+   input Iin_d_d12_d0 ;
+   input Iin_d_d12_d1 ;
+   input Iin_d_d13_d0 ;
+   input Iin_d_d13_d1 ;
+   input Iin_d_d14_d0 ;
+   input Iin_d_d14_d1 ;
+   input Iin_d_d15_d0 ;
+   input Iin_d_d15_d1 ;
+   input Iin_d_d16_d0 ;
+   input Iin_d_d16_d1 ;
+   input Iin_d_d17_d0 ;
+   input Iin_d_d17_d1 ;
+   input Iin_d_d18_d0 ;
+   input Iin_d_d18_d1 ;
+   input Iin_d_d19_d0 ;
+   input Iin_d_d19_d1 ;
+   input Iin_d_d20_d0 ;
+   input Iin_d_d20_d1 ;
+   input Iin_d_d21_d0 ;
+   input Iin_d_d21_d1 ;
+   input Iin_d_d22_d0 ;
+   input Iin_d_d22_d1 ;
+   input Iin_d_d23_d0 ;
+   input Iin_d_d23_d1 ;
+   input Iin_d_d24_d0 ;
+   input Iin_d_d24_d1 ;
+   input Iin_d_d25_d0 ;
+   input Iin_d_d25_d1 ;
+   input Iin_d_d26_d0 ;
+   input Iin_d_d26_d1 ;
+   input Iin_d_d27_d0 ;
+   input Iin_d_d27_d1 ;
+   input Iin_d_d28_d0 ;
+   input Iin_d_d28_d1 ;
+   input Iin_d_d29_d0 ;
+   input Iin_d_d29_d1 ;
+   input Iin_d_d30_d0 ;
+   input Iin_d_d30_d1 ;
+   input Iin_d_d31_d0 ;
+   input Iin_d_d31_d1 ;
+   
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+   
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+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   wire Iin_d_d22_d1 ;
+   output Iout_d_d7_d1 ;
+   output Iout_d_d28_d1 ;
+   wire Iin_d_d20_d1 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d1_d0 ;
+   wire Iin_d_d5_d0 ;
+   output Iin_a ;
+   wire Iin_d_d13_d0 ;
+   wire Ien_buf_out0 ;
+   output Iout_d_d15_d0 ;
+   output Iout_d_d30_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d18_d0 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d0_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire I_reset_BXX0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d18_d1 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d25_d0 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d16_d1 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d25_d1 ;
+   output Iout_d_d14_d1 ;
+   output Iout_d_d15_d1 ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d26_d1 ;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d26_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire _in_v ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d8_d0 ;
+   output Iout_d_d12_d0 ;
+   wire Iout_v ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d31_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d10_d0 ;
+   output Iout_d_d4_d1 ;
+   output Iout_d_d8_d1 ;
+   output Iout_d_d28_d0 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d29_d0 ;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d13_d1 ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d21_d1 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d18_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d25_d0 ;
+   output Iout_d_d0_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d29_d0 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d10_d0 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d17_d0 ;
+   wire _out_a_B ;
+   wire Iin_d_d14_d1 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d16_d1 ;
+   wire Iout_a ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d10_d1 ;
+   output Iout_d_d20_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d23_d0 ;
+   output Iout_d_d24_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d27_d0 ;
+   output Iin_v ;
+   wire Iin_d_d28_d1 ;
+   output Iout_d_d19_d0 ;
+   wire _reset_BX ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d29_d1 ;
+   output Iout_d_d2_d1 ;
+   output Iout_d_d20_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d19_d1 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d30_d0 ;
+   output Iout_d_d27_d1 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d27_d0 ;
+   wire Iin_d_d21_d0 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d30_d1 ;
+   output Iout_d_d14_d0 ;
+   wire Iin_d_d2_d0 ;
+   output Iout_d_d21_d0 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d22_d0 ;
+   wire _en ;
+   wire Iin_d_d14_d0 ;
+   output Iout_d_d18_d1 ;
+   output Iout_d_d31_d1 ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d23_d0 ;
+   wire reset_B;
+   output Iout_d_d24_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d12_d1 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d23_d1 ;
+   output Iout_d_d16_d0 ;
+   wire Iin_d_d17_d0 ;
+   output Iout_d_d31_d0 ;
+   wire Iin_d_d24_d1 ;
+   output Iout_d_d11_d1 ;
+   wire Iin_d_d20_d0 ;
+   output Iout_d_d2_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d31_d1 ;
+   output Iout_d_d13_d1 ;
+   output Iout_d_d4_d0 ;
+   wire Iin_d_d30_d1 ;
+   output Iout_d_d9_d1 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_332_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .Iin_d31_d0 (Iin_d_d31_d0 ), .Iin_d31_d1 (Iin_d_d31_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func7  (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func8  (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func9  (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func10  (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func11  (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func12  (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func13  (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func14  (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func15  (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func16  (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func17  (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func18  (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func19  (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func20  (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func21  (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func22  (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func23  (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func24  (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func25  (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func26  (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func27  (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func28  (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func29  (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func30  (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func31  (.y(Iout_d_d31_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d31_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func7  (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func8  (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func9  (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func10  (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func11  (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func12  (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func13  (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func14  (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func15  (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func16  (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func17  (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func18  (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func19  (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func20  (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func21  (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func22  (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func23  (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func24  (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func25  (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func26  (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func27  (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func28  (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func29  (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func30  (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func31  (.y(Iout_d_d31_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d31_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/verilog.v
@@ -0,0 +1,104 @@
+module tmpl_0_0dataflow__neuro_0_0buffer_37_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin_d_d0_d0 ;
+   input Iin_d_d0_d1 ;
+   input Iin_d_d1_d0 ;
+   input Iin_d_d1_d1 ;
+   input Iin_d_d2_d0 ;
+   input Iin_d_d2_d1 ;
+   input Iin_d_d3_d0 ;
+   input Iin_d_d3_d1 ;
+   input Iin_d_d4_d0 ;
+   input Iin_d_d4_d1 ;
+   input Iin_d_d5_d0 ;
+   input Iin_d_d5_d1 ;
+   input Iin_d_d6_d0 ;
+   input Iin_d_d6_d1 ;
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   input Iout_a ;
+   input Iout_v ;
+   input reset_B;
+
+// -- signals ---
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d3_d1 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d2_d1 ;
+   output Iout_d_d5_d1 ;
+   wire _en ;
+   output Iout_d_d6_d1 ;
+   wire Iout_v ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d5_d0 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Ien_buf_out0 ;
+   output Iout_d_d6_d0 ;
+   wire _in_v ;
+   output Iout_d_d0_d1 ;
+   wire Iin_d_d6_d1 ;
+   wire _out_a_B ;
+   wire _reset_BX ;
+   wire Iin_d_d0_d1 ;
+   wire Iout_a ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d3_d1 ;
+   output Iin_v ;
+   output Iout_d_d0_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iin_a ;
+   output Iout_d_d1_d0 ;
+   output Iout_d_d4_d0 ;
+   wire I_reset_BXX0 ;
+   output Iout_d_d4_d1 ;
+   wire reset_B;
+   wire Iin_d_d3_d0 ;
+   output Iout_d_d3_d0 ;
+
+// --- instances
+tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_37_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/verilog.v
@@ -0,0 +1,55 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_313_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   output out;
+
+// -- signals ---
+   wire Iin3 ;
+   wire Itmp18 ;
+   wire Iin1 ;
+   wire Itmp20 ;
+   wire Iin4 ;
+   wire Iin7 ;
+   wire Itmp15 ;
+   wire Itmp13 ;
+   wire Iin2 ;
+   wire Itmp21 ;
+   wire Itmp19 ;
+   wire Iin6 ;
+   wire Iin9 ;
+   wire Itmp14 ;
+   wire out ;
+   wire Iin8 ;
+   wire Iin5 ;
+   wire Iin0 ;
+   wire Itmp17 ;
+   wire Iin12 ;
+   wire Iin10 ;
+   wire Iin11 ;
+   wire Itmp16 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp13 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp14 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp15 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp16 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp17 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp19 ), .c1(Itmp13 ), .c2(Itmp14 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp20 ), .c1(Itmp15 ), .c2(Itmp16 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp21 ), .c1(Itmp17 ), .c2(Itmp18 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp18 ), .c1(Iin10 ), .c2(Iin11 ), .c3(Iin12 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els1  (.y(out), .c1(Itmp19 ), .c2(Itmp20 ), .c3(Itmp21 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/verilog.v
@@ -0,0 +1,93 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_323_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   output out;
+
+// -- signals ---
+   wire Itmp31 ;
+   wire Iin12 ;
+   wire Iin3 ;
+   wire Itmp32 ;
+   wire Itmp29 ;
+   wire Iin9 ;
+   wire Iin7 ;
+   wire Iin11 ;
+   wire Itmp40 ;
+   wire Iin18 ;
+   wire Iin15 ;
+   wire Itmp23 ;
+   wire Itmp36 ;
+   wire out ;
+   wire Itmp27 ;
+   wire Itmp37 ;
+   wire Iin4 ;
+   wire Iin1 ;
+   wire Itmp34 ;
+   wire Itmp30 ;
+   wire Iin22 ;
+   wire Itmp35 ;
+   wire Itmp39 ;
+   wire Iin2 ;
+   wire Iin10 ;
+   wire Iin8 ;
+   wire Itmp26 ;
+   wire Iin0 ;
+   wire Iin20 ;
+   wire Itmp25 ;
+   wire Iin6 ;
+   wire Itmp38 ;
+   wire Iin13 ;
+   wire Iin19 ;
+   wire Iin5 ;
+   wire Itmp24 ;
+   wire Iin21 ;
+   wire Itmp28 ;
+   wire Iin16 ;
+   wire Itmp33 ;
+   wire Iin17 ;
+   wire Iin14 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp23 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp24 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp25 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp26 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp27 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp28 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp29 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp30 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els8  (.y(Itmp31 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els9  (.y(Itmp32 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els10  (.y(Itmp34 ), .c1(Itmp23 ), .c2(Itmp24 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els11  (.y(Itmp35 ), .c1(Itmp25 ), .c2(Itmp26 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els12  (.y(Itmp36 ), .c1(Itmp27 ), .c2(Itmp28 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els13  (.y(Itmp37 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els14  (.y(Itmp39 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els15  (.y(out), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp33 ), .c1(Iin20 ), .c2(Iin21 ), .c3(Iin22 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els1  (.y(Itmp38 ), .c1(Itmp31 ), .c2(Itmp32 ), .c3(Itmp33 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els2  (.y(Itmp40 ), .c1(Itmp36 ), .c2(Itmp37 ), .c3(Itmp38 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist/verilog.v
@@ -0,0 +1,117 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_329_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   input Iin23 ;
+   input Iin24 ;
+   input Iin25 ;
+   input Iin26 ;
+   input Iin27 ;
+   input Iin28 ;
+   output out;
+
+// -- signals ---
+   wire Itmp50 ;
+   wire Itmp47 ;
+   wire Iin15 ;
+   wire Itmp34 ;
+   wire Itmp40 ;
+   wire Iin17 ;
+   wire Iin9 ;
+   wire Iin0 ;
+   wire Iin10 ;
+   wire Iin6 ;
+   wire Iin3 ;
+   wire Itmp29 ;
+   wire Itmp52 ;
+   wire Iin26 ;
+   wire Iin11 ;
+   wire Iin13 ;
+   wire Iin21 ;
+   wire Iin7 ;
+   wire out ;
+   wire Iin27 ;
+   wire Itmp37 ;
+   wire Itmp35 ;
+   wire Iin16 ;
+   wire Iin19 ;
+   wire Itmp45 ;
+   wire Itmp39 ;
+   wire Itmp44 ;
+   wire Iin12 ;
+   wire Itmp51 ;
+   wire Itmp43 ;
+   wire Iin14 ;
+   wire Itmp49 ;
+   wire Iin5 ;
+   wire Iin1 ;
+   wire Itmp31 ;
+   wire Itmp30 ;
+   wire Itmp38 ;
+   wire Itmp33 ;
+   wire Itmp48 ;
+   wire Iin22 ;
+   wire Iin8 ;
+   wire Itmp42 ;
+   wire Itmp32 ;
+   wire Iin25 ;
+   wire Iin24 ;
+   wire Iin20 ;
+   wire Itmp46 ;
+   wire Iin18 ;
+   wire Iin2 ;
+   wire Iin28 ;
+   wire Itmp36 ;
+   wire Iin23 ;
+   wire Itmp41 ;
+   wire Iin4 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp29 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp30 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp31 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp32 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp33 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp34 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp35 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp36 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els8  (.y(Itmp37 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els9  (.y(Itmp38 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els10  (.y(Itmp39 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els11  (.y(Itmp40 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els12  (.y(Itmp41 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els13  (.y(Itmp43 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els14  (.y(Itmp44 ), .c1(Itmp31 ), .c2(Itmp32 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els15  (.y(Itmp45 ), .c1(Itmp33 ), .c2(Itmp34 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els16  (.y(Itmp46 ), .c1(Itmp35 ), .c2(Itmp36 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els17  (.y(Itmp47 ), .c1(Itmp37 ), .c2(Itmp38 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els18  (.y(Itmp48 ), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els19  (.y(Itmp49 ), .c1(Itmp41 ), .c2(Itmp42 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els20  (.y(Itmp50 ), .c1(Itmp43 ), .c2(Itmp44 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els21  (.y(Itmp51 ), .c1(Itmp45 ), .c2(Itmp46 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp42 ), .c1(Iin26 ), .c2(Iin27 ), .c3(Iin28 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els1  (.y(Itmp52 ), .c1(Itmp47 ), .c2(Itmp48 ), .c3(Itmp49 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els2  (.y(out), .c1(Itmp50 ), .c2(Itmp51 ), .c3(Itmp52 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist/verilog.v
@@ -0,0 +1,121 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_330_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   input Iin23 ;
+   input Iin24 ;
+   input Iin25 ;
+   input Iin26 ;
+   input Iin27 ;
+   input Iin28 ;
+   input Iin29 ;
+   output out;
+
+// -- signals ---
+   wire Iin12 ;
+   wire Itmp39 ;
+   wire Iin13 ;
+   wire Iin22 ;
+   wire Iin2 ;
+   wire Iin23 ;
+   wire Iin19 ;
+   wire Itmp43 ;
+   wire Itmp37 ;
+   wire Iin7 ;
+   wire Itmp52 ;
+   wire Itmp49 ;
+   wire Iin28 ;
+   wire Itmp34 ;
+   wire Iin6 ;
+   wire Itmp31 ;
+   wire Itmp30 ;
+   wire Iin25 ;
+   wire Itmp54 ;
+   wire Iin9 ;
+   wire Iin3 ;
+   wire Iin10 ;
+   wire Iin24 ;
+   wire Iin17 ;
+   wire Itmp41 ;
+   wire Itmp38 ;
+   wire Itmp51 ;
+   wire Iin14 ;
+   wire Iin11 ;
+   wire Iin0 ;
+   wire Iin16 ;
+   wire Itmp33 ;
+   wire Iin29 ;
+   wire Iin4 ;
+   wire Itmp32 ;
+   wire Itmp36 ;
+   wire Itmp40 ;
+   wire Itmp50 ;
+   wire Itmp35 ;
+   wire Iin26 ;
+   wire Iin21 ;
+   wire Itmp53 ;
+   wire Itmp46 ;
+   wire Iin18 ;
+   wire out ;
+   wire Iin5 ;
+   wire Iin1 ;
+   wire Itmp48 ;
+   wire Itmp45 ;
+   wire Iin15 ;
+   wire Iin27 ;
+   wire Iin20 ;
+   wire Itmp47 ;
+   wire Iin8 ;
+   wire Itmp44 ;
+   wire Itmp42 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp30 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp31 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp32 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp33 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp34 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp35 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp36 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp37 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els8  (.y(Itmp38 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els9  (.y(Itmp39 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els10  (.y(Itmp40 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els11  (.y(Itmp41 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els12  (.y(Itmp42 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els13  (.y(Itmp43 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els14  (.y(Itmp44 ), .c1(Iin28 ), .c2(Iin29 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els15  (.y(Itmp45 ), .c1(Itmp30 ), .c2(Itmp31 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els16  (.y(Itmp46 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els17  (.y(Itmp47 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els18  (.y(Itmp48 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els19  (.y(Itmp49 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els20  (.y(Itmp50 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els21  (.y(Itmp52 ), .c1(Itmp45 ), .c2(Itmp46 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els22  (.y(Itmp53 ), .c1(Itmp47 ), .c2(Itmp48 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp51 ), .c1(Itmp42 ), .c2(Itmp43 ), .c3(Itmp44 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els1  (.y(Itmp54 ), .c1(Itmp49 ), .c2(Itmp50 ), .c3(Itmp51 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els2  (.y(out), .c1(Itmp52 ), .c2(Itmp53 ), .c3(Itmp54 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist/verilog.v
@@ -0,0 +1,123 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_331_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   input Iin23 ;
+   input Iin24 ;
+   input Iin25 ;
+   input Iin26 ;
+   input Iin27 ;
+   input Iin28 ;
+   input Iin29 ;
+   input Iin30 ;
+   output out;
+
+// -- signals ---
+   wire Itmp31 ;
+   wire Itmp50 ;
+   wire Itmp48 ;
+   wire Itmp42 ;
+   wire Itmp41 ;
+   wire Iin5 ;
+   wire Iin4 ;
+   wire Itmp43 ;
+   wire Iin28 ;
+   wire Itmp55 ;
+   wire Iin27 ;
+   wire Iin15 ;
+   wire Iin13 ;
+   wire Iin8 ;
+   wire Itmp52 ;
+   wire Itmp36 ;
+   wire Itmp45 ;
+   wire Iin20 ;
+   wire Iin23 ;
+   wire Iin22 ;
+   wire Iin16 ;
+   wire Iin7 ;
+   wire Itmp33 ;
+   wire Iin30 ;
+   wire Iin3 ;
+   wire Itmp49 ;
+   wire Itmp39 ;
+   wire Itmp54 ;
+   wire Itmp38 ;
+   wire Itmp47 ;
+   wire Itmp46 ;
+   wire Iin25 ;
+   wire Iin19 ;
+   wire Iin18 ;
+   wire Itmp40 ;
+   wire out ;
+   wire Iin17 ;
+   wire Itmp37 ;
+   wire Iin10 ;
+   wire Iin26 ;
+   wire Iin12 ;
+   wire Iin6 ;
+   wire Itmp51 ;
+   wire Iin21 ;
+   wire Iin9 ;
+   wire Iin29 ;
+   wire Itmp44 ;
+   wire Itmp35 ;
+   wire Iin0 ;
+   wire Itmp53 ;
+   wire Iin24 ;
+   wire Itmp34 ;
+   wire Iin2 ;
+   wire Iin14 ;
+   wire Iin1 ;
+   wire Iin11 ;
+   wire Itmp32 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp31 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp32 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp33 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp34 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp35 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp36 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp37 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp38 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els8  (.y(Itmp39 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els9  (.y(Itmp40 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els10  (.y(Itmp41 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els11  (.y(Itmp42 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els12  (.y(Itmp43 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els13  (.y(Itmp44 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els14  (.y(Itmp46 ), .c1(Itmp31 ), .c2(Itmp32 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els15  (.y(Itmp47 ), .c1(Itmp33 ), .c2(Itmp34 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els16  (.y(Itmp48 ), .c1(Itmp35 ), .c2(Itmp36 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els17  (.y(Itmp49 ), .c1(Itmp37 ), .c2(Itmp38 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els18  (.y(Itmp50 ), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els19  (.y(Itmp51 ), .c1(Itmp41 ), .c2(Itmp42 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els20  (.y(Itmp53 ), .c1(Itmp46 ), .c2(Itmp47 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els21  (.y(Itmp54 ), .c1(Itmp48 ), .c2(Itmp49 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp45 ), .c1(Iin28 ), .c2(Iin29 ), .c3(Iin30 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els1  (.y(Itmp52 ), .c1(Itmp43 ), .c2(Itmp44 ), .c3(Itmp45 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els2  (.y(Itmp55 ), .c1(Itmp50 ), .c2(Itmp51 ), .c3(Itmp52 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els3  (.y(out), .c1(Itmp53 ), .c2(Itmp54 ), .c3(Itmp55 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist/master.tag
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v
--- a/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist/verilog.v
+++ b/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist/verilog.v
@@ -0,0 +1,135 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_332_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , Iin31 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   input Iin23 ;
+   input Iin24 ;
+   input Iin25 ;
+   input Iin26 ;
+   input Iin27 ;
+   input Iin28 ;
+   input Iin29 ;
+   input Iin30 ;
+   input Iin31 ;
+   output out;
+
+// -- signals ---
+   wire Itmp46 ;
+   wire Iin22 ;
+   wire Iin14 ;
+   wire Itmp36 ;
+   wire Itmp54 ;
+   wire Itmp41 ;
+   wire Iin6 ;
+   wire Iin24 ;
+   wire Iin20 ;
+   wire Iin3 ;
+   wire Iin25 ;
+   wire Iin18 ;
+   wire Itmp48 ;
+   wire Iin27 ;
+   wire Itmp39 ;
+   wire Itmp59 ;
+   wire Itmp57 ;
+   wire Iin30 ;
+   wire Iin10 ;
+   wire Iin9 ;
+   wire Itmp61 ;
+   wire Itmp51 ;
+   wire Itmp37 ;
+   wire Itmp32 ;
+   wire Iin4 ;
+   wire Iin21 ;
+   wire Iin15 ;
+   wire Itmp55 ;
+   wire Iin1 ;
+   wire Iin26 ;
+   wire Iin8 ;
+   wire Iin13 ;
+   wire Iin0 ;
+   wire Itmp49 ;
+   wire Itmp45 ;
+   wire Iin7 ;
+   wire Itmp53 ;
+   wire Itmp43 ;
+   wire Iin19 ;
+   wire Iin31 ;
+   wire Itmp58 ;
+   wire Iin28 ;
+   wire Iin29 ;
+   wire Itmp38 ;
+   wire Itmp50 ;
+   wire Iin11 ;
+   wire Itmp35 ;
+   wire Iin2 ;
+   wire Itmp52 ;
+   wire Iin5 ;
+   wire Iin12 ;
+   wire Itmp40 ;
+   wire Itmp44 ;
+   wire Itmp42 ;
+   wire Itmp33 ;
+   wire Itmp60 ;
+   wire Itmp56 ;
+   wire Itmp47 ;
+   wire out ;
+   wire Iin23 ;
+   wire Iin17 ;
+   wire Iin16 ;
+   wire Itmp34 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp32 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp33 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp34 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp35 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp36 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp37 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp38 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp39 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els8  (.y(Itmp40 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els9  (.y(Itmp41 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els10  (.y(Itmp42 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els11  (.y(Itmp43 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els12  (.y(Itmp44 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els13  (.y(Itmp45 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els14  (.y(Itmp46 ), .c1(Iin28 ), .c2(Iin29 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els15  (.y(Itmp47 ), .c1(Iin30 ), .c2(Iin31 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els16  (.y(Itmp48 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els17  (.y(Itmp49 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els18  (.y(Itmp50 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els19  (.y(Itmp51 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els20  (.y(Itmp52 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els21  (.y(Itmp53 ), .c1(Itmp42 ), .c2(Itmp43 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els22  (.y(Itmp54 ), .c1(Itmp44 ), .c2(Itmp45 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els23  (.y(Itmp55 ), .c1(Itmp46 ), .c2(Itmp47 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els24  (.y(Itmp56 ), .c1(Itmp48 ), .c2(Itmp49 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els25  (.y(Itmp57 ), .c1(Itmp50 ), .c2(Itmp51 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els26  (.y(Itmp58 ), .c1(Itmp52 ), .c2(Itmp53 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els27  (.y(Itmp59 ), .c1(Itmp54 ), .c2(Itmp55 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els28  (.y(Itmp60 ), .c1(Itmp56 ), .c2(Itmp57 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els29  (.y(Itmp61 ), .c1(Itmp58 ), .c2(Itmp59 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els30  (.y(out), .c1(Itmp60 ), .c2(Itmp61 ), .vdd(vdd), .vss(vss));
+endmodule
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
alexmadison	ff077c5169	regenned with cores having new names	2022-07-06 18:25:23 +02:00
alexmadison	1cd1b1d054	wiping split modules	2022-07-06 18:24:32 +02:00
alexmadison	72dab29f5c	regennmed tdc no read to have the same number of reg bits as normal tdcg	2022-07-06 17:43:21 +02:00
alexmadison	502d35b000	added slice before registers, so register sizes can be reduced	2022-07-06 17:26:26 +02:00
alexmadison	27a0d34153	genned texel dualcore glue noread netlist clean	2022-07-06 16:04:34 +02:00
alexmadison	b21b84e78d	added some watches	2022-07-06 15:46:41 +02:00
alexmadison	194a7ad196	created version of tdc_g without register read functionality	2022-07-06 15:35:20 +02:00
alexmadison	2ddbeac978	generated a tdc_glue with only 8 registers	2022-07-06 14:06:19 +02:00
alexmadison	7896e0de24	added tests for dynapse sadc hs	2022-07-05 10:53:17 +02:00
alexmadison	8753540b33	removed inverted inputs from sadc encoder, regenned with proper reset sigs I hope	2022-07-01 17:26:55 +02:00
alexmadison	a70c9a1b6d	removed extra supply vss lines from tiehi/lows	2022-06-29 18:25:44 +02:00
alexmadison	9a7a34c02f	please god let this be the last regen of the act. Tiehi/lo's have been given fake PRs	2022-06-29 16:24:00 +02:00
alexmadison	8e38a0fb01	put fake PRs in tiehi/los lol	2022-06-29 15:58:58 +02:00
alexmadison	f488e5dc81	renamed to sadc_encoder	2022-06-29 13:36:14 +02:00
alexmadison	836e19a72d	added sadc encoder with inputs low active for dynapse sadcs	2022-06-29 13:18:42 +02:00
alexmadison	ba7ae68651	lmao forgot to remove top.vdd/vss	2022-06-28 18:20:57 +02:00