fixe some buffering

dataflow_neuro/chips.act

@@ -166,9 +166,10 @@ defproc chip_texel (bd<N_IN> in, out;
     // Otherwise boom.
     bool DEV_DEBUG;
     pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
-    sigbuf<NSMX4> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+    sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
         .supply = supply);
     DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    [NSMX4 >= 1 ->
         AND2_X1 ands_devmon[NSMX4];
         (i:NSMX4:
             ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
@@ -183,6 +184,8 @@ defproc chip_texel (bd<N_IN> in, out;
                 syn_mon_x[i] = syn_mon_dec_x.out[i];
             ]
         )
+    ]
+    
 
 
 }

dataflow_neuro/coders.act

@@ -732,6 +732,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 			// ortree x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply);
 			// INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
 
+			bool _x_a_B2; // sorry
 			
 			bool _en;
 			A_1C3P2P2N_R_X1 x_ack(); // NEEDS BUFFERING TO X4
@@ -747,14 +748,15 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 			x_ack.n1 = out.v;
 			x_ack.n2 = _in_x_v;
 			//
-			x_ack.y = _x_a_B;
+			x_ack.y = _x_a_B2;
 			//
 			x_ack.vdd = supply.vdd;
 			x_ack.vss = supply.vss;
 			x_ack.pr_B = _reset_BX;
 			x_ack.sr_B = _reset_BX;
 
-			INV_X1 not_x_ack(.a = _x_a_B, .y = _x_a, .vdd = supply.vdd, .vss = supply.vss);
+			INV_X1 not_x_ack(.a = _x_a_B2, .y = _x_a, .vdd = supply.vdd, .vss = supply.vss);
+			INV_X1 not_x_ack2(.a = _x_a, .y = _x_a_B, .vdd = supply.vdd, .vss = supply.vss);
 
 
 			A_1C2P_X1 enabling(.p1 = out.a, .p2 = out.v, .c1 = _x_a, .y = _en, .vdd = supply.vdd, .vss = supply.vss);

dataflow_neuro/primitives.act

@@ -111,13 +111,13 @@ namespace tmpl {
         export template<pint N>
         defproc buffer (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
             //control
-            bool _en, _reset_BX,_reset_BXX[N];
+            bool _en, _reset_BX,_reset_BXX[N*2];
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
 
 
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
+            sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
       
             //validity
             bool _in_v;
@@ -131,8 +131,8 @@ namespace tmpl {
             sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
             sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
             INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
+            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply = supply);
+            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply = supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
@@ -150,8 +150,8 @@ namespace tmpl {
                 t_buf_func[i].vss=supply.vss;
                 t_buf_func[i].pr_B = _reset_BXX[i];
                 t_buf_func[i].sr_B = _reset_BXX[i];
-                f_buf_func[i].pr_B = _reset_BXX[i];
-                f_buf_func[i].sr_B = _reset_BXX[i];
+                f_buf_func[i].pr_B = _reset_BXX[i+N];
+                f_buf_func[i].sr_B = _reset_BXX[i+N];
             )
         }
         // A template creating a FIFO of M buffers with N bits each

test/prsim_plot.py

@@ -99,6 +99,14 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 		if len(r) >= 1:
 			include_all_times = True
 
+
+	# Check if user gave "nowarn" flag
+	plot_warn = True
+	for arg in argv:
+		r = re.findall(r'(-nowarn?)', arg)
+		if len(r) >= 1:
+			plot_warn = False
+
 	# Get list of all times (before filtering)
 	unique_times = np.unique([int(e[0]) for e in entries])
 
@@ -237,6 +245,7 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 				print(f"Couldn't find an appropriate time for warning {a}")
 				continue
 		index = time_to_index(time)
+		if plot_warn:
 			ax.axvline(index+0.5, c = "red", lw = 2)
 			ax.text(index+0.5, -1, a[2], rotation = 90, ha = "center", va = "bottom", c = "red")
 

test/unit_tests/texel_small/test.prsim

@@ -24,20 +24,7 @@ set Reset 0
 cycle
 
 # Reading address 0
-set c.in.d[0] 0
-set c.in.d[1] 0
-set c.in.d[2] 0
-set c.in.d[3] 0
-set c.in.d[4] 0
-set c.in.d[5] 0
-set c.in.d[6] 0
-set c.in.d[7] 0
-set c.in.d[8] 0
-set c.in.d[9] 0
-set c.in.d[10] 0
-set c.in.d[11] 0
-set c.in.d[12] 0
-set c.in.d[13] 1
+set-bd-data-valid "c.in" 14 8192
 cycle
 set c.in.r 1
 cycle
@@ -49,6 +36,7 @@ cycle
 assert c.in.a 0
 
 # Should first get loopback
+# Receiving output 0 from register 0
 assert-bd-channel-valid "c.out" 14 8192
 set c.out.a 1
 cycle
@@ -56,8 +44,10 @@ assert-bd-channel-neutral "c.out" 14
 set c.out.a 0
 cycle
 
+
 # Expect register read packet to arrive
-assert-bd-channel-valid "c.out" 14 4080
+# Receiving output 0 from register 0
+assert-bd-channel-valid "c.out" 14 0
 set c.out.a 1
 cycle
 assert-bd-channel-neutral "c.out" 14
@@ -68,60 +58,214 @@ cycle
 set c.loopback_en 0
 cycle
 
-# Writing 68 to address 1
-set c.in.d[0] 1
-set c.in.d[1] 0
-set c.in.d[2] 0
-set c.in.d[3] 0
-set c.in.d[4] 0
-set c.in.d[5] 0
-set c.in.d[6] 1
-set c.in.d[7] 0
-set c.in.d[8] 0
-set c.in.d[9] 0
-set c.in.d[10] 1
-set c.in.d[11] 0
-set c.in.d[12] 1
-set c.in.d[13] 1
+# Writing 17 to address 1
+set-bd-data-valid "c.in" 14 12561
 cycle
 set c.in.r 1
 cycle
 assert c.in.a 1
 
+
 # Remove input
 set-bd-channel-neutral "c.in" 14
 cycle
 assert c.in.a 0
 
 
-# Reading address 1
-set c.in.d[0] 1
-set c.in.d[1] 0
-set c.in.d[2] 0
-set c.in.d[3] 0
-set c.in.d[4] 0
-set c.in.d[5] 0
-set c.in.d[6] 0
-set c.in.d[7] 0
-set c.in.d[8] 0
-set c.in.d[9] 0
-set c.in.d[10] 0
-set c.in.d[11] 0
-set c.in.d[12] 0
-set c.in.d[13] 1
+# Writing 255 to address 5
+set-bd-data-valid "c.in" 14 16373
 cycle
 set c.in.r 1
 cycle
 assert c.in.a 1
 
- # Remove input
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+# Reading address 1
+set-bd-data-valid "c.in" 14 8193
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
 set-bd-channel-neutral "c.in" 14
 cycle
 assert c.in.a 0
 
     
-# Receiving output 68 from register 1
-assert-bd-channel-valid "c.out" 14 1089
+# Reading address 5
+set-bd-data-valid "c.in" 14 8197
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+
+# Receiving output 17 from register 1
+assert-bd-channel-valid "c.out" 14 273
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Receiving output 255 from register 5
+assert-bd-channel-valid "c.out" 14 4085
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+# SPIKES
+
+
+
+# Sending spike to synapse [0,1]
+set-bd-data-valid "c.in" 14 2
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,1]
+assert-bd-channel-valid "c.out" 14 2
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [1,3]
+set-bd-data-valid "c.in" 14 7
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [1,3]
+assert-bd-channel-valid "c.out" 14 7
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [1,2]
+set-bd-data-valid "c.in" 14 5
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [1,2]
+assert-bd-channel-valid "c.out" 14 5
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [1,3]
+set-bd-data-valid "c.in" 14 7
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [1,3]
+assert-bd-channel-valid "c.out" 14 7
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,2]
+set-bd-data-valid "c.in" 14 4
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,2]
+assert-bd-channel-valid "c.out" 14 4
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,3]
+set-bd-data-valid "c.in" 14 6
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,3]
+assert-bd-channel-valid "c.out" 14 6
 set c.out.a 1
 cycle
 assert-bd-channel-neutral "c.out" 14
@@ -129,21 +273,90 @@ set c.out.a 0
 cycle
 
 # Sending spike to synapse [0,1]
-set c.in.d[0] 0
-set c.in.d[1] 1
-set c.in.d[2] 0
-set c.in.d[3] 0
-set c.in.d[4] 0
-set c.in.d[5] 0
-set c.in.d[6] 0
-set c.in.d[7] 0
-set c.in.d[8] 0
-set c.in.d[9] 0
-set c.in.d[10] 0
-set c.in.d[11] 0
-set c.in.d[12] 0
-set c.in.d[13] 0
+set-bd-data-valid "c.in" 14 2
 cycle
 set c.in.r 1
 cycle
 assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,1]
+assert-bd-channel-valid "c.out" 14 2
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,0]
+set-bd-data-valid "c.in" 14 0
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,0]
+assert-bd-channel-valid "c.out" 14 0
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,0]
+set-bd-data-valid "c.in" 14 0
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,0]
+assert-bd-channel-valid "c.out" 14 0
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,3]
+set-bd-data-valid "c.in" 14 6
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,3]
+assert-bd-channel-valid "c.out" 14 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+