Michele 6f1a970cfd register_rw (formerly register_rw_v2) compiles

2022-03-09 16:44:44 +01:00

..

__all__.act

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

cell_lib_async_test.act

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

cell_lib_async.act

forgot proc in defproc

2022-03-04 19:04:11 +01:00

cell_lib_std_test.act

Added std test

2022-02-21 13:07:14 +01:00

cell_lib_std.act

register_write works

2022-03-07 16:36:01 +01:00

coders.act

encoder sim still not working

2022-03-08 18:49:04 +01:00

Makefile

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

primitives.act

started register_v2 with reading and writing abilities

2022-03-09 13:05:08 +01:00

registers.act

register_rw (formerly register_rw_v2) compiles

2022-03-09 16:44:44 +01:00

treegates.act

Added sigbuf_1output for signals that cannot have array outputs

2022-03-03 19:23:13 +01:00