Michele aa67bd6168 register simulates correctly up to the fake clock generation

2022-03-05 20:28:50 +01:00

..

__all__.act

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

cell_lib_async_test.act

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

cell_lib_async.act

forgot proc in defproc

2022-03-04 19:04:11 +01:00

cell_lib_std_test.act

Added std test

2022-02-21 13:07:14 +01:00

cell_lib_std.act

added flip flop from XFAB

2022-03-04 19:02:34 +01:00

coders.act

I think the encoder2D compiles now

2022-03-04 21:11:34 +01:00

Makefile

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

primitives.act

Added stuff for line end pull U/D

2022-03-04 12:33:49 +01:00

registers.act

register simulates correctly up to the fake clock generation

2022-03-05 20:28:50 +01:00

treegates.act

Added sigbuf_1output for signals that cannot have array outputs

2022-03-03 19:23:13 +01:00