29 lines
886 B
Verilog
29 lines
886 B
Verilog
module tmpl_0_0dataflow__neuro_0_0delayprog_32_4(out, in, Is0 , Is1 , vdd, vss);
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input vdd;
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input vss;
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output out;
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input in;
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input Is0 ;
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input Is1 ;
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// -- signals ---
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wire Idly0_y ;
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wire Is1 ;
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wire Idly0_a ;
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wire Idly2_a ;
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wire Idly2_y ;
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wire out ;
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wire in;
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wire Is0 ;
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wire Idly1_a ;
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wire I_a1 ;
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// --- instances
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AND2_X1 Iand20 (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand21 (.y(Idly1_a ), .a(I_a1 ), .b(Is1 ), .vdd(vdd), .vss(vss));
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MUX2_X1 Imu20 (.y(I_a1 ), .a(in), .b(Idly0_y ), .s(Is0 ), .vdd(vdd), .vss(vss));
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MUX2_X1 Imu21 (.y(out), .a(I_a1 ), .b(Idly2_y ), .s(Is1 ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly0 (.y(Idly0_y ), .a(Idly0_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly1 (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly2 (.y(Idly2_y ), .a(Idly2_a ), .vdd(vdd), .vss(vss));
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endmodule |