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F.M. Quintana Velazquez
2026-02-27 09:47:31 +01:00
parent ddde38deca
commit e7c1016ea0
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sim/mem_stim_db.sv Normal file
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sim/mem_stim_tb.sv Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/20/2026 02:02:47 PM
// Design Name:
// Module Name: mem_stim_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define CLK_HALF_PERIOD 2
module mem_stim_tb(
);
logic CLK;
logic RST_N;
logic ACK;
logic [8:0] ADDR_T;
logic [8:0] ADDR_F;
wire END_SIG;
initial begin
CLK = 1'b0;
forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
end
initial begin
RST_N = 1'b0;
#(4 * `CLK_HALF_PERIOD);
RST_N = 1'b1;
#(20 * `CLK_HALF_PERIOD);
end
mem_stim #(
.DATA_WIDTH(9)
) ut (
.clk(CLK),
.rst_n(RST_N),
.restart(~RST_N),
.ack(ACK),
.addr_t(ADDR_T),
.addr_f(ADDR_F),
.done(END_SIG)
);
autoack auto_ack (
.CLK(CLK),
.RST(!RST_N),
.OUTPUT_BITS_ONION_p(ADDR_T),
.OUTPUT_BITS_ONION_n(ADDR_F),
.OUTPUT_BITS_ONION_A_AO(ACK)
);
endmodule

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sim/olla_testack.sv Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/16/2026 08:28:02 PM
// Design Name:
// Module Name: olla_testack
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module autoack (
input logic CLK,
input logic RST,
input logic [8:0] OUTPUT_BITS_ONION_p,
input logic [8:0] OUTPUT_BITS_ONION_n,
output logic OUTPUT_BITS_ONION_A_AO
);
//---------------------------------------------------------
// Local Parameters
//---------------------------------------------------------
localparam int COUNTER_WIDTH = 27;
// Örnek: CLK = 25 MHz ise 25,000,000 çevrim 1 saniyedir.
// localparam int ONE_SEC_LIMIT = 25_000_000 - 1;
localparam int ONE_SEC_LIMIT = 5 - 1;
//---------------------------------------------------------
// Internal Signals
//---------------------------------------------------------
// FSM State Definitions
typedef enum logic [3:0] {
S_WAIT_DATA_BLANK, // Faz 1: Veri hatlarının ve ACK'nin 0 olmasını bekle.
S_DATA_LATCH, // Faz 2: Veri geldi, veriyi/adresi yakala.
S_TIMER_START, // LED zamanlayıcısını başlat (Sayacı sıfırla).
S_TIMER_WAIT, // LED açıkken 1 saniye bekle (ON Time).
S_LED_BLANK_WAIT, // LED kapalıyken 1 saniye bekle (OFF Time).
S_SEND_ACK, // Faz 3: ACK'yi '1' yap.
S_WAIT_DATA_BLANK_LOW, // Faz 4: Göndericinin veri hatlarını '0' çekmesini bekle.
S_ACK_LOW // Faz 5: ACK'yi '0' yap ve S_WAIT_DATA_BLANK'e dön.
} state_t;
state_t state, next_state;
logic [COUNTER_WIDTH-1:0] counter_reg;
//---------------------------------------------------------
// 1. Dual-Rail Veri Kontrolü
//---------------------------------------------------------
// 'data_arrived' sinyali: Data hatlarından herhangi biri '1' ise veri gelmiştir.
logic data_arrived;
assign data_arrived = |OUTPUT_BITS_ONION_p | |OUTPUT_BITS_ONION_n;
// 'data_is_blank' sinyali: Tüm data hatları '0' ise hat boş/temizdir.
logic data_is_blank;
assign data_is_blank = ~data_arrived;
//---------------------------------------------------------
// 2. Sequential Logic: Counter Register
//---------------------------------------------------------
always_ff @(posedge CLK)
begin
if (RST) begin
counter_reg <= '0;
end
else begin
// Counter Logic: Increments in S_TIMER_WAIT (LED ON time)
// OR S_LED_BLANK_WAIT (LED OFF time)
if (state == S_TIMER_WAIT || state == S_LED_BLANK_WAIT) begin
if (counter_reg == ONE_SEC_LIMIT)
counter_reg <= '0;
else
counter_reg <= counter_reg + 1;
end
// Reset counter when a new timer sequence starts
else if (state == S_TIMER_START)
counter_reg <= '0;
// Reset counter in other states if it's not already 0 (safety)
else if (counter_reg != '0 && state != S_TIMER_WAIT && state != S_LED_BLANK_WAIT)
counter_reg <= '0;
end
end
//---------------------------------------------------------
// 3. Sequential Logic: State Register
//---------------------------------------------------------
always_ff @(posedge CLK)
begin
if (RST) state <= S_WAIT_DATA_BLANK;
else state <= next_state;
end
//----------------------------------------------------------
// 4. Combinational Logic: Next State Determination (FSM)
//----------------------------------------------------------
always_comb begin
next_state = state;
case (state)
S_WAIT_DATA_BLANK: // Faz 1: Hatların boş olmasını bekle
if (data_arrived) // Veri geldiğinde (Dual-rail sinyalleri 0'dan farklı)
next_state = S_DATA_LATCH;
S_DATA_LATCH: // Faz 2: Veri geldi, zamanlayıcıyı başlat
next_state = S_TIMER_START;
S_TIMER_START: // LED ON süresini başlatmak için sayacı sıfırla
next_state = S_TIMER_WAIT;
S_TIMER_WAIT: // LED açıkken 1 saniye bekle
if (counter_reg == ONE_SEC_LIMIT)
next_state = S_LED_BLANK_WAIT; // LED'i söndürme süresine geç
S_LED_BLANK_WAIT: // LED kapalıyken 1 saniye bekle (Blink süresi)
if (counter_reg == ONE_SEC_LIMIT)
next_state = S_SEND_ACK; // ACK gönderme döngüsüne geç
S_SEND_ACK: // Faz 3: ACK'yi '1' yap
next_state = S_WAIT_DATA_BLANK_LOW;
S_WAIT_DATA_BLANK_LOW: // Faz 4: Göndericinin veri hatlarını '0' çekmesini bekle
if (data_is_blank) // Veri hatları boşaldı (tümü '0')
next_state = S_ACK_LOW;
S_ACK_LOW: // Faz 5: ACK'yi '0' yap
next_state = S_WAIT_DATA_BLANK;
default:
next_state = S_WAIT_DATA_BLANK;
endcase
end
//-----------------------------------------------------------
// 5. Combinational Logic: Output Generation
//-----------------------------------------------------------
always_comb begin
// Default değerler
OUTPUT_BITS_ONION_A_AO = 1'b0;
case (state)
S_SEND_ACK, S_WAIT_DATA_BLANK_LOW:
OUTPUT_BITS_ONION_A_AO = 1'b1;
default: ;
endcase
end
endmodule

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sim/stimulus_gen_tb.sv Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/16/2026 05:49:17 PM
// Design Name:
// Module Name: stimulus_gen_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define CLK_HALF_PERIOD 2
module stimulus_gen_tb(
);
logic CLK;
logic RST;
logic ACK;
logic REQ;
logic [4:0] ADDR;
wire END_SIG;
initial begin
CLK = 1'b0;
forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
end
initial begin
RST = 1'b1;
#(4 * `CLK_HALF_PERIOD);
RST = 1'b0;
#(20 * `CLK_HALF_PERIOD);
end
always_ff @(posedge CLK)
begin
if (REQ) begin
ACK <= 1'b1;
end else begin
ACK <= 1'b0;
end
end
stimulus_gen #() ut (
.CLK_I(CLK),
.RST_I(RST),
.REQ_O(REQ),
.ACK_I(ACK),
.ADDR_O(ADDR),
.END_O(END_SIG)
);
endmodule

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sim/top_interface_tb.sv Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/16/2026 07:33:07 PM
// Design Name:
// Module Name: top_interface_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define CLK_HALF_PERIOD 2
module top_interface_tb(
);
logic CLK;
logic RSTN;
logic AERIN_REQ;
logic AERIN_ACK;
logic [4:0] AERIN_ADDR;
logic AEROUT_ACK;
logic [8:0] AEROUT_ADDR_T;
logic [8:0] AEROUT_ADDR_F;
initial begin
CLK = 1'b0;
forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
end
assign RST = !RSTN;
top_interface #() ut (
.CLK(CLK),
.RSTN_O(RSTN),
.AERIN_REQ(AERIN_REQ),
.AERIN_ADDR(AERIN_ADDR),
.AERIN_ACK(AERIN_ACK),
.AEROUT_ACK(AEROUT_ACK),
.AEROUT_ADDR_T(AEROUT_ADDR_T),
.AEROUT_ADDR_F(AEROUT_ADDR_F)
);
autoack auto_ack (
.CLK(CLK),
.RST(RST),
.OUTPUT_BITS_ONION_p(AEROUT_ADDR_T),
.OUTPUT_BITS_ONION_n(AEROUT_ADDR_F),
.OUTPUT_BITS_ONION_A_AO(AEROUT_ACK)
);
stimulus_gen #() stim (
.CLK_I(CLK),
.RST_I(RST),
.REQ_O(AERIN_REQ),
.ACK_I(AERIN_ACK),
.ADDR_O(AERIN_ADDR)
);
endmodule