actlib_dataflow_neuro/test/unit_tests/register_write/test.prsim

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system "echo '[0] start test'"
set-qdi-channel-neutral "t.in" 5
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set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
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set t.registers._in_write.a 0
set t.registers._in_read.a 0
set t.registers._in_write.v 0
set t.registers._in_read.v 0
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set Reset 0
cycle
status X
mode run
assert-qdi-channel-neutral "t.in" 5
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
cycle
assert-qdi-channel-neutral "t.in" 5
system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 19
cycle
assert-qdi-channel-valid "t.registers._in_write" 4 3
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assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
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assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
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cycle
set-qdi-channel-neutral "t.in" 5
cycle
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assert t.registers._clock 1
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assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
system "echo '[3] clock checked'"