actlib_dataflow_neuro/dataflow_neuro/chips.act

/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 * 
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */


import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;

namespace tmpl {
    namespace dataflow_neuro {

export template<pint N_IN,	// Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>

defproc chip_texel (bd<N_IN> in, out;
	Mx1of2<REG_NCW> reg_data[REG_M];
	a1of1 synapses[N_SYN_X * N_SYN_Y];
	a1of1 neurons[N_NRN_X * N_NRN_Y];
    bool? nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
    bool? syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];  
	bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
	bool? loopback_en;
	power supply;
	bool? reset_B){

	bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
        .reset_B = reset_B, .supply = supply);
	fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply);

	fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = reset_B, .supply = supply);

	// Loopback
	fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = reset_B, .supply = supply);
	dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
		.supply = supply);

	// Onwards
	fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = reset_B, .supply = supply);
	demux_bit_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = reset_B, .supply = supply);

	// Register
	fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = reset_B, .supply = supply);
	register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
		.supply = supply, .reset_B = reset_B);
	fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = reset_B, .supply = supply);


	// Spike Decoder
    pint NC_SYN;
    NC_SYN = NC_SYN_X + NC_SYN_Y;
    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
	fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply);
	decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
		.out = synapses,
		.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
		.supply = supply, .reset_B = reset_B);
	(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].f;) // Defaults to max delay

	// Neurons + encoder
    pint NC_NRN;
    NC_NRN = NC_NRN_X + NC_NRN_Y;
	nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
		.supply = supply, .reset_B = reset_B);
	encoder2d<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, 16> encoder(
		.inx = nrn_grid.outx,
		.iny = nrn_grid.outy,
		.reset_B = reset_B, .supply = supply
		);
	fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
		.reset_B = reset_B, .supply = supply);


    // Merge
    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
    append<N_IN-2, 2, 0> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
    merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
        .supply = supply, .reset_B = reset_B);

    merge<N_IN> merge_loop8mrg(.in1 = merge_enc8reg.out, .in2 = _loopback_dropper.out,
        .reset_B = reset_B, .supply = supply);

    // qdi2bd
    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_loop8mrg.out,
        .reset_B = reset_B, .supply = supply);
    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
        .reset_B = reset_B, .supply = supply);



    // Neuron/synapse monitor targeters
    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
    pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
    pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);

    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.out = nrn_mon_x,
        .supply = supply);
    nrn_mon_dec_x.en = register.data[1].d[0].t;
    (i:NC_NRN_MON_X:
        nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
    )

    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.out = nrn_mon_y,
        .supply = supply);
    nrn_mon_dec_y.en = register.data[1].d[0].t;
    (i:NC_NRN_MON_Y:
        nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
    )

    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
        .supply = supply);
    syn_mon_dec_x.en = register.data[1].d[1].t;
    (i:NC_SYN_MON_X:
        syn_mon_dec_x.in.d[i] = register.data[3].d[i];
    )

    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.out = syn_mon_y,
        .supply = supply);
    syn_mon_dec_y.en = register.data[1].d[1].t;
    (i:NC_SYN_MON_Y:
        syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
    )

    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
    // Stops the possibility of dev_mon being high while some other sig is high.
    // Otherwise boom.
    bool DEV_DEBUG;
    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
    sigbuf<NSMX4> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
        .supply = supply);
    DEV_DEBUG = sb_DEV_DEBUG.out[0];
    AND2_X1 ands_devmon[NSMX4];
    (i:NSMX4:
        ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
        ands_devmon[i].b = DEV_DEBUG;
        ands_devmon[i].y = syn_mon_x[1+i*4];
        ands_devmon[i].vdd = supply.vdd;
        ands_devmon[i].vss = supply.vss;
    )
    // Wire up the non-ANDed lines.
    (i:N_SYN_MON_X:
        [~(i%4 = 1) ->
            syn_mon_x[i] = syn_mon_dec_x.out[i];
        ]
    )


}
}
}