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commented out old registers

This commit is contained in:
alexmadison 2022-06-15 18:08:33 +02:00
parent 87577268e5
commit 97dacbfd08
1 changed files with 92 additions and 92 deletions
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dataflow_neuro/registers.act
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@ -48,65 +48,65 @@ namespace tmpl {
* Also, in.a does not wait for out.v to go low to go to low. * Also, in.a does not wait for out.v to go low to go to low.
* Means have a buffer that completes its Right handshake as soon as out data is valid. * Means have a buffer that completes its Right handshake as soon as out data is valid.
*/ */
export template<pint N> // export template<pint N>
defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush, // defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
reset_B; power supply) { // reset_B; power supply) {
//control // //control
bool _en, _reset_BX[N]; // bool _en, _reset_BX[N];
bool _in_aB; // bool _in_aB;
bool _reset; // bool _reset;
bool _resetX[N]; // bool _resetX[N];
// Reset sigs // // Reset sigs
INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss); // INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply); // sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply); // sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB, // A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
.pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss); // .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss); // INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
// Flush sigs // // Flush sigs
bool _flushB, _flushBX[N*2]; // bool _flushB, _flushBX[N*2];
INV_X1 flush_inv(.a = flush, .y = _flushB); // INV_X1 flush_inv(.a = flush, .y = _flushB);
sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply); // sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
_en = _in_aB; // _en = _in_aB;
//validity // //validity
bool _in_v; // bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply); // vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); // BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function // //function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B; // bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
A_1C2N_SB_X4 f_buf_func[N]; // A_1C2N_SB_X4 f_buf_func[N];
A_1C2N_RB_X4 t_buf_func[N]; // A_1C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply); // sigbuf<N*2> en_buf(.in=_en, .supply=supply);
(i:N: // (i:N:
f_buf_func[i].y=out.d[i].f; // f_buf_func[i].y=out.d[i].f;
t_buf_func[i].y=out.d[i].t; // t_buf_func[i].y=out.d[i].t;
f_buf_func[i].c1=_flushBX[i]; // f_buf_func[i].c1=_flushBX[i];
t_buf_func[i].c1=_flushBX[i+N]; // t_buf_func[i].c1=_flushBX[i+N];
f_buf_func[i].n2=en_buf.out[i]; // f_buf_func[i].n2=en_buf.out[i];
t_buf_func[i].n2=en_buf.out[i+N]; // t_buf_func[i].n2=en_buf.out[i+N];
f_buf_func[i].n1=in.d.d[i].f; // f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t; // t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].vdd=supply.vdd; // f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd; // t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss; // f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss; // t_buf_func[i].vss=supply.vss;
f_buf_func[i].pr = _resetX[i]; // f_buf_func[i].pr = _resetX[i];
f_buf_func[i].sr = _resetX[i]; // f_buf_func[i].sr = _resetX[i];
t_buf_func[i].pr_B = _reset_BX[i]; // t_buf_func[i].pr_B = _reset_BX[i];
t_buf_func[i].sr_B = _reset_BX[i]; // t_buf_func[i].sr_B = _reset_BX[i];
) // )
} // }
/** /**
@ -114,63 +114,63 @@ sigbuf<N*2> en_buf(.in=_en, .supply=supply);
* MSB is whether to read or write. * MSB is whether to read or write.
* Currently only handles writing. * Currently only handles writing.
*/ */
export template<pint N> // export template<pint N>
defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out; // defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
bool? reset_B; power supply) { // bool? reset_B; power supply) {
bool _en2; // bool _en2;
bool _w; // bool _w;
bool _out_v, _out_vB; // bool _out_v, _out_vB;
bool _flush, _flushB; // bool _flush, _flushB;
_w = in.d.d[N].t; // _w = in.d.d[N].t;
// Buffer // // Buffer
buffer_register<N> buf(.out = out, .out_v = _out_v, .flush = _flush, // buffer_register<N> buf(.out = out, .out_v = _out_v, .flush = _flush,
.supply = supply, .reset_B = reset_B); // .supply = supply, .reset_B = reset_B);
buf.in.v = in.v; // buf.in.v = in.v;
// In ack stuff // // In ack stuff
INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss); // INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
// To stop in ack going low before en2 has been reset. // // To stop in ack going low before en2 has been reset.
A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a, // A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a,
.vdd = supply.vdd, .vss = supply.vss); // .vdd = supply.vdd, .vss = supply.vss);
// Out valid tree // // Out valid tree
vtree<N> out_valid(.in = buf.out, .out = _out_v, .supply = supply); // vtree<N> out_valid(.in = buf.out, .out = _out_v, .supply = supply);
INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss); // INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss);
// Control // // Control
A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush, // A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush,
.vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B); // .vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B);
INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss); // INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss);
A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2, // A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
.pr_B = reset_B, .sr_B = reset_B); // .pr_B = reset_B, .sr_B = reset_B);
// Pass to let data into the buffer // // Pass to let data into the buffer
NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd); // NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> passX(.in = pass.y, .supply = supply); // sigbuf<N*2> passX(.in = pass.y, .supply = supply);
AND2_X1 gandalf_t[N]; // AND2_X1 gandalf_t[N];
AND2_X1 gandalf_f[N]; // AND2_X1 gandalf_f[N];
(i:0..N-1: // (i:0..N-1:
gandalf_t[i].a = in.d.d[i].t; // gandalf_t[i].a = in.d.d[i].t;
gandalf_f[i].a = in.d.d[i].f; // gandalf_f[i].a = in.d.d[i].f;
gandalf_t[i].b = passX.out[i]; // gandalf_t[i].b = passX.out[i];
gandalf_f[i].b = passX.out[i+N]; // gandalf_f[i].b = passX.out[i+N];
gandalf_t[i].y = buf.in.d.d[i].t; // gandalf_t[i].y = buf.in.d.d[i].t;
gandalf_f[i].y = buf.in.d.d[i].f; // gandalf_f[i].y = buf.in.d.d[i].f;
gandalf_t[i].vdd = supply.vdd; // gandalf_t[i].vdd = supply.vdd;
gandalf_f[i].vdd = supply.vdd; // gandalf_f[i].vdd = supply.vdd;
gandalf_t[i].vss = supply.vss; // gandalf_t[i].vss = supply.vss;
gandalf_f[i].vss = supply.vss; // gandalf_f[i].vss = supply.vss;
) // )
} // }
/** /**
* A single register made out of A cells. * A single register made out of A cells.