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register_write works

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This commit is contained in:
M. Mastella
2022-03-07 16:36:01 +01:00
parent ad318259a5
commit e49866323c
8 changed files with 598 additions and 837 deletions
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16
dataflow_neuro/cell_lib_std.act
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@ -373,22 +373,22 @@ namespace tmpl {
}
sizing { _en{-2}; y{-2,2} }
}
export defproc DFFQ_R_X1 (bool? clk, reset_B, d; bool! q; bool? vdd,vss)
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q; bool? vdd,vss)
{
bool _clk, __clk, _mqi,_mqib,_sqi,_sqib;
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
prs {
// Creating delayed versions of the clock
clk => _clk-
_clk => __clk-
clk_B => _clk_B-
_clk_B => __clk_B-
(~d & ~_clk)|(~reset_B)|(~__clk&~_mqi) -> _mqib+
(d & __clk)|(reset_B & _mqi & _clk) -> _mqib-
(~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
_mqib => _mqi-
(~_mqi &~__clk)|(~reset_B)|(~_sqi&~_clk) -> _sqib+
(_mqi &_clk)|(_sqi&__clk&reset_B) -> _sqib-
(~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
_sqib => _sqi-
_sqib => q-

86
dataflow_neuro/registers.act
View File

@ -41,72 +41,72 @@ namespace tmpl {
namespace dataflow_neuro {
// Circuit for storing, reading and writing registers using AER
// The block has the parameters:
// log_nw -> log2(number of words), parameters you can store
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the first bit is write/read_B
// - the next log_nw bits describe the location,
// - the next lognw bits describe the location,
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint log_nw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
pint _nw = 2<<log_nw;
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
Mx1of2<1+log_nw+wl> _in_temp;
(i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];)
vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
Mx1of2<1+lognw+wl> _in_temp;
(i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Generation of the fake clock pulse
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
// Sending back to the ackowledge
delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*wl];
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
// Creating the different flip flop arrays
bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl];
andtree<log_nw> atree[_nw];
AND2_X1 and_encoder[_nw];
sigbuf<wl> clock_buffer[_nw];
DFFQ_R_X1 ff[_nw*wl];
pint _bitval;
(k:_nw:atree[k].supply = supply;)
(_word_idx:_nw:
bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
andtree<lognw> atree[nw];
AND2_X1 and_encoder[nw];
sigbuf<wl> clock_buffer[nw];
DFFQ_R_X1 ff[nw*wl];
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
// Decoding the bit pattern to understand which word we are looking at
(pin_idx:log_nw:
_bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[_bitval = 1 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] _bitval = 0 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]_bitval >= 2 -> {false : "fuck"};
(pin_idx:lognw:
bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[bitval = 1 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] bitval = 0 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
atree[_word_idx].out = _out_encoder[_word_idx];
and_encoder[_word_idx].a = _out_encoder[_word_idx];
and_encoder[_word_idx].b = _clock;
and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
and_encoder[_word_idx].vdd = supply.vdd;
and_encoder[_word_idx].vss = supply.vss;
clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
clock_buffer[_word_idx].supply = supply;
atree[word_idx].out = _out_encoder[word_idx];
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock;
and_encoder[word_idx].y = _clock_word_temp[word_idx];
and_encoder[word_idx].vdd = supply.vdd;
and_encoder[word_idx].vss = supply.vss;
clock_buffer[word_idx].in = _clock_word_temp[word_idx];
clock_buffer[word_idx].supply = supply;
// Describing all the FF and their connection
(_bit_idx:wl:
clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)];
// ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)];
// ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
// ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
// ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
// ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
// ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
(bit_idx:wl:
ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff[bit_idx+word_idx*(wl)].vss = supply.vss;
)
)
}