bics/actlib_dataflow_neuro
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register_write works

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This commit is contained in:
M. Mastella
2022-03-07 16:36:01 +01:00
parent ad318259a5
commit e49866323c
8 changed files with 598 additions and 837 deletions
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9
test/unit_tests/register_write/test.prsim
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@@ -1,13 +1,12 @@
watchall
system "echo '[0] start test'"
set Reset 1
set-qdi-channel-neutral "t.in" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set Reset 0
cycle
status X
mode run
@@ -16,7 +15,6 @@ assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
set Reset 0
cycle
system "echo '[1] reset completed'"
# Set delay config lines
@@ -28,14 +26,15 @@ system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 3
cycle
assert-qdi-channel-valid "t.in" 5 3
assert t.registers._clock 1
assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
cycle
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 0
assert t.registers._clock 1
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
system "echo '[3] clock checked'"