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aa299fb45f ... dev

Author SHA1 Message Date
Ole Richter
32005f47ee THIS REPOSITORY IS DEPRICATED 2024-12-31 13:22:39 -05:00
P. Gibertini
395bb41346 added demultiplexer, not working yet 2024-09-23 08:45:00 +02:00
P. Gibertini
ee364f99f4 created demultiplexer and tests, not working yet 2024-09-18 16:02:27 +02:00
alexmadison
ae4e63d634 removed weird sigbuf 1output 2023-12-01 13:46:21 +01:00
alexmadison
bf81cfefee added note to get rid of unsued sigbuf1output 2023-12-01 13:44:07 +01:00
alexmadison
76e0e22356 removed unused cells 2023-12-01 13:21:46 +01:00
alexmadison
51327289a7 removed sadc handshake because why would anyone instantiate sadc hs when we have a lovely neuron handshake 2023-12-01 12:13:06 +01:00
alexmadison
b2de1a45d7 removed std and acell instantiate tests in wrong folder, and they are old, acells do not have x1 etc 2023-12-01 12:09:44 +01:00
alexmadison
a0480b0369 removed texel_singlecore: is never used, and is a simplification of dualcore 2023-12-01 12:06:10 +01:00
alexmadison
d0717fbea8 removed texel chip tests with write-only registers 2023-12-01 12:05:30 +01:00
alexmadison
1c4206b7d4 added note 2023-12-01 11:52:55 +01:00
alexmadison
dbad8816a9 renamed decoder dly test to be include dly 2023-12-01 11:40:11 +01:00
alexmadison
9e7b1cd120 fixed std instaitate test by just copying the async instantiate test 2023-12-01 11:22:34 +01:00
alexmadison
ca3a56572d got rid of flip flop reg tests 2023-12-01 11:05:31 +01:00
alexmadison
627caf1aed removed texel small, super old 2023-12-01 11:01:18 +01:00
alexmadison
7e2ae21098 removed texel slim registers, is literally same as texel glue but with less registers, test.prs targets regs that dont exist?? 2023-12-01 10:58:38 +01:00
alexmadison
8cc3c14f83 removed unused texel_in30 instantaitions 2023-12-01 10:55:32 +01:00
alexmadison
e4fbc508af removed unused test and object 2023-11-21 16:17:58 +01:00
alexmadison
99b1d8caaf fixed test 2023-11-21 16:07:52 +01:00
alexmadison
c336e37377 fixed unit tests 2023-11-21 15:59:00 +01:00
alexmadison
bd56ac71e1 fixed register wr array tests 2023-11-21 15:55:15 +01:00
alexmadison
e7158ca2a9 fixed unit test 2023-11-21 15:54:35 +01:00
alexmadison
51010a6095 removed tests of non-A-cell registers 2023-11-21 15:54:11 +01:00
alexmadison
5eb77108ab fixed test 2023-11-21 15:41:57 +01:00
alexmadison
96042d3bea fixed test 2023-11-21 14:49:07 +01:00
alexmadison
023da63c73 removed test because its a stupid component 2023-11-21 14:33:12 +01:00
557 changed files with 358 additions and 965246 deletions
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4
README.md
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@ -1,3 +1,7 @@
# ARCHIVED REPOSITORY
further development and new versions => https://github.com/async-ic/actlib-neurosynaptic-perifery
# A dataflow template library for mixed signal neuromoric processors
the library will be installed in `$ACT_HOME/act/tmpl/dataflow_neuro`.

60
dataflow_neuro/cell_lib_async_test.act
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@ -1,60 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_async.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "cell_lib_async.act";
open tmpl::dataflow_neuro;
A_1C1P2N_RB_X1 cell1;
A_1C1P2N_R_X1 cell2;
A_1C1P_1N_X1 cell3;
A_1C1P_B cell4;
A_1C1P cell5;
A_1C2P1N_X1 cell6;
A_1C2P_B_X1 cell7;
A_1C2P cell8;
A_1C3P2P2N_R_X1 cell9;
A_2C2N2N_RB_X1 cell10;
A_2C2N2N_RB_X2 cell11;
A_2C2N2N_RB_X4 cell12;
A_2C2N2N_R_X1 cell13;
A_2C2N_R_B_X2 cell14;
A_2C2N_R_B_X4 cell15;
A_2C2N_R_X1 cell16;
A_2C_B_X1 cell17;
A_2C_RB_X1 cell18;
A_2C_R_X1 cell19;
A_2C_X1 cell20;
A_3C_RB_X1 cell21;
A_3C_RB_X2 cell22;
A_3C_RB_X4 cell23;
A_3C_R_X1 cell24;
A_3C_X1 cell25;
A_4C_RB_X1 cell26;
A_4C_RB_X2 cell27;
A_4C_RB_X4 cell28;
A_4C_R_X1 cell29;
A_4P1N1N_B_X1 cell30;
A_4P1N1N_X1 cell31;

58
dataflow_neuro/cell_lib_std_test.act
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@ -1,58 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Alex Madison
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "cell_lib_std.act";
open std_cell_template::dataflow_neuro;
TIELO_X1 cell1;
TIEHI_X1 cell2;
INV_X1 cell4;
INV_X2 cell5;
INV_X4 cell6;
INV_X8 cell7;
CLKBUF1 cell8;
CLKBUF2 cell9;
CLKBUF3 cell10;
NOR2_X1 cell11;
NOR3_X1 cell12;
OR2_X1 cell13;
OR2_X2 cell14;
NAND2_X1 cell15;
NAND3_X1 cell16;
AND2_X1 cell17;
AND2_X2 cell18;
XOR2_X1 cell19;
XNOR2_X1 cell20;
MUX2_X1 cell25;
OAI21_X1 cell26;
AOI21_X1 cell27;
OAI22_X1 cell28;
AOI22_X1 cell29;
TBUF1_X1 cell30;
TBUF_X2 cell31;

82
dataflow_neuro/chips.act
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@ -300,88 +300,6 @@ defproc texel_core (avMx1of2<N_IN> in, out;
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_singlecore (bd<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
// a1of1 synapses[N_SYN_X * N_SYN_Y];
// a1of1 neurons[N_NRN_X * N_NRN_Y];
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// Onwards to core
fifo<N_IN,N_BUFFERS> fifo_fork2core(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core(.in = fifo_fork2core.out,
.reg_data = reg_data,
// .synapses = synapses,
// .neurons = neurons,
.nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
.syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
.syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
.syn_mon_AMZO = syn_mon_AMZO, .nrn_mon_AMZO = nrn_mon_AMZO,
.syn_flags_EFO = syn_flags_EFO, .nrn_flags_EFO = nrn_flags_EFO,
.reset_B = _reset_BX,
.supply = supply
);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_core2mrg(.in = core.out,
.reset_B = _reset_BX, .supply = supply);
// merge core output and loopback
merge<N_IN> merge_drop8core(.in1 = fifo_core2mrg.out, .in2 = fifo_drop2mrg.out,
.supply = supply, .reset_B = _reset_BX);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = merge_drop8core.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
export template<pint N_IN, // Size of input data from outside world

467
dataflow_neuro/chips_noread.act
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@ -1,467 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
REG_NCA, REG_NCW, REG_M>
defproc texel_core (avMx1of2<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
// Dummy synapses and neurons in the handshake blocks
// should be removed pre-innovus, else they are floating.
// a1of1 synapses[N_SYN_X * N_SYN_Y];
// a1of1 neurons[N_NRN_X * N_NRN_Y];
// Synapse decoder stuff
// The analogue core and connects to these to replace the above synapses.
bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
bool? dec_ackB[N_SYN_X];
a1of1 syn_pu[N_SYN_X];
// Neuron encoder stuff
a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
// Monitors and flags to/from core, and selected mon out.
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI;
bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful
// Onwards
fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
// Register
slice_data<N_IN-1, 0,REG_NCW+REG_NCA> slice_pre_reg(.in = _demux.out2, .supply = supply);
fifo<REG_NCW+REG_NCA,N_BUFFERS> fifo_dmx2reg(.in = slice_pre_reg.out, .reset_B = _reset_BX, .supply = supply);
register_w_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
.supply = supply, .reset_B = reset_reg_B);
// Spike Decoder
pint NC_SYN;
NC_SYN = NC_SYN_X + NC_SYN_Y;
slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
.ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
.out_req_x = dec_req_x, .out_req_y = dec_req_y,
.to_pu = syn_pu,
.in_ackB_decoder = dec_ackB,
.supply = supply, .reset_B = _reset_BX);
INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG];
(i:N_SYN_DLY_CFG:
dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
dly_cfg_inverters[i].vdd = supply.vdd;
dly_cfg_inverters[i].vss = supply.vss;
decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
)
// Synapse handshake circuits, to be removed for innovus
// decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
// .synapses = synapses,
// .in_req_x = dec_req_x, .in_req_y = dec_req_y,
// .to_pu = syn_pu,
// .out_ackB_decoder = dec_ackB,
// .supply = supply);
// Neurons + encoder
pint NC_NRN;
NC_NRN = NC_NRN_X + NC_NRN_Y;
encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
.inx = enc_inx, .iny = enc_iny,
.reset_B = _reset_BX, .supply = supply,
.to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
.reset_B = _reset_BX, .supply = supply);
// Neuron handshake circuits, to be removed for innovus
// nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
// .outx = enc_inx, .outy = enc_iny,
// .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
// .supply = supply, .reset_B = _reset_BX);
// Merge
append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
// Output
fifo<N_IN, N_BUFFERS> fifo_out(.in = append_enc.out, .out = out,
.reset_B = _reset_BX, .supply = supply);
// Neuron/synapse monitor targeters
pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
nrn_mon_dec_x.en = register.data[1].d[0].t;
(i:NC_NRN_MON_X:
nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
)
sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
nrn_mon_dec_y.en = register.data[1].d[0].t;
(i:NC_NRN_MON_Y:
nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
)
sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
.supply = supply);
syn_mon_dec_x.en = register.data[1].d[1].t;
(i:NC_SYN_MON_X:
syn_mon_dec_x.in.d[i] = register.data[3].d[i];
)
sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
syn_mon_dec_y.en = register.data[1].d[1].t;
(i:NC_SYN_MON_Y:
syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
)
sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
// Stops the possibility of dev_mon being high while some other sig is high.
// Otherwise boom.
// Also the 4th monitor line to each synapse is active LOW, needs inverter.
bool DEV_DEBUG;
pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
.supply = supply);
DEV_DEBUG = sb_DEV_DEBUG.out[0];
INV_X1 syn_targ_set_high_inv[NSMX4];
[NSMX4 >= 1 ->
AND2_X1 ands_devmon[NSMX4];
(i:NSMX4:
ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
ands_devmon[i].b = DEV_DEBUG;
ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
ands_devmon[i].vdd = supply.vdd;
ands_devmon[i].vss = supply.vss;
syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
syn_targ_set_high_inv[i].vdd = supply.vdd;
syn_targ_set_high_inv[i].vss = supply.vss;
)
// Wire up the remaining lines.
(i:N_SYN_MON_X:
[(~(i%4 = 1)) & (~(i%4=3))->
syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
]
)
]
// Create TBUFs for each synapse column,
// ctrl wired to mon line (first in each 4).
TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_SYN:
(i:N_SYN_X:
index = i*N_MON_AMZO_PER_SYN + j;
syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
)
syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
syn_AMZO_keeps[j].vdd = supply.vdd;
syn_AMZO_keeps[j].vss = supply.vss;
)
// Create TBUFs for each neuron column, and add keeps.
// ctrl wired to mon line (first in each 4).
TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_NRN:
(i:N_NRN_X:
index = i*N_MON_AMZO_PER_NRN + j;
nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
)
nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
nrn_AMZO_keeps[j].vdd = supply.vdd;
nrn_AMZO_keeps[j].vss = supply.vss;
)
// Create buffered signals from register to nrns.
sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
(i:N_FLAGS_PER_NRN:
sb_nrn_EFO.in[i] = register.data[5].d[i].t;
)
// Create buffered signals from register to synapses.
// Includes safety on the first 3 flags with dev mon.
sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
(i:3..N_FLAGS_PER_SYN-1:
sb_syn_EFO.in[i] = register.data[4].d[i].t;
)
AND2_X1 syn_flags_dev_safety[3];
(i:0..2:
syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
syn_flags_dev_safety[i].vdd = supply.vdd;
syn_flags_dev_safety[i].vss = supply.vss;
)
// Create non-buffered reset signals for the neuron/syn handshakes
// Since sigs are buffered before each neuron.
sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
}
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI
){
// Reset buffers
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// Onwards to core demux
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
// Cores
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core1(.in = fifo_dmx2core1.out,
.reg_data = c1_reg_data,
// .synapses = c1_synapses,
// .neurons = c1_neurons,
.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
.dec_ackB = c1_dec_ackB,
.syn_pu = c1_syn_pu,
.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
.reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
.supply = supply
);
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core2(.in = fifo_dmx2core2.out,
.reg_data = c2_reg_data,
// .synapses = c2_synapses,
// .neurons = c2_neurons,
.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
.dec_ackB = c2_dec_ackB,
.syn_pu = c2_syn_pu,
.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
.reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
.supply = supply
);
fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
// Merge cores
append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
.supply = supply, .reset_B = _reset_BX);
// Merge cores and loopback
merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
.reset_B = _reset_BX, .supply = supply);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
}
}

187
dataflow_neuro/coders.act
View File

@ -147,23 +147,6 @@ defproc decoder_dualrail_refresh (Mx1of2<Nc> in; bool? out[N]; Mx1of2<Nc> final_
)
}
/**
* Dualrail decoder with buffered outputs.
* Be careful of out[] indexing.
*/
export template<pint Nc, N, OUT_STRENGTH>
defproc decoder_dualrail_x(Mx1of2<Nc> in; bool? out[N]; power supply) {
decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
sigbuf<OUT_STRENGTH> sb[N];
(i:N:
sb[i].in = decoder.out[i];
sb[i].supply = supply;
sb[i].out[0] = out[i];
// (j:OUT_STRENGTH:
// sb[i].out[j] = out[j + i*OUT_STRENGTH];
// )
)
}
/**
* Dualrail decoder with on/off switch.
@ -210,6 +193,9 @@ defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
/**
* @TODO check that this is definitely exactly the same as hybrid, maybe keep
*
*
* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
* Nx is the x size of the decoder array
* NxC is the number of wires in the x channel.
@ -279,6 +265,12 @@ defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
/**
* @TODO if this is going to be released, we should expose the to_pd terminals
* and probably buffer them the same
* like we did in the encoder or the hybrid
* Also we should probably keep the outs to be Nx x lines and Ny y lines,
* not Nx*Ny and-ed lines.
*
* 2D decoder which uses synapse handshaking using line pulldowns.
* Nx is the x size of the decoder array
* NxC is the number of wires in the x channel.
@ -694,67 +686,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
/**
* Buffer function code.
* Is the function block ripped from the buffer_s.
* Used in the encoder2d.
*/
export template<pint N>
defproc buffer_s_func (Mx1of2<N> in; avMx1of2<N> out; bool? in_v, en, reset_B; power supply) {
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N], _in_vX;
// bool _in_vXX_t[N],_in_vXX_f[N];
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
// reset buffers
bool _reset_BX,_reset_BXX[N*2];
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// Enable signal buffers
sigbuf<N> en_buf_t(.in=en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=en, .out=_en_X_f, .supply=supply);
// out ack signal buffers
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
// in val signal buffers
BUF_X4 in_v_prebuf(.a = in_v, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
// sigbuf<N> in_v_buf_t(.in=_in_vX, .out=_in_vXX_t, .supply=supply);
// sigbuf<N> in_v_buf_f(.in=_in_vX, .out=_in_vXX_f, .supply=supply);
sigbuf<N*2> in_v_buf(.in=_in_vX,.supply=supply);
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=in.d[i].f;
t_buf_func[i].n1=in.d[i].t;
f_buf_func[i].n2=in_v_buf.out[i];
t_buf_func[i].n2=in_v_buf.out[i+N];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
export
defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
{
@ -1110,6 +1041,106 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
}
/**
* 2D decoder which uses either synapse handshaking, or just a delay.
* Controlled by the "hs_en" (handshake_enable) config bit.
* hs_en = 0 -> use delayed version.
* hs_en = 1 -> use synapse handshaking.
* Regardless of which version is used, the final ack going to the buffer
* goes through the prog_delay block.
* Thus, for the handshaking version to be used "correctly",
* dly_cfg should be set to all zeros.
* ack_disable blocks the ack being returned to the buffer.
* Is needed in case there are instabilities while we fiddle with delays.
*/
// @TODO : think hard about the fact that the line end pullups are not placed manually,
// and write argumentation about whether this is fine
export template<pint N>
defproc decoder_1d (avMx1of2<std::ceil_log2(N)> in; a1of1 out[N];
bool? reset_B; power supply) {
// Buffer to recieve concat address packet
buffer<std::ceil_log2(N)> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// Decoder And tree
decoder_dualrail_refresh<std::ceil_log2(N),N> d_dr(.supply = supply);
(i:0..std::ceil_log2(N)-1:d_dr.in.d[i] = addr_buf.out.d.d[i];)
(i:0..N-1: d_dr.out[i] = out[i].r;)
// Validity
vtree<std::ceil_log2(N)> vtree (.in = d_dr.final_refresh, .supply = supply);
vtree.out = addr_buf.out.v;
// ORtree from all output acks, back to the buffer ack.
// This is instead of the ack that came from the delayed validity trees,
// in decoder_2d_dly.
ortree<N> _ortree(.supply = supply);
(i:N:
_ortree.in[i] = out[i].a;
)
_ortree.out = addr_buf.out.a;
}
export template<pint N, W>
defproc demux_qdi2bd_1d (avMx1of2<std::ceil_log2(N)+W> in; rbd<W> out[N];
bool? reset_B; power supply) {
// Added by Paolo, to be checked
buffer<std::ceil_log2(N) + W> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
//stop added
sigbuf<N+1> data_t[W];
(i:0..W-1:
data_t[i].in = addr_buf.out.d.d[std::ceil_log2(N) + i].t;
(j:0..N-1:
data_t[i].out[j] = out[j].d.d[0];
)
data_t.supply = supply;
)
// Buffer to recieve concat address packet
buffer<std::ceil_log2(N)+W> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// Decoder And tree
decoder_dualrail_refresh<std::ceil_log2(N),N> d_dr(.supply = supply);
(i:0..std::ceil_log2(N)-1:d_dr.in.d[i] = addr_buf.out.d.d[i];)
(i:0..N-1: d_dr.out[i] = out[i].r;)
// Validity
vtree<std::ceil_log2(N)> vtree (.in = d_dr.final_refresh, .supply = supply);
vtree<W> vtree_data (.supply = supply);
(i:0..W-1:
vtree_data.in[i].t = addr_buf.d.d[i+std::ceil_log2(N)].t;
vtree_data.in[i].f = data_t[i].out[N];
)
A_2C_B_X1 valid_Cel(.c1 = vtree.out, .c2 = vtree_data.out, .y = addr_buf.out.v,
.vdd = supply.vdd, .vss = supply.vss);
// ORtree from all output acks, back to the buffer ack.
// This is instead of the ack that came from the delayed validity trees,
// in decoder_2d_dly.
ortree<N> _ortree(.supply = supply);
(i:N:
_ortree.in[i] = out[i].a;
)
_ortree.out = addr_buf.out.a;
}
}
}

66
dataflow_neuro/dynapse.act
View File

@ -1,66 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
export
defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
bool _en;
bool _out_a_B;
INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
A_1C1P_X1 A_en(.c1 = in.a, .p1 = out.r, .y = _en,
.vdd = supply.vdd, .vss = supply.vss);
}
}
}

27
dataflow_neuro/treegates.act
View File

@ -449,33 +449,6 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
(i:1..N-1:out[i]=out[0];)
}
//Sigbuf in which there is only 1 output. Made for outputs that cannot have multiple wires.
export template<pint N>
defproc sigbuf_1output (bool? in; bool! out; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
{ N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 5 & N <= 7 ->
BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 8 & N <= 10 ->
BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 11 & N <= 14 ->
BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 15 & N <= 18 ->
BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N <= 42 ->
BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
]
}
}}

30
test/unit_tests/flipflop/test.act → test/unit_tests/demux_qdi2bd_1d/test.act
View File

@ -3,10 +3,8 @@
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
* Copyright (c) 2024 University of Groningen - Ole Richter
* Copyright (c) 2024 University of Groningen - Paolo Gibertini
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
@ -26,25 +24,31 @@
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc flipflop_test (bool! q; bool? d,clk){
bool _clk_B;
DFFQ_R_X1 ff(.d=d,.clk_B = _clk_B, .q = q);
defproc demux_qdi2bd_1d_test (avMx1of2<4> in; rbd<4> out[15]){
demux_qdi2bd_1d<15, 4> decoder_test(.in=in, .out=out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
clk => _clk_B-
}
ff.vss = GND;
ff.vdd = Vdd;
ff.reset_B = _reset_B;
decoder_test.supply.vss = GND;
decoder_test.supply.vdd = Vdd;
decoder_test.reset_B = _reset_B;
}
flipflop_test t;
demux_qdi2bd_1d_test t;

73
test/unit_tests/demux_qdi2bd_1d/test.prsim Normal file
View File

@ -0,0 +1,73 @@
set-qdi-channel-neutral "t.in" 4
set t.out[0].a 0
set t.out[1].a 0
set t.out[2].a 0
set t.out[3].a 0
set t.out[4].a 0
set t.out[5].a 0
set t.out[6].a 0
set t.out[7].a 0
set t.out[8].a 0
set t.out[9].a 0
set t.out[10].a 0
set t.out[11].a 0
set t.out[12].a 0
set t.out[13].a 0
set t.out[14].a 0
cycle
system "echo 'reset start'"
set Reset 0
cycle
system "echo 'reset completed'"
status X
mode run
assert-bd-channel-neutral "t.out[0]" 4
assert-bd-channel-neutral "t.out[1]" 4
assert-bd-channel-neutral "t.out[2]" 4
assert-bd-channel-neutral "t.out[3]" 4
assert-bd-channel-neutral "t.out[4]" 4
assert-bd-channel-neutral "t.out[5]" 4
assert-bd-channel-neutral "t.out[6]" 4
assert-bd-channel-neutral "t.out[7]" 4
assert-bd-channel-neutral "t.out[8]" 4
assert-bd-channel-neutral "t.out[9]" 4
assert-bd-channel-neutral "t.out[10]" 4
assert-bd-channel-neutral "t.out[11]" 4
assert-bd-channel-neutral "t.out[12]" 4
assert-bd-channel-neutral "t.out[13]" 4
assert-bd-channel-neutral "t.out[14]" 4
cycle
set-qdi-channel-valid "t.in" 4 5
cycle
assert t.in.v 1
assert-bd-channel-valid "t.out[0]" 4 0
set t.out[5].a 1
cycle
assert t.in.a 1
set-qdi-channel-neutral "t.in" 4
cycle
assert t.out[5].r 0
set t.in.a 0
cycle
assert-bd-channel-neutral "t.out[0]" 4
assert-bd-channel-neutral "t.out[1]" 4
assert-bd-channel-neutral "t.out[2]" 4
assert-bd-channel-neutral "t.out[3]" 4
assert-bd-channel-neutral "t.out[4]" 4
assert-bd-channel-neutral "t.out[5]" 4
assert-bd-channel-neutral "t.out[6]" 4
assert-bd-channel-neutral "t.out[7]" 4
assert-bd-channel-neutral "t.out[8]" 4
assert-bd-channel-neutral "t.out[9]" 4
assert-bd-channel-neutral "t.out[10]" 4
assert-bd-channel-neutral "t.out[11]" 4
assert-bd-channel-neutral "t.out[12]" 4
assert-bd-channel-neutral "t.out[13]" 4
assert-bd-channel-neutral "t.out[14]" 4
system "echo 'Finished'"

0
test/unit_tests/fifo-decoder-neurons-encoder-fifo/test.act → test/unit_tests/fifo-decoder_dly-neurons-encoder-fifo/test.act
View File

0
test/unit_tests/fifo-decoder-neurons-encoder-fifo/test.prsim → test/unit_tests/fifo-decoder_dly-neurons-encoder-fifo/test.prsim
View File

55
test/unit_tests/flipflop/run/prsim.out
View File

@ -1,55 +0,0 @@
t.ff.__clk_B t.ff._clk_B t.d t.clk t._clk_B
[0] start test
15221 Reset : 0
15221 t.clk : 0
15221 t.d : 0
16947 t._clk_B : 1 [by t.clk:=0]
16986 t.ff._clk_B : 0 [by t._clk_B:=1]
17001 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
80587 t._reset_B : 1 [by Reset:=0]
[1] reset completed
[2] tested d = 0, clk rise
80587 t.clk : 1
80587 t.d : 1
80600 t.ff._mqib : 0 [by t.d:=1]
80640 t.ff._mqi : 1 [by t.ff._mqib:=0]
81078 t._clk_B : 0 [by t.clk:=1]
81493 t.ff._clk_B : 1 [by t._clk_B:=0]
81513 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
87554 t.ff._sqib : 0 [by t.ff._clk_B:=1]
87570 t.q : 1 [by t.ff._sqib:=0]
87601 t.ff._sqi : 1 [by t.ff._sqib:=0]
131668 t.ff.q_B : 0 [by t.q:=1]
131668 t.clk : 0
145392 t._clk_B : 1 [by t.clk:=0]
145396 t.ff._clk_B : 0 [by t._clk_B:=1]
154525 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
154525 t.d : 0
154540 t.ff._mqib : 1 [by t.d:=0]
197788 t.ff._mqi : 0 [by t.ff._mqib:=1]
197788 t.clk : 1
234719 t._clk_B : 0 [by t.clk:=1]
234774 t.ff._clk_B : 1 [by t._clk_B:=0]
286427 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
316207 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
330056 t.ff._sqi : 0 [by t.ff._sqib:=1]
341019 t.q : 0 [by t.ff._sqib:=1]
355362 t.ff.q_B : 1 [by t.q:=0]
355362 t.clk : 0
355784 t._clk_B : 1 [by t.clk:=0]
404498 t.ff._clk_B : 0 [by t._clk_B:=1]
404499 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
404499 t.d : 1
404500 t.ff._mqib : 0 [by t.d:=1]
424705 t.ff._mqi : 1 [by t.ff._mqib:=0]
[3] tested d = 1, clk rise and fall
424705 t.clk : 1
424987 t._clk_B : 0 [by t.clk:=1]
425755 t.ff._clk_B : 1 [by t._clk_B:=0]
425758 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
448196 t.ff._sqib : 0 [by t.ff._clk_B:=1]
448747 t.ff._sqi : 1 [by t.ff._sqib:=0]
449267 t.q : 1 [by t.ff._sqib:=0]
450221 t.ff.q_B : 0 [by t.q:=1]
450221 t.d : 0

29
test/unit_tests/flipflop/run/test.prs
View File

@ -1,29 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+
"t.clk"->"t._clk_B"-
~("t.clk")->"t._clk_B"+
= "t._reset_B" "t.ff.reset_B"
"t.ff.clk_B"->"t.ff._clk_B"-
~("t.ff.clk_B")->"t.ff._clk_B"+
"t.ff._clk_B"->"t.ff.__clk_B"-
~("t.ff._clk_B")->"t.ff.__clk_B"+
~"t.ff.d"&~"t.ff._clk_B"|~"t.ff.reset_B"|~"t.ff.__clk_B"&~"t.ff._mqi"->"t.ff._mqib"+
("t.ff.d"&"t.ff.__clk_B"|"t.ff._mqi"&"t.ff._clk_B")&"t.ff.reset_B"->"t.ff._mqib"-
"t.ff._mqib"->"t.ff._mqi"-
~("t.ff._mqib")->"t.ff._mqi"+
~"t.ff._mqi"&~"t.ff.__clk_B"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk_B"->"t.ff._sqib"+
("t.ff._mqi"&"t.ff._clk_B"|"t.ff._sqi"&"t.ff.__clk_B")&"t.ff.reset_B"->"t.ff._sqib"-
"t.ff._sqib"->"t.ff._sqi"-
~("t.ff._sqib")->"t.ff._sqi"+
"t.ff._sqib"->"t.ff.q"-
~("t.ff._sqib")->"t.ff.q"+
"t.ff.q"->"t.ff.q_B"-
~("t.ff.q")->"t.ff.q_B"+
= "Vdd" "t.ff.vdd"
= "GND" "t.ff.vss"
= "t.q" "t.ff.q"
= "t._clk_B" "t.ff.clk_B"
= "t.d" "t.ff.d"

51
test/unit_tests/flipflop/test.prsim
View File

@ -1,51 +0,0 @@
watchall
system "echo '[0] start test'"
set Reset 0
set t.d 0
set t.clk 0
cycle
status X
mode run
assert t.q 0
system "echo '[1] reset completed'"
system "echo '[2] tested d = 0, clk rise'"
set t.clk 1
set t.d 1
cycle
set t.clk 0
cycle
set t.d 0
cycle
assert t.q 1
set t.clk 1
cycle
assert t.q 0
set t.d 0
set t.clk 0
cycle
assert t.q 0
set t.d 1
cycle
set t.clk 0
cycle
assert t.q 0
system "echo '[3] tested d = 1, clk rise and fall'"
set t.d 1
cycle
set t.clk 1
cycle
set t.d 0
cycle
assert t.q 1

48
test/unit_tests/line_end_pull_up/test.act
View File

@ -1,48 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc lepu (a1of1 in; bool! out){
line_end_pull_up lepu(.in=in, .out=out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
lepu.supply.vss = GND;
lepu.supply.vdd = Vdd;
lepu.reset_B = _reset_B;
}
lepu t;

15
test/unit_tests/line_end_pull_up/test.prsim
View File

@ -1,15 +0,0 @@
watchall
set t.in.a 0
cycle
system "echo 'yo man'"
set Reset 0
cycle
set t.in.a 1
cycle
assert t.out 1

47
test/unit_tests/nrn_hs_2D_array_3x5/test.act
View File

@ -31,16 +31,43 @@ import globals;
open tmpl::dataflow_neuro;
defproc nrn_hs_2D_array_3x5(a1of1 in[15]; a1of1 outx[3], outy[5])
pint Nx = 3;
pint Ny = 5;
defproc nrn_hs_2d_array_3x5(a1of1 in[15]; a1of1 outx[3], outy[5])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
nrn_hs_2D_array<3,5,5> b(.in = in, .outx = outx, .outy = outy);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
power supply;
supply.vdd = Vdd;
supply.vss = GND;
bool _reset_B;
prs {
Reset => _reset_B-
}
nrn_hs_2d_array<3,5> b(.in = in, .outx = outx, .outy = outy);
b.supply = supply;
b.reset_B = _reset_B;
nrn_line_end_pull_down pd_x[Nx], pd_y[Ny];
(i:Nx:
pd_x[i].in = b.to_pd_x[i].a;
pd_x[i].out = b.to_pd_x[i].r;
pd_x[i].supply = supply;
pd_x[i].reset_B = _reset_B;
)
(i:Ny:
pd_y[i].in = b.to_pd_y[i].a;
pd_y[i].out = b.to_pd_y[i].r;
pd_y[i].supply = supply;
pd_y[i].reset_B = _reset_B;
)
}
nrn_hs_2D_array_3x5 b;
nrn_hs_2d_array_3x5 b;

20
test/unit_tests/nrn_hs_2D_array_3x5/test.prsim
View File

@ -26,18 +26,18 @@ set b.outy[2].a 0
set b.outy[3].a 0
set b.outy[4].a 0
set b.outx[0].r 1
set b.outx[1].r 1
set b.outx[2].r 1
# set b.outx[0].r 1
# set b.outx[1].r 1
# set b.outx[2].r 1
set b.outy[0].r 1
set b.outy[1].r 1
set b.outy[2].r 1
set b.outy[3].r 1
set b.outy[4].r 0
# set b.outy[0].r 1
# set b.outy[1].r 1
# set b.outy[2].r 1
# set b.outy[3].r 1
# set b.outy[4].r 0
set b.b.neurons[0]._en 0
set b.b.neurons[0]._req 1
# set b.b.neurons[0]._en 0
# set b.b.neurons[0]._req 1
# set Reset 0
cycle

35
test/unit_tests/nrn_hs_2d/test.act
View File

@ -33,14 +33,33 @@ open tmpl::dataflow_neuro;
defproc nrn_hs_2d_inst(a1of1 in; a1of1 outx, outy)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
nrn_hs_2d b(.in = in, .outx = outx, .outy = outy);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
power supply;
supply.vdd = Vdd;
supply.vss = GND;
bool _reset_B;
prs {
Reset => _reset_B-
}
nrn_hs_2d b(.in = in, .outx = outx, .outy = outy,
.supply = supply, .reset_B = _reset_B);
nrn_line_end_pull_down pd_x;
pd_x.in = b.outx.a;
pd_x.out = b.outx.r;
pd_x.supply = supply;
pd_x.reset_B = _reset_B;
nrn_line_end_pull_down pd_y;
pd_y.in = b.outy.a;
pd_y.out = b.outy.r;
pd_y.supply = supply;
pd_y.reset_B = _reset_B;
}
nrn_hs_2d_inst b;

212
test/unit_tests/nrn_hs_2d/test.prsim
View File

@ -1,202 +1,76 @@
watchall
set b.in[0].r 0
set b.in[1].r 0
set b.in[2].r 0
set b.in[3].r 0
set b.in[4].r 0
set b.in[5].r 0
set b.in[6].r 0
set b.in[7].r 0
set b.in[8].r 0
set b.in[9].r 0
set b.in[10].r 0
set b.in[11].r 0
set b.in[12].r 0
set b.in[13].r 0
set b.in[14].r 0
set b.in.r 0
set b.outx[0].a 0
set b.outx[1].a 0
set b.outx[2].a 0
set b.outy[0].a 0
set b.outy[1].a 0
set b.outy[2].a 0
set b.outy[3].a 0
set b.outy[4].a 0
set b.outx[0].r 1
set b.outx[1].r 1
set b.outx[2].r 1
set b.outy[0].r 1
set b.outy[1].r 1
set b.outy[2].r 1
set b.outy[3].r 1
set b.outy[4].r 0
set b.b.neurons[0]._en 0
set b.b.neurons[0]._req 1
# set Reset 0
cycle
set b.outx.a 0
set b.outy.a 0
system "echo '[] set Reset 1'"
set Reset 1
cycle
status X
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] Neurons 0,1,3 spike'"
set b.in[0].r 1
set b.in[1].r 1
set b.in[3].r 1
# spike
set b.in.r 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outx.r 0
assert b.outy.r 1
assert b.in.a 1
assert b.outy[0].r 1
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
assert b.in[0].a 1
assert b.in[1].a 1
assert b.in[3].a 1
system "echo '[] removing in reqs'"
set b.in[0].r 0
set b.in[1].r 0
set b.in[3].r 0
set b.in.r 0
set b.outy.a 1
cycle
assert b.in[0].a 0
assert b.in[1].a 0
assert b.in[3].a 0
assert b.outx.r 1
assert b.in.a 0
system "echo '[] y0 chosen, give ack'"
set b.outy[0].a 1
# send in another spike while its still dealing with previous
set b.in.r 1
cycle
assert b.outx[0].r 1
assert b.outx[1].r 1
assert b.outx[2].r 0
assert b.outx.r 1
assert b.outy.r 0
assert b.in.a 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] x0 chosen, give ack'"
set b.outx[0].a 1
set b.outx.a 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 1
assert b.outx[2].r 0
assert b.outx.r 0
assert b.outy.r 0
assert b.in.a 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] remove x ack'"
set b.outx[0].a 0
set b.outx.a 0
set b.outy.a 0
cycle
assert b.outx[0].r 0
assert b.outx[1].r 1
assert b.outx[2].r 0
assert b.outy.r 1
assert b.outx.r 0
assert b.in.a 1
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] x1 remaining, give ack'"
set b.outx[1].a 1
set b.in.r 0
set b.outy.a 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outx.r 1
assert b.outy.r 0
assert b.in.a 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] remove acks'"
set b.outx[1].a 0
set b.outy[0].a 0
set b.outx.a 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outx.r 0
assert b.outy.r 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] y1 remaining, give ack'"
set b.outy[1].a 1
set b.outx.a 0
set b.outy.a 0
cycle
assert b.outx[0].r 1
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] x0 req, give ack'"
set b.outx[0].a 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
assert b.outx.r 0
assert b.outy.r 0
assert b.in.a 0
system "echo '[] remove acks'"
set b.outx[0].a 0
set b.outy[1].a 0
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0

2
test/unit_tests/registerA_w/test.act
View File

@ -44,7 +44,7 @@ defproc registerA_w (avMx1of2<8> in; Mx1of2<7> out){
supply.vdd = Vdd;
supply.vss = GND;
registerA<7> b(.in = in, .out = out, .reset_B = _reset_B, .supply = supply);
register_acells_improved<7> b(.in = in, .out = out, .reset_B = _reset_B, .supply = supply);
}

4
test/unit_tests/registerA_w_array/test.act
View File

@ -35,7 +35,7 @@ open std::data;
open tmpl::dataflow_neuro;
defproc registerA_w_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]){
defproc registerA_w_array_3x5x8 (avMx1of2<3+5> in; Mx1of2<5> data[8]){
bool _reset_B;
prs {
Reset => _reset_B-
@ -46,7 +46,7 @@ defproc registerA_w_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]){
// Make a register array with 3 bit address (-> 8 registers),
// each register holding 5 bits.
registerA_w_array<3,5,8> b(.in = in, .data = data, .reset_B = _reset_B, .supply = supply);
register_w_array<3,5,8> b(.in = in, .data = data, .reset_B = _reset_B, .supply = supply);
}

42
test/unit_tests/registerA_w_array/test.prsim
View File

@ -1,6 +1,6 @@
watchall
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
@ -13,42 +13,42 @@ assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending packet write 0s to reg0'"
set-qdi-channel-valid "b.in" 9 256
set-qdi-channel-valid "b.in" 8 256
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.data[0]" 5 0
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.data[0]" 5 0
system "echo '[] Sending packet write 0s to reg0'"
set-qdi-channel-valid "b.in" 9 256
set-qdi-channel-valid "b.in" 8 256
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.data[0]" 5 0
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.data[0]" 5 0
system "echo '[] Sending packet write 01100 to reg0'"
set-qdi-channel-valid "b.in" 9 352
set-qdi-channel-valid "b.in" 8 352
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.data[0]" 5 12
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
@ -56,88 +56,88 @@ assert-var-int "b.data[0]" 5 12
system "echo '[] Sending packet write 0s to reg1'"
set-qdi-channel-valid "b.in" 9 257
set-qdi-channel-valid "b.in" 8 257
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.data[1]" 5 0
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending packet write 0s to reg2'"
set-qdi-channel-valid "b.in" 9 258
set-qdi-channel-valid "b.in" 8 258
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.data[2]" 5 0
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.data[2]" 5 0
system "echo '[] Sending packet write 0s to reg3'"
set-qdi-channel-valid "b.in" 9 259
set-qdi-channel-valid "b.in" 8 259
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending packet write 0s to reg4'"
set-qdi-channel-valid "b.in" 9 260
set-qdi-channel-valid "b.in" 8 260
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending packet write 0s to reg5'"
set-qdi-channel-valid "b.in" 9 261
set-qdi-channel-valid "b.in" 8 261
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending packet write 0s to reg6'"
set-qdi-channel-valid "b.in" 9 262
set-qdi-channel-valid "b.in" 8 262
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending packet write 0s to reg7'"
set-qdi-channel-valid "b.in" 9 263
set-qdi-channel-valid "b.in" 8 263
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 9
set-qdi-channel-neutral "b.in" 8
cycle
assert b.in.a 0
assert b.in.v 0

2
test/unit_tests/registerA_wr_array/test.act
View File

@ -46,7 +46,7 @@ defproc registerA_wr_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of
// Make a register array with 3 bit address (-> 8 registers),
// each register holding 5 bits.
registerA_wr_array<3,5,8> b(.in = in, .data = data, .out = out,
register_wr_array<3,5,8> b(.in = in, .data = data, .out = out,
.reset_B = _reset_B, .supply = supply);
}

52
test/unit_tests/register_write/test.act
View File

@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
register_w<2,2,2> registers(.in=in,.data = data);
//Low active Reset
bool _reset_B;
power _supply;
prs {
Reset => _reset_B-
}
registers.supply = _supply;
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_mem_B = _reset_B;
registers.dly_cfg = dly_cfg;
}
register_test t;

49
test/unit_tests/register_write/test.prsim
View File

@ -1,49 +0,0 @@
watchall
system "echo '[0] start test'"
set-qdi-channel-neutral "t.in" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.registers._in_write.a 0
set t.registers._in_read.a 0
set t.registers._in_write.v 0
set t.registers._in_read.v 0
set Reset 0
cycle
status X
mode run
assert-qdi-channel-neutral "t.in" 5
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
cycle
assert-qdi-channel-neutral "t.in" 5
system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 19
cycle
assert-qdi-channel-valid "t.registers._in_write" 4 3
assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
cycle
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 1
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
system "echo '[3] clock checked'"

52
test/unit_tests/register_wrw/test.act
View File

@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[3]){
register_rw<2,2,3> registers(.in=in,.data = data,.out = out);
//Low active Reset
bool _reset_B;
power _supply;
prs {
Reset => _reset_B-
}
registers.supply = _supply;
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_mem_B = _reset_B;
registers.dly_cfg = dly_cfg;
}
register_test t;

465
test/unit_tests/register_wrw/test.prsim
View File

@ -1,465 +0,0 @@
watch t.registers.clock_buffer[0].out[0]
watch t.registers.clock_buffer[1].out[0]
watch t.registers.clock_buffer[2].out[0]
watch t.registers.clock_buffer[3].out[0]
system "echo '[0] start test'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-neutral "t.in" 5
set-qdi-channel-neutral "t.out" 4
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
set t.dly_cfg[2] 1
set t.out.a 0
set t.out.v 0
cycle
set t.in.a 0
set Reset 0
cycle
assert-qdi-channel-neutral "t.in" 5
assert-qdi-channel-neutral "t.out" 4
mode run
cycle
# check delay config programming
assert t.registers.clk_dly.s[0] 1
assert t.registers.clk_dly.s[1] 1
assert t.registers.ff[0].q 0
assert t.registers.ff[1].q 0
assert t.registers.ff[2].q 0
assert t.registers.ff[3].q 0
assert t.registers.ff[4].q 0
assert t.registers.ff[5].q 0
assert t.registers.ff[6].q 0
assert t.registers.ff[7].q 0
assert-qdi-channel-neutral "t.out" 4
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-valid "t.in" 5 3
# 3 -> 00011 -> writing mode, address 00, word 11
cycle
assert t.in.a 1
assert-qdi-channel-neutral "t.out" 4
assert t.registers._in_v_temp 1
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._in_v_temp 0
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
assert t.registers.ff[2].q 0
assert t.registers.ff[3].q 0
assert t.registers.ff[4].q 0
assert t.registers.ff[5].q 0
assert t.registers.ff[6].q 0
assert t.registers.ff[7].q 0
assert t.in.v 0
set t.out.a 0
set t.out.v 0
assert t.in.a 0
cycle
assert t.registers._clock_temp_inv 1
system "echo '[3] first writing done'"
system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 16
# # 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert t.registers.word_to_read_X[0].out[0] 1
# assert t.registers.word_to_read_X[0].out[1] 1
# assert t.registers.word_to_read_X[0].out[2] 1
# assert t.registers.word_to_read_X[0].out[3] 1
# assert-qdi-channel-valid "t.out" 4 3
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 0
# assert t.registers.ff[3].q 0
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[4] reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 7
# # 7 -> 00111 -> writing mode, address 01, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 0
# assert t.registers.ff[5].q 0
# assert t.registers.ff[6].q 0
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# cycle
# assert t.registers._clock_temp_inv 1
# system "echo '[5] second writing done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 11
# # 11 -> 01011 -> writing mode, address 10, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 0
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[6] third writing done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 15
# # 15 -> 01111 -> writing mode, address 11, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 1
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[7] fourth writing done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 28
# # 28 -> 11100 -> reading mode, address 11, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert-qdi-channel-valid "t.out" 4 15
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[8] 11 reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 20
# # 20 -> 10100 -> reading mode, address 01, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert-qdi-channel-valid "t.out" 4 7
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] 01 reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 24
# # 24 -> 11000 -> reading mode, address 10, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert-qdi-channel-valid "t.out" 4 11
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[8] 10 reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 13
# # 13 -> 01101 -> writing mode, address 11, word 01
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 1
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 13 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 1
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 0 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 0 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 13 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 3
# # 13 -> 00011 -> writing mode, address 00, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"

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test/unit_tests/sadc_hs/test.act
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@ -1,67 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/dynapse.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc _sadc_hs (a1of1 in[4], out; bool? reset_B) {
power supply;
supply.vdd = Vdd;
supply.vss = GND;
// pipe loads of inputs into the sadc handshake
// to simulate a neuron going nuts
fifo_t<3> in_fifos[4];
arbtree<4> in_arbtree(.supply = supply);
(i:4:
in_fifos[i].in = in[i];
in_fifos[i].reset_B = reset_B;
in_fifos[i].out = in_arbtree.in[i];
in_fifos[i].supply = supply;
)
sadc_hs c(.in = in_arbtree.out,
.reset_B = reset_B, .supply = supply);
fifo_t<8> out_fifo(.in = c.out, .out = out,
.supply = supply, .reset_B = reset_B);
}
// fifo_decoder_neurons_encoder_fifo e;
_sadc_hs c;

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watchall
set c.reset_B 0
set c.in[0].r 0
set c.in[1].r 0
set c.in[2].r 0
set c.in[3].r 0
set c.out.a 0
cycle
status X
system "echo '[] Set reset 0'"
mode run
set c.reset_B 1
cycle
system "echo '[] Reset finished'"
status X
system "echo '[] Setting all in reqs high'"
set c.in[0].r 1
set c.in[1].r 1
set c.in[2].r 1
set c.in[3].r 1
cycle
assert c.in[0].a 1
assert c.in[1].a 1
assert c.in[2].a 1
assert c.in[3].a 1
set c.in[0].r 0
set c.in[1].r 0
set c.in[2].r 0
set c.in[3].r 0
cycle
assert c.in[0].a 0
assert c.in[1].a 0
assert c.in[2].a 0
assert c.in[3].a 0
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle

3
test/unit_tests/sigbuf_15/test.act
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@ -39,7 +39,8 @@ import globals;
open tmpl::dataflow_neuro;
defproc sigbuf_15 (bool? in; bool! out){
sigbuf<15> sigbuf_test(.in=in, .out=out);
sigbuf<15> sigbuf_test(.in=in);
sigbuf_test.out[0] = out;
sigbuf_test.supply.vss = GND;
sigbuf_test.supply.vdd = Vdd;

15
test/unit_tests/std_instantiate/test.act
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@ -28,7 +28,13 @@
import "../../dataflow_neuro/cell_lib_std.act";
open std_cell_template::dataflow_neuro;
open tmpl::dataflow_neuro;
// open actlib_dataflow_neuro::dataflow_neuro;
// namespace tmpl {
// namespace dataflow_neuro {
TIELO_X1 cell1;
TIEHI_X1 cell2;
@ -36,9 +42,9 @@ INV_X1 cell4;
INV_X2 cell5;
INV_X4 cell6;
INV_X8 cell7;
CLKBUF1 cell8;
CLKBUF2 cell9;
CLKBUF3 cell10;
// CLKBUF1 cell8;
// CLKBUF2 cell9;
// CLKBUF3 cell10;
NOR2_X1 cell11;
NOR3_X1 cell12;
OR2_X1 cell13;
@ -57,3 +63,4 @@ AOI22_X1 cell29;
TBUF1_X1 cell30;
TBUF_X2 cell31;
// }}

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-- Master.tag File, Rev:1.0
verilog.v

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0andtree_33_4(Iin0 , Iin1 , Iin2 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
output out;
// -- signals ---
wire Iin2 ;
wire Iin0 ;
wire out ;
wire Iin1 ;
// --- instances
AND3_X1 Iand3s0 (.y(out), .a(Iin0 ), .b(Iin1 ), .c(Iin2 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0andtree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
output out;
// -- signals ---
wire Iin2 ;
wire Itmp4 ;
wire Iin1 ;
wire Iin3 ;
wire out ;
wire Iin0 ;
wire Itmp5 ;
// --- instances
AND2_X1 Iand2s0 (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s1 (.y(Itmp5 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s2 (.y(out), .a(Itmp4 ), .b(Itmp5 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0andtree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
output out;
// -- signals ---
wire Iin0 ;
wire Iin1 ;
wire Itmp5 ;
wire Itmp6 ;
wire Iin3 ;
wire Iin2 ;
wire out ;
wire Iin4 ;
// --- instances
AND3_X1 Iand3s0 (.y(Itmp6 ), .a(Iin2 ), .b(Iin3 ), .c(Iin4 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s0 (.y(Itmp5 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s1 (.y(out), .a(Itmp5 ), .b(Itmp6 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0andtree_36_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
output out;
// -- signals ---
wire Iin3 ;
wire Iin2 ;
wire Itmp7 ;
wire out ;
wire Iin4 ;
wire Iin1 ;
wire Itmp6 ;
wire Itmp8 ;
wire Iin5 ;
wire Iin0 ;
// --- instances
AND3_X1 Iand3s0 (.y(out), .a(Itmp6 ), .b(Itmp7 ), .c(Itmp8 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s0 (.y(Itmp6 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s1 (.y(Itmp7 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s2 (.y(Itmp8 ), .a(Iin4 ), .b(Iin5 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0andtree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
output out;
// -- signals ---
wire out ;
wire Itmp13 ;
wire Itmp11 ;
wire Iin5 ;
wire Iin2 ;
wire Iin0 ;
wire Itmp9 ;
wire Iin4 ;
wire Itmp10 ;
wire Iin3 ;
wire Iin6 ;
wire Iin1 ;
wire Iin8 ;
wire Itmp14 ;
wire Itmp12 ;
wire Iin7 ;
// --- instances
AND3_X1 Iand3s0 (.y(Itmp12 ), .a(Iin6 ), .b(Iin7 ), .c(Iin8 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s0 (.y(Itmp9 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s1 (.y(Itmp10 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s2 (.y(Itmp11 ), .a(Iin4 ), .b(Iin5 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s3 (.y(Itmp13 ), .a(Itmp9 ), .b(Itmp10 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s4 (.y(Itmp14 ), .a(Itmp11 ), .b(Itmp12 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2s5 (.y(out), .a(Itmp13 ), .b(Itmp14 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Isupply_vss , vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iin_d_d13_d0 ;
input Iin_d_d13_d1 ;
input Iin_d_d14_d0 ;
input Iin_d_d14_d1 ;
input Iin_d_d15_d0 ;
input Iin_d_d15_d1 ;
input Iin_d_d16_d0 ;
input Iin_d_d16_d1 ;
input Iin_d_d17_d0 ;
input Iin_d_d17_d1 ;
input Iin_d_d18_d0 ;
input Iin_d_d18_d1 ;
input Iin_d_d19_d0 ;
input Iin_d_d19_d1 ;
input Iin_d_d20_d0 ;
input Iin_d_d20_d1 ;
input Iin_d_d21_d0 ;
input Iin_d_d21_d1 ;
input Iin_d_d22_d0 ;
input Iin_d_d22_d1 ;
input Iin_d_d23_d0 ;
input Iin_d_d23_d1 ;
input Iin_d_d24_d0 ;
input Iin_d_d24_d1 ;
input Iin_d_d25_d0 ;
input Iin_d_d25_d1 ;
input Iin_d_d26_d0 ;
input Iin_d_d26_d1 ;
input Iin_d_d27_d0 ;
input Iin_d_d27_d1 ;
input Iin_d_d28_d0 ;
input Iin_d_d28_d1 ;
input Iin_d_d29_d0 ;
input Iin_d_d29_d1 ;
input Iin_d_d30_d0 ;
input Iin_d_d30_d1 ;
input Isupply_vss ;
// -- signals ---
output Iout_d_d31_d0 ;
wire Iin_d_d9_d0 ;
wire Isupply_vss ;
wire Iin_d_d20_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d9_d1 ;
wire Isb_in ;
wire Iin_d_d15_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d31_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d18_d0 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
endmodule

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test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/master.tag
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@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

142
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/verilog.v
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module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Isupply_vss , vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iin_d_d13_d0 ;
input Iin_d_d13_d1 ;
input Iin_d_d14_d0 ;
input Iin_d_d14_d1 ;
input Iin_d_d15_d0 ;
input Iin_d_d15_d1 ;
input Iin_d_d16_d0 ;
input Iin_d_d16_d1 ;
input Iin_d_d17_d0 ;
input Iin_d_d17_d1 ;
input Iin_d_d18_d0 ;
input Iin_d_d18_d1 ;
input Iin_d_d19_d0 ;
input Iin_d_d19_d1 ;
input Iin_d_d20_d0 ;
input Iin_d_d20_d1 ;
input Iin_d_d21_d0 ;
input Iin_d_d21_d1 ;
input Iin_d_d22_d0 ;
input Iin_d_d22_d1 ;
input Iin_d_d23_d0 ;
input Iin_d_d23_d1 ;
input Iin_d_d24_d0 ;
input Iin_d_d24_d1 ;
input Iin_d_d25_d0 ;
input Iin_d_d25_d1 ;
input Iin_d_d26_d0 ;
input Iin_d_d26_d1 ;
input Iin_d_d27_d0 ;
input Iin_d_d27_d1 ;
input Iin_d_d28_d0 ;
input Iin_d_d28_d1 ;
input Iin_d_d29_d0 ;
input Iin_d_d29_d1 ;
input Iin_d_d30_d0 ;
input Iin_d_d30_d1 ;
input Isupply_vss ;
// -- signals ---
wire Iin_d_d18_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d6_d0 ;
wire Isb_in ;
wire Iin_d_d27_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d8_d1 ;
output Iout_d_d31_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d3_d1 ;
output Iout_d_d31_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d14_d0 ;
wire Isupply_vss ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/master.tag
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@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

115
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v
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@ -1,115 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d1 , Iout_d_d9_d1 , Iout_d_d10_d1 , Iout_d_d11_d1 , Iout_d_d12_d1 , Iout_d_d13_d1 , Iout_d_d14_d1 , Iout_d_d15_d1 , Iout_d_d16_d1 , Iout_d_d17_d1 , Iout_d_d18_d1 , Iout_d_d19_d1 , Iout_d_d20_d1 , Iout_d_d21_d1 , Iout_d_d22_d1 , Iout_d_d23_d1 , Iout_d_d24_d1 , Iout_d_d25_d1 , Iout_d_d26_d1 , Iout_d_d27_d1 , Iout_d_d28_d1 , Iout_d_d29_d1 , Iout_d_d30_d1 , Isupply_vss , vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Isupply_vss ;
// -- signals ---
output Iout_d_d11_d1 ;
wire Iin_d_d1_d1 ;
output Iout_d_d22_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d30_d1 ;
output Iout_d_d18_d1 ;
wire Iin_d_d5_d0 ;
output Iout_d_d7_d0 ;
wire Iin_d_d3_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d20_d1 ;
output Iout_d_d7_d1 ;
wire Isb_in ;
output Iout_d_d13_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d25_d1 ;
wire Isupply_vss ;
wire Iin_d_d2_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d4_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d8_d1 ;
wire Iin_d_d0_d0 ;
output Iout_d_d10_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d12_d1 ;
output Iout_d_d24_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d9_d1 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d8_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows2 (.y(Iout_d_d9_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows3 (.y(Iout_d_d10_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows4 (.y(Iout_d_d11_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows5 (.y(Iout_d_d12_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows6 (.y(Iout_d_d13_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows7 (.y(Iout_d_d14_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows8 (.y(Iout_d_d15_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows9 (.y(Iout_d_d16_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows10 (.y(Iout_d_d17_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows11 (.y(Iout_d_d18_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows12 (.y(Iout_d_d19_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows13 (.y(Iout_d_d20_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows14 (.y(Iout_d_d21_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows15 (.y(Iout_d_d22_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows16 (.y(Iout_d_d23_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows17 (.y(Iout_d_d24_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows18 (.y(Iout_d_d25_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows19 (.y(Iout_d_d26_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows20 (.y(Iout_d_d27_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows21 (.y(Iout_d_d28_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows22 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows23 (.y(Iout_d_d30_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d7_d0 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
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module tmpl_0_0dataflow__neuro_0_0arbiter__handshake(Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iout_d_d0 , Iout_a , vdd, vss);
input vdd;
input vss;
input Iin1_d_d0 ;
input Iin2_d_d0 ;
input Iout_a ;
// -- signals ---
wire _y2_arb ;
output Iout_d_d0 ;
wire Iin2_d_d0 ;
wire Iin1_d_d0 ;
output Iin2_a ;
output Iin1_a ;
wire _y1_arb ;
wire Iout_a ;
// --- instances
A_2C_B_X1 Iack_cell1 (.y(Iin1_a ), .c1(Iout_a ), .c2(_y1_arb), .vdd(vdd), .vss(vss));
ARBITER Iarbiter (.a(Iin1_d_d0 ), .b(Iin2_d_d0 ), .c(Iin2_a ), .d(Iin1_a ), .y1(_y1_arb), .y2(_y2_arb), .vdd(vdd), .vss(vss));
A_2C_B_X1 Iack_cell2 (.y(Iin2_a ), .c1(Iout_a ), .c2(_y2_arb), .vdd(vdd), .vss(vss));
OR2_X1 Ior_cell (.y(Iout_d_d0 ), .a(_y1_arb), .b(_y2_arb), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0arbtree_315_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iout_d_d0 , Iout_a , vdd, vss);
input vdd;
input vss;
input Iin0_d_d0 ;
input Iin1_d_d0 ;
input Iin2_d_d0 ;
input Iin3_d_d0 ;
input Iin4_d_d0 ;
input Iin5_d_d0 ;
input Iin6_d_d0 ;
input Iin7_d_d0 ;
input Iin8_d_d0 ;
input Iin9_d_d0 ;
input Iin10_d_d0 ;
input Iin11_d_d0 ;
input Iin12_d_d0 ;
input Iin13_d_d0 ;
input Iin14_d_d0 ;
input Iout_a ;
// -- signals ---
wire Itmp20_a ;
wire Iin6_d_d0 ;
output Iin2_a ;
wire Iin2_d_d0 ;
wire Iin1_d_d0 ;
wire Itmp28_a ;
wire Itmp28_d_d0 ;
wire Itmp25_d_d0 ;
output Iin8_a ;
output Iout_d_d0 ;
wire Itmp21_d_d0 ;
wire Itmp27_d_d0 ;
wire Itmp19_a ;
wire Itmp19_d_d0 ;
output Iin9_a ;
wire Iin9_d_d0 ;
wire Iin14_d_d0 ;
wire Itmp17_a ;
wire Iin3_d_d0 ;
wire Itmp21_a ;
wire Iin13_d_d0 ;
wire Itmp15_d_d0 ;
wire Itmp23_a ;
output Iin11_a ;
wire Iin11_d_d0 ;
output Iin7_a ;
wire Itmp17_d_d0 ;
wire Iin12_d_d0 ;
output Iin4_a ;
output Iin1_a ;
wire Itmp25_a ;
wire Itmp20_d_d0 ;
wire Itmp23_d_d0 ;
output Iin12_a ;
wire Itmp16_a ;
wire Itmp16_d_d0 ;
wire Itmp15_a ;
output Iin6_a ;
wire Itmp24_a ;
wire Iin4_d_d0 ;
output Iin14_a ;
wire Itmp26_d_d0 ;
output Iin13_a ;
wire Iin8_d_d0 ;
output Iin10_a ;
output Iin0_a ;
wire Iout_a ;
wire Iin10_d_d0 ;
output Iin5_a ;
wire Itmp27_a ;
wire Itmp26_a ;
wire Itmp18_a ;
output Iin3_a ;
wire Itmp24_d_d0 ;
wire Itmp18_d_d0 ;
wire Iin5_d_d0 ;
wire Iin7_d_d0 ;
wire Iin0_d_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp15_d_d0 ), .Iout_a (Itmp15_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1 (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp16_d_d0 ), .Iout_a (Itmp16_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2 (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp17_d_d0 ), .Iout_a (Itmp17_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3 (.Iin1_d_d0 (Iin6_d_d0 ), .Iin1_a (Iin6_a ), .Iin2_d_d0 (Iin7_d_d0 ), .Iin2_a (Iin7_a ), .Iout_d_d0 (Itmp18_d_d0 ), .Iout_a (Itmp18_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4 (.Iin1_d_d0 (Iin8_d_d0 ), .Iin1_a (Iin8_a ), .Iin2_d_d0 (Iin9_d_d0 ), .Iin2_a (Iin9_a ), .Iout_d_d0 (Itmp19_d_d0 ), .Iout_a (Itmp19_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs5 (.Iin1_d_d0 (Iin10_d_d0 ), .Iin1_a (Iin10_a ), .Iin2_d_d0 (Iin11_d_d0 ), .Iin2_a (Iin11_a ), .Iout_d_d0 (Itmp20_d_d0 ), .Iout_a (Itmp20_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs6 (.Iin1_d_d0 (Iin12_d_d0 ), .Iin1_a (Iin12_a ), .Iin2_d_d0 (Iin13_d_d0 ), .Iin2_a (Iin13_a ), .Iout_d_d0 (Itmp21_d_d0 ), .Iout_a (Itmp21_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs7 (.Iin1_d_d0 (Itmp15_d_d0 ), .Iin1_a (Itmp15_a ), .Iin2_d_d0 (Itmp16_d_d0 ), .Iin2_a (Itmp16_a ), .Iout_d_d0 (Itmp23_d_d0 ), .Iout_a (Itmp23_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs8 (.Iin1_d_d0 (Itmp17_d_d0 ), .Iin1_a (Itmp17_a ), .Iin2_d_d0 (Itmp18_d_d0 ), .Iin2_a (Itmp18_a ), .Iout_d_d0 (Itmp24_d_d0 ), .Iout_a (Itmp24_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs9 (.Iin1_d_d0 (Itmp19_d_d0 ), .Iin1_a (Itmp19_a ), .Iin2_d_d0 (Itmp20_d_d0 ), .Iin2_a (Itmp20_a ), .Iout_d_d0 (Itmp25_d_d0 ), .Iout_a (Itmp25_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs10 (.Iin1_d_d0 (Itmp21_d_d0 ), .Iin1_a (Itmp21_a ), .Iin2_d_d0 (Iin14_d_d0 ), .Iin2_a (Iin14_a ), .Iout_d_d0 (Itmp26_d_d0 ), .Iout_a (Itmp26_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs11 (.Iin1_d_d0 (Itmp23_d_d0 ), .Iin1_a (Itmp23_a ), .Iin2_d_d0 (Itmp24_d_d0 ), .Iin2_a (Itmp24_a ), .Iout_d_d0 (Itmp27_d_d0 ), .Iout_a (Itmp27_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs12 (.Iin1_d_d0 (Itmp25_d_d0 ), .Iin1_a (Itmp25_a ), .Iin2_d_d0 (Itmp26_d_d0 ), .Iin2_a (Itmp26_a ), .Iout_d_d0 (Itmp28_d_d0 ), .Iout_a (Itmp28_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs13 (.Iin1_d_d0 (Itmp27_d_d0 ), .Iin1_a (Itmp27_a ), .Iin2_d_d0 (Itmp28_d_d0 ), .Iin2_a (Itmp28_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0arbtree_36_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iout_d_d0 , Iout_a , vdd, vss);
input vdd;
input vss;
input Iin0_d_d0 ;
input Iin1_d_d0 ;
input Iin2_d_d0 ;
input Iin3_d_d0 ;
input Iin4_d_d0 ;
input Iin5_d_d0 ;
input Iout_a ;
// -- signals ---
wire Iin3_d_d0 ;
wire Itmp6_a ;
output Iin3_a ;
output Iout_d_d0 ;
wire Itmp10_d_d0 ;
output Iin2_a ;
output Iin5_a ;
output Iin4_a ;
wire Itmp7_d_d0 ;
wire Itmp9_d_d0 ;
wire Itmp10_a ;
wire Itmp6_d_d0 ;
wire Iin0_d_d0 ;
wire Iin2_d_d0 ;
wire Itmp9_a ;
wire Iin4_d_d0 ;
wire Itmp7_a ;
wire Iin1_d_d0 ;
output Iin0_a ;
wire Iin5_d_d0 ;
output Iin1_a ;
wire Iout_a ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp6_d_d0 ), .Iout_a (Itmp6_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1 (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp7_d_d0 ), .Iout_a (Itmp7_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2 (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp10_d_d0 ), .Iout_a (Itmp10_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3 (.Iin1_d_d0 (Itmp6_d_d0 ), .Iin1_a (Itmp6_a ), .Iin2_d_d0 (Itmp7_d_d0 ), .Iin2_a (Itmp7_a ), .Iout_d_d0 (Itmp9_d_d0 ), .Iout_a (Itmp9_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4 (.Iin1_d_d0 (Itmp9_d_d0 ), .Iin1_a (Itmp9_a ), .Iin2_d_d0 (Itmp10_d_d0 ), .Iin2_a (Itmp10_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
endmodule

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module tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4(Iin_d0 , Iin_d1 , Iin_d2 , Iin_d3 , Iin_d4 , Iin_d5 , Iin_d6 , Iin_d7 , Iin_d8 , Iin_d9 , Iin_d10 , Iin_d11 , Iin_d12 , Iin_d13 , Iin_d14 , Iin_d15 , Iin_d16 , Iin_d17 , Iin_d18 , Iin_d19 , Iin_d20 , Iin_d21 , Iin_d22 , Iin_d23 , Iin_d24 , Iin_d25 , Iin_d26 , Iin_d27 , Iin_d28 , Iin_d29 , Iin_d30 , Iin_d31 , Iin_r , Iin_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Iout_a , Iout_v , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , Idly_cfg20 , Idly_cfg21 , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d0 ;
input Iin_d1 ;
input Iin_d2 ;
input Iin_d3 ;
input Iin_d4 ;
input Iin_d5 ;
input Iin_d6 ;
input Iin_d7 ;
input Iin_d8 ;
input Iin_d9 ;
input Iin_d10 ;
input Iin_d11 ;
input Iin_d12 ;
input Iin_d13 ;
input Iin_d14 ;
input Iin_d15 ;
input Iin_d16 ;
input Iin_d17 ;
input Iin_d18 ;
input Iin_d19 ;
input Iin_d20 ;
input Iin_d21 ;
input Iin_d22 ;
input Iin_d23 ;
input Iin_d24 ;
input Iin_d25 ;
input Iin_d26 ;
input Iin_d27 ;
input Iin_d28 ;
input Iin_d29 ;
input Iin_d30 ;
input Iin_d31 ;
input Iin_r ;
input Iout_a ;
input Iout_v ;
input Idly_cfg0 ;
input Idly_cfg1 ;
input Idly_cfg2 ;
input Idly_cfg3 ;
input Idly_cfg20 ;
input Idly_cfg21 ;
input reset_B;
// -- signals ---
wire I_inB12 ;
wire Iin_d31 ;
output Iout_d_d7_d0 ;
output Iout_d_d30_d1 ;
wire I_inB22 ;
output Iout_d_d26_d0 ;
wire _reset_BX ;
wire Iin_d4 ;
output Iout_d_d2_d1 ;
output Iout_d_d13_d1 ;
wire I_reset_BXX0 ;
wire I_inB28 ;
output Iout_d_d8_d0 ;
wire I_inB6 ;
wire Iin_d17 ;
wire I_inB19 ;
wire _out_a_B ;
output Iout_d_d16_d0 ;
wire I_inB10 ;
wire Iin_d21 ;
output Iout_d_d17_d0 ;
wire _en ;
wire I_inB0 ;
output Iout_d_d2_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d19_d1 ;
wire I_inB3 ;
wire Iin_d30 ;
wire I_reqXX0 ;
wire I_inB21 ;
output Iout_d_d27_d1 ;
wire Idly_cfg2 ;
wire I_inB16 ;
output Iout_d_d1_d1 ;
wire Iin_d6 ;
wire I_inB15 ;
wire I_inB27 ;
output Iout_d_d31_d1 ;
wire I_inB18 ;
output Iout_d_d27_d0 ;
wire _reqX ;
wire Iin_d5 ;
wire Iin_d18 ;
wire I_inB20 ;
output Iout_d_d8_d1 ;
wire Iin_d20 ;
wire Iin_d2 ;
output Iout_d_d25_d1 ;
output Iout_d_d31_d0 ;
output Iout_d_d6_d1 ;
output Iin_a ;
output Iout_d_d29_d1 ;
wire Idly_cfg21 ;
output Iout_d_d28_d0 ;
output Iout_d_d10_d1 ;
wire Iin_r ;
wire Idly_cfg1 ;
wire I_inB7 ;
wire I_inB31 ;
output Iout_d_d6_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d30_d0 ;
wire reset_B;
output Iout_d_d9_d0 ;
output Iout_d_d17_d1 ;
output Iout_d_d11_d1 ;
wire Idly_cfg20 ;
wire Iin_d23 ;
output Iout_d_d18_d0 ;
wire Iin_d1 ;
wire I_inB14 ;
wire I_inB11 ;
output Iout_d_d1_d0 ;
output Iout_d_d10_d0 ;
wire Ien_buf_out0 ;
wire I_inB9 ;
output Iout_d_d26_d1 ;
wire Iin_d7 ;
wire I_inB26 ;
output Iout_d_d0_d0 ;
output Iout_d_d11_d0 ;
wire I_inB4 ;
wire Iin_d15 ;
wire Iin_d10 ;
output Iout_d_d18_d1 ;
wire I_inB13 ;
wire Iin_d14 ;
wire Iin_d22 ;
wire I_inB24 ;
output Iout_d_d12_d1 ;
wire Iout_a ;
wire Iin_d8 ;
wire Iin_d24 ;
wire I_inB30 ;
output Iout_d_d25_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d28_d1 ;
wire Iout_v ;
wire I_inB2 ;
wire I_inB8 ;
wire Iin_d13 ;
wire Iin_d19 ;
wire I_inB25 ;
wire Iin_d25 ;
wire I_inB1 ;
wire Idly_cfg3 ;
output Iout_d_d4_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d15_d1 ;
wire Idly2_out ;
wire Iin_d12 ;
output Iout_d_d12_d0 ;
output Iout_d_d21_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d5_d1 ;
wire I_inB5 ;
wire Iin_d28 ;
wire If_buf_func31_c2 ;
wire Iin_d11 ;
wire _req ;
wire _req_slowfall ;
output Iout_d_d3_d1 ;
output Iout_d_d0_d1 ;
wire Iin_d3 ;
wire Iin_d27 ;
output Iout_d_d24_d1 ;
wire Iin_d9 ;
wire I_inB29 ;
wire Iin_d29 ;
output Iout_d_d19_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d22_d1 ;
wire Idly_cfg0 ;
output Iout_d_d14_d0 ;
output Iout_d_d23_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d21_d1 ;
output Iout_d_d16_d1 ;
wire Iin_d16 ;
output Iout_d_d5_d0 ;
output Iout_d_d20_d1 ;
wire I_inB17 ;
wire I_inB23 ;
output Iout_d_d14_d1 ;
wire Iin_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d26 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(_req_slowfall), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly (.out(_req), .in(Iin_r ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delayprog_32_4 Idly2 (.out(Idly2_out ), .in(_reqX), .Is0 (Idly_cfg20 ), .Is1 (Idly_cfg21 ), .vdd(vdd), .vss(vss));
BUF_X4 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs0 (.y(I_inB0 ), .a(Iin_d0 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs1 (.y(I_inB1 ), .a(Iin_d1 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs2 (.y(I_inB2 ), .a(Iin_d2 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs3 (.y(I_inB3 ), .a(Iin_d3 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs4 (.y(I_inB4 ), .a(Iin_d4 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs5 (.y(I_inB5 ), .a(Iin_d5 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs6 (.y(I_inB6 ), .a(Iin_d6 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs7 (.y(I_inB7 ), .a(Iin_d7 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs8 (.y(I_inB8 ), .a(Iin_d8 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs9 (.y(I_inB9 ), .a(Iin_d9 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs10 (.y(I_inB10 ), .a(Iin_d10 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs11 (.y(I_inB11 ), .a(Iin_d11 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs12 (.y(I_inB12 ), .a(Iin_d12 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs13 (.y(I_inB13 ), .a(Iin_d13 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs14 (.y(I_inB14 ), .a(Iin_d14 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs15 (.y(I_inB15 ), .a(Iin_d15 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs16 (.y(I_inB16 ), .a(Iin_d16 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs17 (.y(I_inB17 ), .a(Iin_d17 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs18 (.y(I_inB18 ), .a(Iin_d18 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs19 (.y(I_inB19 ), .a(Iin_d19 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs20 (.y(I_inB20 ), .a(Iin_d20 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs21 (.y(I_inB21 ), .a(Iin_d21 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs22 (.y(I_inB22 ), .a(Iin_d22 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs23 (.y(I_inB23 ), .a(Iin_d23 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs24 (.y(I_inB24 ), .a(Iin_d24 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs25 (.y(I_inB25 ), .a(Iin_d25 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs26 (.y(I_inB26 ), .a(Iin_d26 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs27 (.y(I_inB27 ), .a(Iin_d27 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs28 (.y(I_inB28 ), .a(Iin_d28 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs29 (.y(I_inB29 ), .a(Iin_d29 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs30 (.y(I_inB30 ), .a(Iin_d30 ), .vdd(vdd), .vss(vss));
INV_X1 Iinput_invs31 (.y(I_inB31 ), .a(Iin_d31 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (If_buf_func31_c2 ), .vdd(vdd), .vss(vss));
OR2_X1 Ireq_dly_or (.y(_req_slowfall), .a(_reqX), .b(Idly2_out ), .vdd(vdd), .vss(vss));
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireq_bufarray (.in(_reqX), .Iout0 (I_reqXX0 ), .vdd(vdd), .vss(vss));
BUF_X4 Ireq_buf (.y(_reqX), .a(_req), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB0 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB1 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB2 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB3 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB4 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB5 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB6 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB7 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB8 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB9 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB10 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB11 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB12 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB13 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB14 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB15 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB16 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB17 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB18 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB19 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB20 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB21 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB22 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB23 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB24 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB25 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB26 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB27 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB28 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func29 (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB29 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func30 (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB30 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 If_buf_func31 (.y(Iout_d_d31_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB31 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d0 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d1 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d2 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d3 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d4 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d5 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d6 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d7 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d8 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d9 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d10 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d11 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d12 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d13 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d14 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d15 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d16 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d17 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d18 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d19 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d20 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d21 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d22 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d23 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d24 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d25 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d26 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d27 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d28 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func29 (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d29 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func30 (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d30 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C2N_RB_X4 It_buf_func31 (.y(Iout_d_d31_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d31 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/master.tag
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-- Master.tag File, Rev:1.0
verilog.v

164
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/verilog.v
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@ -1,164 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0buffer_313_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
output Iin_a ;
output Iout_d_d12_d1 ;
output Iout_d_d2_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d4_d1 ;
wire Iin_d_d8_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d10_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d7_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d0_d0 ;
wire _in_v ;
output Iout_d_d7_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d2_d0 ;
wire _en ;
output Iout_d_d12_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d1_d0 ;
output Iin_v ;
output Iout_d_d8_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d0_d1 ;
output Iout_d_d3_d0 ;
wire _reset_BX ;
wire Iin_d_d11_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d6_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d11_d0 ;
wire Iin_d_d10_d0 ;
wire Iout_a ;
wire Ien_buf_out0 ;
output Iout_d_d1_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d_d9_d1 ;
wire I_out_a_BX0 ;
wire _out_a_B ;
wire Iin_d_d5_d0 ;
wire Iin_d_d3_d0 ;
wire reset_B;
wire Iout_v ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_313_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/master.tag
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-- Master.tag File, Rev:1.0
verilog.v

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test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/verilog.v
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@ -1,324 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0buffer_329_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iin_d_d13_d0 ;
input Iin_d_d13_d1 ;
input Iin_d_d14_d0 ;
input Iin_d_d14_d1 ;
input Iin_d_d15_d0 ;
input Iin_d_d15_d1 ;
input Iin_d_d16_d0 ;
input Iin_d_d16_d1 ;
input Iin_d_d17_d0 ;
input Iin_d_d17_d1 ;
input Iin_d_d18_d0 ;
input Iin_d_d18_d1 ;
input Iin_d_d19_d0 ;
input Iin_d_d19_d1 ;
input Iin_d_d20_d0 ;
input Iin_d_d20_d1 ;
input Iin_d_d21_d0 ;
input Iin_d_d21_d1 ;
input Iin_d_d22_d0 ;
input Iin_d_d22_d1 ;
input Iin_d_d23_d0 ;
input Iin_d_d23_d1 ;
input Iin_d_d24_d0 ;
input Iin_d_d24_d1 ;
input Iin_d_d25_d0 ;
input Iin_d_d25_d1 ;
input Iin_d_d26_d0 ;
input Iin_d_d26_d1 ;
input Iin_d_d27_d0 ;
input Iin_d_d27_d1 ;
input Iin_d_d28_d0 ;
input Iin_d_d28_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
output Iout_d_d0_d0 ;
output Iout_d_d20_d1 ;
wire Iin_d_d3_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d28_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d7_d0 ;
output Iout_d_d6_d0 ;
output Iout_d_d12_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d8_d0 ;
output Iout_d_d18_d0 ;
wire Iin_d_d11_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d10_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d17_d1 ;
output Iin_v ;
output Iout_d_d23_d0 ;
output Iout_d_d8_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d11_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d14_d0 ;
wire _reset_BX ;
output Iin_a ;
wire Ien_buf_out0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d1_d0 ;
wire I_out_a_BX0 ;
output Iout_d_d26_d1 ;
wire Iin_d_d12_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d9_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d6_d0 ;
output Iout_d_d25_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d_d17_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d27_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d9_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d13_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d18_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d5_d0 ;
wire Iout_v ;
wire _out_a_B ;
output Iout_d_d3_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d7_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d13_d1 ;
wire reset_B;
wire Iin_d_d26_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d_d5_d1 ;
wire Iin_d_d25_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d22_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d1_d1 ;
wire _en ;
output Iout_d_d21_d0 ;
output Iout_d_d17_d0 ;
output Iout_d_d10_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d20_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d15_d1 ;
wire Iout_a ;
output Iout_d_d26_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d22_d0 ;
output Iout_d_d23_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d0_d0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d22_d1 ;
wire _in_v ;
output Iout_d_d4_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d2_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_329_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/master.tag
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-- Master.tag File, Rev:1.0
verilog.v

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test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/verilog.v
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module tmpl_0_0dataflow__neuro_0_0buffer_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iin_d_d13_d0 ;
input Iin_d_d13_d1 ;
input Iin_d_d14_d0 ;
input Iin_d_d14_d1 ;
input Iin_d_d15_d0 ;
input Iin_d_d15_d1 ;
input Iin_d_d16_d0 ;
input Iin_d_d16_d1 ;
input Iin_d_d17_d0 ;
input Iin_d_d17_d1 ;
input Iin_d_d18_d0 ;
input Iin_d_d18_d1 ;
input Iin_d_d19_d0 ;
input Iin_d_d19_d1 ;
input Iin_d_d20_d0 ;
input Iin_d_d20_d1 ;
input Iin_d_d21_d0 ;
input Iin_d_d21_d1 ;
input Iin_d_d22_d0 ;
input Iin_d_d22_d1 ;
input Iin_d_d23_d0 ;
input Iin_d_d23_d1 ;
input Iin_d_d24_d0 ;
input Iin_d_d24_d1 ;
input Iin_d_d25_d0 ;
input Iin_d_d25_d1 ;
input Iin_d_d26_d0 ;
input Iin_d_d26_d1 ;
input Iin_d_d27_d0 ;
input Iin_d_d27_d1 ;
input Iin_d_d28_d0 ;
input Iin_d_d28_d1 ;
input Iin_d_d29_d0 ;
input Iin_d_d29_d1 ;
input Iin_d_d30_d0 ;
input Iin_d_d30_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
wire Iin_d_d6_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d28_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d13_d0 ;
wire _out_a_B ;
wire Iin_d_d19_d0 ;
wire Iin_d_d20_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d7_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d27_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d30_d1 ;
output Iout_d_d23_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d24_d0 ;
output Iin_a ;
wire Iin_d_d19_d1 ;
wire Iin_d_d28_d0 ;
output Iout_d_d26_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d17_d0 ;
output Iout_d_d15_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d17_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d12_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d25_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d19_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d13_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d17_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d7_d0 ;
wire Iin_d_d18_d0 ;
wire reset_B;
output Iout_d_d2_d1 ;
output Iout_d_d30_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d29_d0 ;
wire Iin_d_d3_d1 ;
output Iout_d_d10_d1 ;
wire I_out_a_BX0 ;
wire _en ;
output Iout_d_d19_d1 ;
output Iout_d_d20_d1 ;
output Iout_d_d25_d1 ;
wire Iin_d_d17_d1 ;
output Iout_d_d23_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d_d24_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d20_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d13_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d15_d0 ;
output Iout_d_d15_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d22_d0 ;
output Iout_d_d26_d0 ;
wire _reset_BX ;
output Iout_d_d16_d0 ;
output Iout_d_d12_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d10_d0 ;
output Iout_d_d18_d1 ;
output Iin_v ;
wire Iin_d_d23_d1 ;
wire Iin_d_d24_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d22_d1 ;
wire Iout_a ;
output Iout_d_d21_d1 ;
wire _in_v ;
wire Iin_d_d6_d0 ;
wire Iin_d_d14_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d5_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d21_d0 ;
wire Iout_v ;
wire Iin_d_d11_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d26_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d11_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d30_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d27_d1 ;
output Iout_d_d4_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d5_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func29 (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func30 (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func29 (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func30 (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/master.tag
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@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

354
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/verilog.v
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@ -1,354 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0buffer_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_d_d31_d0 , Iin_d_d31_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iin_d_d13_d0 ;
input Iin_d_d13_d1 ;
input Iin_d_d14_d0 ;
input Iin_d_d14_d1 ;
input Iin_d_d15_d0 ;
input Iin_d_d15_d1 ;
input Iin_d_d16_d0 ;
input Iin_d_d16_d1 ;
input Iin_d_d17_d0 ;
input Iin_d_d17_d1 ;
input Iin_d_d18_d0 ;
input Iin_d_d18_d1 ;
input Iin_d_d19_d0 ;
input Iin_d_d19_d1 ;
input Iin_d_d20_d0 ;
input Iin_d_d20_d1 ;
input Iin_d_d21_d0 ;
input Iin_d_d21_d1 ;
input Iin_d_d22_d0 ;
input Iin_d_d22_d1 ;
input Iin_d_d23_d0 ;
input Iin_d_d23_d1 ;
input Iin_d_d24_d0 ;
input Iin_d_d24_d1 ;
input Iin_d_d25_d0 ;
input Iin_d_d25_d1 ;
input Iin_d_d26_d0 ;
input Iin_d_d26_d1 ;
input Iin_d_d27_d0 ;
input Iin_d_d27_d1 ;
input Iin_d_d28_d0 ;
input Iin_d_d28_d1 ;
input Iin_d_d29_d0 ;
input Iin_d_d29_d1 ;
input Iin_d_d30_d0 ;
input Iin_d_d30_d1 ;
input Iin_d_d31_d0 ;
input Iin_d_d31_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
wire Iin_d_d3_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d26_d0 ;
wire Iout_a ;
output Iout_d_d2_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d30_d0 ;
output Iout_d_d14_d1 ;
output Iout_d_d18_d1 ;
wire Iin_d_d14_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d12_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d_d6_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d19_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d11_d0 ;
wire _out_a_B ;
wire Iin_d_d4_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d3_d0 ;
output Iin_a ;
wire Iin_d_d6_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d31_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d22_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d31_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d23_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d20_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d17_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d24_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d31_d1 ;
output Iin_v ;
wire Iin_d_d11_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d4_d0 ;
wire _reset_BX ;
wire Iin_d_d8_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d1_d0 ;
wire reset_B;
output Iout_d_d1_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d15_d0 ;
output Iout_d_d0_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d27_d1 ;
output Iout_d_d28_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d15_d1 ;
output Iout_d_d20_d1 ;
output Iout_d_d25_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d0_d1 ;
output Iout_d_d13_d1 ;
output Iout_d_d25_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d31_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d19_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d18_d0 ;
output Iout_d_d10_d1 ;
output Iout_d_d11_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d12_d0 ;
output Iout_d_d7_d0 ;
wire _in_v ;
wire Iin_d_d7_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d25_d0 ;
output Iout_d_d30_d1 ;
output Iout_d_d14_d0 ;
output Iout_d_d15_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d13_d0 ;
wire Iin_d_d19_d0 ;
output Iout_d_d17_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d6_d0 ;
output Iout_d_d29_d0 ;
wire Iin_d_d2_d0 ;
output Iout_d_d10_d0 ;
wire Ien_buf_out0 ;
output Iout_d_d27_d0 ;
output Iout_d_d9_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d29_d1 ;
wire _en ;
wire Iin_d_d14_d0 ;
wire Iin_d_d28_d0 ;
wire Iout_v ;
wire Iin_d_d16_d1 ;
output Iout_d_d16_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d7_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d26_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_332_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .Iin_d31_d0 (Iin_d_d31_d0 ), .Iin_d31_d1 (Iin_d_d31_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func29 (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func30 (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func31 (.y(Iout_d_d31_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d31_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func29 (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func30 (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func31 (.y(Iout_d_d31_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d31_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

104
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/verilog.v
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module tmpl_0_0dataflow__neuro_0_0buffer_37_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
wire Iin_d_d6_d0 ;
output Iout_d_d5_d1 ;
wire Iin_d_d6_d1 ;
wire I_reset_BXX0 ;
wire I_out_a_BX0 ;
wire Iin_d_d0_d1 ;
output Iin_a ;
wire Ien_buf_out0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d5_d0 ;
wire Iout_v ;
output Iout_d_d1_d1 ;
wire reset_B;
wire Iin_d_d4_d1 ;
output Iout_d_d3_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d3_d1 ;
wire Iout_a ;
output Iin_v ;
output Iout_d_d2_d1 ;
wire _in_v ;
wire Iin_d_d2_d0 ;
wire Iin_d_d1_d0 ;
output Iout_d_d6_d1 ;
wire _out_a_B ;
output Iout_d_d6_d0 ;
output Iout_d_d4_d0 ;
wire _en ;
output Iout_d_d1_d0 ;
output Iout_d_d0_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d3_d0 ;
wire _reset_BX ;
output Iout_d_d0_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d_d3_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/master.tag
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-- Master.tag File, Rev:1.0
verilog.v

55
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/verilog.v
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module tmpl_0_0dataflow__neuro_0_0ctree_313_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
input Iin9 ;
input Iin10 ;
input Iin11 ;
input Iin12 ;
output out;
// -- signals ---
wire Itmp16 ;
wire Iin5 ;
wire Iin12 ;
wire Iin9 ;
wire Iin7 ;
wire Itmp15 ;
wire Iin11 ;
wire Iin10 ;
wire Iin8 ;
wire Iin0 ;
wire Itmp14 ;
wire Itmp13 ;
wire Itmp18 ;
wire Iin3 ;
wire Iin2 ;
wire Itmp17 ;
wire Iin6 ;
wire Itmp21 ;
wire Iin1 ;
wire Itmp19 ;
wire Itmp20 ;
wire out ;
wire Iin4 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp13 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp14 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(Itmp15 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3 (.y(Itmp16 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4 (.y(Itmp17 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5 (.y(Itmp19 ), .c1(Itmp13 ), .c2(Itmp14 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els6 (.y(Itmp20 ), .c1(Itmp15 ), .c2(Itmp16 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els7 (.y(Itmp21 ), .c1(Itmp17 ), .c2(Itmp18 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0 (.y(Itmp18 ), .c1(Iin10 ), .c2(Iin11 ), .c3(Iin12 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els1 (.y(out), .c1(Itmp19 ), .c2(Itmp20 ), .c3(Itmp21 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/master.tag
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-- Master.tag File, Rev:1.0
verilog.v

93
test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/verilog.v
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module tmpl_0_0dataflow__neuro_0_0ctree_323_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
input Iin9 ;
input Iin10 ;
input Iin11 ;
input Iin12 ;
input Iin13 ;
input Iin14 ;
input Iin15 ;
input Iin16 ;
input Iin17 ;
input Iin18 ;
input Iin19 ;
input Iin20 ;
input Iin21 ;
input Iin22 ;
output out;
// -- signals ---
wire Iin8 ;
wire Iin22 ;
wire Iin21 ;
wire Itmp27 ;
wire Itmp23 ;
wire Itmp39 ;
wire out ;
wire Iin19 ;
wire Itmp26 ;
wire Iin20 ;
wire Iin7 ;
wire Iin13 ;
wire Itmp31 ;
wire Iin4 ;
wire Iin0 ;
wire Iin17 ;
wire Iin9 ;
wire Itmp38 ;
wire Iin15 ;
wire Iin1 ;
wire Iin5 ;
wire Itmp33 ;
wire Iin14 ;
wire Itmp30 ;
wire Iin12 ;
wire Iin11 ;
wire Iin6 ;
wire Itmp35 ;
wire Itmp25 ;
wire Iin2 ;
wire Itmp36 ;
wire Itmp34 ;
wire Iin16 ;
wire Itmp28 ;
wire Itmp40 ;
wire Itmp37 ;
wire Itmp32 ;
wire Iin18 ;
wire Itmp29 ;
wire Itmp24 ;
wire Iin10 ;
wire Iin3 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp23 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp24 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(Itmp25 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3 (.y(Itmp26 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4 (.y(Itmp27 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5 (.y(Itmp28 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els6 (.y(Itmp29 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els7 (.y(Itmp30 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els8 (.y(Itmp31 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els9 (.y(Itmp32 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els10 (.y(Itmp34 ), .c1(Itmp23 ), .c2(Itmp24 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els11 (.y(Itmp35 ), .c1(Itmp25 ), .c2(Itmp26 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els12 (.y(Itmp36 ), .c1(Itmp27 ), .c2(Itmp28 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els13 (.y(Itmp37 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els14 (.y(Itmp39 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els15 (.y(out), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0 (.y(Itmp33 ), .c1(Iin20 ), .c2(Iin21 ), .c3(Iin22 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els1 (.y(Itmp38 ), .c1(Itmp31 ), .c2(Itmp32 ), .c3(Itmp33 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els2 (.y(Itmp40 ), .c1(Itmp36 ), .c2(Itmp37 ), .c3(Itmp38 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0ctree_329_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
input Iin9 ;
input Iin10 ;
input Iin11 ;
input Iin12 ;
input Iin13 ;
input Iin14 ;
input Iin15 ;
input Iin16 ;
input Iin17 ;
input Iin18 ;
input Iin19 ;
input Iin20 ;
input Iin21 ;
input Iin22 ;
input Iin23 ;
input Iin24 ;
input Iin25 ;
input Iin26 ;
input Iin27 ;
input Iin28 ;
output out;
// -- signals ---
wire Itmp37 ;
wire Itmp29 ;
wire Iin28 ;
wire Itmp31 ;
wire Iin2 ;
wire Itmp45 ;
wire Iin25 ;
wire Itmp41 ;
wire Itmp40 ;
wire Itmp38 ;
wire Iin7 ;
wire Iin22 ;
wire Iin13 ;
wire Iin26 ;
wire Iin1 ;
wire Iin18 ;
wire Iin5 ;
wire Itmp51 ;
wire Itmp47 ;
wire Itmp36 ;
wire Iin4 ;
wire Iin10 ;
wire Iin12 ;
wire out ;
wire Iin3 ;
wire Iin27 ;
wire Itmp34 ;
wire Itmp50 ;
wire Itmp46 ;
wire Iin14 ;
wire Itmp44 ;
wire Itmp52 ;
wire Itmp43 ;
wire Iin20 ;
wire Iin11 ;
wire Iin24 ;
wire Iin6 ;
wire Itmp49 ;
wire Iin19 ;
wire Itmp42 ;
wire Itmp30 ;
wire Itmp33 ;
wire Iin16 ;
wire Iin21 ;
wire Itmp39 ;
wire Iin9 ;
wire Iin23 ;
wire Iin15 ;
wire Iin8 ;
wire Iin17 ;
wire Itmp35 ;
wire Itmp32 ;
wire Itmp48 ;
wire Iin0 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp29 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp30 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(Itmp31 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3 (.y(Itmp32 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4 (.y(Itmp33 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5 (.y(Itmp34 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els6 (.y(Itmp35 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els7 (.y(Itmp36 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els8 (.y(Itmp37 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els9 (.y(Itmp38 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els10 (.y(Itmp39 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els11 (.y(Itmp40 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els12 (.y(Itmp41 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els13 (.y(Itmp43 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els14 (.y(Itmp44 ), .c1(Itmp31 ), .c2(Itmp32 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els15 (.y(Itmp45 ), .c1(Itmp33 ), .c2(Itmp34 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els16 (.y(Itmp46 ), .c1(Itmp35 ), .c2(Itmp36 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els17 (.y(Itmp47 ), .c1(Itmp37 ), .c2(Itmp38 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els18 (.y(Itmp48 ), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els19 (.y(Itmp49 ), .c1(Itmp41 ), .c2(Itmp42 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els20 (.y(Itmp50 ), .c1(Itmp43 ), .c2(Itmp44 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els21 (.y(Itmp51 ), .c1(Itmp45 ), .c2(Itmp46 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0 (.y(Itmp42 ), .c1(Iin26 ), .c2(Iin27 ), .c3(Iin28 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els1 (.y(Itmp52 ), .c1(Itmp47 ), .c2(Itmp48 ), .c3(Itmp49 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els2 (.y(out), .c1(Itmp50 ), .c2(Itmp51 ), .c3(Itmp52 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0ctree_330_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
input Iin9 ;
input Iin10 ;
input Iin11 ;
input Iin12 ;
input Iin13 ;
input Iin14 ;
input Iin15 ;
input Iin16 ;
input Iin17 ;
input Iin18 ;
input Iin19 ;
input Iin20 ;
input Iin21 ;
input Iin22 ;
input Iin23 ;
input Iin24 ;
input Iin25 ;
input Iin26 ;
input Iin27 ;
input Iin28 ;
input Iin29 ;
output out;
// -- signals ---
wire Itmp34 ;
wire Itmp46 ;
wire Itmp43 ;
wire Iin22 ;
wire Iin0 ;
wire Iin10 ;
wire Itmp52 ;
wire Iin18 ;
wire Iin11 ;
wire Itmp39 ;
wire Iin5 ;
wire Iin29 ;
wire Iin27 ;
wire Iin24 ;
wire Itmp40 ;
wire Itmp49 ;
wire Iin25 ;
wire Iin6 ;
wire Iin28 ;
wire Iin9 ;
wire Iin20 ;
wire Itmp32 ;
wire Itmp48 ;
wire Iin26 ;
wire Iin19 ;
wire Itmp53 ;
wire Itmp41 ;
wire Itmp42 ;
wire Itmp44 ;
wire Iin14 ;
wire Iin13 ;
wire Iin1 ;
wire Iin12 ;
wire Itmp45 ;
wire Itmp50 ;
wire Iin2 ;
wire Itmp38 ;
wire Itmp30 ;
wire Itmp37 ;
wire Iin4 ;
wire Iin21 ;
wire Itmp31 ;
wire Itmp54 ;
wire Itmp33 ;
wire Iin3 ;
wire Iin8 ;
wire Iin7 ;
wire Iin23 ;
wire Iin17 ;
wire Iin15 ;
wire Itmp35 ;
wire out ;
wire Itmp47 ;
wire Itmp36 ;
wire Itmp51 ;
wire Iin16 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp30 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp31 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(Itmp32 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3 (.y(Itmp33 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4 (.y(Itmp34 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5 (.y(Itmp35 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els6 (.y(Itmp36 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els7 (.y(Itmp37 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els8 (.y(Itmp38 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els9 (.y(Itmp39 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els10 (.y(Itmp40 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els11 (.y(Itmp41 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els12 (.y(Itmp42 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els13 (.y(Itmp43 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els14 (.y(Itmp44 ), .c1(Iin28 ), .c2(Iin29 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els15 (.y(Itmp45 ), .c1(Itmp30 ), .c2(Itmp31 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els16 (.y(Itmp46 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els17 (.y(Itmp47 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els18 (.y(Itmp48 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els19 (.y(Itmp49 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els20 (.y(Itmp50 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els21 (.y(Itmp52 ), .c1(Itmp45 ), .c2(Itmp46 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els22 (.y(Itmp53 ), .c1(Itmp47 ), .c2(Itmp48 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0 (.y(Itmp51 ), .c1(Itmp42 ), .c2(Itmp43 ), .c3(Itmp44 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els1 (.y(Itmp54 ), .c1(Itmp49 ), .c2(Itmp50 ), .c3(Itmp51 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els2 (.y(out), .c1(Itmp52 ), .c2(Itmp53 ), .c3(Itmp54 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0ctree_331_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
input Iin9 ;
input Iin10 ;
input Iin11 ;
input Iin12 ;
input Iin13 ;
input Iin14 ;
input Iin15 ;
input Iin16 ;
input Iin17 ;
input Iin18 ;
input Iin19 ;
input Iin20 ;
input Iin21 ;
input Iin22 ;
input Iin23 ;
input Iin24 ;
input Iin25 ;
input Iin26 ;
input Iin27 ;
input Iin28 ;
input Iin29 ;
input Iin30 ;
output out;
// -- signals ---
wire Iin7 ;
wire Iin25 ;
wire Itmp41 ;
wire Iin6 ;
wire Iin23 ;
wire Iin5 ;
wire Iin22 ;
wire Itmp42 ;
wire Iin16 ;
wire Iin21 ;
wire Itmp33 ;
wire Iin12 ;
wire Iin8 ;
wire Itmp35 ;
wire out ;
wire Iin28 ;
wire Itmp45 ;
wire Itmp48 ;
wire Iin29 ;
wire Itmp50 ;
wire Itmp34 ;
wire Iin27 ;
wire Iin0 ;
wire Iin24 ;
wire Iin4 ;
wire Itmp51 ;
wire Itmp49 ;
wire Itmp36 ;
wire Itmp39 ;
wire Itmp31 ;
wire Itmp53 ;
wire Iin20 ;
wire Iin17 ;
wire Itmp37 ;
wire Iin10 ;
wire Itmp46 ;
wire Itmp40 ;
wire Itmp38 ;
wire Itmp32 ;
wire Itmp47 ;
wire Iin11 ;
wire Itmp54 ;
wire Iin9 ;
wire Iin2 ;
wire Iin19 ;
wire Iin18 ;
wire Iin3 ;
wire Itmp55 ;
wire Iin26 ;
wire Itmp43 ;
wire Iin13 ;
wire Iin15 ;
wire Itmp52 ;
wire Itmp44 ;
wire Iin1 ;
wire Iin30 ;
wire Iin14 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp31 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp32 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(Itmp33 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3 (.y(Itmp34 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4 (.y(Itmp35 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5 (.y(Itmp36 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els6 (.y(Itmp37 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els7 (.y(Itmp38 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els8 (.y(Itmp39 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els9 (.y(Itmp40 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els10 (.y(Itmp41 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els11 (.y(Itmp42 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els12 (.y(Itmp43 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els13 (.y(Itmp44 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els14 (.y(Itmp46 ), .c1(Itmp31 ), .c2(Itmp32 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els15 (.y(Itmp47 ), .c1(Itmp33 ), .c2(Itmp34 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els16 (.y(Itmp48 ), .c1(Itmp35 ), .c2(Itmp36 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els17 (.y(Itmp49 ), .c1(Itmp37 ), .c2(Itmp38 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els18 (.y(Itmp50 ), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els19 (.y(Itmp51 ), .c1(Itmp41 ), .c2(Itmp42 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els20 (.y(Itmp53 ), .c1(Itmp46 ), .c2(Itmp47 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els21 (.y(Itmp54 ), .c1(Itmp48 ), .c2(Itmp49 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0 (.y(Itmp45 ), .c1(Iin28 ), .c2(Iin29 ), .c3(Iin30 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els1 (.y(Itmp52 ), .c1(Itmp43 ), .c2(Itmp44 ), .c3(Itmp45 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els2 (.y(Itmp55 ), .c1(Itmp50 ), .c2(Itmp51 ), .c3(Itmp52 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els3 (.y(out), .c1(Itmp53 ), .c2(Itmp54 ), .c3(Itmp55 ), .vdd(vdd), .vss(vss));
endmodule

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-- Master.tag File, Rev:1.0
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module tmpl_0_0dataflow__neuro_0_0ctree_332_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , Iin31 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
input Iin9 ;
input Iin10 ;
input Iin11 ;
input Iin12 ;
input Iin13 ;
input Iin14 ;
input Iin15 ;
input Iin16 ;
input Iin17 ;
input Iin18 ;
input Iin19 ;
input Iin20 ;
input Iin21 ;
input Iin22 ;
input Iin23 ;
input Iin24 ;
input Iin25 ;
input Iin26 ;
input Iin27 ;
input Iin28 ;
input Iin29 ;
input Iin30 ;
input Iin31 ;
output out;
// -- signals ---
wire Itmp43 ;
wire Itmp61 ;
wire Iin28 ;
wire Itmp40 ;
wire Itmp32 ;
wire Itmp54 ;
wire Iin10 ;
wire Iin9 ;
wire Itmp42 ;
wire Itmp36 ;
wire Iin3 ;
wire Iin2 ;
wire Iin30 ;
wire Itmp44 ;
wire Iin14 ;
wire Iin17 ;
wire Itmp35 ;
wire Itmp59 ;
wire Itmp56 ;
wire Iin24 ;
wire Iin4 ;
wire Itmp41 ;
wire Itmp58 ;
wire Iin31 ;
wire Iin20 ;
wire Itmp52 ;
wire Iin18 ;
wire Iin11 ;
wire Iin26 ;
wire Itmp39 ;
wire Itmp38 ;
wire Iin13 ;
wire Itmp34 ;
wire Itmp37 ;
wire Iin23 ;
wire Iin12 ;
wire Itmp50 ;
wire Itmp51 ;
wire Itmp48 ;
wire Iin16 ;
wire Iin15 ;
wire Iin7 ;
wire Iin0 ;
wire Iin21 ;
wire Iin19 ;
wire Itmp33 ;
wire Itmp53 ;
wire Itmp45 ;
wire Iin22 ;
wire Itmp49 ;
wire Itmp47 ;
wire Iin29 ;
wire Iin8 ;
wire Iin6 ;
wire Iin1 ;
wire Itmp57 ;
wire Iin25 ;
wire Itmp55 ;
wire out ;
wire Itmp60 ;
wire Itmp46 ;
wire Iin27 ;
wire Iin5 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp32 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp33 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(Itmp34 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3 (.y(Itmp35 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4 (.y(Itmp36 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5 (.y(Itmp37 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els6 (.y(Itmp38 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els7 (.y(Itmp39 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els8 (.y(Itmp40 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els9 (.y(Itmp41 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els10 (.y(Itmp42 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els11 (.y(Itmp43 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els12 (.y(Itmp44 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els13 (.y(Itmp45 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els14 (.y(Itmp46 ), .c1(Iin28 ), .c2(Iin29 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els15 (.y(Itmp47 ), .c1(Iin30 ), .c2(Iin31 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els16 (.y(Itmp48 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els17 (.y(Itmp49 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els18 (.y(Itmp50 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els19 (.y(Itmp51 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els20 (.y(Itmp52 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els21 (.y(Itmp53 ), .c1(Itmp42 ), .c2(Itmp43 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els22 (.y(Itmp54 ), .c1(Itmp44 ), .c2(Itmp45 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els23 (.y(Itmp55 ), .c1(Itmp46 ), .c2(Itmp47 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els24 (.y(Itmp56 ), .c1(Itmp48 ), .c2(Itmp49 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els25 (.y(Itmp57 ), .c1(Itmp50 ), .c2(Itmp51 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els26 (.y(Itmp58 ), .c1(Itmp52 ), .c2(Itmp53 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els27 (.y(Itmp59 ), .c1(Itmp54 ), .c2(Itmp55 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els28 (.y(Itmp60 ), .c1(Itmp56 ), .c2(Itmp57 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els29 (.y(Itmp61 ), .c1(Itmp58 ), .c2(Itmp59 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els30 (.y(out), .c1(Itmp60 ), .c2(Itmp61 ), .vdd(vdd), .vss(vss));
endmodule

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module tmpl_0_0dataflow__neuro_0_0ctree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
output out;
// -- signals ---
wire Iin0 ;
wire Iin2 ;
wire Iin1 ;
wire out ;
wire Itmp5 ;
wire Itmp4 ;
wire Iin3 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp4 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp5 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(out), .c1(Itmp4 ), .c2(Itmp5 ), .vdd(vdd), .vss(vss));
endmodule

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module tmpl_0_0dataflow__neuro_0_0ctree_37_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
output out;
// -- signals ---
wire Iin5 ;
wire Itmp9 ;
wire Iin6 ;
wire Iin4 ;
wire Iin2 ;
wire Iin1 ;
wire Itmp7 ;
wire out ;
wire Iin0 ;
wire Itmp8 ;
wire Iin3 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp7 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp8 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0 (.y(Itmp9 ), .c1(Iin4 ), .c2(Iin5 ), .c3(Iin6 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els1 (.y(out), .c1(Itmp7 ), .c2(Itmp8 ), .c3(Itmp9 ), .vdd(vdd), .vss(vss));
endmodule

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module tmpl_0_0dataflow__neuro_0_0ctree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , out, vdd, vss);
input vdd;
input vss;
input Iin0 ;
input Iin1 ;
input Iin2 ;
input Iin3 ;
input Iin4 ;
input Iin5 ;
input Iin6 ;
input Iin7 ;
input Iin8 ;
output out;
// -- signals ---
wire Iin5 ;
wire Itmp9 ;
wire Itmp11 ;
wire Iin2 ;
wire Itmp10 ;
wire Iin6 ;
wire Iin3 ;
wire out ;
wire Iin4 ;
wire Iin0 ;
wire Iin1 ;
wire Itmp12 ;
wire Itmp14 ;
wire Iin8 ;
wire Iin7 ;
wire Itmp13 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp9 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1 (.y(Itmp10 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2 (.y(Itmp11 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3 (.y(Itmp13 ), .c1(Itmp9 ), .c2(Itmp10 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4 (.y(Itmp14 ), .c1(Itmp11 ), .c2(Itmp12 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5 (.y(out), .c1(Itmp13 ), .c2(Itmp14 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0 (.y(Itmp12 ), .c1(Iin6 ), .c2(Iin7 ), .c3(Iin8 ), .vdd(vdd), .vss(vss));
endmodule

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module tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iin_d5_d0 , Iin_d5_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , Iout30 , Iout31 , Iout32 , Iout33 , Iout34 , Iout35 , Iout36 , Iout37 , Iout38 , Iout39 , Iout40 , Iout41 , Iout42 , Iout43 , Iout44 , Iout45 , Iout46 , Iout47 , Iout48 , Iout49 , Iout50 , Iout51 , Iout52 , Iout53 , Iout54 , Iout55 , Iout56 , Iout57 , Iout58 , Iout59 , Iout60 , Iout61 , Iout62 , Iout63 , vdd, vss);
input vdd;
input vss;
input Iin_d0_d0 ;
input Iin_d0_d1 ;
input Iin_d1_d0 ;
input Iin_d1_d1 ;
input Iin_d2_d0 ;
input Iin_d2_d1 ;
input Iin_d3_d0 ;
input Iin_d3_d1 ;
input Iin_d4_d0 ;
input Iin_d4_d1 ;
input Iin_d5_d0 ;
input Iin_d5_d1 ;
// -- signals ---
output Iout61 ;
output Iout7 ;
output Iout1 ;
wire Iatree61_in1 ;
wire Iin_d2_d1 ;
output Iout33 ;
output Iout29 ;
wire Iin_d4_d0 ;
wire Iin_d3_d1 ;
output Iout21 ;
output Iout17 ;
output Iout3 ;
wire Iatree47_in4 ;
output Iout55 ;
output Iout28 ;
output Iout14 ;
output Iout9 ;
wire Iatree63_in3 ;
wire Iin_d0_d0 ;
wire Iin_d4_d1 ;
wire Iin_d5_d1 ;
output Iout50 ;
output Iout41 ;
output Iout5 ;
output Iout6 ;
output Iout60 ;
output Iout42 ;
output Iout58 ;
output Iout44 ;
output Iout37 ;
output Iout31 ;
output Iout4 ;
wire Iatree63_in2 ;
output Iout13 ;
wire Iatree62_in0 ;
wire Iin_d3_d0 ;
wire Iin_d1_d0 ;
output Iout57 ;
output Iout36 ;
output Iout23 ;
wire Iatree59_in2 ;
output Iout49 ;
output Iout30 ;
output Iout20 ;
output Iout2 ;
output Iout51 ;
output Iout10 ;
output Iout16 ;
wire Iin_d5_d0 ;
wire Iin_d1_d1 ;
wire Iatree31_in5 ;
output Iout43 ;
output Iout0 ;
output Iout63 ;
output Iout47 ;
output Iout39 ;
output Iout19 ;
output Iout12 ;
output Iout59 ;
output Iout54 ;
output Iout26 ;
output Iout27 ;
output Iout18 ;
wire Iatree55_in3 ;
output Iout56 ;
output Iout11 ;
output Iout8 ;
output Iout45 ;
wire Iatree63_in4 ;
wire Iatree63_in0 ;
output Iout62 ;
output Iout48 ;
output Iout24 ;
wire Iin_d2_d0 ;
output Iout38 ;
output Iout25 ;
output Iout22 ;
output Iout52 ;
wire Iatree63_in5 ;
output Iout15 ;
output Iout53 ;
wire Iatree63_in1 ;
wire Iin_d0_d1 ;
output Iout46 ;
output Iout34 ;
output Iout40 ;
output Iout35 ;
output Iout32 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree1 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree2 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree3 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree4 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree5 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree6 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout6 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree7 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout7 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree8 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout8 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree9 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout9 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree10 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout10 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree11 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout11 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree12 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout12 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree13 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout13 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree14 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout14 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree15 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout15 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree16 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout16 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree17 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout17 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree18 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout18 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree19 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout19 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree20 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout20 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree21 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout21 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree22 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout22 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree23 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout23 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree24 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout24 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree25 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout25 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree26 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout26 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree27 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout27 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree28 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout28 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree29 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout29 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree30 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout30 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree31 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout31 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree32 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout32 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree33 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout33 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree34 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout34 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree35 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout35 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree36 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout36 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree37 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout37 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree38 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout38 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree39 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout39 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree40 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout40 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree41 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout41 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree42 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout42 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree43 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout43 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree44 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout44 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree45 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout45 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree46 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout46 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree47 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout47 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree48 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout48 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree49 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout49 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree50 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout50 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree51 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout51 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree52 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout52 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree53 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout53 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree54 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout54 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree55 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout55 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree56 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout56 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree57 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout57 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree58 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout58 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree59 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout59 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree60 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout60 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree61 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout61 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree62 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout62 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree63 (.Iin0 (Iatree63_in0 ), .Iin1 (Iatree63_in1 ), .Iin2 (Iatree63_in2 ), .Iin3 (Iatree63_in3 ), .Iin4 (Iatree63_in4 ), .Iin5 (Iatree63_in5 ), .out(Iout63 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_tX0 (.in(Iin_d0_d1 ), .Iout0 (Iatree63_in0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_tX1 (.in(Iin_d1_d1 ), .Iout0 (Iatree63_in1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_tX2 (.in(Iin_d2_d1 ), .Iout0 (Iatree63_in2 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_tX3 (.in(Iin_d3_d1 ), .Iout0 (Iatree63_in3 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_tX4 (.in(Iin_d4_d1 ), .Iout0 (Iatree63_in4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_tX5 (.in(Iin_d5_d1 ), .Iout0 (Iatree63_in5 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_fX0 (.in(Iin_d0_d0 ), .Iout0 (Iatree62_in0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_fX1 (.in(Iin_d1_d0 ), .Iout0 (Iatree61_in1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_fX2 (.in(Iin_d2_d0 ), .Iout0 (Iatree59_in2 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_fX3 (.in(Iin_d3_d0 ), .Iout0 (Iatree55_in3 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_fX4 (.in(Iin_d4_d0 ), .Iout0 (Iatree47_in4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iin_fX5 (.in(Iin_d5_d0 ), .Iout0 (Iatree31_in5 ), .vdd(vdd), .vss(vss));
endmodule

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test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4/netlist/master.tag
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-- Master.tag File, Rev:1.0
verilog.v

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test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4/netlist/verilog.v
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module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , en, Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , vdd, vss);
input vdd;
input vss;
input Iin_d0_d0 ;
input Iin_d0_d1 ;
input Iin_d1_d0 ;
input Iin_d1_d1 ;
input Iin_d2_d0 ;
input Iin_d2_d1 ;
input en;
// -- signals ---
wire Isb_en_out0 ;
wire Iin_d2_d0 ;
wire Idecoder_final_refresh_d0_d1 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout5 ;
wire Idecoder_final_refresh_d2_d0 ;
wire Ien_ands_t2_y ;
wire Idecoder_final_refresh_d1_d0 ;
output Iout4 ;
wire Ien_ands_t0_y ;
wire Iin_d0_d0 ;
output Iout2 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout0 ;
wire Ien_ands_f2_y ;
wire Ien_ands_t1_y ;
wire Ien_ands_f1_y ;
output Iout3 ;
wire Iin_d2_d1 ;
wire Idecoder_final_refresh_d2_d1 ;
wire Iin_d1_d0 ;
wire en;
output Iout1 ;
wire Iin_d1_d1 ;
wire Iin_d0_d1 ;
wire Ien_ands_f0_y ;
// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_36_4 Isb_en (.in(en), .Iout0 (Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t0 (.y(Ien_ands_t0_y ), .a(Iin_d0_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t1 (.y(Ien_ands_t1_y ), .a(Iin_d1_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t2 (.y(Ien_ands_t2_y ), .a(Iin_d2_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f0 (.y(Ien_ands_f0_y ), .a(Iin_d0_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f1 (.y(Ien_ands_f1_y ), .a(Iin_d1_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f2 (.y(Ien_ands_f2_y ), .a(Iin_d2_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
endmodule

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test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4/netlist/master.tag
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-- Master.tag File, Rev:1.0
verilog.v

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