Michele cf66c0e665 added a vtree_5 test		2022-03-05 20:29:02 +01:00
..
andtree_5	added and tree	2022-03-01 12:22:36 +01:00
andtree_15	added and tree	2022-03-01 12:22:36 +01:00
arbiter	pushed merge in primitives.act	2022-02-28 18:58:32 +01:00
arbiter_2	…
arbiter_handshake_adv	…
arbiter_handshake_simple	…
arbiter_tree_test	arbiter_tree works	2022-03-03 12:39:10 +01:00
arbtree_5	arbtree init, using or2s for now	2022-03-03 10:47:37 +01:00
async_instantiate	…
buf_15	…
buf_s_5	unit tests working	2022-03-01 09:58:20 +01:00
buffer_token	…
ctree_15	differentiated between ctree and vtree, all primitives updated	2022-03-01 09:44:51 +01:00
decoder_2d_dly_8_16	decoder 2d dly init	2022-03-02 15:55:26 +01:00
decoder_2d_dly_and_2_4	decoder dly with and grid unit test	2022-03-03 17:10:55 +01:00
delayprog_4	programmable delay tested	2022-03-01 15:26:43 +01:00
demux_7	…
demux_td_2	finished and simmed demuxtd	2022-03-01 17:56:30 +01:00
demux_td_2_SIGN	finished and simmed demuxtd	2022-03-01 17:56:30 +01:00
encoder_7	renamed encoder to dualrail_encoder	2022-03-04 14:53:14 +01:00
fifo3_8bit	…
fifo_t_5	fifo t 5 unit tests checked	2022-02-28 15:52:20 +01:00
fifo_t_15	…
flipflop	flipflop test updated	2022-03-04 21:12:52 +01:00
fork_15	…
line_end_pull_up	Added stuff for line end pull U/D	2022-03-04 12:33:49 +01:00
merge_t_2_adv	merge tested with concurrent inputs work	2022-03-01 17:36:49 +01:00
merge_t_2_simple	merge with simple test is working	2022-03-01 17:14:10 +01:00
ortree_15	…
register_write	register simulates correctly up to the fake clock generation	2022-03-05 20:28:50 +01:00
sigbuf_15	…
std_instantiate	…
vtree_5	added a vtree_5 test	2022-03-05 20:29:02 +01:00
vtree_15	differentiated between ctree and vtree, all primitives updated	2022-03-01 09:44:51 +01:00
buf_15.v	Added stuff for line end pull U/D	2022-03-04 12:33:49 +01:00
helper.scm	…
init.prs	…
init_qdi.prsim	…