started first example of the testbench, got segmentation fault
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@ -12,8 +12,8 @@ begin sim
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string sim::testbench::fcheck_next "check_next"
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string sim::testbench::fdump_to_file "dump_to_file"
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string sim::testbench::fcontrol_next "control_next"
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string sim::testbench::fcontrol_next "control_get"
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string sim::testbench::fcontrol_next "control_wait"
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string sim::testbench::fcontrol_get "control_get"
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string sim::testbench::fcontrol_wait "control_wait"
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end
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end
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end
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@ -24,15 +24,20 @@
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*/
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namespace sim::testbench {
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namespace sim{
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namespace testbench {
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function fsource_init(int verbose) : int;
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function finit (int verbose) : int;
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function fsource_next(int id; int sim_step) : int;
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function fsource_get(int id; int bit_width) : int;
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function fcheck_next(int id; int sim_step) : int;
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function fcheck_in_order(int id; int data) : int;
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function fcheck_out_of_order(int id; int data) : int;
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function fdump_to_file(int id; int sim_step; int data) : int;
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function fcontrol_next(int dontcare) : int;
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function fcontrol_get(int dontcare) : int;
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function fcontrol_wait(int dontcare) : int;
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template<pint BIT_WIDTH;pint ID>
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defproc channel_source(chan!(int<BIT_WIDTH>) out; chan?(int) sim_step; chan!(int) done)
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@ -40,8 +45,8 @@ defproc channel_source(chan!(int<BIT_WIDTH>) out; chan?(int) sim_step; chan!(int
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int current_step, t,data;
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chp {
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*[ sim_step?current_step; t := 1;
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*[ t = 1 -> t := fchannel_source_next(ID,current_step);
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[ t = 1 -> data := fchannel_source_get(ID,BIT_WIDTH); out!data ; log("send ", data, " on source ", ID)
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*[ t = 1 -> t := fsource_next(ID,current_step);
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[ t = 1 -> data := fsource_get(ID,BIT_WIDTH); out!data ; log("send ", data, " on source ", ID)
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[] else -> done!1
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]
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]
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@ -88,10 +93,11 @@ defproc channel_checker_out_of_order(chan?(int<BIT_WIDTH>) in; chan?(int) sim_st
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template<pint BIT_WIDTH;pint ID>
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defproc channel_dump(chan?(int<BIT_WIDTH>) in; chan?(int) sim_step)
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{
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int current_step, t;
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int current_step, t,in_tmp;
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chp {
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*[ [ #sim_step -> sim_step?current_step
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| #in -> t:=fdump_to_file(ID,current_step,in)
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[] #in -> in?in_tmp; t:=fdump_to_file(ID,current_step,in_tmp) //here should be non-deterministic but it doesn't work
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]
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]
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}
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@ -106,13 +112,13 @@ defproc control(chan(int) sim_step_source[NUMBER_SOURCE]; chan(int) sim_step_che
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t:=1;
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failure_free:=1;
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*[ t = 1 -> current_step := fcontrol_get();
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[ current_step = 0 -> skip; // reset here
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[ current_step = 0 -> skip // reset here
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[] else ->
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(,:j:1..NUMBER_SOURCE: sim_step_source[j]!current_step),
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(,:j:1..NUMBER_CHECKER: sim_step_checker[j]!current_step),
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(,:j:1..NUMBER_DUMP: sim_step_dump[j]!current_step);
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(:j:1..NUMBER_SOURCE: done_source[j]?success; failure_free := failure_free & success);
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(:j:1..NUMBER_CHECKER: done_checker[j]?success; failure_free := failure_free & success);
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(,j:1..NUMBER_SOURCE: sim_step_source[j]!current_step),
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(,j:1..NUMBER_CHECKER: sim_step_checker[j]!current_step),
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(,j:1..NUMBER_DUMP: sim_step_dump[j]!current_step);
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(;j:1..NUMBER_SOURCE: done_source[j]?success; failure_free := failure_free & success);
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(;j:1..NUMBER_CHECKER: done_checker[j]?success; failure_free := failure_free & success)
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];
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wait := fcontrol_wait();
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[ wait > 0 -> skip // exec cycle
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@ -125,3 +131,4 @@ defproc control(chan(int) sim_step_source[NUMBER_SOURCE]; chan(int) sim_step_che
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}
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}
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}
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}
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@ -234,7 +234,7 @@ struct expr_res check_in_order (int num, struct expr_res *args)
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t.v = 1;
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}
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else {
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check_errors++
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check_errors++;
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fprintf(logfile,"[FAILURE] expected %d got %d on check %d - %d; Error count %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,i,check_errors); fflush(logfile);
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t.v = 0;
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}
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@ -280,7 +280,7 @@ struct expr_res check_out_of_order (int num, struct expr_res *args)
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if (t.v == 0){
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check_errors++;
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fprintf(logfile,"[FAILURE] could not find %d on check %d; Error count: %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,check_errors); fflush(logfile);
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}s
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}
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t.width = 1;
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return t;
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}
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@ -42,7 +42,10 @@ because the controller sets the time out in verilog set your simulation time in
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this unit is called **control**, it reads a file with the name `control.csv`.
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the csv format is, one line per simulation step:
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``` first line: <start step>, <end step> all other lines: <simulation step>, <time to wait for> ```
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```
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first line: <start step>, <end step> all other lines: <simulation step>, <time to wait for>
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```
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step 0 is the test initialisation - so the reset sequence - and is always
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executed, it can not be used in the test bench.
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@ -101,6 +104,10 @@ the maximum vector width is assumed with 64 bits, as limited by actsim plugin sy
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currenty the files are read and searched in the excecution folder of actsim.
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## Installation
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- make sure you have your ACT flow installed (otherwise go here https://github.com/bics-rug/yale-asyncvlsi-actflow/releases/tag/rowling)
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-
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## running actsim
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the config file has to be included to load the test bench,
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34
test/examples/helloworld.act
Normal file
34
test/examples/helloworld.act
Normal file
@ -0,0 +1,34 @@
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/*************************************************************************
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*
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*
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* Copyright 2022 Ole Richter - University of Groningen
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* Copyright 2022 Michele Mastella - University of Groningen
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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**************************************************************************
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*/
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import "../../act/test_bench_lib.act";
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import globals;
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defproc test(){
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chan(int<5>) channel;
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//sim::testbench::control<1,1,0,1> control;
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//sim::testbench::channel_source<5,0> source(.out=channel,.sim_step=control.sim_step_source[0],.done=control.done_source[0]);
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//sim::testbench::channel_checker_in_order<5,0> sink(.in=channel,.sim_step=control.sim_step_checker,.done=control.done_checker[0]);
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}
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