Michele
|
7fe31f0ed8
|
started testing the register_w (doesn't compile)
|
2022-03-04 21:17:30 +01:00 |
|
Michele
|
8dabc59a03
|
flipflop test updated
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2022-03-04 21:12:52 +01:00 |
|
Michele
|
c30a46d6d8
|
I think the encoder2D compiles now
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2022-03-04 21:11:34 +01:00 |
|
Michele
|
b5fa707c4e
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forgot proc in defproc
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2022-03-04 19:04:11 +01:00 |
|
Michele
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72ec59cbcf
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added flip flop from XFAB
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2022-03-04 19:02:34 +01:00 |
|
Michele
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250f5bcc58
|
Added A_2C2P_RB_X1 because the encoder needs it
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2022-03-04 19:02:12 +01:00 |
alexmadison
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9b3bdc3f6c
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rejigged A cell in encoder2d
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2022-03-04 15:09:49 +01:00 |
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alexmadison
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a53110dda4
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renamed encoder to dualrail_encoder
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2022-03-04 14:53:14 +01:00 |
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alexmadison
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2882bc0f24
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encoder unit test
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2022-03-04 14:32:02 +01:00 |
|
alexmadison
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4a4c4eeb14
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merged encoder
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2022-03-04 14:27:38 +01:00 |
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alexmadison
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f55322bc7c
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encoder init
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2022-03-04 14:10:15 +01:00 |
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Michele
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18cf090b45
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-04 13:11:44 +01:00 |
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Michele
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e8fa8e43a6
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Changed FF in std. Started test (spoiler: is not working)
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2022-03-04 13:11:34 +01:00 |
 Greatorex
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828fccfb38
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-04 12:34:00 +01:00 |
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Greatorex
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1abcc9dc55
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Added stuff for line end pull U/D
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2022-03-04 12:33:49 +01:00 |
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Michele
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9c6a591dc7
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started registers
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2022-03-04 11:44:00 +01:00 |
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Michele
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b6c70f7f5e
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fixed vdd and vss in encoder sigbuf
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2022-03-04 11:43:49 +01:00 |
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Michele
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397c832b7b
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Added Flip Flop to std.act (still need to try it)
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2022-03-04 11:43:33 +01:00 |
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Michele
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15d3fd1b9b
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Added sigbuf_1output for signals that cannot have array outputs
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2022-03-03 19:23:13 +01:00 |
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Michele
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a4889ae844
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fixed conflict with Madison commit
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2022-03-03 17:54:29 +01:00 |
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Michele
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d64afd8c50
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-03 17:53:40 +01:00 |
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Michele
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ba096bf6b2
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wired up most of the stuff in encoder (missing dual rail tree)
Obv not simulated yet and not sure all wires are correct. still need to repass through them
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2022-03-03 17:52:42 +01:00 |
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alexmadison
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382714d11e
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decoder dly with and grid unit test
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2022-03-03 17:10:55 +01:00 |
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alexmadison
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c8412606b3
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merged
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2022-03-03 17:10:16 +01:00 |
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alexmadison
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893f71db92
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AND grid init
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2022-03-03 17:09:00 +01:00 |
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alexmadison
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da5948f493
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added N=1 cases
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2022-03-03 17:05:56 +01:00 |
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Michele
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0e9f2ae506
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started encoder on the coders.act
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2022-03-03 15:10:31 +01:00 |
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Michele
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e53fc88054
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arbiter_tree works
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2022-03-03 12:39:10 +01:00 |
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Michele
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f7cd7006d0
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removed arbiter_tree from primitives because is already in coders
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2022-03-03 12:15:17 +01:00 |
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Michele
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24a6260862
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Merged encoder_wip into dev
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2022-03-03 12:14:48 +01:00 |
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Michele
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f5859040d8
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Arbiter tree test
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2022-03-03 12:11:20 +01:00 |
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Michele
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3e1b63c201
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continued handshaking tree, not finished
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2022-03-03 12:11:20 +01:00 |
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Michele
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b49b9d98c3
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started arbiter tree
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2022-03-03 12:11:20 +01:00 |
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alexmadison
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6fc3e4b99c
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removed arbiter tree
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2022-03-03 11:56:59 +01:00 |
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alexmadison
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af52c688a3
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arbiter tree with arbiters, not tested
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2022-03-03 11:56:34 +01:00 |
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alexmadison
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d0a2fff096
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arbiter init with or2s
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2022-03-03 10:52:29 +01:00 |
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alexmadison
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7f40b48b49
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arbtree init, using or2s for now
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2022-03-03 10:47:37 +01:00 |
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alexmadison
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9c27248e12
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decoder 2d dly init
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2022-03-02 15:55:26 +01:00 |
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alexmadison
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3bba9fefa4
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made buf with dly sorry
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2022-03-02 15:48:54 +01:00 |
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alexmadison
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31d2f35042
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i am a moron re dly cells
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2022-03-02 15:47:36 +01:00 |
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alexmadison
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c61a570f80
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fixed wiring bug in prog delay
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2022-03-02 15:11:22 +01:00 |
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alexmadison
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6bece2f459
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renamed gates in or tree
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2022-03-02 13:51:12 +01:00 |
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alexmadison
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659cd2479c
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oops accidentally hit all trees
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2022-03-02 13:50:04 +01:00 |
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alexmadison
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c5e582ff3e
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renamed vars in atree
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2022-03-02 13:48:57 +01:00 |
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alexmadison
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e52ec9ed61
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renamed var in vtree for consciences
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2022-03-02 11:51:45 +01:00 |
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alexmadison
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c580d21efe
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fixed supply in fifo_t
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2022-03-02 11:24:28 +01:00 |
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alexmadison
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1b7e39bc00
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coders.act file init
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2022-03-02 09:48:41 +01:00 |
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alexmadison
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8060051da0
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Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
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2022-03-02 09:48:11 +01:00 |
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alexmadison
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b456ea40fd
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changed delayprog to outin vs ya naming scheme
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2022-03-02 09:48:05 +01:00 |
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Michele
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9f5bbc487d
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some more supplies added, need still to run all the codes
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2022-03-01 19:02:10 +01:00 |