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base: bics/actlib_dataflow_neuro:4c208bc18a42f0313303de580dfa793f6626dd8e
Branches Tags
bics/actlib_dataflow_neuro:dev bics/actlib_dataflow_neuro:main bics/actlib_dataflow_neuro:encoder_wip
bics/actlib_dataflow_neuro:TexelTapeout
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compare: bics/actlib_dataflow_neuro:encoder_wip
Branches Tags
bics/actlib_dataflow_neuro:main bics/actlib_dataflow_neuro:dev bics/actlib_dataflow_neuro:encoder_wip
bics/actlib_dataflow_neuro:TexelTapeout
2 Commits
4c208bc18a .. encoder_wip
Author SHA1 Message Date
Michele 97732b2f72 continued handshaking tree, not finished 2022-03-02 18:38:17 +01:00
Michele 9e144e1c17 started arbiter tree 2022-03-02 08:22:56 +01:00
223 changed files with 799 additions and 8541529 deletions
Expand all files Collapse all files
Fixing_Verilog.ipynb
-140
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@@ -1,140 +0,0 @@
{
"cells": [
{
"cell_type": "code",
"execution_count": 26,
"metadata": {},
"outputs": [],
"source": [
"import re\n",
"\n",
"with open('/home/p305119/libraries/xp018/actlib_dataflow_neuro/test/unit_tests/texel_small.v') as f:\n",
" veri = f.read()\n",
" \n",
"\"remove all std/acell modules\"\n",
"\n",
" \n",
"mod = re.findall(r'(?<=\\n)module [^A-Z(]*[A-Z][A-Z0-9_]*\\([\\s\\S]*?endmodule', veri)\n",
"\n",
"for i in mod: \n",
" \n",
" veri = veri.replace(i, \"\")\n",
" \n",
"\n",
"std = re.findall(r'((\\S*)(TBUF\\d*|INV|N?AND\\d|N?OR\\d|TIELO|TIEHI|MUX\\d|OAI\\d*|AOI\\d*|(?<!T)BUF\\d*|DLY\\d*|KEEP\\d*)(__X\\d))', veri)\n",
"\n",
"\"\"\"replace all stdcell names\"\"\"\n",
"\n",
"for j in list(set(std)):\n",
" veri = veri.replace(j[0], j[2] + j[3][1:])\n",
" \n",
" \n",
"keep = re.findall(r'((\\S*)(KEEP\\d*)())', veri)\n",
"\n",
"\"\"\"Replace all KEEPs\"\"\"\n",
"\n",
"for j in list(set(keep)):\n",
" veri = veri.replace(j[0], j[2] + j[3][1:])\n",
" \n",
" \n",
"acell = re.findall(r'(\\S*)(A_[1234CPNRSUB_]{2,12}(_X\\d)?\\b(?=[^<>]))', veri)\n",
"\n",
"for j in list(set(acell)):\n",
" veri = veri.replace(j[0] + j[1], j[1].replace('__', '_'))\n",
" \n",
" \n",
"arb = re.findall(r'(\\S*)(ARBITER)', veri)\n",
"\n",
"for j in list(set(arb)):\n",
" veri = veri.replace(j[0] + j[1], 'ARBITER')\n",
" \n",
" \n",
"pullu = re.findall(r'(\\S*)(PULLUP__X4)', veri)\n",
"\n",
"for j in list(set(pullu)):\n",
" veri = veri.replace(j[0] + j[1], 'PULLUP_X4')\n",
" \n",
" \n",
"pulld = re.findall(r'(\\S*)(PULLDOWN__X4)', veri)\n",
"\n",
"for j in list(set(pulld)):\n",
" veri = veri.replace(j[0] + j[1], 'PULLDOWN_X4')\n",
" \n",
"veri = veri.replace('));', '), .vdd(vdd), .vss(vss));')\n",
"\n",
"vddvss = re.findall(r'(?<=\\n)(module [\\([\\s\\S]*?;)', veri)\n",
"\n",
"for j in list(set(vddvss)):\n",
" veri = veri.replace(j, j[:-2] + \", vdd, vss); \\n input vdd;\\n input vss;\")\n",
" \n",
"# veri = veri.replace('[', '')\n",
"veri = veri.replace('_0_0t', 't')\n",
"\n",
"hierac = re.findall(r'(\\\\\\S* )', veri)\n",
"\n",
"for j in list(set(hierac)):\n",
" temp = j.replace(']', '')\n",
" temp = temp.replace('[', '')\n",
" temp = temp.replace('.', '_')\n",
" temp = temp.replace('\\\\', 'I')\n",
" \n",
" veri = veri.replace(j, temp)\n",
" \n",
" \n",
"with open('/home/p305119/libraries/xp018/actlib_dataflow_neuro/test/unit_tests/texel_small_clean.v', 'w') as w:\n",
" w.write(veri)\n",
"\n",
"\n"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
}
],
"metadata": {
"kernelspec": {
"display_name": "Python 3",
"language": "python",
"name": "python3"
},
"language_info": {
"codemirror_mode": {
"name": "ipython",
"version": 3
},
"file_extension": ".py",
"mimetype": "text/x-python",
"name": "python",
"nbconvert_exporter": "python",
"pygments_lexer": "ipython3",
"version": "3.7.3"
}
},
"nbformat": 4,
"nbformat_minor": 2
}
dataflow_neuro/.DS_Store
Vendored
BIN
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dataflow_neuro/cell_lib_async.act
+4 -193
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@@ -26,30 +26,6 @@
namespace tmpl {
namespace dataflow_neuro{
export defcell KEEP (bool y; bool vdd, vss) {
bool _y;
prs{
y => _y-
// [weak=1] _y -> y-
// [weak=1] ~_y -> y+
}
}
export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
(~c1)|~pr_B -> _y+
c1 & n1 & n2 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
@@ -65,22 +41,6 @@ namespace tmpl {
}
}
export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
bool _y;
prs{
(~p1 & ~c1 & ~c2)|~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
prs{
(~p1 & ~c1)|~pr_B -> y-
@@ -130,81 +90,6 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C1N_X1 (bool! y; bool? c1, n1; bool vdd, vss)
{
prs{
~c1 -> y+
c1&n1-> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
// export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
// {
// bool _y;
// prs{
// ~c1 | ~pr_B-> _y+
// c1&n1&sr_B -> _y-
// _y => y-
// }
// sizing {leak_adjust <- 1;
// p_n_mode <- 1;
// y {-4}; _y{-1}}
// }
// export defcell A_1C1N_SB_X4 (bool! y; bool? c1, n1, pr, sr; bool vdd, vss)
// {
// bool _y;
// prs{
// ~c1 & ~sr-> _y+
// c1&n1 | pr -> _y-
// _y => y-
// }
// sizing {leak_adjust <- 1;
// p_n_mode <- 1;
// y {-4}; _y{-1}}
// }
export defcell A_1C2N_R_X1 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{
prs{
~c1 | ~pr_B-> y+
c1&n1&n2&sr_B -> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}}
}
export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{
bool _y;
prs{
~c1 | ~pr_B-> _y+
c1&n1&n2&sr_B -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_1C2N_SB_X4 (bool! y; bool? c1, n1, n2, pr, sr; bool vdd, vss)
{
bool _y;
prs{
~c1 & ~sr-> _y+
c1&n1&n2 | pr -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
{
prs{
@@ -252,12 +137,12 @@ namespace tmpl {
y {-1}}
}
export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, na1, na2, nb1, nb2, pr_B, sr_B; bool vdd, vss)
export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & ((na1 & na2) | (nb1 & nb2)) & sr_B -> _y-
c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
_y => y-
}
sizing {
@@ -429,19 +314,6 @@ namespace tmpl {
p_n_mode <- 1;
y {-1}; _y{-1}}
}
export defcell A_2C1N_R_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
prs{
(~c1 & ~c2) | ~pr_B -> y+
c1 & c2 & n1 & sr_B -> y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
export defcell A_2C1N_RB_X4(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
@@ -610,11 +482,11 @@ namespace tmpl {
y {-1}; _y{-1} }
}
export defcell A_4P1N1N_X1 (bool! y; bool? na1, nb1, p1, p2, p3, p4; bool? vdd, vss)
export defcell A_4P1N1N_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
{
prs{
~p1 & ~p2 & ~p3 & ~p4 -> y+
na1 | nb1 -> y-
n1 | n2 -> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
@@ -652,67 +524,6 @@ namespace tmpl {
mk_excllo(_y1, _y2)
}
}
export
defproc A_1N_U_X4(bool? n1; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] n1 -> y-
}
}
export
defproc A_2N_U_X4(bool? n1, n2; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] n1 & n2 -> y-
}
}
export
defproc A_1P_U_X4(bool? p1; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 -> y+
}
}
export
defproc A_2P_U_X4(bool? p1, p2; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 & ~p2 -> y+
}
}
export
defproc A_3P_U_X4(bool? p1, p2, p3; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 & ~p2 & ~p3-> y+
}
}
export
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
A_1N_U_X4 cell(.n1 = a, .y = y, .vdd = vdd, .vss = vss);
}
export
defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) {
A_1P_U_X4 cell(.p1 = a, .y = y, .vdd = vdd, .vss = vss);
}
defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
bool _y;
prs{
(~p1 & ~p2 & ~c1 & ~c2)|~reset_B -> _y+
(c1 & c2 & reset_B) -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1} }
}
}}
dataflow_neuro/cell_lib_std.act
+11 -73
View File
@@ -94,19 +94,7 @@ namespace tmpl {
{
sizing { _y {-4,2}; y {-8,4} }
}
export defcell BUF_X12<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X16<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X24<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X32<: buf()
export defcell BUF_X12<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
@@ -114,23 +102,13 @@ namespace tmpl {
/*-- delay cells --*/
// TODO properly
// export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
// {
// bool _y, __y, ___y;
// prs {
// a => _y-
// _y => __y-
// __y => ___y-
// ___y => y-
// }
// }
export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
{
BUF_X1 bufchain[16];
(i:0..14: bufchain[i].y = bufchain[i+1].a;)
bufchain[0].a = a;
bufchain[15].y = y;
bool _y;
prs {
a => _y-
_y => y-
}
}
@@ -294,9 +272,7 @@ namespace tmpl {
export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
{
// y = !( S ? b : a )
// Actually looks more like
// if s = 0 -> use A
// y = !( S ? a : b )
// Adjusted to fit the XFAB Muxes
bool _s;
bool _y;
@@ -378,8 +354,8 @@ namespace tmpl {
prs {
en => _en-
~a & ~_en -> y-
a & en -> y+
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-1}; y{-1} }
}
@@ -390,49 +366,11 @@ namespace tmpl {
prs {
en => _en-
~a & ~_en -> y-
a & en -> y+
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-2}; y{-2,2} }
}
export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y-
a & en -> y+
}
sizing { _en{-4}; y{-4,4} }
}
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
{
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
prs {
// Creating delayed versions of the clock
clk_B => _clk_B-
_clk_B => __clk_B-
(~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
_mqib => _mqi-
(~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
_sqib => _sqi-
_sqib => q-
q => q_B-
}
}
}
}
dataflow_neuro/chips.act
-795
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@@ -1,795 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
REG_NCA, REG_NCW, REG_M>
defproc texel_core (avMx1of2<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
// Dummy synapses and neurons in the handshake blocks
// should be removed pre-innovus, else they are floating.
// a1of1 synapses[N_SYN_X * N_SYN_Y];
// a1of1 neurons[N_NRN_X * N_NRN_Y];
// Synapse decoder stuff
// The analogue core and connects to these to replace the above synapses.
bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
bool? dec_ackB[N_SYN_X];
a1of1 syn_pu[N_SYN_X];
// Neuron encoder stuff
a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
// Monitors and flags to/from core, and selected mon out.
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI;
bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful
// Onwards
fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
// Register
fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
.supply = supply, .reset_B = reset_reg_B);
fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
// Spike Decoder
pint NC_SYN;
NC_SYN = NC_SYN_X + NC_SYN_Y;
slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
.ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
.out_req_x = dec_req_x, .out_req_y = dec_req_y,
.to_pu = syn_pu,
.in_ackB_decoder = dec_ackB,
.supply = supply, .reset_B = _reset_BX);
INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG];
(i:N_SYN_DLY_CFG:
dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
dly_cfg_inverters[i].vdd = supply.vdd;
dly_cfg_inverters[i].vss = supply.vss;
decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
)
// Synapse handshake circuits, to be removed for innovus
// decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
// .synapses = synapses,
// .in_req_x = dec_req_x, .in_req_y = dec_req_y,
// .to_pu = syn_pu,
// .out_ackB_decoder = dec_ackB,
// .supply = supply);
// Neurons + encoder
pint NC_NRN;
NC_NRN = NC_NRN_X + NC_NRN_Y;
encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
.inx = enc_inx, .iny = enc_iny,
.reset_B = _reset_BX, .supply = supply,
.to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
.reset_B = _reset_BX, .supply = supply);
// Neuron handshake circuits, to be removed for innovus
// nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
// .outx = enc_inx, .outy = enc_iny,
// .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
// .supply = supply, .reset_B = _reset_BX);
// Merge
append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
append<N_IN-2, 2, 2> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
.supply = supply, .reset_B = _reset_BX);
// Output
fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
.reset_B = _reset_BX, .supply = supply);
// Neuron/synapse monitor targeters
pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
nrn_mon_dec_x.en = register.data[1].d[0].t;
(i:NC_NRN_MON_X:
nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
)
sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
nrn_mon_dec_y.en = register.data[1].d[0].t;
(i:NC_NRN_MON_Y:
nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
)
sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
.supply = supply);
syn_mon_dec_x.en = register.data[1].d[1].t;
(i:NC_SYN_MON_X:
syn_mon_dec_x.in.d[i] = register.data[3].d[i];
)
sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
syn_mon_dec_y.en = register.data[1].d[1].t;
(i:NC_SYN_MON_Y:
syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
)
sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
// Stops the possibility of dev_mon being high while some other sig is high.
// Otherwise boom.
// Also the 4th monitor line to each synapse is active LOW, needs inverter.
bool DEV_DEBUG;
pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
.supply = supply);
DEV_DEBUG = sb_DEV_DEBUG.out[0];
INV_X1 syn_targ_set_high_inv[NSMX4];
[NSMX4 >= 1 ->
AND2_X1 ands_devmon[NSMX4];
(i:NSMX4:
ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
ands_devmon[i].b = DEV_DEBUG;
ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
ands_devmon[i].vdd = supply.vdd;
ands_devmon[i].vss = supply.vss;
syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
syn_targ_set_high_inv[i].vdd = supply.vdd;
syn_targ_set_high_inv[i].vss = supply.vss;
)
// Wire up the remaining lines.
(i:N_SYN_MON_X:
[(~(i%4 = 1)) & (~(i%4=3))->
syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
]
)
]
// Create TBUFs for each synapse column,
// ctrl wired to mon line (first in each 4).
TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_SYN:
(i:N_SYN_X:
index = i*N_MON_AMZO_PER_SYN + j;
syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
)
syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
syn_AMZO_keeps[j].vdd = supply.vdd;
syn_AMZO_keeps[j].vss = supply.vss;
)
// Create TBUFs for each neuron column, and add keeps.
// ctrl wired to mon line (first in each 4).
TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_NRN:
(i:N_NRN_X:
index = i*N_MON_AMZO_PER_NRN + j;
nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
)
nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
nrn_AMZO_keeps[j].vdd = supply.vdd;
nrn_AMZO_keeps[j].vss = supply.vss;
)
// Create buffered signals from register to nrns.
sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
(i:N_FLAGS_PER_NRN:
sb_nrn_EFO.in[i] = register.data[5].d[i].t;
)
// Create buffered signals from register to synapses.
// Includes safety on the first 3 flags with dev mon.
sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
(i:3..N_FLAGS_PER_SYN-1:
sb_syn_EFO.in[i] = register.data[4].d[i].t;
)
AND2_X1 syn_flags_dev_safety[3];
(i:0..2:
syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
syn_flags_dev_safety[i].vdd = supply.vdd;
syn_flags_dev_safety[i].vss = supply.vss;
)
// Create non-buffered reset signals for the neuron/syn handshakes
// Since sigs are buffered before each neuron.
sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
}
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_singlecore (bd<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
// a1of1 synapses[N_SYN_X * N_SYN_Y];
// a1of1 neurons[N_NRN_X * N_NRN_Y];
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// Onwards to core
fifo<N_IN,N_BUFFERS> fifo_fork2core(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core(.in = fifo_fork2core.out,
.reg_data = reg_data,
// .synapses = synapses,
// .neurons = neurons,
.nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
.syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
.syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
.syn_mon_AMZO = syn_mon_AMZO, .nrn_mon_AMZO = nrn_mon_AMZO,
.syn_flags_EFO = syn_flags_EFO, .nrn_flags_EFO = nrn_flags_EFO,
.reset_B = _reset_BX,
.supply = supply
);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_core2mrg(.in = core.out,
.reset_B = _reset_BX, .supply = supply);
// merge core output and loopback
merge<N_IN> merge_drop8core(.in1 = fifo_core2mrg.out, .in2 = fifo_drop2mrg.out,
.supply = supply, .reset_B = _reset_BX);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = merge_drop8core.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI
){
// Reset buffers
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// Onwards to core demux
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
// Cores
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core1(.in = fifo_dmx2core1.out,
.reg_data = c1_reg_data,
// .synapses = c1_synapses,
// .neurons = c1_neurons,
.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
.dec_ackB = c1_dec_ackB,
.syn_pu = c1_syn_pu,
.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
.reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
.supply = supply
);
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core2(.in = fifo_dmx2core2.out,
.reg_data = c2_reg_data,
// .synapses = c2_synapses,
// .neurons = c2_neurons,
.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
.dec_ackB = c2_dec_ackB,
.syn_pu = c2_syn_pu,
.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
.reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
.supply = supply
);
fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
// Merge cores
append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
.supply = supply, .reset_B = _reset_BX);
// Merge cores and loopback
merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
.reset_B = _reset_BX, .supply = supply);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_dualcore_mapper (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI;
// MAPPER STUFF
bool? mapper_en;
avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
avMx1of2<29> in_sram_r; // Readout packets from SRAM
avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
){
// Reset buffers
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// dmx to SRAM
bool is_to_sram, is_to_cores;
fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX);
sram_dmx.cond.d.d[0].t = is_to_sram;
sram_dmx.cond.d.d[0].f = is_to_cores;
AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t,
.y = is_to_sram,
.vdd = supply.vdd, .vss = supply.vss);
OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f,
.y = is_to_cores,
.vdd = supply.vdd, .vss = supply.vss);
slice_data<32, 0, 30> pre_sram_slice(.supply = supply);
pre_sram_slice.in.a = sram_dmx.out2.a;
pre_sram_slice.in.v = sram_dmx.out2.v;
(i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
.reset_B = _reset_BX, .supply = supply);
// fifo_out_sram_wr.in.a = pre_sram_slice.out.a;
// fifo_out_sram_wr.in.v = pre_sram_slice.out.v;
// (i:29:fifo_out_sram_wr.in.d.d[i] = pre_sram_slice.out.d.d[i];)
// fifo_out_sram_wr.in.d.d[29] = pre_sram_slice.in.d.d[31];
// spikes from sram
// requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]
fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply);
append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply);
merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply);
merge_dmx8spk.in2.a = sram_spk_in_append.out.a;
merge_dmx8spk.in2.v = sram_spk_in_append.out.v;
(i:13: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i];)
merge_dmx8spk.in2.d.d[31] = sram_spk_in_append.out.d.d[13];
(i:13..30: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i+1];)
// Onwards to core demux
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = merge_dmx8spk.out, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
// Cores
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core1(.in = fifo_dmx2core1.out,
.reg_data = c1_reg_data,
// .synapses = c1_synapses,
// .neurons = c1_neurons,
.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
.dec_ackB = c1_dec_ackB,
.syn_pu = c1_syn_pu,
.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
.reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
.supply = supply
);
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core2(.in = fifo_dmx2core2.out,
.reg_data = c2_reg_data,
// .synapses = c2_synapses,
// .neurons = c2_neurons,
.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
.dec_ackB = c2_dec_ackB,
.syn_pu = c2_syn_pu,
.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
.reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
.supply = supply
);
fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
// Merge cores
append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
.supply = supply, .reset_B = _reset_BX);
// fork after core merge then go to mapper if its a spike
fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply);
dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply);
// Need to have it then drop the spike if its from a register.
demux_td<32, false> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data
drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30];
drop_if_reg.token.r = drop_if_reg.token.a;
fifo<8,N_BUFFERS> fifo_out_sram_spk(.out = out_sram_spk, .reset_B = _reset_BX, .supply = supply);
slice_data<32,0,8> slice_to_sram(.in = drop_if_reg.out, .out = fifo_out_sram_spk.in, .supply = supply);
// And move the msb (core bit) to just after the neuron address...
slice_to_sram.in.a = drop_if_reg.out.a;
slice_to_sram.in.v = drop_if_reg.out.v;
(i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];)
slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31];
(i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];)
// merge from cores and sram read in
fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply);
fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply);
append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply);
merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out,
.reset_B = _reset_BX, .supply = supply);
// Merge cores and loopback
fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply);
merge<N_IN> merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
.reset_B = _reset_BX, .supply = supply);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
}
}
dataflow_neuro/coders.act
-1184
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dataflow_neuro/dummy.act
-91
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@@ -1,91 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* Creates a synapse-neuron dummy block,
* where any synapse being triggered makes the neuron "spike".
*/
export template<pint N_SYN>
defproc dummy_neuron_block (a1of1 synapses[N_SYN], neuron; power supply){
// OR over reqs from syn in to neuron out
ortree<N_SYN> _ortree(.out = neuron.r, .supply = supply);
(i:N_SYN: _ortree.in[i] = synapses[i].r;)
// ANDs piping the ack back to the proper synapse
AND2_X1 ands[N_SYN];
(i:N_SYN:
ands[i].a = neuron.a;
ands[i].b = synapses[i].r;
ands[i].y = synapses[i].a;
ands[i].vss = supply.vss;
ands[i].vdd = supply.vdd;
)
}
/**
* Create an array of neuron dummy blocks.
* Note that this is custom made for the indexing on the texel chip.
* And so should be reused *with care*.
*/
export template<pint N_SYN_PER_NRN, N_NRN, N_NRN_X>
defproc dummy_neuron_core (a1of1 synapses[N_SYN_PER_NRN * N_NRN], neurons[N_NRN]; power supply){
dummy_neuron_block<N_SYN_PER_NRN> blocks[N_NRN];
pint Xn, Yn, Xs, Ys;
(i:N_NRN:
Yn = i/N_NRN_X;
Xn = i-Yn*N_NRN_X;
neurons[i] = blocks[i].neuron;
blocks[i].supply = supply;
(j:N_SYN_PER_NRN: // moron, need to think about neuron indexxing too
Xs = Xn;
Ys = Yn*N_SYN_PER_NRN + j;
blocks[i].synapses[j] = synapses[Ys*N_NRN_X + Xs];
)
)
}
}
}
dataflow_neuro/interfaces.act
-174
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@@ -1,174 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import std::channel;
open std::channel;
// import std::func;
open std;
import std::data;
open std::data;
namespace tmpl {
namespace dataflow_neuro {
/**
* Bundled data (non dual rail, with req)
* 2
* quasi delay insensitive channel (dual rail).
* Basically a buffer with a bitwise conversion in front of it.
*/
export template<pint N, N_dly_cfg, N_dly_cfg2>
defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
power supply; bool? reset_B) {
// Delay on req_in
bool _req;
delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
// sig buff the reset signal
bool _reset_BX, _reset_BXX[N*2];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// sig buff the req
bool _reqX, _reqXX[N*2];
BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
// For reasons of pure spice, the control circuitry
// requires a req signal that FALLS SLOWER than the req going to the function block.
// Thus need another delay prog.
bool _req_slowfall;
delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
.vss = supply.vss, .vdd = supply.vdd);
// bd2qdi conversion
// Each line goes to a t pin, its not to an f.
bool _inB[N];
INV_X1 input_invs[N];
(i:N:
input_invs[i].a = in.d[i];
input_invs[i].y = _inB[i];
input_invs[i].vss = supply.vss;
input_invs[i].vdd = supply.vdd;
)
// BUFFER
// Basically the buffer_s but with the validity tree ripped out
// and just connected to in_req instead.
// And probably need a delay on the in_ack to ensure en has time to disable
// before the inputs go to another state.
// Actually apparently no: there is a fixed, huge delay, already incurred
// by communicating with pads-> uC -> windows 95 and back again.
// Since the input is never invalid, also need a mechanism
// for the output to become invalid, when an out_ack is received.
//control
bool _en;
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_B;
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=out_a_B_buf.out[i];
t_buf_func[i].c2=out_a_B_buf.out[i+N];
f_buf_func[i].n1=_inB[i];
t_buf_func[i].n1=in.d[i];
f_buf_func[i].n2=_reqXX[i];
t_buf_func[i].n2=_reqXX[i+N];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
/**
* quasi delay insensitive channel (dual rail).
* 2
* Bundled data (non dual rail, with req)
*/
export template<pint N, N_dly_cfg>
defproc qdi2bd(avMx1of2<N> in; bd<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
// Buffer
buffer<N> buf(.in = in, .supply = supply, .reset_B = reset_B);
buf.out.a = out.a;
// Vtree
vtree<N> out_vtree(.supply = supply);
(i:N:
out_vtree.in.d[i].t = buf.out.d.d[i].t;
out_vtree.in.d[i].f = buf.out.d.d[i].f;
)
buf.out.v = out_vtree.out;
// Delay
delayprog<N_dly_cfg> dly(.in = out_vtree.out, .out = out.r, .s = dly_cfg, .supply = supply);
out_vtree.out = dly.in;
// Wire output data bits to buffer True lines
(i:N:
buf.out.d.d[i].t = out.d[i];
)
}
}
}
dataflow_neuro/primitives.act
+243 -361
View File
@@ -33,9 +33,6 @@ import "../../dataflow_neuro/treegates.act";
import std::channel;
open std::channel;
// import std::func;
namespace tmpl {
namespace dataflow_neuro {
@@ -78,8 +75,8 @@ namespace tmpl {
[(&i:M: d.d[i].t | d.d[i].f)];
self := 0;
(;i:M: [ d.d[i].t -> self := self | (1 << i)
[] else -> skip
]
[] else -> skip
]
)
}
@@ -111,35 +108,37 @@ namespace tmpl {
export template<pint N>
defproc buffer (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N*2];
bool _en, _reset_BX,_reset_BXX[N];
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_BX[N*2],_out_a_B;
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
A_2C1N_RB_X4 f_buf_func[N];
A_2C1N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B,.out=_out_a_BX, .supply = supply);
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=_out_a_BX[i];
t_buf_func[i].c2=_out_a_BX[i+N];
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].vdd=supply.vdd;
@@ -148,8 +147,8 @@ namespace tmpl {
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
// A template creating a FIFO of M buffers with N bits each
@@ -166,7 +165,7 @@ namespace tmpl {
fifo_element[i].supply = supply;
fifo_element[i].reset_B = _reset_BXX[i];
)
fifo_element[M-1].out = out;
fifo_element[N-1].out = out;
// reset buffers
bool _reset_BX;
@@ -194,31 +193,33 @@ namespace tmpl {
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
//validity
bool _in_v;
bool _in_v, _in_vX[N];
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf4(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> in_v_bufN(.in = in.v, .supply = supply);
sigbuf<N> in_v_bufN(.in = in.v, .out = _in_vX, .supply = supply);
//function
bool _out_a_B;
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=out_a_B_buf.out[i];
t_buf_func[i].c2=out_a_B_buf.out[i+N];
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].n2=in_v_bufN.out[i];
t_buf_func[i].n2=in_v_bufN.out[i+N];
f_buf_func[i].n2=_in_vX[i];
t_buf_func[i].n2=_in_vX[i];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
@@ -237,8 +238,6 @@ namespace tmpl {
OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
cond.a = in.a; // THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
cond.v = _in_c_v_;
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
@@ -257,19 +256,21 @@ namespace tmpl {
//function
//func buffer out1
bool _out1_a_B;
bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
A_2C2N_RB_X4 out1_f_buf_func[N];
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N*4> out_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out_en_buf.out[i];
out1_t_buf_func[i].c1=out_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].c1=_en1_X_f[i];
out1_t_buf_func[i].c1=_en1_X_t[i];
out1_f_buf_func[i].c2=_out1_a_BX_f[i];
out1_t_buf_func[i].c2=_out1_a_BX_t[i];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
@@ -280,36 +281,38 @@ namespace tmpl {
out1_t_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].pr_B = _reset_BXX[i];
out1_f_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].n2=_c_f_buf[i];
out1_t_buf_func[i].n2=_c_f_buf[i];
out1_f_buf_func[i].n2=_c_t_buf[i];
out1_t_buf_func[i].n2=_c_t_buf[i];
)
//func buffer out2
bool _out2_a_B;
bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
A_2C2N_RB_X4 out2_f_buf_func[N];
A_2C2N_RB_X4 out2_t_buf_func[N];
// sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
(i:N:
out2_f_buf_func[i].y=out2.d.d[i].f;
out2_t_buf_func[i].y=out2.d.d[i].t;
out2_f_buf_func[i].c1=out_en_buf.out[i+2*N];
out2_t_buf_func[i].c1=out_en_buf.out[i+3*N];
out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
out2_f_buf_func[i].c1=_en2_X_f[i];
out2_t_buf_func[i].c1=_en2_X_t[i];
out2_f_buf_func[i].c2=_out2_a_BX_f[i];
out2_t_buf_func[i].c2=_out2_a_BX_t[i];
out2_f_buf_func[i].n1=in.d.d[i].f;
out2_t_buf_func[i].n1=in.d.d[i].t;
out2_f_buf_func[i].vdd=supply.vdd;
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].n2=_c_t_buf[i];
out2_t_buf_func[i].n2=_c_t_buf[i];
out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].n2=_c_f_buf[i];
out2_t_buf_func[i].n2=_c_f_buf[i];
)
}
@@ -334,19 +337,21 @@ namespace tmpl {
//function
//func buffer out1
bool _out1_a_B;
bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
A_2C1N_RB_X4 out1_f_buf_func[N];
A_2C1N_RB_X4 out1_t_buf_func[N];
sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B);
sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t);
sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out1_en_buf.out[i];
out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].c1=_en1_X_f[i];
out1_t_buf_func[i].c1=_en1_X_t[i];
out1_f_buf_func[i].c2=_out1_a_BX_f[i];
out1_t_buf_func[i].c2=_out1_a_BX_t[i];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
@@ -359,64 +364,60 @@ namespace tmpl {
out1_f_buf_func[i].sr_B = _reset_BXX[i];
)
//func buffer out2
bool _out2_a_B;
bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
A_2C1N_RB_X4 out2_f_buf_func[N];
A_2C1N_RB_X4 out2_t_buf_func[N];
sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
(i:N:
out2_f_buf_func[i].y=out2.d.d[i].f;
out2_t_buf_func[i].y=out2.d.d[i].t;
out2_f_buf_func[i].c1=out2_en_buf.out[i];
out2_t_buf_func[i].c1=out2_en_buf.out[i+N];
out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
out2_f_buf_func[i].c1=_en2_X_f[i];
out2_t_buf_func[i].c1=_en2_X_t[i];
out2_f_buf_func[i].c2=_out2_a_BX_f[i];
out2_t_buf_func[i].c2=_out2_a_BX_t[i];
out2_f_buf_func[i].n1=in.d.d[i].f;
out2_t_buf_func[i].n1=in.d.d[i].t;
out2_f_buf_func[i].vdd=supply.vdd;
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i];
out2_t_buf_func[i].sr_B = _reset_BXX[i];
out2_f_buf_func[i].pr_B = _reset_BXX[i];
out2_f_buf_func[i].sr_B = _reset_BXX[i];
out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
)
}
// Demux
export template<pint N; pbool CONDITION_SIGN>
defproc demux_td (avMx1of2<N> in; avMx1of2<N> out; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
defproc demux_td (avMx1of2<N> in; avMx1of2<N> out1; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N], _out_v, _in_c_v_, _reset_BXt;
avMx1of2<N> out1 = out;
OR2_X1 out_or(.a=out1.v, .b=token.r, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_token(.a=_reset_BX, .y=_reset_BXt,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v, _c_tk_buf, _c_d_buf[N], _c_v, cond_inv_t, cond_inv_f;
cond.a = in.a;
cond.v = _c_v;
OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
//orientation of condition
[ CONDITION_SIGN ->
BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf, .supply=supply);
BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf);
sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf);
[] else ->
INV_X1 invout_t(.a = cond.d.d[0].t,.y=cond_inv_t,.vdd = supply.vdd,.vss=supply.vss);
INV_X1 invout_f(.a = cond.d.d[0].f,.y=cond_inv_f,.vdd = supply.vdd,.vss=supply.vss);
BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf, .supply=supply);
BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf);
sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf);
]
@@ -428,19 +429,21 @@ namespace tmpl {
//function
//func buffer out1
bool _out1_a_B;
bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
A_2C2N_RB_X4 out1_f_buf_func[N];
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t);
sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out1_en_buf.out[i];
out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].c1=_en1_X_f[i];
out1_t_buf_func[i].c1=_en1_X_t[i];
out1_f_buf_func[i].c2=_out1_a_BX_f[i];
out1_t_buf_func[i].c2=_out1_a_BX_t[i];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
@@ -459,8 +462,7 @@ namespace tmpl {
bool token_a_out;
A_2C2N_RB_X4 token_buf;
INV_X1 outt_a_inv(.a=token.a,.y=token_a_out, .vss = supply.vss, .vdd = supply.vdd);
INV_X1 outt_a_inv(.a=token.a,.y=token_a_out);
token_buf.y = token.r;
token_buf.c1 = _en;
@@ -473,64 +475,6 @@ namespace tmpl {
token_buf.pr_B = _reset_BXt;
token_buf.sr_B = _reset_BXt;
}
/**
* Drops a packet if condition is met, otherwise passes it on.
* This is a very lazy implementation, where the cond MUST NOT CHANGE DURING OPERATION.
* Means that this should be used in a very small set of circumstances.
*
* params:
* N: size of packet
* CONDITION_DROP: value of cond when packets are dropped.
*/
export template<pint N; pbool CONDITION_DROP>
defproc dropper_static (avMx1of2<N> in; avMx1of2<N> out; bool? cond; power supply) {
bool _drop, _dropB;
INV_X1 inv(.a = cond, .vss = supply.vss, .vdd = supply.vdd);
[~CONDITION_DROP ->
_dropB = cond;
_drop = inv.y;
[] CONDITION_DROP ->
_drop = cond;
_dropB = inv.y;
]
bool _in_vX;
vtree<N> vt(.in = in.d, .supply = supply);
BUF_X4 in_v_buf(.a = vt.out, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
AND2_X1 and2(.a = _drop, .b = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
OR2_X1 or2(.a = out.a, .b = and2.y, .vss = supply.vss, .vdd = supply.vdd);
A_2C_B_X1 ack_Cel(.c1 = or2.y, .c2 = _in_vX, .y = in.a);
// _in_vX = in.v;
// Sigbufs
sigbuf<N*2> sb_dropB(.in = _dropB, .supply = supply);
sigbuf<N*2+1> sb_in_v(.in = _in_vX, .supply = supply);
sb_in_v.out[2*N] = in.v;
AND3_X1 and_t[N];
AND3_X1 and_f[N];
(i:N:
and_t[i].a = in.d.d[i].t;
and_f[i].a = in.d.d[i].f;
and_t[i].y = out.d.d[i].t;
and_f[i].y = out.d.d[i].f;
and_t[i].b = sb_dropB.out[i];
and_f[i].b = sb_dropB.out[i+N];
and_t[i].c = sb_in_v.out[i];
and_f[i].c = sb_in_v.out[i+N];
and_t[i].vss = supply.vss;
and_t[i].vdd = supply.vdd;
)
}
export
@@ -545,26 +489,140 @@ namespace tmpl {
}
//The buffer_t_valid doesn't work
// export
// defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
// {
// //control
// bool _en, _reset_BX;
// A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
export
defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
{
//control
bool _en, _reset_BX;
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
// //function
// bool _out_a_B;
// INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
// A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
//function
bool _out_a_B;
INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
// //reset buffers
// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// }
//reset buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
}
// A tree composed by arbiters. The first layer takes N signals
export template<pint N>
defproc arbiter_tree(a1of1 in[N]; a1of1 out; power supply)
{
bool tout;
{ N > 0 : "Invalid N, should be greater than 0" };
/* We calculate here how many arbiters we need to create for the full tree */
pint inputs_in_layer, end, elements_in_layer;
pint odd_element_idx = 0;
pint odd_element_flag = 0;
inputs_in_layer = 0;
end = N-1;
pint element_counter = 0;
// Here we start a for loop to count the elements in the tree
// The loop iterates for every successive layer
// i is the variable used to iterate the inputs,
// j counts the elements in the layer
*[ inputs_in_layer != end ->
elements_in_layer = 0; // At every layer the counter of the elements is resetted
*[ inputs_in_layer < end ->
[ inputs_in_layer + 1 >= end ->
//In this case, the number of input is even: the layer finishes
inputs_in_layer = end;
odd_element_flag = 0;
[] inputs_in_layer + 2 >= end ->
//In this case, we arrived at the last input, this means the inputs are odd
//We need to save the odd input index and move it to the next layer,
//up to when the resulting number is even
odd_element_idx = end;
odd_element_flag = 1;
inputs_in_layer = end;
[] else ->
//If we are not close to the end, analyzes the next two inputs
inputs_in_layer = inputs_in_layer +2;
]
elements_in_layer = elements_in_layer + 1; //At every step the elements count is updated
]
//Move the inputs_in_layer to the next layer
//Increase the end to account for the next layer elements
//If there was an odd element, count it also in the end
inputs_in_layer = end + 1;
end = end + elements_in_layer + odd_element_flag;
element_counter = element_counter + elements_in_layer;
]
{ element_counter = 4 : "Michele you did wrong" };
// Creating the elements of the tree
arbiter_handshake arb_array[element_counter];
(i:element_counter:arb_array[i].supply = supply;)
// These are the wires that connect one element of the tree to the others
a1of1 channels[element_counter*2];
//Connecting the first channels to the inputs
(i:N:channels[i] = in[i];)
channels[element_counter*2-1] = out;
//Now we redo the for loop but here to assign the channels to the elements
odd_element_idx = 0;
odd_element_flag = 0;
inputs_in_layer = 0;
end = N-1;
{ end=4 : "Michele you did wrong" };
// Here we start a for loop to count the elements in the tree
// The loop iterates for every successive layer
// i is the variable used to iterate the inputs,
// j counts the elements in the layer
*[ inputs_in_layer != end ->
elements_in_layer = 0; // At every layer the counter of the elements is resetted
*[ inputs_in_layer < end ->
[ inputs_in_layer + 1 >= end ->
//In this case, the number of input is even: the layer finishes
[ odd_element_flag >= 1 ->
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[odd_element_idx];
[] else ->
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[inputs_in_layer+1];
]
inputs_in_layer = end;
odd_element_flag = 0;
[] inputs_in_layer + 2 >= end ->
//In this case, we arrived at the last input, this means the inputs are odd
//We need to save the odd input index and move it to the next layer,
//up to when the resulting number is even
odd_element_idx = end;
odd_element_flag = 1;
{ end<8 : "Michele you did wrong" };
{ odd_element_idx=4 : "Michele you did wrong" };
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[inputs_in_layer+1];
inputs_in_layer = end;
[] else ->
//If we are not close to the end, analyzes the next two inputs
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[inputs_in_layer+1];
inputs_in_layer = inputs_in_layer +2;
]
elements_in_layer = elements_in_layer + 1; //At every step the elements count is updated
]
//Move the inputs_in_layer to the next layer
//Increase the end to account for the next layer elements
//If there was an odd element, count it also in the end
inputs_in_layer = end + 1;
end = end + elements_in_layer + odd_element_flag;
element_counter = element_counter + elements_in_layer;
]
}
export template<pint N>
defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
@@ -578,7 +636,7 @@ namespace tmpl {
bool _in1_arb,_in2_arb,_in1_arb_X[2*N],_in2_arb_X[2*N];
A_4C_RB_X4 in1ack_ctl(.c1=_in1_arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_4C_RB_X4 in2ack_ctl(.c1=_in2_arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .na1 = in1.a,.nb1 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .n1 = in1.a,.n2 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> en_buffer(.in = _en,.out = _en_X,.supply=supply);
INV_X1 in1ack_ctl_inv(.a=in1.a,.y=_in1_a_B,.vdd=supply.vdd,.vss=supply.vss);
INV_X1 in2ack_ctl_inv(.a=in2.a,.y=_in2_a_B,.vdd=supply.vdd,.vss=supply.vss);
@@ -609,10 +667,10 @@ namespace tmpl {
(i:N:
merge_func_t[i].c1 = _en_X[i];
merge_func_t[i].c2 = _out_a_BX[i];
merge_func_t[i].na1 = _in1_arb_X[i];
merge_func_t[i].na2 = in1.d.d[i].t;
merge_func_t[i].nb1 = _in2_arb_X[i];
merge_func_t[i].nb2 = in2.d.d[i].t;
merge_func_t[i].n1 = _in1_arb_X[i];
merge_func_t[i].n2 = in1.d.d[i].t;
merge_func_t[i].n3 = _in2_arb_X[i];
merge_func_t[i].n4 = in2.d.d[i].t;
merge_func_t[i].y = out.d.d[i].t;
merge_func_t[i].vdd=supply.vdd;
merge_func_t[i].vss=supply.vss;
@@ -621,10 +679,10 @@ namespace tmpl {
merge_func_f[i].c1 = _en_X[i+N];
merge_func_f[i].c2 = _out_a_BX[i+N];
merge_func_f[i].na1 = _in1_arb_X[i+N];
merge_func_f[i].na2 = in1.d.d[i].f;
merge_func_f[i].nb1 = _in2_arb_X[i+N];
merge_func_f[i].nb2 = in2.d.d[i].f;
merge_func_f[i].n1 = _in1_arb_X[i+N];
merge_func_f[i].n2 = in1.d.d[i].f;
merge_func_f[i].n3 = _in2_arb_X[i+N];
merge_func_f[i].n4 = in2.d.d[i].f;
merge_func_f[i].y = out.d.d[i].f;
merge_func_f[i].vdd=supply.vdd;
merge_func_f[i].vss=supply.vss;
@@ -678,21 +736,12 @@ namespace tmpl {
// Programmable delay line.
// N is the number of layers,
// the longest layer having 2**N DLY elements
// Circuit for creating delays, there are N delay layers.
// The block has the parameters:
// N -> the number is the number of layers with the longest being 2**N elements
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data
// out -> output data
// s -> bit word with size N that sets delay configuration. int(s) = number of delays
export template<pint N>
defproc delayprog (bool! out; bool? in, s[N]; power supply)
defproc delayprog (bool! y; bool? a, s[N]; power supply)
{
{ N >= 0 : "What?" };
{ N < 10 : "Delay prog size is given in 2**N. Given N is ridiculous." };
{ N < 9 : "Delay prog size is given in 2**N. Given N is too big." };
AND2_X1 and2[N];
@@ -701,7 +750,7 @@ namespace tmpl {
bool _a[N+1]; // Holds the input to each row
_a[0] = in;
_a[0] = a;
pint i_delay;
i_delay = 0; // Index of the last connected delay element
@@ -714,7 +763,7 @@ namespace tmpl {
// Delays
dly[i_delay].a = and2[i].y;
i_delay = i_delay + 1;
(j:1..(1<<i)-1:
(j:1..i-1:
dly[i_delay].a = dly[i_delay-1].y;
i_delay = i_delay +1;
)
@@ -726,7 +775,7 @@ namespace tmpl {
_a[i+1] = mu2[i].y;
)
out = mu2[N-1].y;
y = mu2[N-1].y;
// Connect everything to vdd/gnd
@@ -738,171 +787,4 @@ namespace tmpl {
(i:N:mu2[i].vss = supply.vss;)
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
// Non programmable delays
// N is number of delays to have in series (not log!!).
// Is useful for testing purposes.
// But should probably remove before running innovus etc.
export template<pint N>
defproc delay_chain (bool out; bool in; power supply) {
{ N >= 0 : "What?" };
[N >= 1 ->
DLY4_X1 dly[N];
dly[0].vdd = supply.vdd;
dly[0].vss = supply.vss;
dly[0].a = in;
(i:1..N-1:
dly[i].vdd = supply.vdd;
dly[i].vss = supply.vss;
dly[i].a = dly[i-1].y;
)
dly[N-1].vdd = supply.vdd;
dly[N-1].vss = supply.vss;
dly[N-1].y = out;
[] N = 0 ->
in = out;
]
}
/**
* Appends a hard-coded word "VAL" to an input.
* Works by piping through all sigs, but adding
* some extra sigs when the input is valid.
* N is size of channel to pipe through.
* NVAL is size of word to be put on output.
* VAL is word to be put on output.
* Output looks like
* 0..............N........N+NVAL-1
* --input_data----LSB....MSB
*
*/
export template<pint N, NVAL, VAL>
defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
{
{ N >= 0 : "What?" };
{ NVAL >= 0 : "What?" };
{ VAL < 1<<NVAL : "VAL too big!" };
// valid tree
vtree<N> in_val(.supply = supply);
(i:N:
in_val.in.d[i].t = in.d.d[i].t;
in_val.in.d[i].f = in.d.d[i].f;
)
// wire through most signals
(i:N:
in.d.d[i].t = out.d.d[i].t;
in.d.d[i].f = out.d.d[i].f;
)
in.a = out.a;
in.v = out.v;
// appender
pint bitval;
sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
TIELO_X1 tielows[NVAL];
(i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
(i:0..NVAL-1:
bitval = (VAL & ( 1 << i )) >> i;
[ bitval = 1 ->
out.d.d[i+N].t = sb.out[i];
out.d.d[i+N].f = tielows[i].y;
[] bitval = 0 ->
out.d.d[i+N].f = sb.out[i];
out.d.d[i+N].t = tielows[i].y;
[] bitval >= 2 -> {false : "fuck"};
]
)
}
/**
* Drops bits. Slices lines. Crop in. Enhance.
* Useful if say, have an 8 bit packet coming in, but
* receiver only needs 3 of them.
* KEEPS all bits between the two bounds.
* e.g. drop_lines(8, 0, 3) would keep lines [0,1,2]
**/
export template<pint N, N0, N1>
defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out; power supply) {
// {N0 >= 0 : "N0 can be minimum 0!"};
// {N1 <= N : "N1 can be maximum N"};
pint _N1, _N0;
_N1 = std::min(N1,N);
_N0 = std::max(N0,0);
// BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
(i:_N1-_N0:
in.d.d[i + _N0] = out.d.d[i];
)
// in.a = out.a;
A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
}
export template<pint N; pint CONDITION_BIT>
defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
A_2C_B_X1 val_Cel(.c1 = demux.in.v, .c2 = demux.cond.v, .y = in.v,
.vdd = supply.vdd, .vss = supply.vss);
// Not actually needed bc the current version of demux
// Something like below should be added once the handshakes are properly decoupled.
// wires the data and cond ack lines together anyway.
// A_2C_B_X1 ack_Cel(.c1 = demux.in.a, .c2 = demux.cond.a, .y = in.a,
// .vdd = supply.vdd, .vss = supply.vss);
// in.v = demux.in.v;
in.a = demux.in.a;
(i:0..CONDITION_BIT-1:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
(i:CONDITION_BIT+1..N:
in.d.d[i].f = demux.in.d.d[i-1].f;
in.d.d[i].t = demux.in.d.d[i-1].t;)
}
export template<pint N>
defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux_bit<N,N> demux(.in = in, .out1 = out1, .out2 = out2, .reset_B = reset_B, .out1=out1, .out2=out2);
}
/**
* Create M sigbufs to buffer an M bool array to N strength.
* Done lazily.
**/
export template<pint M, N>
defproc sigbuf_boolarray(bool? in[M]; bool! out[M]; power supply) {
sigbuf<N> sb[M];
(i:M:
sb[i].in = in[i];
sb[i].out[0] = out[i];
sb[i].supply = supply;
)
}
}}
dataflow_neuro/registers.act
-410
View File
@@ -1,410 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* Buffer for use in an A-cell register.
* Basically the same as a normal buffer, except that when out.v goes high,
* in.a goes high too.
* Also, in.a does not wait for out.v to go low to go to low.
* Means have a buffer that completes its Right handshake as soon as out data is valid.
*/
export template<pint N>
defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
reset_B; power supply) {
//control
bool _en, _reset_BX[N];
bool _in_aB;
bool _reset;
bool _resetX[N];
// Reset sigs
INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
.pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
// Flush sigs
bool _flushB, _flushBX[N*2];
INV_X1 flush_inv(.a = flush, .y = _flushB);
sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
_en = _in_aB;
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
A_1C2N_SB_X4 f_buf_func[N];
A_1C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
(i:N:
f_buf_func[i].y=out.d[i].f;
t_buf_func[i].y=out.d[i].t;
f_buf_func[i].c1=_flushBX[i];
t_buf_func[i].c1=_flushBX[i+N];
f_buf_func[i].n2=en_buf.out[i];
t_buf_func[i].n2=en_buf.out[i+N];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
f_buf_func[i].pr = _resetX[i];
f_buf_func[i].sr = _resetX[i];
t_buf_func[i].pr_B = _reset_BX[i];
t_buf_func[i].sr_B = _reset_BX[i];
)
}
/**
* A single register made out of A cells.
* MSB is whether to read or write.
* Currently only handles writing.
*/
export template<pint N>
defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
bool? reset_B; power supply) {
bool _en2;
bool _w;
bool _out_v, _out_vB;
bool _flush, _flushB;
_w = in.d.d[N].t;
// Buffer
buffer_register<N> buf(.out = out, .out_v = _out_v, .flush = _flush,
.supply = supply, .reset_B = reset_B);
buf.in.v = in.v;
// In ack stuff
INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
// To stop in ack going low before en2 has been reset.
A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a,
.vdd = supply.vdd, .vss = supply.vss);
// Out valid tree
vtree<N> out_valid(.in = buf.out, .out = _out_v, .supply = supply);
INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss);
// Control
A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush,
.vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B);
INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss);
A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
.pr_B = reset_B, .sr_B = reset_B);
// Pass to let data into the buffer
NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> passX(.in = pass.y, .supply = supply);
AND2_X1 gandalf_t[N];
AND2_X1 gandalf_f[N];
(i:0..N-1:
gandalf_t[i].a = in.d.d[i].t;
gandalf_f[i].a = in.d.d[i].f;
gandalf_t[i].b = passX.out[i];
gandalf_f[i].b = passX.out[i+N];
gandalf_t[i].y = buf.in.d.d[i].t;
gandalf_f[i].y = buf.in.d.d[i].f;
gandalf_t[i].vdd = supply.vdd;
gandalf_f[i].vdd = supply.vdd;
gandalf_t[i].vss = supply.vss;
gandalf_f[i].vss = supply.vss;
)
}
/**
* Array of registers made out of A-cells
* params:
* NcW: number of bits in Words to be stored in buffers
* NcA: number of bits in Address
* M: number of registers. M = 2^Nc_addr would be a natural choice.
* Input packets should be
* [-addr-][-word-][r/w]
*/
// UNUSED
// UNUSED
// UNUSED
// UNUSED
// export template<pint NcA, NcW, M>
// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
// bool? reset_B; power supply) {
// // BIG TODO
// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
// .supply = supply);
// // Address decoder
// decoder_dualrail<NcA, M> decoder(.supply = supply);
// (i:NcA:
// decoder.in.d[i] = in.d.d[i];
// )
// // OrTree over acks from all registers
// ortree<M> ack_ortree(.supply = supply);
// // C element handling in ack
// A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
// .vss = supply.vss, .vdd = supply.vdd);
// // Write bit selector
// bool _w = in.d.d[NcA+NcW].t;
// A_2C_B_X1 write_selectors[M];
// (i:M:
// write_selectors[i].c1 = _w;
// write_selectors[i].c2 = decoder.out[i];
// write_selectors[i].vdd = supply.vdd;
// write_selectors[i].vss = supply.vss;
// )
// // Registers
// register_acells<NcW> registers[M];
// TIELO_X1 tielow_writebit_f[M];
// (i:M:
// // Connect each register to word inputs.
// (j:NcW:
// registers[i].in.d.d[j] = in.d.d[j + NcA];
// )
// // Connect the (selected) write bit
// registers[i].in.d.d[NcW].t = write_selectors[i].y;
// tielow_writebit_f[i].vdd = supply.vdd;
// tielow_writebit_f[i].vss = supply.vss;
// registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// // Connect to ack ortree
// registers[i].in.a = ack_ortree.in[i];
// // Connect outputs
// data[i] = registers[i].out;
// registers[i].supply = supply;
// registers[i].reset_B = reset_B;
// )
// }
/**
* Array of registers made out of A-cells
* params:
* NcW: number of bits in Words to be stored in buffers
* NcA: number of bits in Address
* M: number of registers. M = 2^Nc_addr would be a natural choice.
* Input packets should be
* [-addr-][-word-][r/w]
*/
export template<pint NcA, NcW, M>
defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
bool? reset_B; power supply) {
// Input valid tree
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
.supply = supply);
// Address decoder
decoder_dualrail<NcA, M> decoder(.supply = supply);
(i:NcA:
decoder.in.d[i] = in.d.d[i];
)
// OrTree over acks from all registers
ortree<M> ack_ortree(.supply = supply);
bool _write_ack;
// C element handling in ack
A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
.vss = supply.vss, .vdd = supply.vdd);
// Bit to join the acks either from read or write
bool _read_ack;
_read_ack = out.a;
OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
.vdd = supply.vdd, .vss = supply.vss);
A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
// Write bit selector
bool _w = in.d.d[NcA+NcW].t;
bool _wX[M];
sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
A_2C_B_X1 write_selectors[M];
(i:M:
write_selectors[i].c1 = _wX[i];
write_selectors[i].c2 = decoder.out[i];
write_selectors[i].vdd = supply.vdd;
write_selectors[i].vss = supply.vss;
)
// Registers
register_acells<NcW> registers[M];
TIELO_X1 tielow_writebit_f[M];
(i:M:
// Connect each register to word inputs.
(j:NcW:
registers[i].in.d.d[j] = in.d.d[j + NcA];
)
// Connect the (selected) write bit
registers[i].in.d.d[NcW].t = write_selectors[i].y;
tielow_writebit_f[i].vdd = supply.vdd;
tielow_writebit_f[i].vss = supply.vss;
registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// Connect to ack ortree
registers[i].in.a = ack_ortree.in[i];
// Connect outputs
data[i] = registers[i].out;
registers[i].supply = supply;
registers[i].reset_B = reset_B;
)
// Read bit selector
bool _r = in.d.d[NcA+NcW].f;
bool _rX[M+NcA];
sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
A_2C_B_X1 read_selectors[M];
sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
(i:M:
read_selectors[i].c1 = _rX[i];
read_selectors[i].c2 = decoder.out[i];
read_selectors[i].vdd = supply.vdd;
read_selectors[i].vss = supply.vss;
read_selectorsX.in[i] = read_selectors[i].y;
)
// OrTrees for each output word bit on read
ortree<M> out_ortrees_t[NcW];
ortree<M> out_ortrees_f[NcW];
(i:NcW:
out_ortrees_t[i].out = out.d.d[i+NcA].t;
out_ortrees_f[i].out = out.d.d[i+NcA].f;
out_ortrees_t[i].supply = supply;
out_ortrees_f[i].supply = supply;
)
// ANDs over each reg's data
// and whether it is selected for read.
AND2_X1 and_reads_t[NcW * M];
AND2_X1 and_reads_f[NcW * M];
pint index;
(i:NcW:
(j:M:
index = i + j*NcW;
and_reads_t[index].a = data[j].d[i].t;
and_reads_t[index].b = read_selectorsX.out[j];
and_reads_f[index].a = data[j].d[i].f;
and_reads_f[index].b = read_selectorsX.out[j];
and_reads_t[index].y = out_ortrees_t[i].in[j];
and_reads_f[index].y = out_ortrees_f[i].in[j];
and_reads_t[index].vss = supply.vss;
and_reads_t[index].vdd = supply.vdd;
and_reads_f[index].vss = supply.vss;
and_reads_f[index].vdd = supply.vdd;
)
)
// C elements passing address to out on read.
A_2C_B_X1 addr_read_t[NcA];
A_2C_B_X1 addr_read_f[NcA];
(i:NcA:
addr_read_t[i].c1 = in.d.d[i].t;
addr_read_f[i].c1 = in.d.d[i].f;
addr_read_t[i].c2 = _rX[M+i];
addr_read_f[i].c2 = _rX[M+i];
addr_read_t[i].y = out.d.d[i].t;
addr_read_f[i].y = out.d.d[i].f;
addr_read_t[i].vdd = supply.vdd;
addr_read_t[i].vss = supply.vss;
addr_read_f[i].vdd = supply.vdd;
addr_read_f[i].vss = supply.vss;
)
}
}}
dataflow_neuro/treegates.act
+38 -99
View File
@@ -26,7 +26,6 @@
**************************************************************************/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import std::channel;
open std::channel;
namespace tmpl {
@@ -48,9 +47,6 @@ defproc ortree (bool? in[N]; bool! out; power supply)
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
@@ -87,18 +83,18 @@ defproc ortree (bool? in[N]; bool! out; power supply)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
OR2_X1 or2s[lenTree2Count];
OR2_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
OR3_X1 or3s[lenTree3Count];
OR3_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:or2s[h].vdd = supply.vdd;)
(h:lenTree3Count:or3s[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:or2s[h].vss = supply.vss;)
(h:lenTree3Count:or3s[h].vss = supply.vss;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
@@ -121,25 +117,25 @@ defproc ortree (bool? in[N]; bool! out; power supply)
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
or3s[tree3Index].a = tmp[i];
or3s[tree3Index].b = tmp[i+1];
or3s[tree3Index].c = tmp[i+2];
or3s[tree3Index].y = tmp[end+j];
C3Els[tree3Index].a = tmp[i];
C3Els[tree3Index].b = tmp[i+1];
C3Els[tree3Index].c = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
@@ -151,8 +147,6 @@ defproc ortree (bool? in[N]; bool! out; power supply)
]
out = tmp[end];
]
}
export template<pint N>
@@ -162,11 +156,6 @@ defproc andtree (bool? in[N]; bool! out; power supply)
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
@@ -203,18 +192,18 @@ defproc andtree (bool? in[N]; bool! out; power supply)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
AND2_X1 and2s[lenTree2Count];
AND2_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
AND3_X1 and3s[lenTree3Count];
AND3_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:and2s[h].vdd = supply.vdd;)
(h:lenTree3Count:and3s[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:and2s[h].vss = supply.vss;)
(h:lenTree3Count:and3s[h].vss = supply.vss;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
@@ -237,25 +226,25 @@ defproc andtree (bool? in[N]; bool! out; power supply)
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
and3s[tree3Index].a = tmp[i];
and3s[tree3Index].b = tmp[i+1];
and3s[tree3Index].c = tmp[i+2];
and3s[tree3Index].y = tmp[end+j];
C3Els[tree3Index].a = tmp[i];
C3Els[tree3Index].b = tmp[i+1];
C3Els[tree3Index].c = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
@@ -267,8 +256,6 @@ defproc andtree (bool? in[N]; bool! out; power supply)
]
out = tmp[end];
]
}
/*
@@ -282,10 +269,6 @@ defproc ctree (bool? in[N]; bool! out; power supply)
{ N > 0 : "What?" };
bool meaningless_var;
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
@@ -389,11 +372,6 @@ defproc ctree (bool? in[N]; bool! out; power supply)
]
out = tmp[end];
]
}
@@ -402,23 +380,23 @@ defproc vtree (std::data::Mx1of2?<N> in; bool! out; power supply)
{
// OR layer for making OR between true and false of in (they are then sent to Ctree)
OR2_X1 OR2_tf[N];
ctree<N> ct;
ctree<N> myctree;
(l:N:
OR2_tf[l].a = in.d[l].t;
OR2_tf[l].b = in.d[l].f;
OR2_tf[l].y = ct.in[l];
OR2_tf[l].y = myctree.in[l];
OR2_tf[l].vdd = supply.vdd;
OR2_tf[l].vss = supply.vss;
)
ct.supply = supply;
out = ct.out;
myctree.supply = supply;
out = myctree.out;
}
export template<pint N>
defproc sigbuf (bool? in; bool! out[N]; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
// { N <= 43 : "sigbuf: parameter error, N too big" };
{ N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
@@ -433,49 +411,10 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 ->
[] N >= 30 & N <= 42 ->
BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 49 & N <= 64 ->
BUF_X16 buf16 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 65 & N <= 96 ->
BUF_X24 buf24 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 97 & N <=128 ->
BUF_X32 buf32 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
// [] N >= 129 & N <=192 ->
// BUF_X48 buf48 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
// [] N >= 193 & N <= 256->
// BUF_X64 buf64 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
]
(i:1..N-1:out[i]=out[0];)
}
//Sigbuf in which there is only 1 output. Made for outputs that cannot have multiple wires.
export template<pint N>
defproc sigbuf_1output (bool? in; bool! out; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
{ N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 5 & N <= 7 ->
BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 8 & N <= 10 ->
BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 11 & N <= 14 ->
BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 15 & N <= 18 ->
BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N <= 42 ->
BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
]
}
}}
test/prsim_plot.py
+7 -25
View File
@@ -1,4 +1,4 @@
#!/usr/bin/env python3
#!/usr/bin/python3
import sys
import glob
@@ -54,21 +54,17 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
raise Exception("Unknown colour given. I cba to code up general colours atm.")
# Check if start time given
t0 = None
for arg in argv:
r = re.findall(r'-t0=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
t0 = int[r[0]]
entries = [e for e in entries if int(e[0]) >= int(r[0])]
# Check if end time given
t1 = None
for arg in argv:
r = re.findall(r'-t1=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by end time t1 = {r[0]}")
t1 = int[r[0]]
entries = [e for e in entries if int(e[0]) <= int(r[0])]
@@ -99,18 +95,10 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
if len(r) >= 1:
include_all_times = True
# Check if user gave "nowarn" flag
plot_warn = True
for arg in argv:
r = re.findall(r'(-nowarn?)', arg)
if len(r) >= 1:
plot_warn = False
# Get list of all times (before filtering)
unique_times = np.unique([int(e[0]) for e in entries])
# assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
if include_given: print(f"Including signals that match regex {include_re}")
if exclude_given: print(f"Excluding signals that match regex {exclude_re}")
@@ -127,7 +115,6 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
# Get list of all times (after filtering)
times = np.array([int(e[0]) for e in entries])
if not include_all_times: unique_times = np.unique(times)
num_times = unique_times.shape[0]
# Get list of all sigs
sigs = np.array([e[1] for e in entries])
@@ -186,12 +173,8 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
# ax.set_ylabel("Signal")
ax.set_yticks([])
# Plot signal names
sig_repeat_period = 20
for sig in unique_sigs:
ax.text(-1, sig_to_index(sig), sig, ha = "right", va = "center", size = 10)
ax.text(num_times, sig_to_index(sig), sig, ha = "left", va = "center", size = 10)
for i in range(num_sigs-1):
ax.axhline(i+0.5, c = "white", lw = 2)
@@ -233,8 +216,8 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
ax.text(time_to_index(time), num_sigs, time, ha = "center", va = "top", size = 10, rotation = 90)
# Find and plot wrong Assert statements
asserts = re.findall(r"\t *(\d+) .*\n(WRONG ASSERT|WARNING):\t?(.+)", f)
if len(asserts): print("Warnings found!")
asserts = re.findall(r"\t *(\d+) .*\nWRONG ASSERT:\t(.+)", f)
if len(asserts): print("Failed asserts found!")
for a in asserts:
print(a)
time = int(a[0])
@@ -242,12 +225,11 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
try:
time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
except:
print(f"Couldn't find an appropriate time for warning {a}")
print(f"Couldn't find an appropriate time for assert {a}")
continue
index = time_to_index(time)
if plot_warn:
ax.axvline(index+0.5, c = "red", lw = 2)
ax.text(index+0.5, -1, a[2], rotation = 90, ha = "center", va = "bottom", c = "red")
ax.axvline(index+0.5, c = "red", lw = 2)
ax.text(index+0.5, -1, a[1], rotation = 90, ha = "center", va = "bottom", c = "red")
# Find echoed statements of the form "[digits] text"
echoes = re.findall(r"\t *(\d+) [^\t]*\n(\[\d*\].+)", f)
test/repeat_unit.sh
+75 -84
View File
@@ -1,94 +1,85 @@
#!/bin/sh
# repeatedly run prsim on one unit_test's PRs
fail=0
faildirs=""
proc=""
bold=$(tput bold)
normal=$(tput sgr0)
und=$(tput smul)
i=${unit}
proc="$i<>"
faildirs=""
failed=0
iteration=0
numberofruns=100
#
# run_test name [option]
#
run_test () {
echo "Testing ${bold}$1 ${normal} for $2 random delay runs"
# clear run directory
if [ -d $1/run ]; then
rm -rf $1/run
fi
mkdir $1/run
cp init.prs $1/run/test.prs
if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
echo "random_seed $2" > $1/run/prsim.in
cat init_qdi.prsim $1/test.prsim >> $1/run/prsim.in
cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
echo "${bold}*** simulation failed seed: $2 ***${normal}"
faildirs="${faildirs} ${1}-sim($2)"
failed=1
echo
fi
else
echo "${bold}*** circuit construction failed ***${normal}"
faildirs="${faildirs} ${1}-ckt"
failed=1
echo
fi
}
if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
echo "${bold}Error:${bold} aflat & prsim necessary for tests."
exit 1
fi
if [ ! -d "unit_tests" ];
then
echo "${bold}Error:${bold} no unit_tests directory."
exit 1
fi
echo ""
echo "${bold}******************************************"
echo "* ${i} repetitions , show warnings=${warning}*"
echo "******************************************${normal}"
cd "unit_tests"
echo "${bold}... checking aflat${normal}"
# run all test except single one is specified
if [ ! -z $3 ]; then
iteration=$3
fi
if [ ! -z $2 ]; then
numberofruns=$2
fi
if [ -z $1 ]; then
for i in *
do
if [ -d $i -a -f $i/test.act ]; then
while [ $iteration -lt $numberofruns ]
do
run_test $iteration
iteration=$iteration+1
done
fi
done
else
while [ $iteration -lt $numberofruns ]
do
run_test $1 $iteration
iteration=$((iteration+1))
done
# check aflat
if ($ACT_HOME/bin/aflat "$i/test_final.act" > "$i/test.prs");
then
echo "${bold}... aflat complete, checking in prsim${normal}"
# run prsim on prs
(($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test.prsim") > "$i/prsim.out");
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found")
then
echo "FAILED in first prsim"
else
# show warnings setting
if [ "${warning}" = "1" ];
then
echo "${bold}Exit on prsim warnings turned ON${normal}"
else
echo "${bold}Exit on prsim warnings turned OFF${normal}"
fi
echo ""
# begin prsim test loop
has_failed=0
iter=0
echo "${bold}using random_seed${normal}"
echo "\nusing random_seed" >> "$i/prsim.out"
while [ has_failed=0 ]
do
# write prsim test file with random seed appended to top of file
(echo "random_seed $iter \nrandom" > "$i/test_rand.prsim");
(cat "$i/test.prsim" >> "$i/test_rand.prsim");
(echo "\nTEST $iter\n" >> "$i/prsim.out");
# validate prsim output
if (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test_rand.prsim") >> "$i/prsim.out");
then
if [ "${warning}" = "1" ];
then
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found" -e "WARNING:");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
else
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
fi
else
has_failed=1
exit 0
fi
done
(cd ".."; pwd);
exit 1
fi
else
echo "FAILED in aflat conversion"
fi
if [ $failed -eq 1 ]; then
echo ""
echo "${bold}*********************************"
echo "* FAILED DIRECTORIES:${normal}$faildirs ${bold}*"
echo "*********************************${normal}"
fi
exit $failed
test/run.sh
+1 -2
View File
@@ -22,8 +22,7 @@ run_test () {
mkdir $1/run
cp init.prs $1/run/test.prs
if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
cat init_qdi.prsim $1/test.prsim > $1/run/prsim.in
cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
cat init_qdi.prsim $1/test.prsim | prsim -r $1/run/test.prs > $1/run/prsim.out
if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
echo "${bold}*** simulation failed ***${normal}"
faildirs="${faildirs} ${1}-sim"
test/unit_tests/.DS_Store
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test/unit_tests/append_5_3_2/run/prsim.out
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test/unit_tests/append_5_3_2/run/prsim.pdf
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test/unit_tests/append_5_3_2/test.act
-53
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@@ -1,53 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc append_5_3_2(avMx1of2<5> in; avMx1of2<8> out)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
fifo<5,4> fifo_pre(.in = in, .reset_B = _reset_B);
append<5,3,3> app(.in = fifo_pre.out);
fifo<5+3,4> fifo_post(.in = app.out, .out = out, .reset_B = _reset_B);
app.supply.vdd = Vdd;
app.supply.vss = GND;
fifo_pre.supply.vdd = Vdd;
fifo_pre.supply.vss = GND;
fifo_post.supply.vdd = Vdd;
fifo_post.supply.vss = GND;
}
append_5_3_2 b;
test/unit_tests/append_5_3_2/test.prsim
-78
View File
@@ -1,78 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set Reset 0
set-qdi-channel-neutral "b.in" 5
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 8
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 31'"
set-qdi-channel-valid "b.in" 5 31
cycle
assert-qdi-channel-valid "b.out" 8 127
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 0'"
set-qdi-channel-valid "b.in" 5 0
cycle
# assert-qdi-channel-valid "b.out" 8 96
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-valid "b.out" 8 96
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-neutral "b.out" 8
test/unit_tests/arbiter_tree_simple_nosim/run/prsim.out
-98
View File
@@ -1,98 +0,0 @@
my_tree.in[4].r my_tree.at_cell.tmp[6].r my_tree.at_cell.arbs[0].arbiter._y1 my_tree.in[2].a my_tree.at_cell.tmp[8].a my_tree.at_cell.arbs[0]._y1_arb my_tree.out.r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[2]._y2_arb my_tree.at_cell.arbs[3].ack_cell1._y my_tree.in[0].a my_tree.at_cell.tmp[6].a my_tree.in[4].a my_tree.at_cell.arbs[2].arbiter._y2 my_tree.in[1].a my_tree.out.a my_tree.at_cell.arbs[0].ack_cell1._y my_tree.in[0].r my_tree.at_cell.arbs[3].ack_cell2._y my_tree.in[3].r my_tree.at_cell.tmp[5].r my_tree.in[1].r my_tree.at_cell.arbs[0]._y2_arb my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1]._y1_arb my_tree.at_cell.arbs[1].ack_cell2._y my_tree.in[2].r my_tree.in[3].a my_tree.at_cell.tmp[8].r my_tree.at_cell.arbs[1]._y2_arb my_tree.at_cell.arbs[3]._y1_arb my_tree.at_cell.arbs[3].or_cell._y my_tree.at_cell.arbs[1].arbiter._y2 my_tree.at_cell.arbs[3].arbiter._y2 my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.arbs[3].arbiter._y1 my_tree.at_cell.arbs[0].ack_cell2._y my_tree.at_cell.arbs[3]._y2_arb my_tree.at_cell.arbs[2].ack_cell1._y my_tree.at_cell.arbs[1].or_cell._y my_tree.at_cell.arbs[2]._y1_arb my_tree.at_cell.arbs[1].arbiter._y1 my_tree.at_cell.arbs[0].or_cell._y my_tree.at_cell.arbs[0].arbiter._y2 my_tree.at_cell.arbs[2].or_cell._y my_tree.at_cell.arbs[2].arbiter._y1
1 my_tree.in[0].r : 0
1 my_tree.out.a : 0
1 my_tree.in[2].r : 0
1 my_tree.in[4].r : 0
1 my_tree.in[1].r : 0
1 my_tree.in[3].r : 0
3 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
117 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
1138 my_tree.at_cell.arbs[1].arbiter._y2 : 1 [by my_tree.in[3].r:=0]
2864 my_tree.at_cell.arbs[1]._y2_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y2:=1]
4754 my_tree.at_cell.arbs[0].arbiter._y2 : 1 [by my_tree.in[1].r:=0]
4793 my_tree.at_cell.arbs[0]._y2_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y2:=1]
7093 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree.in[0].r:=0]
7108 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
7599 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
7612 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
7652 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
8067 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
10468 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree.in[2].r:=0]
10488 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
16549 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
16596 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
16612 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
60710 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
65483 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
65487 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
74434 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
83563 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
83578 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
126826 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
126881 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
163757 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
178534 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
193537 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
207386 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218349 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218771 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
218772 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
218773 my_tree.in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
221729 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222011 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
222779 my_tree.in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
241934 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
241937 my_tree.in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
267485 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
289926 my_tree.in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
-------------------------------------------------
[0] System initialized
289926 Reset : 0
290477 my_tree._reset_B : 1 [by Reset:=0]
-------------------------------------------------
[1] System reset completed
290477 my_tree.in[0].r : 1
290477 my_tree.in[4].r : 1
290477 my_tree.in[2].r : 1
291431 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree.in[4].r:=1]
291548 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree.in[0].r:=1]
291558 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree.in[2].r:=1]
291576 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
292530 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
295589 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
296533 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
318117 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
322877 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
323379 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
323582 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
325436 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
340490 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
345901 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
346040 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
382386 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
382386 my_tree.out.a : 1
382455 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
382466 my_tree.in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
-------------------------------------------------
[2] Number 4 was chosen, move to the next one
382466 my_tree.in[4].r : 0
434252 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
434267 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434268 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
434305 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
434456 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434456 my_tree.out.a : 0
435195 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
435307 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
482819 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.in[4].a:=0]
482859 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
483116 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
483116 my_tree.out.a : 1
483203 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
483497 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
483498 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
485304 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
487311 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
488520 my_tree.in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
-------------------------------------------------
[2] Number 0 was chosen, finish test
test/unit_tests/arbiter_tree_simple_nosim/run/test.prs
-325
View File
@@ -1,325 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"my_tree._reset_B"-
~("Reset")->"my_tree._reset_B"+
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].arbiter.d"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].ack_cell1.y"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.a"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
~"my_tree.at_cell.arbs[0].ack_cell1.c1"&~"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"+
"my_tree.at_cell.arbs[0].ack_cell1.c1"&"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"-
"my_tree.at_cell.arbs[0].ack_cell1._y"->"my_tree.at_cell.arbs[0].ack_cell1.y"-
~("my_tree.at_cell.arbs[0].ack_cell1._y")->"my_tree.at_cell.arbs[0].ack_cell1.y"+
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].arbiter.c"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].ack_cell2.y"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.b"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].arbiter.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].or_cell.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell2.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell1.vdd"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].arbiter.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].or_cell.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell2.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell1.vss"
"my_tree.at_cell.arbs[0].arbiter.a"&"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"-
~"my_tree.at_cell.arbs[0].arbiter.a"|~"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"+
"my_tree.at_cell.arbs[0].arbiter.b"&"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"-
~"my_tree.at_cell.arbs[0].arbiter.b"|~"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"+
"my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c"->"my_tree.at_cell.arbs[0].arbiter.y1"-
~("my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c")->"my_tree.at_cell.arbs[0].arbiter.y1"+
"my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d"->"my_tree.at_cell.arbs[0].arbiter.y2"-
~("my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d")->"my_tree.at_cell.arbs[0].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[0].arbiter._y1","my_tree.at_cell.arbs[0].arbiter._y2")
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].arbiter.y1"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].or_cell.a"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].ack_cell1.c2"
~"my_tree.at_cell.arbs[0].ack_cell2.c1"&~"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"+
"my_tree.at_cell.arbs[0].ack_cell2.c1"&"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"-
"my_tree.at_cell.arbs[0].ack_cell2._y"->"my_tree.at_cell.arbs[0].ack_cell2.y"-
~("my_tree.at_cell.arbs[0].ack_cell2._y")->"my_tree.at_cell.arbs[0].ack_cell2.y"+
"my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b"->"my_tree.at_cell.arbs[0].or_cell._y"-
~("my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b")->"my_tree.at_cell.arbs[0].or_cell._y"+
"my_tree.at_cell.arbs[0].or_cell._y"->"my_tree.at_cell.arbs[0].or_cell.y"-
~("my_tree.at_cell.arbs[0].or_cell._y")->"my_tree.at_cell.arbs[0].or_cell.y"+
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell2.c1"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell1.c1"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].or_cell.y"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].arbiter.y2"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].or_cell.b"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].ack_cell2.c2"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].arbiter.d"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].ack_cell1.y"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.a"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
~"my_tree.at_cell.arbs[1].ack_cell1.c1"&~"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"+
"my_tree.at_cell.arbs[1].ack_cell1.c1"&"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"-
"my_tree.at_cell.arbs[1].ack_cell1._y"->"my_tree.at_cell.arbs[1].ack_cell1.y"-
~("my_tree.at_cell.arbs[1].ack_cell1._y")->"my_tree.at_cell.arbs[1].ack_cell1.y"+
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].arbiter.c"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].ack_cell2.y"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.b"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].arbiter.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].or_cell.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell2.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell1.vdd"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].arbiter.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].or_cell.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell2.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell1.vss"
"my_tree.at_cell.arbs[1].arbiter.a"&"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"-
~"my_tree.at_cell.arbs[1].arbiter.a"|~"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"+
"my_tree.at_cell.arbs[1].arbiter.b"&"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"-
~"my_tree.at_cell.arbs[1].arbiter.b"|~"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"+
"my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c"->"my_tree.at_cell.arbs[1].arbiter.y1"-
~("my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c")->"my_tree.at_cell.arbs[1].arbiter.y1"+
"my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d"->"my_tree.at_cell.arbs[1].arbiter.y2"-
~("my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d")->"my_tree.at_cell.arbs[1].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[1].arbiter._y1","my_tree.at_cell.arbs[1].arbiter._y2")
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].arbiter.y1"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].or_cell.a"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].ack_cell1.c2"
~"my_tree.at_cell.arbs[1].ack_cell2.c1"&~"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"+
"my_tree.at_cell.arbs[1].ack_cell2.c1"&"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"-
"my_tree.at_cell.arbs[1].ack_cell2._y"->"my_tree.at_cell.arbs[1].ack_cell2.y"-
~("my_tree.at_cell.arbs[1].ack_cell2._y")->"my_tree.at_cell.arbs[1].ack_cell2.y"+
"my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b"->"my_tree.at_cell.arbs[1].or_cell._y"-
~("my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b")->"my_tree.at_cell.arbs[1].or_cell._y"+
"my_tree.at_cell.arbs[1].or_cell._y"->"my_tree.at_cell.arbs[1].or_cell.y"-
~("my_tree.at_cell.arbs[1].or_cell._y")->"my_tree.at_cell.arbs[1].or_cell.y"+
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell2.c1"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell1.c1"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].or_cell.y"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].arbiter.y2"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].or_cell.b"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].ack_cell2.c2"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].arbiter.d"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].ack_cell1.y"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.a"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
~"my_tree.at_cell.arbs[2].ack_cell1.c1"&~"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"+
"my_tree.at_cell.arbs[2].ack_cell1.c1"&"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"-
"my_tree.at_cell.arbs[2].ack_cell1._y"->"my_tree.at_cell.arbs[2].ack_cell1.y"-
~("my_tree.at_cell.arbs[2].ack_cell1._y")->"my_tree.at_cell.arbs[2].ack_cell1.y"+
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].arbiter.c"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].ack_cell2.y"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.b"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].arbiter.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].or_cell.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell2.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell1.vdd"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].arbiter.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].or_cell.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell2.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell1.vss"
"my_tree.at_cell.arbs[2].arbiter.a"&"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"-
~"my_tree.at_cell.arbs[2].arbiter.a"|~"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"+
"my_tree.at_cell.arbs[2].arbiter.b"&"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"-
~"my_tree.at_cell.arbs[2].arbiter.b"|~"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"+
"my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c"->"my_tree.at_cell.arbs[2].arbiter.y1"-
~("my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c")->"my_tree.at_cell.arbs[2].arbiter.y1"+
"my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d"->"my_tree.at_cell.arbs[2].arbiter.y2"-
~("my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d")->"my_tree.at_cell.arbs[2].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[2].arbiter._y1","my_tree.at_cell.arbs[2].arbiter._y2")
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].arbiter.y1"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].or_cell.a"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].ack_cell1.c2"
~"my_tree.at_cell.arbs[2].ack_cell2.c1"&~"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"+
"my_tree.at_cell.arbs[2].ack_cell2.c1"&"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"-
"my_tree.at_cell.arbs[2].ack_cell2._y"->"my_tree.at_cell.arbs[2].ack_cell2.y"-
~("my_tree.at_cell.arbs[2].ack_cell2._y")->"my_tree.at_cell.arbs[2].ack_cell2.y"+
"my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b"->"my_tree.at_cell.arbs[2].or_cell._y"-
~("my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b")->"my_tree.at_cell.arbs[2].or_cell._y"+
"my_tree.at_cell.arbs[2].or_cell._y"->"my_tree.at_cell.arbs[2].or_cell.y"-
~("my_tree.at_cell.arbs[2].or_cell._y")->"my_tree.at_cell.arbs[2].or_cell.y"+
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell2.c1"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell1.c1"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].or_cell.y"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].arbiter.y2"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].or_cell.b"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].ack_cell2.c2"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].arbiter.d"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].ack_cell1.y"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.a"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
~"my_tree.at_cell.arbs[3].ack_cell1.c1"&~"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"+
"my_tree.at_cell.arbs[3].ack_cell1.c1"&"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"-
"my_tree.at_cell.arbs[3].ack_cell1._y"->"my_tree.at_cell.arbs[3].ack_cell1.y"-
~("my_tree.at_cell.arbs[3].ack_cell1._y")->"my_tree.at_cell.arbs[3].ack_cell1.y"+
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].arbiter.c"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].ack_cell2.y"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.b"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].arbiter.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].or_cell.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell2.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell1.vdd"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].arbiter.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].or_cell.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell2.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell1.vss"
"my_tree.at_cell.arbs[3].arbiter.a"&"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"-
~"my_tree.at_cell.arbs[3].arbiter.a"|~"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"+
"my_tree.at_cell.arbs[3].arbiter.b"&"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"-
~"my_tree.at_cell.arbs[3].arbiter.b"|~"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"+
"my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c"->"my_tree.at_cell.arbs[3].arbiter.y1"-
~("my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c")->"my_tree.at_cell.arbs[3].arbiter.y1"+
"my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d"->"my_tree.at_cell.arbs[3].arbiter.y2"-
~("my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d")->"my_tree.at_cell.arbs[3].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[3].arbiter._y1","my_tree.at_cell.arbs[3].arbiter._y2")
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].arbiter.y1"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].or_cell.a"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].ack_cell1.c2"
~"my_tree.at_cell.arbs[3].ack_cell2.c1"&~"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"+
"my_tree.at_cell.arbs[3].ack_cell2.c1"&"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"-
"my_tree.at_cell.arbs[3].ack_cell2._y"->"my_tree.at_cell.arbs[3].ack_cell2.y"-
~("my_tree.at_cell.arbs[3].ack_cell2._y")->"my_tree.at_cell.arbs[3].ack_cell2.y"+
"my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b"->"my_tree.at_cell.arbs[3].or_cell._y"-
~("my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b")->"my_tree.at_cell.arbs[3].or_cell._y"+
"my_tree.at_cell.arbs[3].or_cell._y"->"my_tree.at_cell.arbs[3].or_cell.y"-
~("my_tree.at_cell.arbs[3].or_cell._y")->"my_tree.at_cell.arbs[3].or_cell.y"+
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell2.c1"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell1.c1"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].or_cell.y"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].arbiter.y2"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].or_cell.b"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].ack_cell2.c2"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[2].in1.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[2].in1.d.d[0]"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[0].out.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[0].out.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[2].in2.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[2].in2.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[1].out.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[1].out.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[3].in1.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[3].in1.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[2].out.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[2].out.d.d[0]"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[3].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[3].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[2].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[2].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[1].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[1].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[0].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[0].supply.vdd"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.arbs[0].in1.a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.arbs[0].in1.d.d[0]"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.tmp[0].r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.tmp[0].a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.tmp[0].d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.arbs[0].in2.a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.arbs[0].in2.d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.tmp[1].r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.tmp[1].a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.tmp[1].d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.arbs[1].in1.a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.arbs[1].in1.d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.tmp[2].r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.tmp[2].a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.tmp[2].d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.arbs[1].in2.a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.arbs[1].in2.d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.tmp[3].r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.tmp[3].a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.tmp[3].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.arbs[3].in2.a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.arbs[3].in2.d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[9].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[9].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[9].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[7].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[7].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[7].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[4].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[4].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[4].d.d[0]"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree.at_cell.out.r" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.arbs[3].out.a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.arbs[3].out.d.d[0]"
= "my_tree.at_cell.out.r" "my_tree.at_cell.tmp[10].r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.tmp[10].a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.tmp[10].d.d[0]"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree._supply.vss" "my_tree.at_cell.supply.vss"
= "my_tree._supply.vdd" "my_tree.at_cell.supply.vdd"
= "Vdd" "my_tree._supply.vdd"
= "GND" "my_tree._supply.vss"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.out.r" "my_tree.at_cell.out.r"
= "my_tree.out.a" "my_tree.at_cell.out.a"
= "my_tree.out.d.d[0]" "my_tree.at_cell.out.d.d[0]"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[0].r" "my_tree.at_cell.in[0].r"
= "my_tree.in[1].r" "my_tree.at_cell.in[1].r"
= "my_tree.in[2].r" "my_tree.at_cell.in[2].r"
= "my_tree.in[3].r" "my_tree.at_cell.in[3].r"
= "my_tree.in[4].r" "my_tree.at_cell.in[4].r"
= "my_tree.in[0].a" "my_tree.at_cell.in[0].a"
= "my_tree.in[1].a" "my_tree.at_cell.in[1].a"
= "my_tree.in[2].a" "my_tree.at_cell.in[2].a"
= "my_tree.in[3].a" "my_tree.at_cell.in[3].a"
= "my_tree.in[4].a" "my_tree.at_cell.in[4].a"
= "my_tree.in[0].d.d[0]" "my_tree.at_cell.in[0].d.d[0]"
= "my_tree.in[1].d.d[0]" "my_tree.at_cell.in[1].d.d[0]"
= "my_tree.in[2].d.d[0]" "my_tree.at_cell.in[2].d.d[0]"
= "my_tree.in[3].d.d[0]" "my_tree.at_cell.in[3].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.at_cell.in[4].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"
test/unit_tests/arbiter_tree_simple_nosim/test.act
-55
View File
@@ -1,55 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
arbtree<5> at_cell(.in=in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;
test/unit_tests/arbiter_tree_simple_nosim/test.prsim
-52
View File
@@ -1,52 +0,0 @@
watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[4].a 1
set my_tree.in[4].r 0
system "echo '-------------------------------------------------'"
system "echo '[2] Number 4 was chosen, move to the next one'"
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.in[4].a 0
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[0].a 1
system "echo '-------------------------------------------------'"
system "echo '[2] Number 0 was chosen, finish test'"
test/unit_tests/arbiter_tree_test/run/prsim.out
-232
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@@ -1,232 +0,0 @@
my_tree.in[1].r my_tree.at_cell.tmp[8].a my_tree.in[3].r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[3].ack_cell1._y my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B my_tree._in[1].a my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B my_tree._in[3].a my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B my_tree._in[2].a my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1].ack_cell2._y my_tree._in[4].a my_tree.out.a my_tree._in[0].a my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.tmp[6].a my_tree.in[2].r my_tree.in[4].r my_tree.at_cell.arbs[2].ack_cell1._y my_tree.in[0].r my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B my_tree.at_cell.arbs[0].ack_cell1._y my_tree.at_cell.arbs[3].ack_cell2._y my_tree.at_cell.arbs[0].ack_cell2._y
217204 my_tree.in[0].r : 0
217204 my_tree.out.a : 0
217204 my_tree.in[4].r : 0
217204 my_tree.in[2].r : 0
217204 my_tree.in[1].r : 0
217204 my_tree.in[3].r : 0
217205 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
217216 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
217586 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
217752 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
217819 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
217835 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220460 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220988 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222397 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
223423 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
223425 my_tree._in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
235438 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
235441 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
235470 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
246322 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
246639 my_tree._in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
247868 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
248021 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
248065 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
248240 my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B : 1 [by my_tree._in[1].a:=0]
284383 my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B : 1 [by my_tree._in[3].a:=0]
-------------------------------------------------
[0] System initialized
284383 Reset : 0
287144 my_tree._reset_B : 1 [by Reset:=0]
287145 my_tree.fifo_to_tree[3].reset_buf._y : 0 [by my_tree._reset_B:=1]
287145 my_tree.fifo_to_tree[0].reset_buf._y : 0 [by my_tree._reset_B:=1]
287166 my_tree.fifo_to_tree[1].reset_buf._y : 0 [by my_tree._reset_B:=1]
287325 my_tree.fifo_to_tree[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].reset_buf._y:=0]
287361 my_tree.fifo_to_tree[2].reset_buf._y : 0 [by my_tree._reset_B:=1]
288648 my_tree.fifo_to_tree[2]._reset_BX : 1 [by my_tree.fifo_to_tree[2].reset_buf._y:=0]
288726 my_tree.fifo_to_tree[3]._reset_BX : 1 [by my_tree.fifo_to_tree[3].reset_buf._y:=0]
288871 my_tree.fifo_to_tree[3].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[3]._reset_BX:=1]
290880 my_tree.fifo_to_tree[2].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[2]._reset_BX:=1]
291703 my_tree.fifo_to_tree[3]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[3].reset_bufarray.buf1._y:=0]
291704 my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
291866 my_tree.fifo_to_tree[3].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y:=0]
296490 my_tree.fifo_to_tree[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].reset_buf._y:=0]
297234 my_tree.fifo_to_tree[2]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[2].reset_bufarray.buf1._y:=0]
297241 my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297248 my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297401 my_tree.fifo_to_tree[2].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y:=0]
300827 my_tree.fifo_to_tree[4].reset_buf._y : 0 [by my_tree._reset_B:=1]
300828 my_tree.fifo_to_tree[4]._reset_BX : 1 [by my_tree.fifo_to_tree[4].reset_buf._y:=0]
300829 my_tree.fifo_to_tree[4].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[4]._reset_BX:=1]
300830 my_tree.fifo_to_tree[4]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[4].reset_bufarray.buf1._y:=0]
301017 my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
301018 my_tree.fifo_to_tree[4].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y:=0]
303073 my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
303859 my_tree.fifo_to_tree[0].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[0]._reset_BX:=1]
307001 my_tree.fifo_to_tree[1].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[1]._reset_BX:=1]
307002 my_tree.fifo_to_tree[1]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[1].reset_bufarray.buf1._y:=0]
307007 my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307255 my_tree.fifo_to_tree[4].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y:=0]
307855 my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307856 my_tree.fifo_to_tree[1].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y:=0]
307898 my_tree.fifo_to_tree[1].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y:=0]
318805 my_tree.fifo_to_tree[2].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y:=0]
330987 my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
331004 my_tree.fifo_to_tree[3].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y:=0]
338641 my_tree.fifo_to_tree[0]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[0].reset_bufarray.buf1._y:=0]
341214 my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
341217 my_tree.fifo_to_tree[0].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y:=0]
347002 my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
347943 my_tree.fifo_to_tree[0].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y:=0]
-------------------------------------------------
[1] System reset completed
347943 my_tree.in[0].r : 1
347943 my_tree.in[4].r : 1
347943 my_tree.in[2].r : 1
347944 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 0 [by my_tree.in[4].r:=1]
347985 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 0 [by my_tree.in[2].r:=1]
350761 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=0]
350856 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
350864 my_tree._in[4].r : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=0]
350898 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree._in[4].r:=1]
351096 my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
351100 my_tree.in[4].a : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y:=0]
351816 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
354214 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
357429 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
361718 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=0]
361766 my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
361769 my_tree.in[2].a : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y:=0]
361947 my_tree.fifo_to_tree[2].fifo_element[0]._en : 0 [by my_tree.in[2].a:=1]
364751 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[4].r:=1]
385728 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=0]
391679 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
397478 my_tree.fifo_to_tree[4].fifo_element[0]._en : 0 [by my_tree.in[4].a:=1]
397627 my_tree.fifo_to_tree[4].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
406905 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 0 [by my_tree.in[0].r:=1]
407732 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=0]
407905 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407906 my_tree._in[0].r : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=0]
407910 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[0].r:=1]
407916 my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407979 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree._in[0].r:=1]
408012 my_tree.in[0].a : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y:=0]
408013 my_tree.fifo_to_tree[0].fifo_element[0]._en : 0 [by my_tree.in[0].a:=1]
408115 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
408837 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
409078 my_tree._in[2].r : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=0]
409090 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[2].r:=1]
412990 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=0]
412991 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
413037 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree._in[2].r:=1]
413047 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B:=0]
413048 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=1]
414019 my_tree.fifo_to_tree[2].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
414056 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._en:=0]
427161 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
427162 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
430726 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
432418 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
432431 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
436963 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[0]._en:=0]
437320 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=1]
437345 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=0]
437366 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=1]
437367 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=0]
437431 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=1]
445198 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=0]
445199 my_tree.fifo_to_tree[0].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445199 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445360 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B:=0]
446397 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=1]
446402 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=0]
446983 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=1]
447079 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=0]
447391 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=0]
449415 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
458043 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
458054 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
459101 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
459101 my_tree.out.a : 1
459115 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
459133 my_tree._in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
459137 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 0 [by my_tree._in[4].a:=1]
459241 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B:=0]
490685 my_tree._in[4].r : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=1]
491889 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree._in[4].r:=0]
492117 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
492732 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
494191 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
494261 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
499140 my_tree.fifo_to_tree[4].fifo_element[1]._en : 1 [by my_tree._in[4].r:=0]
499140 my_tree.out.a : 0
549562 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
549573 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
549576 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree._in[4].a:=0]
549627 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
550724 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
551885 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
551885 my_tree.out.a : 1
560537 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
560618 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
571695 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
589678 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
589770 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
598081 my_tree._in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
599825 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 0 [by my_tree._in[0].a:=1]
600438 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B:=0]
614460 my_tree._in[0].r : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=1]
614505 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree._in[0].r:=0]
615457 my_tree.fifo_to_tree[0].fifo_element[1]._en : 1 [by my_tree._in[0].r:=0]
616154 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
616679 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
617579 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
617631 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
617638 my_tree.at_cell.arbs[2].arbiter._y2 : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
633243 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
639710 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y1_arb:=0]
639712 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
640066 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
640199 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
640200 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
640204 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
640204 my_tree.out.a : 0
640750 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
686313 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
686314 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
698692 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
698771 my_tree.at_cell.arbs[2]._y2_arb : 1 [by my_tree.at_cell.tmp[5].a:=0]
698859 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y2_arb:=1]
701125 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
706641 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
706700 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.tmp[8].r:=1]
706730 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y1:=0]
708197 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
729452 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
748836 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
767701 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
767701 my_tree.out.a : 1
768386 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
785101 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
785228 my_tree.at_cell.arbs[2].ack_cell2._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
785397 my_tree.at_cell.tmp[6].a : 1 [by my_tree.at_cell.arbs[2].ack_cell2._y:=0]
785440 my_tree.at_cell.arbs[1].ack_cell1._y : 0 [by my_tree.at_cell.tmp[6].a:=1]
785452 my_tree._in[2].a : 1 [by my_tree.at_cell.arbs[1].ack_cell1._y:=0]
786731 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 0 [by my_tree._in[2].a:=1]
786964 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B:=0]
786967 my_tree._in[2].r : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=1]
786968 my_tree.fifo_to_tree[2].fifo_element[1]._en : 1 [by my_tree._in[2].r:=0]
787005 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree._in[2].r:=0]
799757 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
799849 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
802576 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
802578 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
802579 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
804080 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
804082 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
804100 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
804219 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
809939 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
809947 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
809947 my_tree.out.a : 0
810001 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
860539 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
860544 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
861611 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
861612 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
861750 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
861751 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
-------------------------------------------------
[3] Sent three inputs, received 3 outputs
test/unit_tests/arbiter_tree_test/run/test.prs
-1085
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test/unit_tests/arbiter_tree_test/test.act
-64
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@@ -1,64 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
a1of1 _in[5];
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
fifo_t<2> fifo_to_tree[5];
(i:5:
fifo_to_tree[i].in = in[i];
fifo_to_tree[i].out = _in[i];
fifo_to_tree[i].supply = _supply;
fifo_to_tree[i].reset_B = _reset_B;
)
arbtree<5> at_cell(.in=_in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;
test/unit_tests/arbiter_tree_test/test.prsim
-63
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@@ -1,63 +0,0 @@
watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[3] Sent three inputs, received 3 outputs'"
test/unit_tests/arbtree_5/.DS_Store
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test/unit_tests/arbtree_5/run/prsim.out
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t.at.arbs[2]._y1_arb t.in[2].r t.at.arbs[0].ack_cell1._y t.at.arbs[0]._y1_arb t.at.tmp[6].a t.at.arbs[1]._y1_arb t.at.arbs[3]._y1_arb t.in[1].a t.out.r t.in[4].r t.at.tmp[8].a t.at.tmp[5].r t.in[1].r t.in[3].r t.in[0].r t.at.tmp[6].r t.at.arbs[0].ack_cell2._y t.in[3].a t.at.tmp[8].r t.at.tmp[5].a t.at.arbs[2]._y2_arb t.in[0].a t.at.arbs[2].arbiter._y1 t.at.arbs[3]._y2_arb t.in[2].a t.out.a t.at.arbs[1].arbiter._y2 t.at.arbs[0].arbiter._y1 t.in[4].a t.at.arbs[2].arbiter._y2 t.at.arbs[0]._y2_arb t.at.arbs[3].ack_cell2._y t.at.arbs[2].ack_cell2._y t.at.arbs[1]._y2_arb t.at.arbs[1].or_cell._y t.at.arbs[1].arbiter._y1 t.at.arbs[3].arbiter._y1 t.at.arbs[3].ack_cell1._y t.at.arbs[0].or_cell._y t.at.arbs[1].ack_cell2._y t.at.arbs[2].ack_cell1._y t.at.arbs[3].arbiter._y2 t.at.arbs[0].arbiter._y2 t.at.arbs[2].or_cell._y t.at.arbs[1].ack_cell1._y t.at.arbs[3].or_cell._y
0
test/unit_tests/arbtree_5/run/test.prs
-321
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@@ -1,321 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
= "t.at.arbs[0].in1.a" "t.at.arbs[0].arbiter.d"
= "t.at.arbs[0].in1.a" "t.at.arbs[0].ack_cell1.y"
= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].arbiter.a"
= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
~"t.at.arbs[0].ack_cell1.c1"&~"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"+
"t.at.arbs[0].ack_cell1.c1"&"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"-
"t.at.arbs[0].ack_cell1._y"->"t.at.arbs[0].ack_cell1.y"-
~("t.at.arbs[0].ack_cell1._y")->"t.at.arbs[0].ack_cell1.y"+
= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
= "t.at.arbs[0].in2.a" "t.at.arbs[0].arbiter.c"
= "t.at.arbs[0].in2.a" "t.at.arbs[0].ack_cell2.y"
= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].arbiter.b"
= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].arbiter.vdd"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].or_cell.vdd"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell2.vdd"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell1.vdd"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].arbiter.vss"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].or_cell.vss"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell2.vss"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell1.vss"
"t.at.arbs[0].arbiter.a"&"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"-
~"t.at.arbs[0].arbiter.a"|~"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"+
"t.at.arbs[0].arbiter.b"&"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"-
~"t.at.arbs[0].arbiter.b"|~"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"+
"t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c"->"t.at.arbs[0].arbiter.y1"-
~("t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c")->"t.at.arbs[0].arbiter.y1"+
"t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d"->"t.at.arbs[0].arbiter.y2"-
~("t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d")->"t.at.arbs[0].arbiter.y2"+
mk_excllo("t.at.arbs[0].arbiter._y1","t.at.arbs[0].arbiter._y2")
= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].arbiter.y1"
= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].or_cell.a"
= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].ack_cell1.c2"
~"t.at.arbs[0].ack_cell2.c1"&~"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"+
"t.at.arbs[0].ack_cell2.c1"&"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"-
"t.at.arbs[0].ack_cell2._y"->"t.at.arbs[0].ack_cell2.y"-
~("t.at.arbs[0].ack_cell2._y")->"t.at.arbs[0].ack_cell2.y"+
"t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b"->"t.at.arbs[0].or_cell._y"-
~("t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b")->"t.at.arbs[0].or_cell._y"+
"t.at.arbs[0].or_cell._y"->"t.at.arbs[0].or_cell.y"-
~("t.at.arbs[0].or_cell._y")->"t.at.arbs[0].or_cell.y"+
= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell2.c1"
= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell1.c1"
= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].or_cell.y"
= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].arbiter.y2"
= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].or_cell.b"
= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].ack_cell2.c2"
= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
= "t.at.arbs[1].in1.a" "t.at.arbs[1].arbiter.d"
= "t.at.arbs[1].in1.a" "t.at.arbs[1].ack_cell1.y"
= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].arbiter.a"
= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
~"t.at.arbs[1].ack_cell1.c1"&~"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"+
"t.at.arbs[1].ack_cell1.c1"&"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"-
"t.at.arbs[1].ack_cell1._y"->"t.at.arbs[1].ack_cell1.y"-
~("t.at.arbs[1].ack_cell1._y")->"t.at.arbs[1].ack_cell1.y"+
= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
= "t.at.arbs[1].in2.a" "t.at.arbs[1].arbiter.c"
= "t.at.arbs[1].in2.a" "t.at.arbs[1].ack_cell2.y"
= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].arbiter.b"
= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].arbiter.vdd"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].or_cell.vdd"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell2.vdd"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell1.vdd"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].arbiter.vss"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].or_cell.vss"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell2.vss"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell1.vss"
"t.at.arbs[1].arbiter.a"&"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"-
~"t.at.arbs[1].arbiter.a"|~"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"+
"t.at.arbs[1].arbiter.b"&"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"-
~"t.at.arbs[1].arbiter.b"|~"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"+
"t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c"->"t.at.arbs[1].arbiter.y1"-
~("t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c")->"t.at.arbs[1].arbiter.y1"+
"t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d"->"t.at.arbs[1].arbiter.y2"-
~("t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d")->"t.at.arbs[1].arbiter.y2"+
mk_excllo("t.at.arbs[1].arbiter._y1","t.at.arbs[1].arbiter._y2")
= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].arbiter.y1"
= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].or_cell.a"
= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].ack_cell1.c2"
~"t.at.arbs[1].ack_cell2.c1"&~"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"+
"t.at.arbs[1].ack_cell2.c1"&"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"-
"t.at.arbs[1].ack_cell2._y"->"t.at.arbs[1].ack_cell2.y"-
~("t.at.arbs[1].ack_cell2._y")->"t.at.arbs[1].ack_cell2.y"+
"t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b"->"t.at.arbs[1].or_cell._y"-
~("t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b")->"t.at.arbs[1].or_cell._y"+
"t.at.arbs[1].or_cell._y"->"t.at.arbs[1].or_cell.y"-
~("t.at.arbs[1].or_cell._y")->"t.at.arbs[1].or_cell.y"+
= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell2.c1"
= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell1.c1"
= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].or_cell.y"
= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].arbiter.y2"
= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].or_cell.b"
= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].ack_cell2.c2"
= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
= "t.at.arbs[2].in1.a" "t.at.arbs[2].arbiter.d"
= "t.at.arbs[2].in1.a" "t.at.arbs[2].ack_cell1.y"
= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].arbiter.a"
= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
~"t.at.arbs[2].ack_cell1.c1"&~"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"+
"t.at.arbs[2].ack_cell1.c1"&"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"-
"t.at.arbs[2].ack_cell1._y"->"t.at.arbs[2].ack_cell1.y"-
~("t.at.arbs[2].ack_cell1._y")->"t.at.arbs[2].ack_cell1.y"+
= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
= "t.at.arbs[2].in2.a" "t.at.arbs[2].arbiter.c"
= "t.at.arbs[2].in2.a" "t.at.arbs[2].ack_cell2.y"
= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].arbiter.b"
= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].arbiter.vdd"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].or_cell.vdd"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell2.vdd"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell1.vdd"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].arbiter.vss"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].or_cell.vss"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell2.vss"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell1.vss"
"t.at.arbs[2].arbiter.a"&"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"-
~"t.at.arbs[2].arbiter.a"|~"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"+
"t.at.arbs[2].arbiter.b"&"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"-
~"t.at.arbs[2].arbiter.b"|~"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"+
"t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c"->"t.at.arbs[2].arbiter.y1"-
~("t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c")->"t.at.arbs[2].arbiter.y1"+
"t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d"->"t.at.arbs[2].arbiter.y2"-
~("t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d")->"t.at.arbs[2].arbiter.y2"+
mk_excllo("t.at.arbs[2].arbiter._y1","t.at.arbs[2].arbiter._y2")
= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].arbiter.y1"
= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].or_cell.a"
= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].ack_cell1.c2"
~"t.at.arbs[2].ack_cell2.c1"&~"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"+
"t.at.arbs[2].ack_cell2.c1"&"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"-
"t.at.arbs[2].ack_cell2._y"->"t.at.arbs[2].ack_cell2.y"-
~("t.at.arbs[2].ack_cell2._y")->"t.at.arbs[2].ack_cell2.y"+
"t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b"->"t.at.arbs[2].or_cell._y"-
~("t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b")->"t.at.arbs[2].or_cell._y"+
"t.at.arbs[2].or_cell._y"->"t.at.arbs[2].or_cell.y"-
~("t.at.arbs[2].or_cell._y")->"t.at.arbs[2].or_cell.y"+
= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell2.c1"
= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell1.c1"
= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].or_cell.y"
= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].arbiter.y2"
= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].or_cell.b"
= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].ack_cell2.c2"
= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
= "t.at.arbs[3].in1.a" "t.at.arbs[3].arbiter.d"
= "t.at.arbs[3].in1.a" "t.at.arbs[3].ack_cell1.y"
= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].arbiter.a"
= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
~"t.at.arbs[3].ack_cell1.c1"&~"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"+
"t.at.arbs[3].ack_cell1.c1"&"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"-
"t.at.arbs[3].ack_cell1._y"->"t.at.arbs[3].ack_cell1.y"-
~("t.at.arbs[3].ack_cell1._y")->"t.at.arbs[3].ack_cell1.y"+
= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
= "t.at.arbs[3].in2.a" "t.at.arbs[3].arbiter.c"
= "t.at.arbs[3].in2.a" "t.at.arbs[3].ack_cell2.y"
= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].arbiter.b"
= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].arbiter.vdd"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].or_cell.vdd"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell2.vdd"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell1.vdd"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].arbiter.vss"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].or_cell.vss"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell2.vss"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell1.vss"
"t.at.arbs[3].arbiter.a"&"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"-
~"t.at.arbs[3].arbiter.a"|~"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"+
"t.at.arbs[3].arbiter.b"&"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"-
~"t.at.arbs[3].arbiter.b"|~"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"+
"t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c"->"t.at.arbs[3].arbiter.y1"-
~("t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c")->"t.at.arbs[3].arbiter.y1"+
"t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d"->"t.at.arbs[3].arbiter.y2"-
~("t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d")->"t.at.arbs[3].arbiter.y2"+
mk_excllo("t.at.arbs[3].arbiter._y1","t.at.arbs[3].arbiter._y2")
= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].arbiter.y1"
= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].or_cell.a"
= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].ack_cell1.c2"
~"t.at.arbs[3].ack_cell2.c1"&~"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"+
"t.at.arbs[3].ack_cell2.c1"&"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"-
"t.at.arbs[3].ack_cell2._y"->"t.at.arbs[3].ack_cell2.y"-
~("t.at.arbs[3].ack_cell2._y")->"t.at.arbs[3].ack_cell2.y"+
"t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b"->"t.at.arbs[3].or_cell._y"-
~("t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b")->"t.at.arbs[3].or_cell._y"+
"t.at.arbs[3].or_cell._y"->"t.at.arbs[3].or_cell.y"-
~("t.at.arbs[3].or_cell._y")->"t.at.arbs[3].or_cell.y"+
= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell2.c1"
= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell1.c1"
= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].or_cell.y"
= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].arbiter.y2"
= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].or_cell.b"
= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].ack_cell2.c2"
= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
= "t.at.tmp[5].r" "t.at.arbs[2].in1.r"
= "t.at.tmp[5].a" "t.at.arbs[2].in1.a"
= "t.at.tmp[5].d.d[0]" "t.at.arbs[2].in1.d.d[0]"
= "t.at.tmp[5].r" "t.at.arbs[0].out.r"
= "t.at.tmp[5].a" "t.at.arbs[0].out.a"
= "t.at.tmp[5].d.d[0]" "t.at.arbs[0].out.d.d[0]"
= "t.at.tmp[6].r" "t.at.arbs[2].in2.r"
= "t.at.tmp[6].a" "t.at.arbs[2].in2.a"
= "t.at.tmp[6].d.d[0]" "t.at.arbs[2].in2.d.d[0]"
= "t.at.tmp[6].r" "t.at.arbs[1].out.r"
= "t.at.tmp[6].a" "t.at.arbs[1].out.a"
= "t.at.tmp[6].d.d[0]" "t.at.arbs[1].out.d.d[0]"
= "t.at.tmp[8].r" "t.at.arbs[3].in1.r"
= "t.at.tmp[8].a" "t.at.arbs[3].in1.a"
= "t.at.tmp[8].d.d[0]" "t.at.arbs[3].in1.d.d[0]"
= "t.at.tmp[8].r" "t.at.arbs[2].out.r"
= "t.at.tmp[8].a" "t.at.arbs[2].out.a"
= "t.at.tmp[8].d.d[0]" "t.at.arbs[2].out.d.d[0]"
= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
= "t.at.supply.vss" "t.at.arbs[3].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[3].supply.vdd"
= "t.at.supply.vss" "t.at.arbs[2].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[2].supply.vdd"
= "t.at.supply.vss" "t.at.arbs[1].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[1].supply.vdd"
= "t.at.supply.vss" "t.at.arbs[0].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[0].supply.vdd"
= "t.at.in[0].d.d[0]" "t.at.in[0].r"
= "t.at.in[1].d.d[0]" "t.at.in[1].r"
= "t.at.in[2].d.d[0]" "t.at.in[2].r"
= "t.at.in[3].d.d[0]" "t.at.in[3].r"
= "t.at.in[4].d.d[0]" "t.at.in[4].r"
= "t.at.in[0].r" "t.at.arbs[0].in1.r"
= "t.at.in[0].a" "t.at.arbs[0].in1.a"
= "t.at.in[0].d.d[0]" "t.at.arbs[0].in1.d.d[0]"
= "t.at.in[0].r" "t.at.tmp[0].r"
= "t.at.in[0].a" "t.at.tmp[0].a"
= "t.at.in[0].d.d[0]" "t.at.tmp[0].d.d[0]"
= "t.at.in[1].r" "t.at.arbs[0].in2.r"
= "t.at.in[1].a" "t.at.arbs[0].in2.a"
= "t.at.in[1].d.d[0]" "t.at.arbs[0].in2.d.d[0]"
= "t.at.in[1].r" "t.at.tmp[1].r"
= "t.at.in[1].a" "t.at.tmp[1].a"
= "t.at.in[1].d.d[0]" "t.at.tmp[1].d.d[0]"
= "t.at.in[2].r" "t.at.arbs[1].in1.r"
= "t.at.in[2].a" "t.at.arbs[1].in1.a"
= "t.at.in[2].d.d[0]" "t.at.arbs[1].in1.d.d[0]"
= "t.at.in[2].r" "t.at.tmp[2].r"
= "t.at.in[2].a" "t.at.tmp[2].a"
= "t.at.in[2].d.d[0]" "t.at.tmp[2].d.d[0]"
= "t.at.in[3].r" "t.at.arbs[1].in2.r"
= "t.at.in[3].a" "t.at.arbs[1].in2.a"
= "t.at.in[3].d.d[0]" "t.at.arbs[1].in2.d.d[0]"
= "t.at.in[3].r" "t.at.tmp[3].r"
= "t.at.in[3].a" "t.at.tmp[3].a"
= "t.at.in[3].d.d[0]" "t.at.tmp[3].d.d[0]"
= "t.at.in[4].r" "t.at.arbs[3].in2.r"
= "t.at.in[4].a" "t.at.arbs[3].in2.a"
= "t.at.in[4].d.d[0]" "t.at.arbs[3].in2.d.d[0]"
= "t.at.in[4].r" "t.at.tmp[9].r"
= "t.at.in[4].a" "t.at.tmp[9].a"
= "t.at.in[4].d.d[0]" "t.at.tmp[9].d.d[0]"
= "t.at.in[4].r" "t.at.tmp[7].r"
= "t.at.in[4].a" "t.at.tmp[7].a"
= "t.at.in[4].d.d[0]" "t.at.tmp[7].d.d[0]"
= "t.at.in[4].r" "t.at.tmp[4].r"
= "t.at.in[4].a" "t.at.tmp[4].a"
= "t.at.in[4].d.d[0]" "t.at.tmp[4].d.d[0]"
= "t.at.in[4].d.d[0]" "t.at.in[4].r"
= "t.at.in[3].d.d[0]" "t.at.in[3].r"
= "t.at.in[2].d.d[0]" "t.at.in[2].r"
= "t.at.in[1].d.d[0]" "t.at.in[1].r"
= "t.at.in[0].d.d[0]" "t.at.in[0].r"
= "t.at.out.d.d[0]" "t.at.out.r"
= "t.at.out.r" "t.at.arbs[3].out.r"
= "t.at.out.a" "t.at.arbs[3].out.a"
= "t.at.out.d.d[0]" "t.at.arbs[3].out.d.d[0]"
= "t.at.out.r" "t.at.tmp[10].r"
= "t.at.out.a" "t.at.tmp[10].a"
= "t.at.out.d.d[0]" "t.at.tmp[10].d.d[0]"
= "t.at.out.d.d[0]" "t.at.out.r"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out.d.d[0]" "t.out.r"
= "t.out.r" "t.at.out.r"
= "t.out.a" "t.at.out.a"
= "t.out.d.d[0]" "t.at.out.d.d[0]"
= "t.out.d.d[0]" "t.out.r"
= "t.in[0].d.d[0]" "t.in[0].r"
= "t.in[1].d.d[0]" "t.in[1].r"
= "t.in[2].d.d[0]" "t.in[2].r"
= "t.in[3].d.d[0]" "t.in[3].r"
= "t.in[4].d.d[0]" "t.in[4].r"
= "t.in[0].r" "t.at.in[0].r"
= "t.in[1].r" "t.at.in[1].r"
= "t.in[2].r" "t.at.in[2].r"
= "t.in[3].r" "t.at.in[3].r"
= "t.in[4].r" "t.at.in[4].r"
= "t.in[0].a" "t.at.in[0].a"
= "t.in[1].a" "t.at.in[1].a"
= "t.in[2].a" "t.at.in[2].a"
= "t.in[3].a" "t.at.in[3].a"
= "t.in[4].a" "t.at.in[4].a"
= "t.in[0].d.d[0]" "t.at.in[0].d.d[0]"
= "t.in[1].d.d[0]" "t.at.in[1].d.d[0]"
= "t.in[2].d.d[0]" "t.at.in[2].d.d[0]"
= "t.in[3].d.d[0]" "t.at.in[3].d.d[0]"
= "t.in[4].d.d[0]" "t.at.in[4].d.d[0]"
= "t.in[4].d.d[0]" "t.in[4].r"
= "t.in[3].d.d[0]" "t.in[3].r"
= "t.in[2].d.d[0]" "t.in[2].r"
= "t.in[1].d.d[0]" "t.in[1].r"
= "t.in[0].d.d[0]" "t.in[0].r"
test/unit_tests/arbtree_5/test.act
-53
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@@ -1,53 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbtree (a1of1 in[5]; a1of1 out)
{
a1of1 _in[5];
power _supply
_supply.vdd = Vdd;
_supply.vss = GND;
fifo_t<2> fifo_to_tree[5];
(i:5:
fifo_to_tree[i].in = in[i];
fifo_to_tree[i].out = _in[i];
fifo_to_tree.supply = _supply;
fifo_to_tree.reset_B = _reset_B;
)
arbtree<5> at(.in=_in, .out = out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
at.supply = _supply;
}
arbtree t;
test/unit_tests/arbtree_5/test.prsim
-127
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@@ -1,127 +0,0 @@
watchall
system "echo '[] setting channels neutral'"
set t.in[0].r 0
set t.in[1].r 0
set t.in[2].r 0
set t.in[3].r 0
set t.in[4].r 0
set t.out.a 0
cycle
mode run
assert t.out.r 0
assert t.in[0].a 0
assert t.in[1].a 0
assert t.in[2].a 0
assert t.in[3].a 0
assert t.in[4].a 0
system "echo '[] setting some reqs high'"
set t.in[0].r 1
set t.in[1].r 1
set t.in[2].r 1
cycle
assert t.out.r 1
system "echo '[] receiving ack'"
set t.out.a 1
cycle
assert t.in.a 1
system "echo '[] removing first req (guess)'"
set t.in[0].r 0
cycle
assert t.out.r
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# system "echo '1'"
# cycle
# mode run
# # assert t.out 0
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 0 high'"
# set t.in[0] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 1 high'"
# set t.in[0] 0
# set t.in[1] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 2 high'"
# set t.in[1] 0
# set t.in[2] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 3 high'"
# set t.in[2] 0
# set t.in[3] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 4 high'"
# set t.in[3] 0
# set t.in[4] 1
# cycle
test/unit_tests/bd-fifo-register-fifo-bd/run/prsim.out
-8674
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test/unit_tests/bd-fifo-register-fifo-bd/run/prsim.pdf
BIN
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test/unit_tests/bd-fifo-register-fifo-bd/run/test.prs
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test/unit_tests/bd-fifo-register-fifo-bd/test.act
-64
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@@ -1,64 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/interfaces.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
bd2qdi<9,4> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);
// Make a register array with 3 bit address (-> 8 registers),
// each register holding 5 bits.
registerA_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
.reset_B = _reset_B, .supply = supply);
fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);
qdi2bd<8,4> _qdi2bd(.in = fifo_post.out, .out = out, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_reg_fifo_3x5x8 b;
test/unit_tests/bd-fifo-register-fifo-bd/test.prsim
-202
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@@ -1,202 +0,0 @@
watchall
set-bd-channel-neutral "b.in" 9
# set b.in.r 0
set b.out.a 0
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
assert b.in.a 0
assert-bd-channel-neutral "b.out" 8
system "echo '[] Sending packet write 0s to reg0'"
set-bd-channel-valid "b.in" 9 256
cycle
assert b.in.a 1
# assert b.in.v 1
assert-var-int "b.data[0]" 5 0
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
# assert b.in.v 0
assert-var-int "b.data[0]" 5 0
# system "echo '[] Sending packet write 0s to reg0'"
# set-qdi-channel-valid "b.in" 9 256
# cycle
# assert b.in.a 1
# assert b.in.v 1
# assert-var-int "b.data[0]" 5 0
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# assert-var-int "b.data[0]" 5 0
system "echo '[] Sending packet write 01100=12 to reg0'"
set-bd-channel-valid "b.in" 9 352
cycle
assert b.in.a 1
# assert b.in.v 1
assert-var-int "b.data[0]" 5 12
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
# assert b.in.v 0
assert-var-int "b.data[0]" 5 12
# system "echo '[] Sending packet write 0s to reg1'"
# set-qdi-channel-valid "b.in" 9 257
# cycle
# assert b.in.a 1
# assert b.in.v 1
# assert-var-int "b.data[1]" 5 0
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg2'"
# set-qdi-channel-valid "b.in" 9 258
# cycle
# assert b.in.a 1
# assert b.in.v 1
# assert-var-int "b.data[2]" 5 0
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# assert-var-int "b.data[2]" 5 0
# system "echo '[] Sending packet write 0s to reg3'"
# set-qdi-channel-valid "b.in" 9 259
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg4'"
# set-qdi-channel-valid "b.in" 9 260
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg5'"
# set-qdi-channel-valid "b.in" 9 261
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg6'"
# set-qdi-channel-valid "b.in" 9 262
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg7'"
# set-qdi-channel-valid "b.in" 9 263
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# assert-var-int "b.data[2]" 5 0
# assert-var-int "b.data[3]" 5 0
# assert-var-int "b.data[4]" 5 0
# assert-var-int "b.data[5]" 5 0
# assert-var-int "b.data[6]" 5 0
# assert-var-int "b.data[7]" 5 0
system "echo '[] Reading register 0'"
set-bd-channel-valid "b.in" 9 0
cycle
assert-bd-channel-valid "b.out" 8 96
assert b.out.r 1
# assert b.in.v 1
assert b.in.a 1
set b.out.a 1
cycle
assert-bd-channel-neutral "b.out" 8
assert b.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
set b.out.a 0
cycle
# system "echo '[] Reading register 1'"
# set-qdi-channel-valid "b.in" 9 1
# cycle
# assert-qdi-channel-valid "b.out" 8 1
# assert b.in.v 1
# assert b.in.a 1
# set b.out.a 1
# set b.out.v 1
# cycle
# assert b.in.a 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert-qdi-channel-neutral "b.out" 8
# set b.out.a 0
# set b.out.v 0
# cycle
# assert b.in.a 0
# assert b.in.v 0
test/unit_tests/bd2qdi_5/run/prsim.out
-615
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@@ -1,615 +0,0 @@
b.b._out_a_BX_f[0] b.b.dly.dly[5].__y b.b.dly.mu2[0]._s b.b._inB[1] b.b.dly.dly[9].__y b.in.r b.b._inB[4] b.b.dly.dly[6].y b.in.d[1] b.b.dly.dly[3].a b.in.d[4] b.b.dly.dly[11].__y b.b._reqX b.b._en_X_f[0] b.b.dly.dly[13].y b.b.dly.dly[4]._y b.dly_cfg[3] b.in.d[2] b.b.dly.dly[11].y b.b.dly.dly[0].a b.b._en_X_t[0] b.b.dly.mu2[3].b b.dly_cfg[2] b.b._out_a_BX_t[0] b.b._reqXX[0] b.out.v b.b.dly.dly[7].___y b.b._out_a_B b.b._inB[2] b.b._inB[0] b.b.dly._a[1] b.dly_cfg[1] b.b.dly.dly[8].__y b.b.dly.dly[4].___y b.in.d[0] b.b.dly.dly[8]._y b.b.dly.dly[0].__y b.dly_cfg[0] b.b.dly.dly[7].a b.b.req_buf._y b.b.dly.dly[8].y b.b.en_buf_f.buf2._y b.b.dly.dly[10].y b.b.dly.dly[3].___y b.b.dly.mu2[1]._y b.b.dly.dly[5].y b.b.dly._a[2] b.b.dly.dly[6]._y b.b.dly.mu2[3]._s b.b.dly.dly[7].y b.b.en_buf_t.buf2._y b.b._en b.b.dly._a[3] b.b.dly.dly[1].___y b.out.a b.in.d[3] b.b.dly.dly[2]._y b.b.dly.dly[7].__y b.b._req b.b.dly.dly[12].___y b.b.dly.dly[12].y b.b.dly.dly[8].___y b.b.dly.dly[1].a b.b.dly.dly[9].___y b.b.dly.dly[3].y b.b.dly.dly[2].y b.b.dly.dly[14].___y b.b._inB[3] b.b.dly.mu2[0]._y b.b.dly.dly[6].___y b.b.dly.and2[0]._y b.b.dly.dly[3]._y b.b.dly.dly[10].__y b.b.out_a_B_buf_t.buf2._y b.b.dly.mu2[3]._y b.b.req_bufarray.buf2._y b.b.dly.dly[5]._y b.b.dly.mu2[1]._s b.b.dly.dly[4].y b.b.dly.dly[1]._y b.b.dly.and2[3]._y b.b.dly.dly[13].___y b.b.dly.dly[0]._y b.b.dly.dly[11]._y b.b.dly.dly[14].__y b.b.dly.dly[1].__y b.b.dly.mu2[2]._y b.b.dly.and2[1]._y b.b.out_a_B_buf_f.buf2._y b.b.dly.dly[9].y b.b.dly.dly[0].___y b.b.dly.dly[7]._y b.b.dly.dly[13]._y b.b.dly.dly[4].__y b.b.dly.and2[2]._y b.b.dly.dly[12].__y b.b.dly.dly[11].___y b.b.dly.dly[1].y b.b.dly.dly[12]._y b.b.dly.dly[2].__y b.b.dly.dly[14]._y b.b.dly.dly[5].___y b.b.dly.dly[2].___y b.b.dly.dly[0].y b.b.dly.dly[3].__y b.b.dly.mu2[2]._s b.b.dly.dly[13].__y b.b.dly.dly[10].___y b.b.dly.dly[9]._y b.b.dly.dly[6].__y b.b.dly.dly[10]._y
87848 b.out.a : 0
87848 Reset : 0
87848 b.in.r : 0
87848 b.dly_cfg[3] : 1
87848 b.dly_cfg[2] : 1
87848 b.in.d[4] : 0
87848 b.out.v : 0
87848 b.dly_cfg[1] : 1
87848 b.in.d[3] : 1
87848 b.in.d[2] : 0
87848 b.dly_cfg[0] : 1
87848 b.in.d[1] : 0
87848 b.in.d[0] : 1
87849 b.b.dly.mu2[1]._s : 0 [by b.dly_cfg[1]:=1]
87849 b.b._inB[3] : 0 [by b.in.d[3]:=1]
87851 b.b._inB[0] : 0 [by b.in.d[0]:=1]
88130 b.b.dly.mu2[0]._s : 0 [by b.dly_cfg[0]:=1]
88270 b.b._inB[4] : 1 [by b.in.d[4]:=0]
88616 b.b._inB[1] : 1 [by b.in.d[1]:=0]
101697 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
102191 b.b.dly.mu2[2]._s : 0 [by b.dly_cfg[2]:=1]
108053 b.b._inB[2] : 1 [by b.in.d[2]:=0]
112660 b.b.dly.mu2[3]._s : 0 [by b.dly_cfg[3]:=1]
117628 b._reset_B : 1 [by Reset:=0]
118179 b.b.reset_buf._y : 0 [by b._reset_B:=1]
119250 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
120204 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
121285 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
121303 b.b.f_buf_func[4]._y : X [by b.b._reset_BXX[0]:=1]
122267 b.b.f_buf_func[2]._y : X [by b.b._reset_BXX[0]:=1]
124138 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
125288 b.b.t_buf_func[3]._y : X [by b.b._reset_BXX[0]:=1]
125298 b.b.t_buf_func[0]._y : X [by b.b._reset_BXX[0]:=1]
125501 b.b.t_buf_func[0].y : X [by b.b.t_buf_func[0]._y:=X]
125790 b.b.t_buf_func[3].y : X [by b.b.t_buf_func[3]._y:=X]
128898 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
130752 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
130891 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
136562 b.b._en : 1 [by b.out.v:=0]
136573 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
136631 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
136835 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
139501 b.b._out_a_B : 1 [by b.out.a:=0]
139502 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
139516 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
139539 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
140255 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
143851 b.b.f_buf_func[2].y : X [by b.b.f_buf_func[2]._y:=X]
166204 b.b.f_buf_func[4].y : X [by b.b.f_buf_func[4]._y:=X]
167237 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
167349 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
175755 b.b.f_buf_func[1]._y : X [by b.b._reset_BXX[0]:=1]
175795 b.b.f_buf_func[1].y : X [by b.b.f_buf_func[1]._y:=X]
188359 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
214861 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
215118 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
215205 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
215499 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
215500 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
217306 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
219313 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
220522 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
221112 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
221290 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
222093 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
222257 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
224452 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
224474 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
225321 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
255449 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
255582 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
271244 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
271603 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
285719 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
285940 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
285947 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
285977 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
292690 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
350151 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
350242 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
352431 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
352438 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
355225 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
355331 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
355409 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
355684 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
374680 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
375135 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
375147 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
375551 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
375563 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
381479 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
385755 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
388654 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
392949 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
392951 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
397486 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
398735 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
402234 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
402400 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
402475 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
402820 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
402958 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
408221 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
408223 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
452140 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
452141 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
452689 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
452700 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
453070 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
453137 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
455778 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
455794 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
460356 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
460884 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
463319 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
490199 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
514124 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
527165 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
527167 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
588125 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
588128 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
588157 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
588474 b.b.req_buf._y : 1 [by b.b._req:=0]
590075 b.b._reqX : 0 [by b.b.req_buf._y:=1]
590228 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
590272 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] set Reset 1
590272 Reset : 1
593033 b._reset_B : 0 [by Reset:=1]
606716 b.b.reset_buf._y : 1 [by b._reset_B:=0]
606717 b.b._reset_BX : 0 [by b.b.reset_buf._y:=1]
606934 b.b.reset_bufarray.buf2._y : 1 [by b.b._reset_BX:=0]
606956 b.b._reset_BXX[0] : 0 [by b.b.reset_bufarray.buf2._y:=1]
606957 b.b.f_buf_func[1]._y : 1 [by b.b._reset_BXX[0]:=0]
607115 b.b.t_buf_func[0]._y : 1 [by b.b._reset_BXX[0]:=0]
608244 b.b.f_buf_func[1].y : 0 [by b.b.f_buf_func[1]._y:=1]
608537 b.b.f_buf_func[2]._y : 1 [by b.b._reset_BXX[0]:=0]
608682 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]
609347 b.b.t_buf_func[0].y : 0 [by b.b.t_buf_func[0]._y:=1]
616301 b.b.f_buf_func[4]._y : 1 [by b.b._reset_BXX[0]:=0]
619133 b.b.f_buf_func[4].y : 0 [by b.b.f_buf_func[4]._y:=1]
626632 b.b.t_buf_func[3]._y : 1 [by b.b._reset_BXX[0]:=0]
632986 b.b.t_buf_func[3].y : 0 [by b.b.t_buf_func[3]._y:=1]
[] set Reset 0
632986 Reset : 0
632987 b._reset_B : 1 [by Reset:=0]
672271 b.b.reset_buf._y : 0 [by b._reset_B:=1]
672433 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
679802 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
679816 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
[] Reset finished, setting data
679816 b.in.d[0] : 0
679816 b.in.d[4] : 1
679816 b.in.d[2] : 1
679816 b.in.d[1] : 1
679816 b.in.d[3] : 0
679817 b.b._inB[1] : 0 [by b.in.d[1]:=1]
679817 b.b._inB[3] : 1 [by b.in.d[3]:=0]
679823 b.b._inB[0] : 1 [by b.in.d[0]:=0]
679976 b.b._inB[4] : 0 [by b.in.d[4]:=1]
701373 b.b._inB[2] : 0 [by b.in.d[2]:=1]
[] Reset finished, setting req 1
701373 b.in.r : 1
701374 b.b.dly.and2[0]._y : 0 [by b.in.r:=1]
703617 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
703804 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
703805 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
707987 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
742769 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
742770 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
743623 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
743628 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
744519 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
744520 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
744537 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
747110 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
755471 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
755474 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
756415 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
815377 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
815378 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
815420 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
818237 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
831970 b.b.dly.and2[2]._y : 0 [by b.b.dly._a[2]:=1]
832065 b.b.dly.dly[3].a : 1 [by b.b.dly.and2[2]._y:=0]
832400 b.b.dly.dly[3]._y : 0 [by b.b.dly.dly[3].a:=1]
832408 b.b.dly.dly[3].__y : 1 [by b.b.dly.dly[3]._y:=0]
832442 b.b.dly.dly[3].___y : 0 [by b.b.dly.dly[3].__y:=1]
846329 b.b.dly.dly[3].y : 1 [by b.b.dly.dly[3].___y:=0]
847247 b.b.dly.dly[4]._y : 0 [by b.b.dly.dly[3].y:=1]
847251 b.b.dly.dly[4].__y : 1 [by b.b.dly.dly[4]._y:=0]
893629 b.b.dly.dly[4].___y : 0 [by b.b.dly.dly[4].__y:=1]
896027 b.b.dly.dly[4].y : 1 [by b.b.dly.dly[4].___y:=0]
899242 b.b.dly.dly[5]._y : 0 [by b.b.dly.dly[4].y:=1]
946361 b.b.dly.dly[5].__y : 1 [by b.b.dly.dly[5]._y:=0]
946409 b.b.dly.dly[5].___y : 0 [by b.b.dly.dly[5].__y:=1]
946412 b.b.dly.dly[5].y : 1 [by b.b.dly.dly[5].___y:=0]
946590 b.b.dly.dly[6]._y : 0 [by b.b.dly.dly[5].y:=1]
967567 b.b.dly.dly[6].__y : 1 [by b.b.dly.dly[6]._y:=0]
979466 b.b.dly.dly[6].___y : 0 [by b.b.dly.dly[6].__y:=1]
985417 b.b.dly.dly[6].y : 1 [by b.b.dly.dly[6].___y:=0]
1024902 b.b.dly.mu2[2]._y : 0 [by b.b.dly.dly[6].y:=1]
1025729 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
1025902 b.b.dly.and2[3]._y : 0 [by b.b.dly._a[3]:=1]
1026086 b.b.dly.dly[7].a : 1 [by b.b.dly.and2[3]._y:=0]
1026087 b.b.dly.dly[7]._y : 0 [by b.b.dly.dly[7].a:=1]
1026160 b.b.dly.dly[7].__y : 1 [by b.b.dly.dly[7]._y:=0]
1026164 b.b.dly.dly[7].___y : 0 [by b.b.dly.dly[7].__y:=1]
1063452 b.b.dly.dly[7].y : 1 [by b.b.dly.dly[7].___y:=0]
1063548 b.b.dly.dly[8]._y : 0 [by b.b.dly.dly[7].y:=1]
1063684 b.b.dly.dly[8].__y : 1 [by b.b.dly.dly[8]._y:=0]
1063685 b.b.dly.dly[8].___y : 0 [by b.b.dly.dly[8].__y:=1]
1082731 b.b.dly.dly[8].y : 1 [by b.b.dly.dly[8].___y:=0]
1082972 b.b.dly.dly[9]._y : 0 [by b.b.dly.dly[8].y:=1]
1086931 b.b.dly.dly[9].__y : 1 [by b.b.dly.dly[9]._y:=0]
1086943 b.b.dly.dly[9].___y : 0 [by b.b.dly.dly[9].__y:=1]
1090843 b.b.dly.dly[9].y : 1 [by b.b.dly.dly[9].___y:=0]
1091872 b.b.dly.dly[10]._y : 0 [by b.b.dly.dly[9].y:=1]
1091873 b.b.dly.dly[10].__y : 1 [by b.b.dly.dly[10]._y:=0]
1091929 b.b.dly.dly[10].___y : 0 [by b.b.dly.dly[10].__y:=1]
1136935 b.b.dly.dly[10].y : 1 [by b.b.dly.dly[10].___y:=0]
1136936 b.b.dly.dly[11]._y : 0 [by b.b.dly.dly[10].y:=1]
1136973 b.b.dly.dly[11].__y : 1 [by b.b.dly.dly[11]._y:=0]
1160348 b.b.dly.dly[11].___y : 0 [by b.b.dly.dly[11].__y:=1]
1160349 b.b.dly.dly[11].y : 1 [by b.b.dly.dly[11].___y:=0]
1163913 b.b.dly.dly[12]._y : 0 [by b.b.dly.dly[11].y:=1]
1165605 b.b.dly.dly[12].__y : 1 [by b.b.dly.dly[12]._y:=0]
1165618 b.b.dly.dly[12].___y : 0 [by b.b.dly.dly[12].__y:=1]
1182602 b.b.dly.dly[12].y : 1 [by b.b.dly.dly[12].___y:=0]
1182959 b.b.dly.dly[13]._y : 0 [by b.b.dly.dly[12].y:=1]
1182984 b.b.dly.dly[13].__y : 1 [by b.b.dly.dly[13]._y:=0]
1183005 b.b.dly.dly[13].___y : 0 [by b.b.dly.dly[13].__y:=1]
1183006 b.b.dly.dly[13].y : 1 [by b.b.dly.dly[13].___y:=0]
1192654 b.b.dly.dly[14]._y : 0 [by b.b.dly.dly[13].y:=1]
1192655 b.b.dly.dly[14].__y : 1 [by b.b.dly.dly[14]._y:=0]
1192656 b.b.dly.dly[14].___y : 0 [by b.b.dly.dly[14].__y:=1]
1192817 b.b.dly.mu2[3].b : 1 [by b.b.dly.dly[14].___y:=0]
1193854 b.b.dly.mu2[3]._y : 0 [by b.b.dly.mu2[3].b:=1]
1193859 b.b._req : 1 [by b.b.dly.mu2[3]._y:=0]
1194440 b.b.req_buf._y : 0 [by b.b._req:=1]
1194848 b.b._reqX : 1 [by b.b.req_buf._y:=0]
1194859 b.b.req_bufarray.buf2._y : 0 [by b.b._reqX:=1]
1195906 b.b._reqXX[0] : 1 [by b.b.req_bufarray.buf2._y:=0]
1195910 b.b.t_buf_func[1]._y : 0 [by b.b._reqXX[0]:=1]
1195920 b.b.f_buf_func[0]._y : 0 [by b.b._reqXX[0]:=1]
1195924 b.b.f_buf_func[3]._y : 0 [by b.b._reqXX[0]:=1]
1196010 b.b.t_buf_func[2]._y : 0 [by b.b._reqXX[0]:=1]
1196152 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
1196853 b.b.t_buf_func[2].y : 1 [by b.b.t_buf_func[2]._y:=0]
1197114 b.b.t_buf_func[1].y : 1 [by b.b.t_buf_func[1]._y:=0]
1204375 b.b.f_buf_func[0].y : 1 [by b.b.f_buf_func[0]._y:=0]
1227350 b.b.t_buf_func[4]._y : 0 [by b.b._reqXX[0]:=1]
1228809 b.b.t_buf_func[4].y : 1 [by b.b.t_buf_func[4]._y:=0]
[] Receiving val out
1228809 b.out.v : 1
1228879 b.b.inack_ctl._y : 0 [by b.out.v:=1]
1279301 b.in.a : 1 [by b.b.inack_ctl._y:=0]
1279312 b.b._en : 0 [by b.in.a:=1]
1279315 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
1279366 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
1280463 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
1280527 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
[] Changing some input data
1280527 b.in.d[0] : 1
1289179 b.b._inB[0] : 0 [by b.in.d[0]:=1]
[] Removing req
[] Changing more data
1289179 b.in.r : 0
1289179 b.in.d[4] : 0
1289260 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
1300256 b.b._inB[4] : 1 [by b.in.d[4]:=0]
1307243 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
1307335 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
1315646 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
1317390 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
1318003 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
1332025 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
1332070 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
1333067 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
1334716 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
1335241 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
1336141 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
1336193 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
1336200 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
1351812 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
1358279 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
1358281 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
1358635 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
1358768 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
1358769 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
1358773 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
1359319 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
1404882 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
1404883 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
1417261 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
1417340 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
1419773 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
1419861 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
1427643 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
1455970 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
1456029 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
1456059 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
1457526 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
1517030 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
1536414 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
1537099 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
1553814 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
1553941 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
1554110 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
1554153 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
1554165 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
1555444 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
1555677 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
1555680 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
1555718 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
1555719 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
1568471 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
1568563 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
1571290 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
1571292 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
1571293 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
1572794 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
1572796 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
1572814 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
1572933 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
1578653 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
1578661 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
1578715 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
1629253 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
1629258 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
1630325 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
1630326 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
1630464 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
1630465 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
1630529 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
1630652 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
1630654 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
1630691 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
1630834 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
1630885 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
1631327 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
1631338 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
1631339 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
1631348 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
1631373 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
1641626 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
1645147 b.b.req_buf._y : 1 [by b.b._req:=0]
1645292 b.b._reqX : 0 [by b.b.req_buf._y:=1]
1661460 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
1661690 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] Receiving ack out
1661690 b.out.a : 1
1662381 b.b._out_a_B : 0 [by b.out.a:=1]
1662395 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
1663924 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
1664006 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
1664007 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
1664008 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
1664017 b.b.f_buf_func[0]._y : 1 [by b.b._out_a_BX_f[0]:=0]
1670518 b.b.f_buf_func[0].y : 0 [by b.b.f_buf_func[0]._y:=1]
1681436 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
1681568 b.b.t_buf_func[4]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1681569 b.b.t_buf_func[4].y : 0 [by b.b.t_buf_func[4]._y:=1]
1682075 b.b.t_buf_func[1]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1682092 b.b.t_buf_func[1].y : 0 [by b.b.t_buf_func[1]._y:=1]
1683229 b.b.t_buf_func[2]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1683381 b.b.t_buf_func[2].y : 0 [by b.b.t_buf_func[2]._y:=1]
1683381 b.out.v : 0
1686364 b.b.inack_ctl._y : 1 [by b.out.v:=0]
1686367 b.in.a : 0 [by b.b.inack_ctl._y:=1]
1686791 b.b._en : 1 [by b.in.a:=0]
1686797 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
1689258 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
1689379 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
1690209 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
[] Set ack out 0
1690209 b.out.a : 0
1713141 b.b._out_a_B : 1 [by b.out.a:=0]
1713143 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
1713335 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
1713473 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
1713746 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
[] Again!!! setting data
1713746 b.in.d[0] : 0
1713746 b.in.d[2] : 0
1713746 b.in.d[1] : 0
1713763 b.b._inB[2] : 1 [by b.in.d[2]:=0]
1713763 b.b._inB[0] : 1 [by b.in.d[0]:=0]
1714172 b.b._inB[1] : 1 [by b.in.d[1]:=0]
[] Again!!! setting req 1
1714172 b.in.r : 1
1714173 b.b.dly.and2[0]._y : 0 [by b.in.r:=1]
1714174 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
1715200 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
1715201 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
1715220 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
1715388 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
1715927 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
1716088 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
1716261 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
1718808 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
1733869 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
1733870 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
1733871 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
1734261 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
1734468 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
1735301 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
1735329 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
1735336 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
1735750 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
1735754 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
1737533 b.b.dly.and2[2]._y : 0 [by b.b.dly._a[2]:=1]
1760407 b.b.dly.dly[3].a : 1 [by b.b.dly.and2[2]._y:=0]
1760573 b.b.dly.dly[3]._y : 0 [by b.b.dly.dly[3].a:=1]
1800443 b.b.dly.dly[3].__y : 1 [by b.b.dly.dly[3]._y:=0]
1809088 b.b.dly.dly[3].___y : 0 [by b.b.dly.dly[3].__y:=1]
1810021 b.b.dly.dly[3].y : 1 [by b.b.dly.dly[3].___y:=0]
1810877 b.b.dly.dly[4]._y : 0 [by b.b.dly.dly[3].y:=1]
1811016 b.b.dly.dly[4].__y : 1 [by b.b.dly.dly[4]._y:=0]
1837225 b.b.dly.dly[4].___y : 0 [by b.b.dly.dly[4].__y:=1]
1837420 b.b.dly.dly[4].y : 1 [by b.b.dly.dly[4].___y:=0]
1837422 b.b.dly.dly[5]._y : 0 [by b.b.dly.dly[4].y:=1]
1890871 b.b.dly.dly[5].__y : 1 [by b.b.dly.dly[5]._y:=0]
1890877 b.b.dly.dly[5].___y : 0 [by b.b.dly.dly[5].__y:=1]
1891131 b.b.dly.dly[5].y : 1 [by b.b.dly.dly[5].___y:=0]
1891139 b.b.dly.dly[6]._y : 0 [by b.b.dly.dly[5].y:=1]
1891140 b.b.dly.dly[6].__y : 1 [by b.b.dly.dly[6]._y:=0]
1891146 b.b.dly.dly[6].___y : 0 [by b.b.dly.dly[6].__y:=1]
1942182 b.b.dly.dly[6].y : 1 [by b.b.dly.dly[6].___y:=0]
1945272 b.b.dly.mu2[2]._y : 0 [by b.b.dly.dly[6].y:=1]
1945498 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
1946317 b.b.dly.and2[3]._y : 0 [by b.b.dly._a[3]:=1]
1946318 b.b.dly.dly[7].a : 1 [by b.b.dly.and2[3]._y:=0]
1946324 b.b.dly.dly[7]._y : 0 [by b.b.dly.dly[7].a:=1]
1946326 b.b.dly.dly[7].__y : 1 [by b.b.dly.dly[7]._y:=0]
1949888 b.b.dly.dly[7].___y : 0 [by b.b.dly.dly[7].__y:=1]
1949903 b.b.dly.dly[7].y : 1 [by b.b.dly.dly[7].___y:=0]
1970704 b.b.dly.dly[8]._y : 0 [by b.b.dly.dly[7].y:=1]
1970811 b.b.dly.dly[8].__y : 1 [by b.b.dly.dly[8]._y:=0]
1970904 b.b.dly.dly[8].___y : 0 [by b.b.dly.dly[8].__y:=1]
1972556 b.b.dly.dly[8].y : 1 [by b.b.dly.dly[8].___y:=0]
1976495 b.b.dly.dly[9]._y : 0 [by b.b.dly.dly[8].y:=1]
1977253 b.b.dly.dly[9].__y : 1 [by b.b.dly.dly[9]._y:=0]
1979876 b.b.dly.dly[9].___y : 0 [by b.b.dly.dly[9].__y:=1]
1980592 b.b.dly.dly[9].y : 1 [by b.b.dly.dly[9].___y:=0]
1980593 b.b.dly.dly[10]._y : 0 [by b.b.dly.dly[9].y:=1]
1982333 b.b.dly.dly[10].__y : 1 [by b.b.dly.dly[10]._y:=0]
1982334 b.b.dly.dly[10].___y : 0 [by b.b.dly.dly[10].__y:=1]
1994486 b.b.dly.dly[10].y : 1 [by b.b.dly.dly[10].___y:=0]
2022685 b.b.dly.dly[11]._y : 0 [by b.b.dly.dly[10].y:=1]
2022686 b.b.dly.dly[11].__y : 1 [by b.b.dly.dly[11]._y:=0]
2022692 b.b.dly.dly[11].___y : 0 [by b.b.dly.dly[11].__y:=1]
2022693 b.b.dly.dly[11].y : 1 [by b.b.dly.dly[11].___y:=0]
2062182 b.b.dly.dly[12]._y : 0 [by b.b.dly.dly[11].y:=1]
2083781 b.b.dly.dly[12].__y : 1 [by b.b.dly.dly[12]._y:=0]
2083803 b.b.dly.dly[12].___y : 0 [by b.b.dly.dly[12].__y:=1]
2106311 b.b.dly.dly[12].y : 1 [by b.b.dly.dly[12].___y:=0]
2106318 b.b.dly.dly[13]._y : 0 [by b.b.dly.dly[12].y:=1]
2106383 b.b.dly.dly[13].__y : 1 [by b.b.dly.dly[13]._y:=0]
2106396 b.b.dly.dly[13].___y : 0 [by b.b.dly.dly[13].__y:=1]
2107520 b.b.dly.dly[13].y : 1 [by b.b.dly.dly[13].___y:=0]
2107624 b.b.dly.dly[14]._y : 0 [by b.b.dly.dly[13].y:=1]
2107665 b.b.dly.dly[14].__y : 1 [by b.b.dly.dly[14]._y:=0]
2107666 b.b.dly.dly[14].___y : 0 [by b.b.dly.dly[14].__y:=1]
2107667 b.b.dly.mu2[3].b : 1 [by b.b.dly.dly[14].___y:=0]
2172045 b.b.dly.mu2[3]._y : 0 [by b.b.dly.mu2[3].b:=1]
2185217 b.b._req : 1 [by b.b.dly.mu2[3]._y:=0]
2185218 b.b.req_buf._y : 0 [by b.b._req:=1]
2205043 b.b._reqX : 1 [by b.b.req_buf._y:=0]
2208179 b.b.req_bufarray.buf2._y : 0 [by b.b._reqX:=1]
2209005 b.b._reqXX[0] : 1 [by b.b.req_bufarray.buf2._y:=0]
2209063 b.b.f_buf_func[2]._y : 0 [by b.b._reqXX[0]:=1]
2210838 b.b.f_buf_func[0]._y : 0 [by b.b._reqXX[0]:=1]
2210852 b.b.f_buf_func[0].y : 1 [by b.b.f_buf_func[0]._y:=0]
2211448 b.b.f_buf_func[3]._y : 0 [by b.b._reqXX[0]:=1]
2211804 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
2225553 b.b.f_buf_func[1]._y : 0 [by b.b._reqXX[0]:=1]
2225778 b.b.f_buf_func[4]._y : 0 [by b.b._reqXX[0]:=1]
2225883 b.b.f_buf_func[4].y : 1 [by b.b.f_buf_func[4]._y:=0]
2246262 b.b.f_buf_func[2].y : 1 [by b.b.f_buf_func[2]._y:=0]
2261391 b.b.f_buf_func[1].y : 1 [by b.b.f_buf_func[1]._y:=0]
[] Receiving val out
2261391 b.out.v : 1
2261500 b.b.inack_ctl._y : 0 [by b.out.v:=1]
2261501 b.in.a : 1 [by b.b.inack_ctl._y:=0]
2261510 b.b._en : 0 [by b.in.a:=1]
2261511 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
2297905 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
2299463 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
2299464 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
[] Changing some input data
2299464 b.in.d[0] : 1
2299464 b.in.d[2] : 1
2299464 b.in.d[1] : 1
2300214 b.b._inB[1] : 0 [by b.in.d[1]:=1]
2302553 b.b._inB[0] : 0 [by b.in.d[0]:=1]
2348190 b.b._inB[2] : 0 [by b.in.d[2]:=1]
[] Removing req
[] Changing more data
2348190 b.in.r : 0
2354945 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
2354996 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
2355006 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
2355326 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
2362908 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
2362909 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
2362910 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
2364640 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
2366327 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
2366342 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
2390616 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
2391070 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
2391386 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
2391387 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
2391770 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
2399233 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
2399253 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
2400576 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
2400663 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
2407385 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
2407397 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
2407542 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
2408443 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
2409792 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
2410011 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
2418342 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
2449923 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
2449941 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
2452135 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
2490107 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
2490227 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
2496542 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
2498606 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
2499198 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
2499205 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
2499206 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
2499330 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
2505260 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
2506312 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
2506672 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
2516866 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
2517963 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
2537855 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
2537859 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
2549523 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
2587442 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
2605103 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
2608484 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
2608740 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
2623670 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
2623707 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
2623719 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
2623728 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
2624155 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
2624397 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
2625232 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
2671968 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
2673528 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
2710621 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
2710881 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
2719869 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
2719870 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
2755920 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
2756304 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
2756323 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
2756332 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
2778286 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
2778474 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
2824250 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
2827850 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
2827998 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
2846875 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
2846890 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
2857499 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
2858386 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
2866368 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
2866369 b.b.req_buf._y : 1 [by b.b._req:=0]
2873095 b.b._reqX : 0 [by b.b.req_buf._y:=1]
2873460 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
2882418 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] Receiving ack out
2882418 b.out.a : 1
2883802 b.b._out_a_B : 0 [by b.out.a:=1]
2883823 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
2883826 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
2883828 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2883829 b.b.f_buf_func[4]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2883829 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
2883843 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
2884408 b.b.f_buf_func[2]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2885268 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]
2885703 b.b.f_buf_func[0]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2885704 b.b.f_buf_func[0].y : 0 [by b.b.f_buf_func[0]._y:=1]
2887281 b.b.f_buf_func[4].y : 0 [by b.b.f_buf_func[4]._y:=1]
2890976 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
2893335 b.b.f_buf_func[1]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2893410 b.b.f_buf_func[1].y : 0 [by b.b.f_buf_func[1]._y:=1]
2893410 b.out.v : 0
2921361 b.b.inack_ctl._y : 1 [by b.out.v:=0]
2921435 b.in.a : 0 [by b.b.inack_ctl._y:=1]
2923705 b.b._en : 1 [by b.in.a:=0]
2923803 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
2929476 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
2933329 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
2955531 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
[] Set ack out 0
2955531 b.out.a : 0
2961672 b.b._out_a_B : 1 [by b.out.a:=0]
2961676 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
2961681 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
2964032 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
2964323 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
test/unit_tests/bd2qdi_5/run/test.prs
-731
View File
@@ -1,731 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"&~"b.b.inack_ctl.c3"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl._y"+
"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.c3"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl._y"-
"b.b.inack_ctl._y"->"b.b.inack_ctl.y"-
~("b.b.inack_ctl._y")->"b.b.inack_ctl.y"+
"b.b.dly.and2[0].a"&"b.b.dly.and2[0].b"->"b.b.dly.and2[0]._y"-
~("b.b.dly.and2[0].a"&"b.b.dly.and2[0].b")->"b.b.dly.and2[0]._y"+
"b.b.dly.and2[0]._y"->"b.b.dly.and2[0].y"-
~("b.b.dly.and2[0]._y")->"b.b.dly.and2[0].y"+
"b.b.dly.and2[1].a"&"b.b.dly.and2[1].b"->"b.b.dly.and2[1]._y"-
~("b.b.dly.and2[1].a"&"b.b.dly.and2[1].b")->"b.b.dly.and2[1]._y"+
"b.b.dly.and2[1]._y"->"b.b.dly.and2[1].y"-
~("b.b.dly.and2[1]._y")->"b.b.dly.and2[1].y"+
"b.b.dly.and2[2].a"&"b.b.dly.and2[2].b"->"b.b.dly.and2[2]._y"-
~("b.b.dly.and2[2].a"&"b.b.dly.and2[2].b")->"b.b.dly.and2[2]._y"+
"b.b.dly.and2[2]._y"->"b.b.dly.and2[2].y"-
~("b.b.dly.and2[2]._y")->"b.b.dly.and2[2].y"+
"b.b.dly.and2[3].a"&"b.b.dly.and2[3].b"->"b.b.dly.and2[3]._y"-
~("b.b.dly.and2[3].a"&"b.b.dly.and2[3].b")->"b.b.dly.and2[3]._y"+
"b.b.dly.and2[3]._y"->"b.b.dly.and2[3].y"-
~("b.b.dly.and2[3]._y")->"b.b.dly.and2[3].y"+
= "b.b.dly.s[0]" "b.b.dly.mu2[0].s"
= "b.b.dly.s[0]" "b.b.dly.and2[0].b"
= "b.b.dly.s[1]" "b.b.dly.mu2[1].s"
= "b.b.dly.s[1]" "b.b.dly.and2[1].b"
= "b.b.dly.s[2]" "b.b.dly.mu2[2].s"
= "b.b.dly.s[2]" "b.b.dly.and2[2].b"
= "b.b.dly.s[3]" "b.b.dly.mu2[3].s"
= "b.b.dly.s[3]" "b.b.dly.and2[3].b"
= "b.b.dly.supply.vdd" "b.b.dly.dly[14].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[13].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[12].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[11].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[10].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[9].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[8].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[7].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[6].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[5].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[4].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[0].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[0].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[0].vdd"
= "b.b.dly.supply.vss" "b.b.dly.dly[14].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[13].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[12].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[11].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[10].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[9].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[8].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[7].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[6].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[5].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[4].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[0].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[0].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[0].vss"
"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._s"-
~("b.b.dly.mu2[0].s")->"b.b.dly.mu2[0]._s"+
~"b.b.dly.mu2[0].a"&~"b.b.dly.mu2[0].s"|~"b.b.dly.mu2[0].b"&~"b.b.dly.mu2[0]._s"->"b.b.dly.mu2[0]._y"+
"b.b.dly.mu2[0].a"&"b.b.dly.mu2[0]._s"|"b.b.dly.mu2[0].b"&"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._y"-
"b.b.dly.mu2[0]._y"->"b.b.dly.mu2[0].y"-
~("b.b.dly.mu2[0]._y")->"b.b.dly.mu2[0].y"+
"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._s"-
~("b.b.dly.mu2[1].s")->"b.b.dly.mu2[1]._s"+
~"b.b.dly.mu2[1].a"&~"b.b.dly.mu2[1].s"|~"b.b.dly.mu2[1].b"&~"b.b.dly.mu2[1]._s"->"b.b.dly.mu2[1]._y"+
"b.b.dly.mu2[1].a"&"b.b.dly.mu2[1]._s"|"b.b.dly.mu2[1].b"&"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._y"-
"b.b.dly.mu2[1]._y"->"b.b.dly.mu2[1].y"-
~("b.b.dly.mu2[1]._y")->"b.b.dly.mu2[1].y"+
"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._s"-
~("b.b.dly.mu2[2].s")->"b.b.dly.mu2[2]._s"+
~"b.b.dly.mu2[2].a"&~"b.b.dly.mu2[2].s"|~"b.b.dly.mu2[2].b"&~"b.b.dly.mu2[2]._s"->"b.b.dly.mu2[2]._y"+
"b.b.dly.mu2[2].a"&"b.b.dly.mu2[2]._s"|"b.b.dly.mu2[2].b"&"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._y"-
"b.b.dly.mu2[2]._y"->"b.b.dly.mu2[2].y"-
~("b.b.dly.mu2[2]._y")->"b.b.dly.mu2[2].y"+
"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._s"-
~("b.b.dly.mu2[3].s")->"b.b.dly.mu2[3]._s"+
~"b.b.dly.mu2[3].a"&~"b.b.dly.mu2[3].s"|~"b.b.dly.mu2[3].b"&~"b.b.dly.mu2[3]._s"->"b.b.dly.mu2[3]._y"+
"b.b.dly.mu2[3].a"&"b.b.dly.mu2[3]._s"|"b.b.dly.mu2[3].b"&"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._y"-
"b.b.dly.mu2[3]._y"->"b.b.dly.mu2[3].y"-
~("b.b.dly.mu2[3]._y")->"b.b.dly.mu2[3].y"+
"b.b.dly.dly[0].a"->"b.b.dly.dly[0]._y"-
~("b.b.dly.dly[0].a")->"b.b.dly.dly[0]._y"+
"b.b.dly.dly[0]._y"->"b.b.dly.dly[0].__y"-
~("b.b.dly.dly[0]._y")->"b.b.dly.dly[0].__y"+
"b.b.dly.dly[0].__y"->"b.b.dly.dly[0].___y"-
~("b.b.dly.dly[0].__y")->"b.b.dly.dly[0].___y"+
"b.b.dly.dly[0].___y"->"b.b.dly.dly[0].y"-
~("b.b.dly.dly[0].___y")->"b.b.dly.dly[0].y"+
"b.b.dly.dly[1].a"->"b.b.dly.dly[1]._y"-
~("b.b.dly.dly[1].a")->"b.b.dly.dly[1]._y"+
"b.b.dly.dly[1]._y"->"b.b.dly.dly[1].__y"-
~("b.b.dly.dly[1]._y")->"b.b.dly.dly[1].__y"+
"b.b.dly.dly[1].__y"->"b.b.dly.dly[1].___y"-
~("b.b.dly.dly[1].__y")->"b.b.dly.dly[1].___y"+
"b.b.dly.dly[1].___y"->"b.b.dly.dly[1].y"-
~("b.b.dly.dly[1].___y")->"b.b.dly.dly[1].y"+
"b.b.dly.dly[2].a"->"b.b.dly.dly[2]._y"-
~("b.b.dly.dly[2].a")->"b.b.dly.dly[2]._y"+
"b.b.dly.dly[2]._y"->"b.b.dly.dly[2].__y"-
~("b.b.dly.dly[2]._y")->"b.b.dly.dly[2].__y"+
"b.b.dly.dly[2].__y"->"b.b.dly.dly[2].___y"-
~("b.b.dly.dly[2].__y")->"b.b.dly.dly[2].___y"+
"b.b.dly.dly[2].___y"->"b.b.dly.dly[2].y"-
~("b.b.dly.dly[2].___y")->"b.b.dly.dly[2].y"+
"b.b.dly.dly[3].a"->"b.b.dly.dly[3]._y"-
~("b.b.dly.dly[3].a")->"b.b.dly.dly[3]._y"+
"b.b.dly.dly[3]._y"->"b.b.dly.dly[3].__y"-
~("b.b.dly.dly[3]._y")->"b.b.dly.dly[3].__y"+
"b.b.dly.dly[3].__y"->"b.b.dly.dly[3].___y"-
~("b.b.dly.dly[3].__y")->"b.b.dly.dly[3].___y"+
"b.b.dly.dly[3].___y"->"b.b.dly.dly[3].y"-
~("b.b.dly.dly[3].___y")->"b.b.dly.dly[3].y"+
"b.b.dly.dly[4].a"->"b.b.dly.dly[4]._y"-
~("b.b.dly.dly[4].a")->"b.b.dly.dly[4]._y"+
"b.b.dly.dly[4]._y"->"b.b.dly.dly[4].__y"-
~("b.b.dly.dly[4]._y")->"b.b.dly.dly[4].__y"+
"b.b.dly.dly[4].__y"->"b.b.dly.dly[4].___y"-
~("b.b.dly.dly[4].__y")->"b.b.dly.dly[4].___y"+
"b.b.dly.dly[4].___y"->"b.b.dly.dly[4].y"-
~("b.b.dly.dly[4].___y")->"b.b.dly.dly[4].y"+
"b.b.dly.dly[5].a"->"b.b.dly.dly[5]._y"-
~("b.b.dly.dly[5].a")->"b.b.dly.dly[5]._y"+
"b.b.dly.dly[5]._y"->"b.b.dly.dly[5].__y"-
~("b.b.dly.dly[5]._y")->"b.b.dly.dly[5].__y"+
"b.b.dly.dly[5].__y"->"b.b.dly.dly[5].___y"-
~("b.b.dly.dly[5].__y")->"b.b.dly.dly[5].___y"+
"b.b.dly.dly[5].___y"->"b.b.dly.dly[5].y"-
~("b.b.dly.dly[5].___y")->"b.b.dly.dly[5].y"+
"b.b.dly.dly[6].a"->"b.b.dly.dly[6]._y"-
~("b.b.dly.dly[6].a")->"b.b.dly.dly[6]._y"+
"b.b.dly.dly[6]._y"->"b.b.dly.dly[6].__y"-
~("b.b.dly.dly[6]._y")->"b.b.dly.dly[6].__y"+
"b.b.dly.dly[6].__y"->"b.b.dly.dly[6].___y"-
~("b.b.dly.dly[6].__y")->"b.b.dly.dly[6].___y"+
"b.b.dly.dly[6].___y"->"b.b.dly.dly[6].y"-
~("b.b.dly.dly[6].___y")->"b.b.dly.dly[6].y"+
"b.b.dly.dly[7].a"->"b.b.dly.dly[7]._y"-
~("b.b.dly.dly[7].a")->"b.b.dly.dly[7]._y"+
"b.b.dly.dly[7]._y"->"b.b.dly.dly[7].__y"-
~("b.b.dly.dly[7]._y")->"b.b.dly.dly[7].__y"+
"b.b.dly.dly[7].__y"->"b.b.dly.dly[7].___y"-
~("b.b.dly.dly[7].__y")->"b.b.dly.dly[7].___y"+
"b.b.dly.dly[7].___y"->"b.b.dly.dly[7].y"-
~("b.b.dly.dly[7].___y")->"b.b.dly.dly[7].y"+
"b.b.dly.dly[8].a"->"b.b.dly.dly[8]._y"-
~("b.b.dly.dly[8].a")->"b.b.dly.dly[8]._y"+
"b.b.dly.dly[8]._y"->"b.b.dly.dly[8].__y"-
~("b.b.dly.dly[8]._y")->"b.b.dly.dly[8].__y"+
"b.b.dly.dly[8].__y"->"b.b.dly.dly[8].___y"-
~("b.b.dly.dly[8].__y")->"b.b.dly.dly[8].___y"+
"b.b.dly.dly[8].___y"->"b.b.dly.dly[8].y"-
~("b.b.dly.dly[8].___y")->"b.b.dly.dly[8].y"+
"b.b.dly.dly[9].a"->"b.b.dly.dly[9]._y"-
~("b.b.dly.dly[9].a")->"b.b.dly.dly[9]._y"+
"b.b.dly.dly[9]._y"->"b.b.dly.dly[9].__y"-
~("b.b.dly.dly[9]._y")->"b.b.dly.dly[9].__y"+
"b.b.dly.dly[9].__y"->"b.b.dly.dly[9].___y"-
~("b.b.dly.dly[9].__y")->"b.b.dly.dly[9].___y"+
"b.b.dly.dly[9].___y"->"b.b.dly.dly[9].y"-
~("b.b.dly.dly[9].___y")->"b.b.dly.dly[9].y"+
"b.b.dly.dly[10].a"->"b.b.dly.dly[10]._y"-
~("b.b.dly.dly[10].a")->"b.b.dly.dly[10]._y"+
"b.b.dly.dly[10]._y"->"b.b.dly.dly[10].__y"-
~("b.b.dly.dly[10]._y")->"b.b.dly.dly[10].__y"+
"b.b.dly.dly[10].__y"->"b.b.dly.dly[10].___y"-
~("b.b.dly.dly[10].__y")->"b.b.dly.dly[10].___y"+
"b.b.dly.dly[10].___y"->"b.b.dly.dly[10].y"-
~("b.b.dly.dly[10].___y")->"b.b.dly.dly[10].y"+
"b.b.dly.dly[11].a"->"b.b.dly.dly[11]._y"-
~("b.b.dly.dly[11].a")->"b.b.dly.dly[11]._y"+
"b.b.dly.dly[11]._y"->"b.b.dly.dly[11].__y"-
~("b.b.dly.dly[11]._y")->"b.b.dly.dly[11].__y"+
"b.b.dly.dly[11].__y"->"b.b.dly.dly[11].___y"-
~("b.b.dly.dly[11].__y")->"b.b.dly.dly[11].___y"+
"b.b.dly.dly[11].___y"->"b.b.dly.dly[11].y"-
~("b.b.dly.dly[11].___y")->"b.b.dly.dly[11].y"+
"b.b.dly.dly[12].a"->"b.b.dly.dly[12]._y"-
~("b.b.dly.dly[12].a")->"b.b.dly.dly[12]._y"+
"b.b.dly.dly[12]._y"->"b.b.dly.dly[12].__y"-
~("b.b.dly.dly[12]._y")->"b.b.dly.dly[12].__y"+
"b.b.dly.dly[12].__y"->"b.b.dly.dly[12].___y"-
~("b.b.dly.dly[12].__y")->"b.b.dly.dly[12].___y"+
"b.b.dly.dly[12].___y"->"b.b.dly.dly[12].y"-
~("b.b.dly.dly[12].___y")->"b.b.dly.dly[12].y"+
"b.b.dly.dly[13].a"->"b.b.dly.dly[13]._y"-
~("b.b.dly.dly[13].a")->"b.b.dly.dly[13]._y"+
"b.b.dly.dly[13]._y"->"b.b.dly.dly[13].__y"-
~("b.b.dly.dly[13]._y")->"b.b.dly.dly[13].__y"+
"b.b.dly.dly[13].__y"->"b.b.dly.dly[13].___y"-
~("b.b.dly.dly[13].__y")->"b.b.dly.dly[13].___y"+
"b.b.dly.dly[13].___y"->"b.b.dly.dly[13].y"-
~("b.b.dly.dly[13].___y")->"b.b.dly.dly[13].y"+
"b.b.dly.dly[14].a"->"b.b.dly.dly[14]._y"-
~("b.b.dly.dly[14].a")->"b.b.dly.dly[14]._y"+
"b.b.dly.dly[14]._y"->"b.b.dly.dly[14].__y"-
~("b.b.dly.dly[14]._y")->"b.b.dly.dly[14].__y"+
"b.b.dly.dly[14].__y"->"b.b.dly.dly[14].___y"-
~("b.b.dly.dly[14].__y")->"b.b.dly.dly[14].___y"+
"b.b.dly.dly[14].___y"->"b.b.dly.dly[14].y"-
~("b.b.dly.dly[14].___y")->"b.b.dly.dly[14].y"+
= "b.b.dly.dly[14].y" "b.b.dly.mu2[3].b"
= "b.b.dly.dly[14].a" "b.b.dly.dly[13].y"
= "b.b.dly.dly[13].a" "b.b.dly.dly[12].y"
= "b.b.dly.dly[12].a" "b.b.dly.dly[11].y"
= "b.b.dly.dly[11].a" "b.b.dly.dly[10].y"
= "b.b.dly.dly[10].a" "b.b.dly.dly[9].y"
= "b.b.dly.dly[9].a" "b.b.dly.dly[8].y"
= "b.b.dly.dly[8].a" "b.b.dly.dly[7].y"
= "b.b.dly.dly[7].a" "b.b.dly.and2[3].y"
= "b.b.dly.dly[6].y" "b.b.dly.mu2[2].b"
= "b.b.dly.dly[6].a" "b.b.dly.dly[5].y"
= "b.b.dly.dly[5].a" "b.b.dly.dly[4].y"
= "b.b.dly.dly[4].a" "b.b.dly.dly[3].y"
= "b.b.dly.dly[3].a" "b.b.dly.and2[2].y"
= "b.b.dly.dly[2].y" "b.b.dly.mu2[1].b"
= "b.b.dly.dly[2].a" "b.b.dly.dly[1].y"
= "b.b.dly.dly[1].a" "b.b.dly.and2[1].y"
= "b.b.dly.dly[0].y" "b.b.dly.mu2[0].b"
= "b.b.dly.dly[0].a" "b.b.dly.and2[0].y"
= "b.b.dly._a[1]" "b.b.dly.mu2[1].a"
= "b.b.dly._a[1]" "b.b.dly.and2[1].a"
= "b.b.dly._a[1]" "b.b.dly.mu2[0].y"
= "b.b.dly._a[2]" "b.b.dly.mu2[2].a"
= "b.b.dly._a[2]" "b.b.dly.and2[2].a"
= "b.b.dly._a[2]" "b.b.dly.mu2[1].y"
= "b.b.dly._a[3]" "b.b.dly.mu2[3].a"
= "b.b.dly._a[3]" "b.b.dly.and2[3].a"
= "b.b.dly._a[3]" "b.b.dly.mu2[2].y"
= "b.b.dly.out" "b.b.dly.mu2[3].y"
= "b.b.dly.out" "b.b.dly._a[4]"
= "b.b.dly.in" "b.b.dly.mu2[0].a"
= "b.b.dly.in" "b.b.dly.and2[0].a"
= "b.b.dly.in" "b.b.dly._a[0]"
= "b.b._out_a_BX_f[0]" "b.b.out_a_B_buf_t.out[0]"
= "b.b._out_a_BX_f[1]" "b.b.out_a_B_buf_t.out[1]"
= "b.b._out_a_BX_f[2]" "b.b.out_a_B_buf_t.out[2]"
= "b.b._out_a_BX_f[3]" "b.b.out_a_B_buf_t.out[3]"
= "b.b._out_a_BX_f[4]" "b.b.out_a_B_buf_t.out[4]"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[4].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[3].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[2].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[1].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[0].c2"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[4]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[3]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[2]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[1]"
"b.b.out_a_inv.a"->"b.b.out_a_inv.y"-
~("b.b.out_a_inv.a")->"b.b.out_a_inv.y"+
= "b.b._en" "b.b.en_buf_f.in"
= "b.b._en" "b.b.en_buf_t.in"
= "b.b._en" "b.b.en_ctl.y"
= "b.b._en" "b.b.inack_ctl.c1"
timing("b.b.in.a"-,"b.b.in.d[0]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[1]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[2]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[3]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[4]","b.b.in.r"+)
= "b.b.in.r" "b.b.dly.in"
= "b.b.in.a" "b.b.en_ctl.c1"
= "b.b.in.a" "b.b.inack_ctl.y"
= "b.b.in.d[0]" "b.b.t_buf_func[0].n1"
= "b.b.in.d[0]" "b.b.input_invs[0].a"
= "b.b.in.d[1]" "b.b.t_buf_func[1].n1"
= "b.b.in.d[1]" "b.b.input_invs[1].a"
= "b.b.in.d[2]" "b.b.t_buf_func[2].n1"
= "b.b.in.d[2]" "b.b.input_invs[2].a"
= "b.b.in.d[3]" "b.b.t_buf_func[3].n1"
= "b.b.in.d[3]" "b.b.input_invs[3].a"
= "b.b.in.d[4]" "b.b.t_buf_func[4].n1"
= "b.b.in.d[4]" "b.b.input_invs[4].a"
= "b.b._inB[0]" "b.b.f_buf_func[0].n1"
= "b.b._inB[0]" "b.b.input_invs[0].y"
= "b.b._inB[1]" "b.b.f_buf_func[1].n1"
= "b.b._inB[1]" "b.b.input_invs[1].y"
= "b.b._inB[2]" "b.b.f_buf_func[2].n1"
= "b.b._inB[2]" "b.b.input_invs[2].y"
= "b.b._inB[3]" "b.b.f_buf_func[3].n1"
= "b.b._inB[3]" "b.b.input_invs[3].y"
= "b.b._inB[4]" "b.b.f_buf_func[4].n1"
= "b.b._inB[4]" "b.b.input_invs[4].y"
"b.b.reset_buf.a"->"b.b.reset_buf._y"-
~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
"b.b.reset_buf._y"->"b.b.reset_buf.y"-
~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
= "b.b._reset_BX" "b.b.reset_bufarray.in"
= "b.b._reset_BX" "b.b.reset_buf.y"
= "b.b.reset_B" "b.b.reset_buf.a"
= "b.b._out_a_BX_t[0]" "b.b.out_a_B_buf_f.out[0]"
= "b.b._out_a_BX_t[1]" "b.b.out_a_B_buf_f.out[1]"
= "b.b._out_a_BX_t[2]" "b.b.out_a_B_buf_f.out[2]"
= "b.b._out_a_BX_t[3]" "b.b.out_a_B_buf_f.out[3]"
= "b.b._out_a_BX_t[4]" "b.b.out_a_B_buf_f.out[4]"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[4].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[3].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[2].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[1].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[0].c2"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[4]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[3]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[2]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[1]"
= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
"b.b.input_invs[0].a"->"b.b.input_invs[0].y"-
~("b.b.input_invs[0].a")->"b.b.input_invs[0].y"+
"b.b.input_invs[1].a"->"b.b.input_invs[1].y"-
~("b.b.input_invs[1].a")->"b.b.input_invs[1].y"+
"b.b.input_invs[2].a"->"b.b.input_invs[2].y"-
~("b.b.input_invs[2].a")->"b.b.input_invs[2].y"+
"b.b.input_invs[3].a"->"b.b.input_invs[3].y"-
~("b.b.input_invs[3].a")->"b.b.input_invs[3].y"+
"b.b.input_invs[4].a"->"b.b.input_invs[4].y"-
~("b.b.input_invs[4].a")->"b.b.input_invs[4].y"+
"b.b.out_a_B_buf_t.buf2.a"->"b.b.out_a_B_buf_t.buf2._y"-
~("b.b.out_a_B_buf_t.buf2.a")->"b.b.out_a_B_buf_t.buf2._y"+
"b.b.out_a_B_buf_t.buf2._y"->"b.b.out_a_B_buf_t.buf2.y"-
~("b.b.out_a_B_buf_t.buf2._y")->"b.b.out_a_B_buf_t.buf2.y"+
= "b.b.out_a_B_buf_t.supply.vdd" "b.b.out_a_B_buf_t.buf2.vdd"
= "b.b.out_a_B_buf_t.supply.vss" "b.b.out_a_B_buf_t.buf2.vss"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[4]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[3]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[2]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[1]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.buf2.y"
= "b.b.out_a_B_buf_t.in" "b.b.out_a_B_buf_t.buf2.a"
= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
= "b.b._en_X_f[0]" "b.b.f_buf_func[4].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[3].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[2].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[1].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[0].c1"
= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
= "b.b.dly_cfg[0]" "b.b.dly.s[0]"
= "b.b.dly_cfg[1]" "b.b.dly.s[1]"
= "b.b.dly_cfg[2]" "b.b.dly.s[2]"
= "b.b.dly_cfg[3]" "b.b.dly.s[3]"
= "b.b.supply.vss" "b.b.out_a_B_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.out_a_B_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.out_a_B_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.out_a_B_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.req_bufarray.supply.vss"
= "b.b.supply.vdd" "b.b.req_bufarray.supply.vdd"
= "b.b.supply.vss" "b.b.reset_bufarray.supply.vss"
= "b.b.supply.vdd" "b.b.reset_bufarray.supply.vdd"
= "b.b.supply.vss" "b.b.dly.supply.vss"
= "b.b.supply.vdd" "b.b.dly.supply.vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.out_a_inv.vdd"
= "b.b.supply.vdd" "b.b.en_ctl.vdd"
= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
= "b.b.supply.vdd" "b.b.input_invs[4].vdd"
= "b.b.supply.vdd" "b.b.input_invs[3].vdd"
= "b.b.supply.vdd" "b.b.input_invs[2].vdd"
= "b.b.supply.vdd" "b.b.input_invs[1].vdd"
= "b.b.supply.vdd" "b.b.input_invs[0].vdd"
= "b.b.supply.vdd" "b.b.req_buf.vdd"
= "b.b.supply.vdd" "b.b.reset_buf.vdd"
= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
= "b.b.supply.vss" "b.b.out_a_inv.vss"
= "b.b.supply.vss" "b.b.en_ctl.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
= "b.b.supply.vss" "b.b.input_invs[4].vss"
= "b.b.supply.vss" "b.b.input_invs[3].vss"
= "b.b.supply.vss" "b.b.input_invs[2].vss"
= "b.b.supply.vss" "b.b.input_invs[1].vss"
= "b.b.supply.vss" "b.b.input_invs[0].vss"
= "b.b.supply.vss" "b.b.req_buf.vss"
= "b.b.supply.vss" "b.b.reset_buf.vss"
~"b.b.en_ctl.p1"&~"b.b.en_ctl.c1"->"b.b.en_ctl.y"+
"b.b.en_ctl.c1"->"b.b.en_ctl.y"-
"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
~("b.b.out_a_B_buf_f.buf2._y")->"b.b.out_a_B_buf_f.buf2.y"+
= "b.b.out_a_B_buf_f.supply.vdd" "b.b.out_a_B_buf_f.buf2.vdd"
= "b.b.out_a_B_buf_f.supply.vss" "b.b.out_a_B_buf_f.buf2.vss"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[4]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[3]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[2]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[1]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.buf2.y"
= "b.b.out_a_B_buf_f.in" "b.b.out_a_B_buf_f.buf2.a"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.a" "b.b.out_a_inv.a"
= "b.b.out.v" "b.b.en_ctl.p1"
= "b.b.out.v" "b.b.inack_ctl.c3"
= "b.b.out.d.d[4].d[0]" "b.b.f_buf_func[4].y"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.t_buf_func[4].y"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.f_buf_func[3].y"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.t_buf_func[3].y"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.f_buf_func[2].y"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.t_buf_func[2].y"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.f_buf_func[1].y"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.t_buf_func[1].y"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.f_buf_func[0].y"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.t_buf_func[0].y"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b._reqXX[0]" "b.b.req_bufarray.out[0]"
= "b.b._reqXX[1]" "b.b.req_bufarray.out[1]"
= "b.b._reqXX[2]" "b.b.req_bufarray.out[2]"
= "b.b._reqXX[3]" "b.b.req_bufarray.out[3]"
= "b.b._reqXX[4]" "b.b.req_bufarray.out[4]"
= "b.b._reqXX[0]" "b.b.t_buf_func[4].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[4].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[3].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[3].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[2].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[2].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[1].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[1].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[0].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[0].n2"
= "b.b._reqXX[0]" "b.b._reqXX[4]"
= "b.b._reqXX[0]" "b.b._reqXX[3]"
= "b.b._reqXX[0]" "b.b._reqXX[2]"
= "b.b._reqXX[0]" "b.b._reqXX[1]"
= "b.b._req" "b.b.req_buf.a"
= "b.b._req" "b.b.dly.out"
"b.b.req_bufarray.buf2.a"->"b.b.req_bufarray.buf2._y"-
~("b.b.req_bufarray.buf2.a")->"b.b.req_bufarray.buf2._y"+
"b.b.req_bufarray.buf2._y"->"b.b.req_bufarray.buf2.y"-
~("b.b.req_bufarray.buf2._y")->"b.b.req_bufarray.buf2.y"+
= "b.b.req_bufarray.supply.vdd" "b.b.req_bufarray.buf2.vdd"
= "b.b.req_bufarray.supply.vss" "b.b.req_bufarray.buf2.vss"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[4]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[3]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[2]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[1]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.buf2.y"
= "b.b.req_bufarray.in" "b.b.req_bufarray.buf2.a"
= "b.b._reqX" "b.b.inack_ctl.c2"
= "b.b._reqX" "b.b.req_bufarray.in"
= "b.b._reqX" "b.b.req_buf.y"
= "b.b._out_a_B" "b.b.out_a_B_buf_t.in"
= "b.b._out_a_B" "b.b.out_a_B_buf_f.in"
= "b.b._out_a_B" "b.b.out_a_inv.y"
"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
"b.b.req_buf.a"->"b.b.req_buf._y"-
~("b.b.req_buf.a")->"b.b.req_buf._y"+
"b.b.req_buf._y"->"b.b.req_buf.y"-
~("b.b.req_buf._y")->"b.b.req_buf.y"+
= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
= "b.b._en_X_t[0]" "b.b.t_buf_func[4].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[3].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[2].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[1].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[0].c1"
= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
~"b.b.f_buf_func[0].c1"&~"b.b.f_buf_func[0].c2"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].c2"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
~"b.b.f_buf_func[1].c1"&~"b.b.f_buf_func[1].c2"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].c2"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
~"b.b.f_buf_func[2].c1"&~"b.b.f_buf_func[2].c2"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].c2"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
~"b.b.f_buf_func[3].c1"&~"b.b.f_buf_func[3].c2"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].c2"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
~"b.b.f_buf_func[4].c1"&~"b.b.f_buf_func[4].c2"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].c2"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].c2"|~"b.b.t_buf_func[0].pr_B"->"b.b.t_buf_func[0]._y"+
"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].c2"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"&"b.b.t_buf_func[0].sr_B"->"b.b.t_buf_func[0]._y"-
"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].c2"|~"b.b.t_buf_func[1].pr_B"->"b.b.t_buf_func[1]._y"+
"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].c2"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"&"b.b.t_buf_func[1].sr_B"->"b.b.t_buf_func[1]._y"-
"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].c2"|~"b.b.t_buf_func[2].pr_B"->"b.b.t_buf_func[2]._y"+
"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].c2"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"&"b.b.t_buf_func[2].sr_B"->"b.b.t_buf_func[2]._y"-
"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].c2"|~"b.b.t_buf_func[3].pr_B"->"b.b.t_buf_func[3]._y"+
"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].c2"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"&"b.b.t_buf_func[3].sr_B"->"b.b.t_buf_func[3]._y"-
"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].c2"|~"b.b.t_buf_func[4].pr_B"->"b.b.t_buf_func[4]._y"+
"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].c2"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"&"b.b.t_buf_func[4].sr_B"->"b.b.t_buf_func[4]._y"-
"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
= "Vdd" "b.b.supply.vdd"
= "GND" "b.b.supply.vss"
= "b._reset_B" "b.b.reset_B"
= "b.dly_cfg[0]" "b.b.dly_cfg[0]"
= "b.dly_cfg[1]" "b.b.dly_cfg[1]"
= "b.dly_cfg[2]" "b.b.dly_cfg[2]"
= "b.dly_cfg[3]" "b.b.dly_cfg[3]"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.v" "b.b.out.v"
= "b.out.a" "b.b.out.a"
= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
timing("b.in.a"-,"b.in.d[0]","b.in.r"+)
timing("b.in.a"-,"b.in.d[1]","b.in.r"+)
timing("b.in.a"-,"b.in.d[2]","b.in.r"+)
timing("b.in.a"-,"b.in.d[3]","b.in.r"+)
timing("b.in.a"-,"b.in.d[4]","b.in.r"+)
= "b.in.a" "b.b.in.a"
= "b.in.r" "b.b.in.r"
= "b.in.d[0]" "b.b.in.d[0]"
= "b.in.d[1]" "b.b.in.d[1]"
= "b.in.d[2]" "b.b.in.d[2]"
= "b.in.d[3]" "b.b.in.d[3]"
= "b.in.d[4]" "b.b.in.d[4]"
test/unit_tests/bd2qdi_5/test.act
-45
View File
@@ -1,45 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/interfaces.act";
import globals;
open tmpl::dataflow_neuro;
defproc bd2qdi_5(bd<5> in; avMx1of2<5> out; bool? dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
bd2qdi<5,4> b(.in = in, .out = out, .reset_B = _reset_B, .dly_cfg = dly_cfg);
b.supply.vdd = Vdd;
b.supply.vss = GND;
}
bd2qdi_5 b;
test/unit_tests/bd2qdi_5/test.prsim
-137
View File
@@ -1,137 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set b.in.r 0
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
set b.in.d[0] 1
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 1
set b.in.d[4] 0
set Reset 0
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Reset finished, setting data'"
set b.in.d[0] 0
set b.in.d[1] 1
set b.in.d[2] 1
set b.in.d[3] 0
set b.in.d[4] 1
cycle
system "echo '[] Reset finished, setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 22
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Again!!! setting data'"
set b.in.d[0] 0
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 0
set b.in.d[4] 0
cycle
system "echo '[] Again!!! setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 0
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
test/unit_tests/buf_15.v
-685
View File
@@ -1,685 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire sr_B;
wire pr_B;
wire c3;
wire c1;
reg _y;
reg y;
wire c2;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg _y;
wire a;
reg y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
reg y;
reg _y;
wire c2;
wire c1;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
reg _y;
reg y;
wire c3;
wire c1;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
reg y;
wire a;
reg _y;
wire b;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
reg y;
wire c1;
wire p1;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire pr_B;
wire c2;
wire n1;
wire c1;
reg _y;
wire sr_B;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule
test/unit_tests/buf_15_friendly2.v
-571
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@@ -1,571 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] , vdd, vss);
input vdd;
input vss;
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
BUF_X6 \buf6 (.y(\out[0] ), .a(in), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
//
// Verilog module for: BUF_X4<>
//
//
// Verilog module for: INV_X1<>
//
//
// Verilog module for: A_2C_B_X1<>
//
//
// Verilog module for: A_3C_B_X1<>
//
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out, vdd, vss);
input vdd;
input vss;
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
A_2C_B_X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: OR2_X1<>
//
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out, vdd, vss);
input vdd;
input vss;
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
//
// Verilog module for: BUF_X1<>
//
//
// Verilog module for: A_2C1N_RB_X4<>
//
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B, vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
BUF_X4 \in_v_buf (.y(\in.v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 \out_a_inv (.y(_out_a_B), .a(\out.a ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ), .vdd(vdd), .vss(vss));
A_1C1P_X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ), .vdd(vdd), .vss(vss));
BUF_X1 \reset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
endmodule
test/unit_tests/buf_s_5/run/prsim.out
+34 -34
View File
@@ -1,4 +1,4 @@
b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[0].y b.b.vc.OR2_tf[1]._y b.b.vc.OR2_tf[1].y b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.vc.OR2_tf[4].y b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.myctree.tmp[5] b.b.vc.OR2_tf[3].y b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.myctree.C3Els[0]._y b.b.vc.OR2_tf[2]._y b.b.vc.myctree.tmp[6] b.b.en_buf_f.buf2._y b.b._in_v b.b.vc.myctree.C2Els[0]._y b.b.en_buf_t.buf2._y b.b._en b.b.vc.OR2_tf[4]._y b.out.a b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.out_a_B_buf_f.buf2._y b.b.vc.myctree.C2Els[1]._y b.b.vc.OR2_tf[3]._y
b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.vc.tmp[0] b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.tmp[2] b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.OR2_tf[2]._y b.b.en_buf_f.buf2._y b.b.vc.tmp[5] b.b.en_buf_t.buf2._y b.b._en b.b.vc.tmp[4] b.b.vc.C3Els[0]._y b.b.vc.OR2_tf[4]._y b.out.a b.b._in_v b.b.vc.tmp[6] b.b.vc.tmp[3] b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.vc.C2Els[0]._y b.b.out_a_B_buf_f.buf2._y b.b.vc.OR2_tf[3]._y
84120 b.b.f_buf_func[0].n1 : 0
84120 b.b.f_buf_func[4].y : 1
84120 b.b.t_buf_func[4].y : 1
@@ -25,7 +25,7 @@ b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1
84121 b.b.f_buf_func[2].y : 0
84121 b.b._en : 1 [by b.out.v:=0]
84123 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
84141 b.b.vc.OR2_tf[1].y : 0 [by b.b.vc.OR2_tf[1]._y:=1]
84141 b.b.vc.tmp[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
84402 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
84542 b.b.t_buf_func[0].y : 0
84671 b.b.t_buf_func[2].y : 0
@@ -34,16 +34,16 @@ b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1
85103 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
85191 b.b.vc.OR2_tf[3]._y : 1 [by b.b.t_buf_func[3].n1:=0]
85201 b.b.t_buf_func[1].y : 0
88415 b.b.vc.OR2_tf[2].y : 0 [by b.b.vc.OR2_tf[2]._y:=1]
88415 b.b.vc.tmp[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
88891 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
89393 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
89951 b.b.vc.OR2_tf[3].y : 0 [by b.b.vc.OR2_tf[3]._y:=1]
89951 b.b.vc.tmp[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
97969 b.b.f_buf_func[3].y : 0
98463 b.b.f_buf_func[0].y : 0
104325 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
104528 b.b.vc.OR2_tf[0].y : 0 [by b.b.vc.OR2_tf[0]._y:=1]
106382 b.b.vc.myctree.C2Els[0]._y : 1 [by b.b.vc.OR2_tf[0].y:=0]
106521 b.b.vc.myctree.tmp[5] : 0 [by b.b.vc.myctree.C2Els[0]._y:=1]
104528 b.b.vc.tmp[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
106382 b.b.vc.C2Els[0]._y : 1 [by b.b.vc.tmp[0]:=0]
106521 b.b.vc.tmp[5] : 0 [by b.b.vc.C2Els[0]._y:=1]
106561 b.b.vc.OR2_tf[4]._y : 1 [by b.b.f_buf_func[4].n1:=0]
106687 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
108932 b.b.t_buf_func[3].y : 0
@@ -55,11 +55,11 @@ b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1
135773 b.b.f_buf_func[4].y : 0
138591 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
138795 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
142907 b.b.vc.OR2_tf[4].y : 0 [by b.b.vc.OR2_tf[4]._y:=1]
142922 b.b.vc.myctree.C3Els[0]._y : 1 [by b.b.vc.OR2_tf[4].y:=0]
142923 b.b.vc.myctree.tmp[6] : 0 [by b.b.vc.myctree.C3Els[0]._y:=1]
142960 b.b.vc.myctree.C2Els[1]._y : 1 [by b.b.vc.myctree.tmp[6]:=0]
143699 b.b._in_v : 0 [by b.b.vc.myctree.C2Els[1]._y:=1]
142907 b.b.vc.tmp[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
142922 b.b.vc.C3Els[0]._y : 1 [by b.b.vc.tmp[4]:=0]
142923 b.b.vc.tmp[6] : 0 [by b.b.vc.C3Els[0]._y:=1]
142960 b.b.vc.C2Els[1]._y : 1 [by b.b.vc.tmp[6]:=0]
143699 b.b._in_v : 0 [by b.b.vc.C2Els[1]._y:=1]
143811 b.b.in_v_buf4._y : 1 [by b.b._in_v:=0]
184631 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
184671 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
@@ -88,23 +88,23 @@ b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1
200679 b.b.f_buf_func[2].n1 : 1
200679 b.b.t_buf_func[1].n1 : 1
200812 b.b.vc.OR2_tf[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
201171 b.b.vc.OR2_tf[2].y : 1 [by b.b.vc.OR2_tf[2]._y:=0]
201171 b.b.vc.tmp[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
201526 b.b.vc.OR2_tf[0]._y : 0 [by b.b.t_buf_func[0].n1:=1]
215642 b.b.vc.OR2_tf[0].y : 1 [by b.b.vc.OR2_tf[0]._y:=0]
215642 b.b.vc.tmp[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
216341 b.b.vc.OR2_tf[1]._y : 0 [by b.b.t_buf_func[1].n1:=1]
216562 b.b.vc.OR2_tf[1].y : 1 [by b.b.vc.OR2_tf[1]._y:=0]
216569 b.b.vc.myctree.C2Els[0]._y : 0 [by b.b.vc.OR2_tf[1].y:=1]
216599 b.b.vc.myctree.tmp[5] : 1 [by b.b.vc.myctree.C2Els[0]._y:=0]
216562 b.b.vc.tmp[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
216569 b.b.vc.C2Els[0]._y : 0 [by b.b.vc.tmp[1]:=1]
216599 b.b.vc.tmp[5] : 1 [by b.b.vc.C2Els[0]._y:=0]
230807 b.b.vc.OR2_tf[3]._y : 0 [by b.b.f_buf_func[3].n1:=1]
237520 b.b.vc.OR2_tf[3].y : 1 [by b.b.vc.OR2_tf[3]._y:=0]
237520 b.b.vc.tmp[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
[] Setting final input
237520 b.b.t_buf_func[4].n1 : 1
294981 b.b.vc.OR2_tf[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
295072 b.b.vc.OR2_tf[4].y : 1 [by b.b.vc.OR2_tf[4]._y:=0]
297261 b.b.vc.myctree.C3Els[0]._y : 0 [by b.b.vc.OR2_tf[4].y:=1]
297268 b.b.vc.myctree.tmp[6] : 1 [by b.b.vc.myctree.C3Els[0]._y:=0]
300055 b.b.vc.myctree.C2Els[1]._y : 0 [by b.b.vc.myctree.tmp[6]:=1]
300161 b.b._in_v : 1 [by b.b.vc.myctree.C2Els[1]._y:=0]
295072 b.b.vc.tmp[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
297261 b.b.vc.C3Els[0]._y : 0 [by b.b.vc.tmp[4]:=1]
297268 b.b.vc.tmp[6] : 1 [by b.b.vc.C3Els[0]._y:=0]
300055 b.b.vc.C2Els[1]._y : 0 [by b.b.vc.tmp[6]:=1]
300161 b.b._in_v : 1 [by b.b.vc.C2Els[1]._y:=0]
300239 b.b.in_v_buf4._y : 0 [by b.b._in_v:=1]
300514 b.in.v : 1 [by b.b.in_v_buf4._y:=0]
319510 b.b.in_v_bufN.buf2._y : 0 [by b.in.v:=1]
@@ -136,20 +136,20 @@ b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1
337917 b.b.f_buf_func[3].n1 : 0
337918 b.b.vc.OR2_tf[4]._y : 1 [by b.b.t_buf_func[4].n1:=0]
337928 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
337985 b.b.vc.OR2_tf[4].y : 0 [by b.b.vc.OR2_tf[4]._y:=1]
337985 b.b.vc.tmp[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
338287 b.b.vc.OR2_tf[3]._y : 1 [by b.b.f_buf_func[3].n1:=0]
338303 b.b.vc.OR2_tf[3].y : 0 [by b.b.vc.OR2_tf[3]._y:=1]
338303 b.b.vc.tmp[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
338465 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
340569 b.b.vc.OR2_tf[1].y : 0 [by b.b.vc.OR2_tf[1]._y:=1]
343027 b.b.vc.OR2_tf[2].y : 0 [by b.b.vc.OR2_tf[2]._y:=1]
343555 b.b.vc.myctree.C3Els[0]._y : 1 [by b.b.vc.OR2_tf[2].y:=0]
345990 b.b.vc.myctree.tmp[6] : 0 [by b.b.vc.myctree.C3Els[0]._y:=1]
340569 b.b.vc.tmp[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
343027 b.b.vc.tmp[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
343555 b.b.vc.C3Els[0]._y : 1 [by b.b.vc.tmp[2]:=0]
345990 b.b.vc.tmp[6] : 0 [by b.b.vc.C3Els[0]._y:=1]
381834 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
408714 b.b.vc.OR2_tf[0].y : 0 [by b.b.vc.OR2_tf[0]._y:=1]
432639 b.b.vc.myctree.C2Els[0]._y : 1 [by b.b.vc.OR2_tf[0].y:=0]
445680 b.b.vc.myctree.tmp[5] : 0 [by b.b.vc.myctree.C2Els[0]._y:=1]
445682 b.b.vc.myctree.C2Els[1]._y : 1 [by b.b.vc.myctree.tmp[5]:=0]
506640 b.b._in_v : 0 [by b.b.vc.myctree.C2Els[1]._y:=1]
408714 b.b.vc.tmp[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
432639 b.b.vc.C2Els[0]._y : 1 [by b.b.vc.tmp[0]:=0]
445680 b.b.vc.tmp[5] : 0 [by b.b.vc.C2Els[0]._y:=1]
445682 b.b.vc.C2Els[1]._y : 1 [by b.b.vc.tmp[5]:=0]
506640 b.b._in_v : 0 [by b.b.vc.C2Els[1]._y:=1]
506643 b.b.in_v_buf4._y : 1 [by b.b._in_v:=0]
506672 b.in.v : 0 [by b.b.in_v_buf4._y:=1]
506989 b.b.in_v_bufN.buf2._y : 1 [by b.in.v:=0]
test/unit_tests/buf_s_5/run/prsim.pdf
BIN
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test/unit_tests/buf_s_5/run/test.prs
+34 -42
View File
@@ -101,40 +101,18 @@
= "b.b.supply.vss" "b.b.reset_buf.vss"
= "b.b.supply.vss" "b.b.en_ctl.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
~"b.b.vc.myctree.C2Els[0].c1"&~"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"+
"b.b.vc.myctree.C2Els[0].c1"&"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"-
"b.b.vc.myctree.C2Els[0]._y"->"b.b.vc.myctree.C2Els[0].y"-
~("b.b.vc.myctree.C2Els[0]._y")->"b.b.vc.myctree.C2Els[0].y"+
~"b.b.vc.myctree.C2Els[1].c1"&~"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"+
"b.b.vc.myctree.C2Els[1].c1"&"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"-
"b.b.vc.myctree.C2Els[1]._y"->"b.b.vc.myctree.C2Els[1].y"-
~("b.b.vc.myctree.C2Els[1]._y")->"b.b.vc.myctree.C2Els[1].y"+
~"b.b.vc.myctree.C3Els[0].c1"&~"b.b.vc.myctree.C3Els[0].c2"&~"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"+
"b.b.vc.myctree.C3Els[0].c1"&"b.b.vc.myctree.C3Els[0].c2"&"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"-
"b.b.vc.myctree.C3Els[0]._y"->"b.b.vc.myctree.C3Els[0].y"-
~("b.b.vc.myctree.C3Els[0]._y")->"b.b.vc.myctree.C3Els[0].y"+
= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[1].c1"
= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[0].y"
= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C2Els[1].c2"
= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C3Els[0].y"
= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C3Els[0].vdd"
= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[1].vdd"
= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[0].vdd"
= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C3Els[0].vss"
= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[1].vss"
= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[0].vss"
= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.C2Els[0].c1"
= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.tmp[0]"
= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.C2Els[0].c2"
= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.tmp[1]"
= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.C3Els[0].c1"
= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.tmp[2]"
= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.C3Els[0].c2"
= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.tmp[3]"
= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.C3Els[0].c3"
= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.tmp[4]"
= "b.b.vc.myctree.out" "b.b.vc.myctree.C2Els[1].y"
= "b.b.vc.myctree.out" "b.b.vc.myctree.tmp[7]"
~"b.b.vc.C2Els[0].c1"&~"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"+
"b.b.vc.C2Els[0].c1"&"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"-
"b.b.vc.C2Els[0]._y"->"b.b.vc.C2Els[0].y"-
~("b.b.vc.C2Els[0]._y")->"b.b.vc.C2Els[0].y"+
~"b.b.vc.C2Els[1].c1"&~"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"+
"b.b.vc.C2Els[1].c1"&"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"-
"b.b.vc.C2Els[1]._y"->"b.b.vc.C2Els[1].y"-
~("b.b.vc.C2Els[1]._y")->"b.b.vc.C2Els[1].y"+
~"b.b.vc.C3Els[0].c1"&~"b.b.vc.C3Els[0].c2"&~"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"+
"b.b.vc.C3Els[0].c1"&"b.b.vc.C3Els[0].c2"&"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"-
"b.b.vc.C3Els[0]._y"->"b.b.vc.C3Els[0].y"-
~("b.b.vc.C3Els[0]._y")->"b.b.vc.C3Els[0].y"+
"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
@@ -155,24 +133,36 @@
~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
= "b.b.vc.OR2_tf[4].y" "b.b.vc.myctree.in[4]"
= "b.b.vc.OR2_tf[3].y" "b.b.vc.myctree.in[3]"
= "b.b.vc.OR2_tf[2].y" "b.b.vc.myctree.in[2]"
= "b.b.vc.OR2_tf[1].y" "b.b.vc.myctree.in[1]"
= "b.b.vc.OR2_tf[0].y" "b.b.vc.myctree.in[0]"
= "b.b.vc.supply.vss" "b.b.vc.myctree.supply.vss"
= "b.b.vc.supply.vdd" "b.b.vc.myctree.supply.vdd"
= "b.b.vc.tmp[0]" "b.b.vc.C2Els[0].c1"
= "b.b.vc.tmp[0]" "b.b.vc.OR2_tf[0].y"
= "b.b.vc.tmp[1]" "b.b.vc.C2Els[0].c2"
= "b.b.vc.tmp[1]" "b.b.vc.OR2_tf[1].y"
= "b.b.vc.tmp[2]" "b.b.vc.C3Els[0].c1"
= "b.b.vc.tmp[2]" "b.b.vc.OR2_tf[2].y"
= "b.b.vc.tmp[3]" "b.b.vc.C3Els[0].c2"
= "b.b.vc.tmp[3]" "b.b.vc.OR2_tf[3].y"
= "b.b.vc.tmp[4]" "b.b.vc.C3Els[0].c3"
= "b.b.vc.tmp[4]" "b.b.vc.OR2_tf[4].y"
= "b.b.vc.tmp[5]" "b.b.vc.C2Els[1].c1"
= "b.b.vc.tmp[5]" "b.b.vc.C2Els[0].y"
= "b.b.vc.tmp[6]" "b.b.vc.C2Els[1].c2"
= "b.b.vc.tmp[6]" "b.b.vc.C3Els[0].y"
= "b.b.vc.supply.vdd" "b.b.vc.C3Els[0].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.C2Els[1].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.C2Els[0].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
= "b.b.vc.supply.vss" "b.b.vc.C3Els[0].vss"
= "b.b.vc.supply.vss" "b.b.vc.C2Els[1].vss"
= "b.b.vc.supply.vss" "b.b.vc.C2Els[0].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
= "b.b.vc.out" "b.b.vc.myctree.out"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
@@ -213,6 +203,8 @@
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.out" "b.b.vc.C2Els[1].y"
= "b.b.vc.out" "b.b.vc.tmp[7]"
"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
test/unit_tests/buff.v
-685
View File
@@ -1,685 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
wire a;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
reg \out[0] ;
wire in;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire pr_B;
wire c3;
wire c1;
wire sr_B;
wire c2;
reg _y;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
wire c2;
wire c1;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
wire c1;
reg y;
reg _y;
wire c3;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[9] ;
wire \in[11] ;
reg \tmp[18] ;
reg \tmp[16] ;
reg \tmp[24] ;
wire \in[0] ;
reg \tmp[22] ;
reg out;
wire \in[7] ;
reg \tmp[23] ;
wire \in[4] ;
wire \in[3] ;
wire \in[12] ;
reg \tmp[20] ;
wire \in[2] ;
reg \tmp[19] ;
wire \in[14] ;
wire \in[6] ;
wire \in[10] ;
wire \in[5] ;
wire \in[8] ;
wire \in[13] ;
wire \in[1] ;
reg \tmp[21] ;
reg \tmp[17] ;
reg \tmp[15] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
wire a;
wire b;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
wire \in.d[2].d[1] ;
wire \in.d[14].d[1] ;
reg \ct.in[8] ;
wire \in.d[10].d[1] ;
wire \in.d[7].d[1] ;
reg \ct.in[14] ;
wire \in.d[3].d[0] ;
reg \ct.in[0] ;
wire \in.d[8].d[1] ;
wire \in.d[6].d[1] ;
reg out;
wire \in.d[14].d[0] ;
wire \in.d[6].d[0] ;
wire \in.d[10].d[0] ;
wire \in.d[5].d[1] ;
wire \in.d[7].d[0] ;
wire \in.d[3].d[1] ;
wire \in.d[2].d[0] ;
reg \ct.in[6] ;
reg \ct.in[4] ;
wire \in.d[5].d[0] ;
wire \in.d[1].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[5] ;
reg \ct.in[1] ;
wire \in.d[9].d[0] ;
wire \in.d[0].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[12] ;
wire \in.d[12].d[1] ;
wire \in.d[8].d[0] ;
reg \ct.in[2] ;
wire \in.d[13].d[0] ;
wire \in.d[4].d[0] ;
wire \in.d[12].d[0] ;
wire \in.d[11].d[0] ;
wire \in.d[13].d[1] ;
reg \ct.in[9] ;
reg \ct.in[3] ;
reg \ct.in[11] ;
wire \in.d[1].d[0] ;
reg \ct.in[7] ;
wire \in.d[11].d[1] ;
wire \in.d[9].d[1] ;
reg \ct.in[10] ;
reg \ct.in[13] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
wire c1;
wire p1;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire n1;
wire sr_B;
wire pr_B;
wire c2;
wire c1;
reg _y;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
wire \in.d.d[9].d[0] ;
reg _out_a_B;
reg \out.d.d[1].d[0] ;
wire \in.d.d[4].d[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[5].d[0] ;
wire \out.v ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[1].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
reg _reset_BX;
reg \in.v ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[10].d[1] ;
reg \out.d.d[9].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[5].d[1] ;
reg _en;
reg \_out_a_BX_f[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[13].d[1] ;
reg \out.d.d[11].d[0] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[1].d[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[4].d[1] ;
reg _in_v;
reg \out.d.d[13].d[0] ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[2].d[1] ;
reg \in.a ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[10].d[0] ;
wire \out.a ;
reg \out.d.d[12].d[1] ;
wire reset_B;
wire \in.d.d[7].d[1] ;
wire \in.d.d[6].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
reg \_reset_BXX[0] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[13].d[1] ;
reg \_en_X_f[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[8].d[1] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[1].d[0] ;
reg _reset_B;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[2].d[1] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[5].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[10].d[0] ;
wire \in.d.d[3].d[1] ;
wire \in.d.d[11].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[2].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[4].d[1] ;
wire \in.d.d[1].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[1].d[1] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[0].d[1] ;
wire \out.v ;
wire \in.d.d[12].d[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[7].d[1] ;
wire \out.a ;
reg \in.a ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[12].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[1] ;
reg \in.v ;
wire \in.d.d[14].d[0] ;
reg \out.d.d[13].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[0].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule
test/unit_tests/buffer_register_7/run/prsim.out
-417
View File
@@ -1,417 +0,0 @@
b.b.f_buf_func[3].n1 b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.f_buf_func[5].n1 b.b.vc.ct.in[6] b.in.v b.b._flushB b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b.f_buf_func[6].n1 b.b.vc.OR2_tf[6]._y b.b.vc.ct.in[1] b.out_v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b.vc.ct.C3Els[1]._y b.b.t_buf_func[2].n1 b.b.t_buf_func[6].n1 b.b.vc.OR2_tf[0]._y b.b.vc.ct.in[3] b.b.t_buf_func[0].n1 b.flush b.b._in_v b.b.vc.ct.in[4] b.b.f_buf_func[4].n1 b.b.vc.ct.in[5] b.b.vc.OR2_tf[2]._y b.b.vc.ct.tmp[8] b.b.vc.ct.tmp[9] b.b.vc.ct.C2Els[0]._y b.b.t_buf_func[5].n1 b.b.vc.OR2_tf[4]._y b.b.vc.ct.in[2] b.b.vc.ct.tmp[7] b.b.vc.OR2_tf[5]._y b.b.vc.ct.in[0] b.b.vc.OR2_tf[3]._y b.b.in_v_buf._y b.b.vc.ct.C3Els[0]._y b.b.vc.ct.C2Els[1]._y
74426 b.out_v : 0
74426 b.b.t_buf_func[6].n1 : 0
74426 b.b.f_buf_func[6].n1 : 0
74426 b.b.t_buf_func[5].n1 : 0
74426 b.b.f_buf_func[0].n1 : 0
74426 b.b.f_buf_func[5].n1 : 0
74426 b.b.t_buf_func[4].n1 : 0
74426 b.b.f_buf_func[2].n1 : 0
74426 b.b.f_buf_func[4].n1 : 0
74426 b.b.t_buf_func[3].n1 : 0
74426 b.b.t_buf_func[1].n1 : 0
74426 b.b.f_buf_func[3].n1 : 0
74426 b.b.t_buf_func[2].n1 : 0
74426 b.flush : 0
74426 b.b.f_buf_func[1].n1 : 0
74426 b.b.t_buf_func[0].n1 : 0
74444 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
74977 b.b.vc.OR2_tf[5]._y : 1 [by b.b.f_buf_func[5].n1:=0]
75380 b.b.vc.OR2_tf[3]._y : 1 [by b.b.f_buf_func[3].n1:=0]
75408 b.b.vc.OR2_tf[1]._y : 1 [by b.b.f_buf_func[1].n1:=0]
75497 b.b.vc.OR2_tf[4]._y : 1 [by b.b.f_buf_func[4].n1:=0]
75507 b.b.vc.OR2_tf[2]._y : 1 [by b.b.t_buf_func[2].n1:=0]
76009 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
78457 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
78980 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
80257 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
96867 b.b.vc.OR2_tf[6]._y : 1 [by b.b.f_buf_func[6].n1:=0]
96992 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
97070 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
97209 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[6]:=0]
98846 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[1]:=0]
98915 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
120281 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
120292 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[3]:=0]
128896 b.b._flushB : 1 [by b.flush:=0]
133555 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
172078 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
172282 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[8]:=0]
172297 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
172298 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
172335 b.in.v : 0 [by b.b.in_v_buf._y:=1]
[] Set reset 0
172335 Reset : 0
173074 b._reset_B : 1 [by Reset:=0]
173186 b.b.reset_buf._y : 0 [by b._reset_B:=1]
173226 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
173483 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
173570 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
220586 b.b._reset : 0 [by b._reset_B:=1]
[] Flushing data
220586 b.flush : 1
220880 b.b._flushB : 0 [by b.flush:=1]
220881 b.b.t_buf_func[0]._y : 1 [by b.b._flushB:=0]
221045 b.out.d[0].t : 0 [by b.b.t_buf_func[0]._y:=1]
221058 b.b.t_buf_func[5]._y : 1 [by b.b._flushB:=0]
221470 b.b.t_buf_func[4]._y : 1 [by b.b._flushB:=0]
221492 b.out.d[4].t : 0 [by b.b.t_buf_func[4]._y:=1]
221683 b.b.t_buf_func[6]._y : 1 [by b.b._flushB:=0]
222089 b.b.t_buf_func[3]._y : 1 [by b.b._flushB:=0]
222530 b.out.d[6].t : 0 [by b.b.t_buf_func[6]._y:=1]
222686 b.b.t_buf_func[1]._y : 1 [by b.b._flushB:=0]
222819 b.out.d[1].t : 0 [by b.b.t_buf_func[1]._y:=1]
222887 b.b.t_buf_func[2]._y : 1 [by b.b._flushB:=0]
223253 b.out.d[5].t : 0 [by b.b.t_buf_func[5]._y:=1]
238549 b.out.d[2].t : 0 [by b.b.t_buf_func[2]._y:=1]
252217 b.out.d[3].t : 0 [by b.b.t_buf_func[3]._y:=1]
252217 b.flush : 0
252576 b.b._flushB : 1 [by b.flush:=0]
[] Sending in a 0
252576 b.b.f_buf_func[0].n1 : 1
252576 b.b.f_buf_func[6].n1 : 1
252576 b.b.f_buf_func[2].n1 : 1
252576 b.b.f_buf_func[5].n1 : 1
252576 b.b.f_buf_func[1].n1 : 1
252576 b.b.f_buf_func[4].n1 : 1
252576 b.b.f_buf_func[3].n1 : 1
252583 b.b.vc.OR2_tf[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
252583 b.b.vc.OR2_tf[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
252595 b.b.vc.ct.in[6] : 1 [by b.b.vc.OR2_tf[6]._y:=0]
252606 b.b.f_buf_func[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
252654 b.b.f_buf_func[4]._y : 0 [by b.b.f_buf_func[4].n1:=1]
252666 b.out.d[4].f : 1 [by b.b.f_buf_func[4]._y:=0]
252667 b.b.vc.OR2_tf[5]._y : 0 [by b.b.f_buf_func[5].n1:=1]
252682 b.b.vc.OR2_tf[4]._y : 0 [by b.b.f_buf_func[4].n1:=1]
252797 b.b.f_buf_func[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
252851 b.b.vc.OR2_tf[3]._y : 0 [by b.b.f_buf_func[3].n1:=1]
253010 b.out.d[6].f : 1 [by b.b.f_buf_func[6]._y:=0]
253038 b.b.vc.ct.in[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
254765 b.b.f_buf_func[5]._y : 0 [by b.b.f_buf_func[5].n1:=1]
254767 b.out.d[5].f : 1 [by b.b.f_buf_func[5]._y:=0]
255363 b.b.f_buf_func[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
255696 b.out.d[0].f : 1 [by b.b.f_buf_func[0]._y:=0]
256958 b.b.vc.ct.in[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
257146 b.b.vc.ct.in[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
258583 b.b.vc.ct.in[5] : 1 [by b.b.vc.OR2_tf[5]._y:=0]
259289 b.b.vc.OR2_tf[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
259832 b.b.vc.ct.C3Els[0]._y : 0 [by b.b.vc.ct.in[5]:=1]
259898 b.out.d[1].f : 1 [by b.b.f_buf_func[1]._y:=0]
259998 b.b.vc.ct.tmp[9] : 1 [by b.b.vc.ct.C3Els[0]._y:=0]
262788 b.b.vc.ct.in[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
262863 b.b.vc.ct.C2Els[1]._y : 0 [by b.b.vc.ct.in[2]:=1]
263208 b.b.vc.ct.tmp[8] : 1 [by b.b.vc.ct.C2Els[1]._y:=0]
266692 b.b.vc.OR2_tf[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
266830 b.b.vc.ct.in[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
271572 b.b.f_buf_func[3]._y : 0 [by b.b.f_buf_func[3].n1:=1]
271574 b.out.d[3].f : 1 [by b.b.f_buf_func[3]._y:=0]
272093 b.b.vc.ct.C2Els[0]._y : 0 [by b.b.vc.ct.in[0]:=1]
310037 b.b.f_buf_func[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
310038 b.out.d[2].f : 1 [by b.b.f_buf_func[2]._y:=0]
316010 b.b.vc.ct.tmp[7] : 1 [by b.b.vc.ct.C2Els[0]._y:=0]
316558 b.b.vc.ct.C3Els[1]._y : 0 [by b.b.vc.ct.tmp[7]:=1]
316569 b.b._in_v : 1 [by b.b.vc.ct.C3Els[1]._y:=0]
316939 b.b.in_v_buf._y : 0 [by b.b._in_v:=1]
317006 b.in.v : 1 [by b.b.in_v_buf._y:=0]
[] Sending in output valid
317006 b.out_v : 1
319647 b.b._en : 0 [by b.out_v:=1]
319663 b.in.a : 1 [by b.b._en:=0]
320175 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
322610 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
324209 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
351089 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
[] Removing input
351089 b.b.f_buf_func[0].n1 : 0
351089 b.b.f_buf_func[6].n1 : 0
351089 b.b.f_buf_func[2].n1 : 0
351089 b.b.f_buf_func[5].n1 : 0
351089 b.b.f_buf_func[1].n1 : 0
351089 b.b.f_buf_func[4].n1 : 0
351089 b.b.f_buf_func[3].n1 : 0
351091 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
351092 b.b.vc.OR2_tf[1]._y : 1 [by b.b.f_buf_func[1].n1:=0]
351118 b.b.vc.OR2_tf[4]._y : 1 [by b.b.f_buf_func[4].n1:=0]
351162 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
351245 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
351406 b.b.vc.OR2_tf[3]._y : 1 [by b.b.f_buf_func[3].n1:=0]
352692 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
354167 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
364130 b.b.vc.OR2_tf[6]._y : 1 [by b.b.f_buf_func[6].n1:=0]
364131 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
367850 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[3]:=0]
368067 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
375014 b.b.vc.OR2_tf[0]._y : 1 [by b.b.f_buf_func[0].n1:=0]
375036 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
375037 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[0]:=0]
376618 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
412047 b.b.vc.OR2_tf[5]._y : 1 [by b.b.f_buf_func[5].n1:=0]
421392 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
421551 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[5]:=0]
441227 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
442514 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[9]:=0]
444746 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
444891 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
447723 b.in.v : 0 [by b.b.in_v_buf._y:=1]
454077 b.b._en : 1 [by b.in.v:=0]
454078 b.in.a : 0 [by b.b._en:=1]
454239 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
461608 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
493361 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
493375 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
[] Flushing data
493375 b.flush : 1
493382 b.b._flushB : 0 [by b.flush:=1]
493383 b.b.f_buf_func[2]._y : 1 [by b.b._flushB:=0]
493383 b.b.f_buf_func[3]._y : 1 [by b.b._flushB:=0]
493383 b.b.f_buf_func[4]._y : 1 [by b.b._flushB:=0]
493384 b.out.d[2].f : 0 [by b.b.f_buf_func[2]._y:=1]
493542 b.b.f_buf_func[0]._y : 1 [by b.b._flushB:=0]
493543 b.out.d[0].f : 0 [by b.b.f_buf_func[0]._y:=1]
493569 b.b.f_buf_func[6]._y : 1 [by b.b._flushB:=0]
494422 b.out.d[6].f : 0 [by b.b.f_buf_func[6]._y:=1]
495625 b.b.f_buf_func[5]._y : 1 [by b.b._flushB:=0]
495630 b.out.d[5].f : 0 [by b.b.f_buf_func[5]._y:=1]
497565 b.out.d[3].f : 0 [by b.b.f_buf_func[3]._y:=1]
514939 b.b.f_buf_func[1]._y : 1 [by b.b._flushB:=0]
515830 b.out.d[1].f : 0 [by b.b.f_buf_func[1]._y:=1]
528165 b.out.d[4].f : 0 [by b.b.f_buf_func[4]._y:=1]
528165 b.out_v : 0
528165 b.flush : 0
528166 b.b._flushB : 1 [by b.flush:=0]
[] Sending in a 127
528166 b.b.t_buf_func[0].n1 : 1
528166 b.b.t_buf_func[6].n1 : 1
528166 b.b.t_buf_func[2].n1 : 1
528166 b.b.t_buf_func[5].n1 : 1
528166 b.b.t_buf_func[1].n1 : 1
528166 b.b.t_buf_func[4].n1 : 1
528166 b.b.t_buf_func[3].n1 : 1
528167 b.b.vc.OR2_tf[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
528169 b.b.t_buf_func[6]._y : 0 [by b.b.t_buf_func[6].n1:=1]
528174 b.b.vc.OR2_tf[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
528178 b.b.vc.ct.in[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
528183 b.b.vc.OR2_tf[0]._y : 0 [by b.b.t_buf_func[0].n1:=1]
528200 b.b.t_buf_func[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
528208 b.b.t_buf_func[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
528261 b.b.vc.OR2_tf[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
528501 b.b.t_buf_func[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
528549 b.out.d[4].t : 1 [by b.b.t_buf_func[4]._y:=0]
529087 b.out.d[6].t : 1 [by b.b.t_buf_func[6]._y:=0]
529107 b.b.vc.OR2_tf[2]._y : 0 [by b.b.t_buf_func[2].n1:=1]
529110 b.b.vc.ct.in[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
529288 b.b.vc.ct.C2Els[1]._y : 0 [by b.b.vc.ct.in[2]:=1]
530598 b.out.d[3].t : 1 [by b.b.t_buf_func[3]._y:=0]
530739 b.b.t_buf_func[0]._y : 0 [by b.b.t_buf_func[0].n1:=1]
530983 b.b.vc.OR2_tf[1]._y : 0 [by b.b.t_buf_func[1].n1:=1]
531423 b.out.d[5].t : 1 [by b.b.t_buf_func[5]._y:=0]
536527 b.b.vc.OR2_tf[6]._y : 0 [by b.b.t_buf_func[6].n1:=1]
536934 b.b.vc.ct.in[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
541899 b.b.t_buf_func[1]._y : 0 [by b.b.t_buf_func[1].n1:=1]
542054 b.b.vc.ct.in[5] : 1 [by b.b.vc.OR2_tf[5]._y:=0]
542638 b.out.d[0].t : 1 [by b.b.t_buf_func[0]._y:=0]
542726 b.out.d[1].t : 1 [by b.b.t_buf_func[1]._y:=0]
550265 b.b.vc.ct.tmp[8] : 1 [by b.b.vc.ct.C2Els[1]._y:=0]
574561 b.b.vc.ct.in[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
574734 b.b.vc.ct.C2Els[0]._y : 0 [by b.b.vc.ct.in[0]:=1]
574918 b.b.vc.ct.tmp[7] : 1 [by b.b.vc.ct.C2Els[0]._y:=0]
575380 b.b.vc.ct.in[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
576012 b.b.vc.ct.in[6] : 1 [by b.b.vc.OR2_tf[6]._y:=0]
576013 b.b.vc.ct.C3Els[0]._y : 0 [by b.b.vc.ct.in[6]:=1]
576086 b.b.vc.ct.tmp[9] : 1 [by b.b.vc.ct.C3Els[0]._y:=0]
576090 b.b.vc.ct.C3Els[1]._y : 0 [by b.b.vc.ct.tmp[9]:=1]
587128 b.b.t_buf_func[2]._y : 0 [by b.b.t_buf_func[2].n1:=1]
587224 b.out.d[2].t : 1 [by b.b.t_buf_func[2]._y:=0]
613378 b.b._in_v : 1 [by b.b.vc.ct.C3Els[1]._y:=0]
613514 b.b.in_v_buf._y : 0 [by b.b._in_v:=1]
613515 b.in.v : 1 [by b.b.in_v_buf._y:=0]
[] Sending in output valid
613515 b.out_v : 1
632561 b.b._en : 0 [by b.out_v:=1]
632573 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
632802 b.in.a : 1 [by b.b._en:=0]
636473 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
636520 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
637549 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
[] Removing input
637549 b.b.t_buf_func[0].n1 : 0
637549 b.b.t_buf_func[6].n1 : 0
637549 b.b.t_buf_func[2].n1 : 0
637549 b.b.t_buf_func[5].n1 : 0
637549 b.b.t_buf_func[1].n1 : 0
637549 b.b.t_buf_func[4].n1 : 0
637549 b.b.t_buf_func[3].n1 : 0
637550 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
637550 b.b.vc.OR2_tf[3]._y : 1 [by b.b.t_buf_func[3].n1:=0]
637550 b.b.vc.OR2_tf[5]._y : 1 [by b.b.t_buf_func[5].n1:=0]
637563 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
637586 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
637605 b.b.vc.OR2_tf[6]._y : 1 [by b.b.t_buf_func[6].n1:=0]
637962 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
639242 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
641114 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
654570 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
654595 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[1]:=0]
654616 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
660924 b.b.vc.OR2_tf[4]._y : 1 [by b.b.t_buf_func[4].n1:=0]
660925 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
670573 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[4]:=0]
670574 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
682555 b.b.vc.OR2_tf[2]._y : 1 [by b.b.t_buf_func[2].n1:=0]
682556 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
682717 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[2]:=0]
683754 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
683759 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[8]:=0]
684340 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
684748 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
684759 b.in.v : 0 [by b.b.in_v_buf._y:=1]
685806 b.b._en : 1 [by b.in.v:=0]
685810 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
685820 b.in.a : 0 [by b.b._en:=1]
685824 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
685914 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
717268 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
[] Flushing data
717268 b.flush : 1
718472 b.b._flushB : 0 [by b.flush:=1]
718483 b.b.t_buf_func[6]._y : 1 [by b.b._flushB:=0]
718486 b.out.d[6].t : 0 [by b.b.t_buf_func[6]._y:=1]
718542 b.b.t_buf_func[4]._y : 1 [by b.b._flushB:=0]
718596 b.out.d[4].t : 0 [by b.b.t_buf_func[4]._y:=1]
718700 b.b.t_buf_func[1]._y : 1 [by b.b._flushB:=0]
719315 b.b.t_buf_func[2]._y : 1 [by b.b._flushB:=0]
719848 b.out.d[1].t : 0 [by b.b.t_buf_func[1]._y:=1]
719931 b.b.t_buf_func[3]._y : 1 [by b.b._flushB:=0]
720476 b.out.d[2].t : 0 [by b.b.t_buf_func[2]._y:=1]
726927 b.b.t_buf_func[0]._y : 1 [by b.b._flushB:=0]
727008 b.out.d[0].t : 0 [by b.b.t_buf_func[0]._y:=1]
728583 b.out.d[3].t : 0 [by b.b.t_buf_func[3]._y:=1]
768894 b.b.t_buf_func[5]._y : 1 [by b.b._flushB:=0]
779971 b.out.d[5].t : 0 [by b.b.t_buf_func[5]._y:=1]
779971 b.out_v : 0
779971 b.flush : 0
797954 b.b._flushB : 1 [by b.flush:=0]
[] Sending in a 56
797954 b.b.f_buf_func[0].n1 : 1
797954 b.b.f_buf_func[6].n1 : 1
797954 b.b.f_buf_func[2].n1 : 1
797954 b.b.t_buf_func[5].n1 : 1
797954 b.b.f_buf_func[1].n1 : 1
797954 b.b.t_buf_func[4].n1 : 1
797954 b.b.t_buf_func[3].n1 : 1
797961 b.b.t_buf_func[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
797963 b.out.d[4].t : 1 [by b.b.t_buf_func[4]._y:=0]
797999 b.b.f_buf_func[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
798006 b.b.vc.OR2_tf[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
798046 b.b.vc.OR2_tf[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
798047 b.b.vc.ct.in[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
798139 b.b.vc.ct.in[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
798353 b.out.d[2].f : 1 [by b.b.f_buf_func[2]._y:=0]
798479 b.b.vc.OR2_tf[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
798483 b.b.vc.ct.in[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
798567 b.b.f_buf_func[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
798854 b.b.f_buf_func[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
798855 b.out.d[1].f : 1 [by b.b.f_buf_func[1]._y:=0]
798951 b.b.vc.OR2_tf[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
799029 b.b.vc.ct.C2Els[0]._y : 0 [by b.b.vc.ct.in[1]:=1]
799108 b.b.vc.ct.tmp[7] : 1 [by b.b.vc.ct.C2Els[0]._y:=0]
799603 b.b.t_buf_func[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
799698 b.b.vc.OR2_tf[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
799786 b.b.vc.ct.in[6] : 1 [by b.b.vc.OR2_tf[6]._y:=0]
802036 b.out.d[5].t : 1 [by b.b.t_buf_func[5]._y:=0]
804421 b.b.t_buf_func[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
806265 b.b.f_buf_func[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
811329 b.b.vc.ct.in[5] : 1 [by b.b.vc.OR2_tf[5]._y:=0]
811388 b.b.vc.ct.C3Els[0]._y : 0 [by b.b.vc.ct.in[5]:=1]
811418 b.b.vc.ct.tmp[9] : 1 [by b.b.vc.ct.C3Els[0]._y:=0]
811976 b.b.vc.OR2_tf[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
812203 b.out.d[3].t : 1 [by b.b.t_buf_func[3]._y:=0]
813443 b.b.vc.ct.in[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
813566 b.b.vc.OR2_tf[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
834592 b.out.d[0].f : 1 [by b.b.f_buf_func[0]._y:=0]
844130 b.out.d[6].f : 1 [by b.b.f_buf_func[6]._y:=0]
873070 b.b.vc.ct.in[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
892454 b.b.vc.ct.C2Els[1]._y : 0 [by b.b.vc.ct.in[3]:=1]
893139 b.b.vc.ct.tmp[8] : 1 [by b.b.vc.ct.C2Els[1]._y:=0]
909854 b.b.vc.ct.C3Els[1]._y : 0 [by b.b.vc.ct.tmp[8]:=1]
909981 b.b._in_v : 1 [by b.b.vc.ct.C3Els[1]._y:=0]
910150 b.b.in_v_buf._y : 0 [by b.b._in_v:=1]
910193 b.in.v : 1 [by b.b.in_v_buf._y:=0]
[] Sending in output valid
910193 b.out_v : 1
910205 b.b._en : 0 [by b.out_v:=1]
910208 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
910246 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
910438 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
910439 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
911484 b.in.a : 1 [by b.b._en:=0]
[] Removing input
911484 b.b.f_buf_func[0].n1 : 0
911484 b.b.f_buf_func[6].n1 : 0
911484 b.b.f_buf_func[2].n1 : 0
911484 b.b.t_buf_func[5].n1 : 0
911484 b.b.f_buf_func[1].n1 : 0
911484 b.b.t_buf_func[4].n1 : 0
911484 b.b.t_buf_func[3].n1 : 0
911485 b.b.vc.OR2_tf[1]._y : 1 [by b.b.f_buf_func[1].n1:=0]
911486 b.b.vc.OR2_tf[3]._y : 1 [by b.b.t_buf_func[3].n1:=0]
911486 b.b.vc.OR2_tf[5]._y : 1 [by b.b.t_buf_func[5].n1:=0]
911503 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
911576 b.b.vc.OR2_tf[6]._y : 1 [by b.b.f_buf_func[6].n1:=0]
911584 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
911605 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
912985 b.b.vc.OR2_tf[4]._y : 1 [by b.b.t_buf_func[4].n1:=0]
913039 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
914211 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
917206 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
917211 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[5]:=0]
918278 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
924236 b.b.vc.OR2_tf[0]._y : 1 [by b.b.f_buf_func[0].n1:=0]
924237 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
924375 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[0]:=0]
924376 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
964749 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
964813 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[2]:=0]
964936 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
964938 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[8]:=0]
964975 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
965118 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
965169 b.in.v : 0 [by b.b.in_v_buf._y:=1]
965611 b.b._en : 1 [by b.in.v:=0]
965612 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
965620 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
965622 b.in.a : 0 [by b.b._en:=1]
965637 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
975873 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
[] Resetting
975873 Reset : 1
979394 b._reset_B : 0 [by Reset:=1]
979539 b.b.reset_buf._y : 1 [by b._reset_B:=0]
979769 b.b._reset_BX : 0 [by b.b.reset_buf._y:=1]
980460 b.b.reset_bufarray.buf2._y : 1 [by b.b._reset_BX:=0]
980474 b.b._reset_BXX[0] : 0 [by b.b.reset_bufarray.buf2._y:=1]
980485 b.b.f_buf_func[6]._y : 1 [by b.b._reset_BXX[0]:=0]
980486 b.out.d[6].f : 0 [by b.b.f_buf_func[6]._y:=1]
982017 b.b.f_buf_func[0]._y : 1 [by b.b._reset_BXX[0]:=0]
982018 b.out.d[0].f : 0 [by b.b.f_buf_func[0]._y:=1]
982085 b.b.f_buf_func[1]._y : 1 [by b.b._reset_BXX[0]:=0]
988586 b.out.d[1].f : 0 [by b.b.f_buf_func[1]._y:=1]
995562 b.b._reset : 1 [by b._reset_B:=0]
995563 b.b.t_buf_func[6]._y : 0 [by b.b._reset:=1]
995580 b.out.d[6].t : 1 [by b.b.t_buf_func[6]._y:=0]
995694 b.b.t_buf_func[2]._y : 0 [by b.b._reset:=1]
995846 b.out.d[2].t : 1 [by b.b.t_buf_func[2]._y:=0]
996201 b.b.t_buf_func[0]._y : 0 [by b.b._reset:=1]
997355 b.b.t_buf_func[1]._y : 0 [by b.b._reset:=1]
997358 b.out.d[1].t : 1 [by b.b.t_buf_func[1]._y:=0]
997986 b.b.f_buf_func[2]._y : 1 [by b.b._reset_BXX[0]:=0]
998410 b.out.d[2].f : 0 [by b.b.f_buf_func[2]._y:=1]
999184 b.out.d[0].t : 1 [by b.b.t_buf_func[0]._y:=0]
999184 Reset : 0
999190 b._reset_B : 1 [by Reset:=0]
1001651 b.b._reset : 0 [by b._reset_B:=1]
1001778 b.b.reset_buf._y : 0 [by b._reset_B:=1]
1002608 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
1025540 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
1025542 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
test/unit_tests/buffer_register_7/run/test.prs
-746
View File
@@ -1,746 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
= "b.b._en_X_f[5]" "b.b.en_buf_f.out[5]"
= "b.b._en_X_f[6]" "b.b.en_buf_f.out[6]"
= "b.b._en_X_f[0]" "b.b.f_buf_func[6].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[5].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[4].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[3].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[2].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[1].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[0].n2"
= "b.b._en_X_f[0]" "b.b._en_X_f[6]"
= "b.b._en_X_f[0]" "b.b._en_X_f[5]"
= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
"b.b.in_v_buf.a"->"b.b.in_v_buf._y"-
~("b.b.in_v_buf.a")->"b.b.in_v_buf._y"+
"b.b.in_v_buf._y"->"b.b.in_v_buf.y"-
~("b.b.in_v_buf._y")->"b.b.in_v_buf.y"+
"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[6]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[5]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
= "b.b.flush" "b.b.flush_inv.a"
~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl.y"+
"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.n1"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl.y"-
~"b.b.vc.ct.C2Els[0].c1"&~"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"+
"b.b.vc.ct.C2Els[0].c1"&"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"-
"b.b.vc.ct.C2Els[0]._y"->"b.b.vc.ct.C2Els[0].y"-
~("b.b.vc.ct.C2Els[0]._y")->"b.b.vc.ct.C2Els[0].y"+
~"b.b.vc.ct.C2Els[1].c1"&~"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"+
"b.b.vc.ct.C2Els[1].c1"&"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"-
"b.b.vc.ct.C2Els[1]._y"->"b.b.vc.ct.C2Els[1].y"-
~("b.b.vc.ct.C2Els[1]._y")->"b.b.vc.ct.C2Els[1].y"+
~"b.b.vc.ct.C3Els[0].c1"&~"b.b.vc.ct.C3Els[0].c2"&~"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"+
"b.b.vc.ct.C3Els[0].c1"&"b.b.vc.ct.C3Els[0].c2"&"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"-
"b.b.vc.ct.C3Els[0]._y"->"b.b.vc.ct.C3Els[0].y"-
~("b.b.vc.ct.C3Els[0]._y")->"b.b.vc.ct.C3Els[0].y"+
~"b.b.vc.ct.C3Els[1].c1"&~"b.b.vc.ct.C3Els[1].c2"&~"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"+
"b.b.vc.ct.C3Els[1].c1"&"b.b.vc.ct.C3Els[1].c2"&"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"-
"b.b.vc.ct.C3Els[1]._y"->"b.b.vc.ct.C3Els[1].y"-
~("b.b.vc.ct.C3Els[1]._y")->"b.b.vc.ct.C3Els[1].y"+
= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C3Els[1].c1"
= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C2Els[0].y"
= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C3Els[1].c2"
= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C2Els[1].y"
= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[1].c3"
= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[0].y"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[1].vdd"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[0].vdd"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[1].vdd"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[0].vdd"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[1].vss"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[0].vss"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[1].vss"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[0].vss"
= "b.b.vc.ct.in[0]" "b.b.vc.ct.C2Els[0].c1"
= "b.b.vc.ct.in[0]" "b.b.vc.ct.tmp[0]"
= "b.b.vc.ct.in[1]" "b.b.vc.ct.C2Els[0].c2"
= "b.b.vc.ct.in[1]" "b.b.vc.ct.tmp[1]"
= "b.b.vc.ct.in[2]" "b.b.vc.ct.C2Els[1].c1"
= "b.b.vc.ct.in[2]" "b.b.vc.ct.tmp[2]"
= "b.b.vc.ct.in[3]" "b.b.vc.ct.C2Els[1].c2"
= "b.b.vc.ct.in[3]" "b.b.vc.ct.tmp[3]"
= "b.b.vc.ct.in[4]" "b.b.vc.ct.C3Els[0].c1"
= "b.b.vc.ct.in[4]" "b.b.vc.ct.tmp[4]"
= "b.b.vc.ct.in[5]" "b.b.vc.ct.C3Els[0].c2"
= "b.b.vc.ct.in[5]" "b.b.vc.ct.tmp[5]"
= "b.b.vc.ct.in[6]" "b.b.vc.ct.C3Els[0].c3"
= "b.b.vc.ct.in[6]" "b.b.vc.ct.tmp[6]"
= "b.b.vc.ct.out" "b.b.vc.ct.C3Els[1].y"
= "b.b.vc.ct.out" "b.b.vc.ct.tmp[10]"
= "b.b.vc.ct.in[0]" "b.b.vc.OR2_tf[0].y"
= "b.b.vc.ct.in[1]" "b.b.vc.OR2_tf[1].y"
= "b.b.vc.ct.in[2]" "b.b.vc.OR2_tf[2].y"
= "b.b.vc.ct.in[3]" "b.b.vc.OR2_tf[3].y"
= "b.b.vc.ct.in[4]" "b.b.vc.OR2_tf[4].y"
= "b.b.vc.ct.in[5]" "b.b.vc.OR2_tf[5].y"
= "b.b.vc.ct.in[6]" "b.b.vc.OR2_tf[6].y"
"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
~("b.b.vc.OR2_tf[0]._y")->"b.b.vc.OR2_tf[0].y"+
"b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b"->"b.b.vc.OR2_tf[1]._y"-
~("b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b")->"b.b.vc.OR2_tf[1]._y"+
"b.b.vc.OR2_tf[1]._y"->"b.b.vc.OR2_tf[1].y"-
~("b.b.vc.OR2_tf[1]._y")->"b.b.vc.OR2_tf[1].y"+
"b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b"->"b.b.vc.OR2_tf[2]._y"-
~("b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b")->"b.b.vc.OR2_tf[2]._y"+
"b.b.vc.OR2_tf[2]._y"->"b.b.vc.OR2_tf[2].y"-
~("b.b.vc.OR2_tf[2]._y")->"b.b.vc.OR2_tf[2].y"+
"b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b"->"b.b.vc.OR2_tf[3]._y"-
~("b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b")->"b.b.vc.OR2_tf[3]._y"+
"b.b.vc.OR2_tf[3]._y"->"b.b.vc.OR2_tf[3].y"-
~("b.b.vc.OR2_tf[3]._y")->"b.b.vc.OR2_tf[3].y"+
"b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b"->"b.b.vc.OR2_tf[4]._y"-
~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
"b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b"->"b.b.vc.OR2_tf[5]._y"-
~("b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b")->"b.b.vc.OR2_tf[5]._y"+
"b.b.vc.OR2_tf[5]._y"->"b.b.vc.OR2_tf[5].y"-
~("b.b.vc.OR2_tf[5]._y")->"b.b.vc.OR2_tf[5].y"+
"b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b"->"b.b.vc.OR2_tf[6]._y"-
~("b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b")->"b.b.vc.OR2_tf[6]._y"+
"b.b.vc.OR2_tf[6]._y"->"b.b.vc.OR2_tf[6].y"-
~("b.b.vc.OR2_tf[6]._y")->"b.b.vc.OR2_tf[6].y"+
= "b.b.vc.supply.vss" "b.b.vc.ct.supply.vss"
= "b.b.vc.supply.vdd" "b.b.vc.ct.supply.vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[6].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[5].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[6].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[5].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
= "b.b.vc.out" "b.b.vc.ct.out"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.OR2_tf[6].b"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.OR2_tf[6].a"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.OR2_tf[5].b"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.OR2_tf[5].a"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.OR2_tf[4].b"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.OR2_tf[4].a"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.OR2_tf[3].b"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.OR2_tf[3].a"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.OR2_tf[2].b"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.OR2_tf[2].a"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.OR2_tf[1].b"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.OR2_tf[1].a"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.OR2_tf[0].b"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.vc.supply.vss"
= "b.b.supply.vdd" "b.b.vc.supply.vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[6].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[6].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[5].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[5].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.in_v_buf.vdd"
= "b.b.supply.vdd" "b.b.reset_buf.vdd"
= "b.b.supply.vdd" "b.b.inack_inv.vdd"
= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
= "b.b.supply.vss" "b.b.t_buf_func[6].vss"
= "b.b.supply.vss" "b.b.f_buf_func[6].vss"
= "b.b.supply.vss" "b.b.t_buf_func[5].vss"
= "b.b.supply.vss" "b.b.f_buf_func[5].vss"
= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
= "b.b.supply.vss" "b.b.in_v_buf.vss"
= "b.b.supply.vss" "b.b.reset_buf.vss"
= "b.b.supply.vss" "b.b.inack_inv.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
= "b.b._en" "b.b.en_buf_f.in"
= "b.b._en" "b.b.en_buf_t.in"
= "b.b._en" "b.b.inack_inv.a"
= "b.b._en" "b.b.inack_ctl.y"
= "b.b._en" "b.b.inack_ctl.c1"
= "b.b._en" "b.b._in_aB"
"b.b.reset_inv.a"->"b.b.reset_inv.y"-
~("b.b.reset_inv.a")->"b.b.reset_inv.y"+
= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
= "b.b.out.d[6].d[0]" "b.b.f_buf_func[6].y"
= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
= "b.b.out.d[6].d[1]" "b.b.t_buf_func[6].y"
= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
= "b.b.out.d[5].d[0]" "b.b.f_buf_func[5].y"
= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
= "b.b.out.d[5].d[1]" "b.b.t_buf_func[5].y"
= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
= "b.b.out.d[4].d[0]" "b.b.f_buf_func[4].y"
= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
= "b.b.out.d[4].d[1]" "b.b.t_buf_func[4].y"
= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
= "b.b.out.d[3].d[0]" "b.b.f_buf_func[3].y"
= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
= "b.b.out.d[3].d[1]" "b.b.t_buf_func[3].y"
= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
= "b.b.out.d[2].d[0]" "b.b.f_buf_func[2].y"
= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
= "b.b.out.d[2].d[1]" "b.b.t_buf_func[2].y"
= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
= "b.b.out.d[1].d[0]" "b.b.f_buf_func[1].y"
= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
= "b.b.out.d[1].d[1]" "b.b.t_buf_func[1].y"
= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
= "b.b.out.d[0].d[0]" "b.b.f_buf_func[0].y"
= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
= "b.b.out.d[0].d[1]" "b.b.t_buf_func[0].y"
= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[0].f" "b.b.vc.in.d[0].f"
= "b.b.in.d.d[0].t" "b.b.vc.in.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.vc.in.d[0].d[0]"
= "b.b.in.d.d[0].d[1]" "b.b.vc.in.d[0].d[1]"
= "b.b.in.d.d[1].f" "b.b.vc.in.d[1].f"
= "b.b.in.d.d[1].t" "b.b.vc.in.d[1].t"
= "b.b.in.d.d[1].d[0]" "b.b.vc.in.d[1].d[0]"
= "b.b.in.d.d[1].d[1]" "b.b.vc.in.d[1].d[1]"
= "b.b.in.d.d[2].f" "b.b.vc.in.d[2].f"
= "b.b.in.d.d[2].t" "b.b.vc.in.d[2].t"
= "b.b.in.d.d[2].d[0]" "b.b.vc.in.d[2].d[0]"
= "b.b.in.d.d[2].d[1]" "b.b.vc.in.d[2].d[1]"
= "b.b.in.d.d[3].f" "b.b.vc.in.d[3].f"
= "b.b.in.d.d[3].t" "b.b.vc.in.d[3].t"
= "b.b.in.d.d[3].d[0]" "b.b.vc.in.d[3].d[0]"
= "b.b.in.d.d[3].d[1]" "b.b.vc.in.d[3].d[1]"
= "b.b.in.d.d[4].f" "b.b.vc.in.d[4].f"
= "b.b.in.d.d[4].t" "b.b.vc.in.d[4].t"
= "b.b.in.d.d[4].d[0]" "b.b.vc.in.d[4].d[0]"
= "b.b.in.d.d[4].d[1]" "b.b.vc.in.d[4].d[1]"
= "b.b.in.d.d[5].f" "b.b.vc.in.d[5].f"
= "b.b.in.d.d[5].t" "b.b.vc.in.d[5].t"
= "b.b.in.d.d[5].d[0]" "b.b.vc.in.d[5].d[0]"
= "b.b.in.d.d[5].d[1]" "b.b.vc.in.d[5].d[1]"
= "b.b.in.d.d[6].f" "b.b.vc.in.d[6].f"
= "b.b.in.d.d[6].t" "b.b.vc.in.d[6].t"
= "b.b.in.d.d[6].d[0]" "b.b.vc.in.d[6].d[0]"
= "b.b.in.d.d[6].d[1]" "b.b.vc.in.d[6].d[1]"
= "b.b.in.a" "b.b.inack_inv.y"
= "b.b.in.v" "b.b.in_v_buf.y"
= "b.b.in.v" "b.b.inack_ctl.c2"
= "b.b.in.d.d[6].d[0]" "b.b.f_buf_func[6].n1"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.t_buf_func[6].n1"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.f_buf_func[5].n1"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.t_buf_func[5].n1"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.f_buf_func[4].n1"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.t_buf_func[4].n1"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.f_buf_func[3].n1"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.t_buf_func[3].n1"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.f_buf_func[2].n1"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.t_buf_func[2].n1"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.f_buf_func[1].n1"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.t_buf_func[1].n1"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.f_buf_func[0].n1"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.t_buf_func[0].n1"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
"b.b.inack_inv.a"->"b.b.inack_inv.y"-
~("b.b.inack_inv.a")->"b.b.inack_inv.y"+
= "b.b._in_v" "b.b.in_v_buf.a"
= "b.b._in_v" "b.b.vc.out"
"b.b.reset_buf.a"->"b.b.reset_buf._y"-
~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
"b.b.reset_buf._y"->"b.b.reset_buf.y"-
~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
"b.b.flush_inv.a"->"b.b.flush_inv.y"-
~("b.b.flush_inv.a")->"b.b.flush_inv.y"+
= "b.b._reset_BX" "b.b.reset_bufarray.in"
= "b.b._reset_BX" "b.b.reset_buf.y"
= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
= "b.b.reset_B" "b.b.reset_buf.a"
= "b.b.reset_B" "b.b.reset_inv.a"
= "b.b._reset" "b.b.t_buf_func[6].sr"
= "b.b._reset" "b.b.t_buf_func[6].pr"
= "b.b._reset" "b.b.t_buf_func[5].sr"
= "b.b._reset" "b.b.t_buf_func[5].pr"
= "b.b._reset" "b.b.t_buf_func[4].sr"
= "b.b._reset" "b.b.t_buf_func[4].pr"
= "b.b._reset" "b.b.t_buf_func[3].sr"
= "b.b._reset" "b.b.t_buf_func[3].pr"
= "b.b._reset" "b.b.t_buf_func[2].sr"
= "b.b._reset" "b.b.t_buf_func[2].pr"
= "b.b._reset" "b.b.t_buf_func[1].sr"
= "b.b._reset" "b.b.t_buf_func[1].pr"
= "b.b._reset" "b.b.t_buf_func[0].sr"
= "b.b._reset" "b.b.t_buf_func[0].pr"
= "b.b._reset" "b.b.reset_inv.y"
= "b.b._flushB" "b.b.t_buf_func[6].c1"
= "b.b._flushB" "b.b.f_buf_func[6].c1"
= "b.b._flushB" "b.b.t_buf_func[5].c1"
= "b.b._flushB" "b.b.f_buf_func[5].c1"
= "b.b._flushB" "b.b.t_buf_func[4].c1"
= "b.b._flushB" "b.b.f_buf_func[4].c1"
= "b.b._flushB" "b.b.t_buf_func[3].c1"
= "b.b._flushB" "b.b.f_buf_func[3].c1"
= "b.b._flushB" "b.b.t_buf_func[2].c1"
= "b.b._flushB" "b.b.f_buf_func[2].c1"
= "b.b._flushB" "b.b.t_buf_func[1].c1"
= "b.b._flushB" "b.b.f_buf_func[1].c1"
= "b.b._flushB" "b.b.t_buf_func[0].c1"
= "b.b._flushB" "b.b.f_buf_func[0].c1"
= "b.b._flushB" "b.b.flush_inv.y"
"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[6]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[5]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[6]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[5]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
= "b.b._reset_BXX[5]" "b.b.reset_bufarray.out[5]"
= "b.b._reset_BXX[6]" "b.b.reset_bufarray.out[6]"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[6]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[5]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].sr"->"b.b.t_buf_func[0]._y"+
"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"|"b.b.t_buf_func[0].pr"->"b.b.t_buf_func[0]._y"-
"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].sr"->"b.b.t_buf_func[1]._y"+
"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"|"b.b.t_buf_func[1].pr"->"b.b.t_buf_func[1]._y"-
"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].sr"->"b.b.t_buf_func[2]._y"+
"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"|"b.b.t_buf_func[2].pr"->"b.b.t_buf_func[2]._y"-
"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].sr"->"b.b.t_buf_func[3]._y"+
"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"|"b.b.t_buf_func[3].pr"->"b.b.t_buf_func[3]._y"-
"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].sr"->"b.b.t_buf_func[4]._y"+
"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"|"b.b.t_buf_func[4].pr"->"b.b.t_buf_func[4]._y"-
"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
~"b.b.t_buf_func[5].c1"&~"b.b.t_buf_func[5].sr"->"b.b.t_buf_func[5]._y"+
"b.b.t_buf_func[5].c1"&"b.b.t_buf_func[5].n1"&"b.b.t_buf_func[5].n2"|"b.b.t_buf_func[5].pr"->"b.b.t_buf_func[5]._y"-
"b.b.t_buf_func[5]._y"->"b.b.t_buf_func[5].y"-
~("b.b.t_buf_func[5]._y")->"b.b.t_buf_func[5].y"+
~"b.b.t_buf_func[6].c1"&~"b.b.t_buf_func[6].sr"->"b.b.t_buf_func[6]._y"+
"b.b.t_buf_func[6].c1"&"b.b.t_buf_func[6].n1"&"b.b.t_buf_func[6].n2"|"b.b.t_buf_func[6].pr"->"b.b.t_buf_func[6]._y"-
"b.b.t_buf_func[6]._y"->"b.b.t_buf_func[6].y"-
~("b.b.t_buf_func[6]._y")->"b.b.t_buf_func[6].y"+
~"b.b.f_buf_func[0].c1"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
~"b.b.f_buf_func[1].c1"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
~"b.b.f_buf_func[2].c1"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
~"b.b.f_buf_func[3].c1"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
~"b.b.f_buf_func[4].c1"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
~"b.b.f_buf_func[5].c1"|~"b.b.f_buf_func[5].pr_B"->"b.b.f_buf_func[5]._y"+
"b.b.f_buf_func[5].c1"&"b.b.f_buf_func[5].n1"&"b.b.f_buf_func[5].n2"&"b.b.f_buf_func[5].sr_B"->"b.b.f_buf_func[5]._y"-
"b.b.f_buf_func[5]._y"->"b.b.f_buf_func[5].y"-
~("b.b.f_buf_func[5]._y")->"b.b.f_buf_func[5].y"+
~"b.b.f_buf_func[6].c1"|~"b.b.f_buf_func[6].pr_B"->"b.b.f_buf_func[6]._y"+
"b.b.f_buf_func[6].c1"&"b.b.f_buf_func[6].n1"&"b.b.f_buf_func[6].n2"&"b.b.f_buf_func[6].sr_B"->"b.b.f_buf_func[6]._y"-
"b.b.f_buf_func[6]._y"->"b.b.f_buf_func[6].y"-
~("b.b.f_buf_func[6]._y")->"b.b.f_buf_func[6].y"+
= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
= "b.b._en_X_t[5]" "b.b.en_buf_t.out[5]"
= "b.b._en_X_t[6]" "b.b.en_buf_t.out[6]"
= "b.b._en_X_t[0]" "b.b.t_buf_func[6].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[5].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[4].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[3].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[2].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[1].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[0].n2"
= "b.b._en_X_t[0]" "b.b._en_X_t[6]"
= "b.b._en_X_t[0]" "b.b._en_X_t[5]"
= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
= "b.b.out_v" "b.b.inack_ctl.n1"
= "b._reset_B" "b.b.reset_B"
= "b.flush" "b.b.flush"
= "Vdd" "b.supply.vdd"
= "GND" "b.supply.vss"
= "b.out_v" "b.b.out_v"
= "b.out.d[0].d[0]" "b.out.d[0].f"
= "b.out.d[0].d[1]" "b.out.d[0].t"
= "b.out.d[1].d[0]" "b.out.d[1].f"
= "b.out.d[1].d[1]" "b.out.d[1].t"
= "b.out.d[2].d[0]" "b.out.d[2].f"
= "b.out.d[2].d[1]" "b.out.d[2].t"
= "b.out.d[3].d[0]" "b.out.d[3].f"
= "b.out.d[3].d[1]" "b.out.d[3].t"
= "b.out.d[4].d[0]" "b.out.d[4].f"
= "b.out.d[4].d[1]" "b.out.d[4].t"
= "b.out.d[5].d[0]" "b.out.d[5].f"
= "b.out.d[5].d[1]" "b.out.d[5].t"
= "b.out.d[6].d[0]" "b.out.d[6].f"
= "b.out.d[6].d[1]" "b.out.d[6].t"
= "b.out.d[6].d[0]" "b.out.d[6].f"
= "b.out.d[6].d[1]" "b.out.d[6].t"
= "b.out.d[5].d[0]" "b.out.d[5].f"
= "b.out.d[5].d[1]" "b.out.d[5].t"
= "b.out.d[4].d[0]" "b.out.d[4].f"
= "b.out.d[4].d[1]" "b.out.d[4].t"
= "b.out.d[3].d[0]" "b.out.d[3].f"
= "b.out.d[3].d[1]" "b.out.d[3].t"
= "b.out.d[2].d[0]" "b.out.d[2].f"
= "b.out.d[2].d[1]" "b.out.d[2].t"
= "b.out.d[1].d[0]" "b.out.d[1].f"
= "b.out.d[1].d[1]" "b.out.d[1].t"
= "b.out.d[0].d[0]" "b.out.d[0].f"
= "b.out.d[0].d[1]" "b.out.d[0].t"
= "b.out.d[0].f" "b.b.out.d[0].f"
= "b.out.d[0].t" "b.b.out.d[0].t"
= "b.out.d[0].d[0]" "b.b.out.d[0].d[0]"
= "b.out.d[0].d[1]" "b.b.out.d[0].d[1]"
= "b.out.d[1].f" "b.b.out.d[1].f"
= "b.out.d[1].t" "b.b.out.d[1].t"
= "b.out.d[1].d[0]" "b.b.out.d[1].d[0]"
= "b.out.d[1].d[1]" "b.b.out.d[1].d[1]"
= "b.out.d[2].f" "b.b.out.d[2].f"
= "b.out.d[2].t" "b.b.out.d[2].t"
= "b.out.d[2].d[0]" "b.b.out.d[2].d[0]"
= "b.out.d[2].d[1]" "b.b.out.d[2].d[1]"
= "b.out.d[3].f" "b.b.out.d[3].f"
= "b.out.d[3].t" "b.b.out.d[3].t"
= "b.out.d[3].d[0]" "b.b.out.d[3].d[0]"
= "b.out.d[3].d[1]" "b.b.out.d[3].d[1]"
= "b.out.d[4].f" "b.b.out.d[4].f"
= "b.out.d[4].t" "b.b.out.d[4].t"
= "b.out.d[4].d[0]" "b.b.out.d[4].d[0]"
= "b.out.d[4].d[1]" "b.b.out.d[4].d[1]"
= "b.out.d[5].f" "b.b.out.d[5].f"
= "b.out.d[5].t" "b.b.out.d[5].t"
= "b.out.d[5].d[0]" "b.b.out.d[5].d[0]"
= "b.out.d[5].d[1]" "b.b.out.d[5].d[1]"
= "b.out.d[6].f" "b.b.out.d[6].f"
= "b.out.d[6].t" "b.b.out.d[6].t"
= "b.out.d[6].d[0]" "b.b.out.d[6].d[0]"
= "b.out.d[6].d[1]" "b.b.out.d[6].d[1]"
= "b.out.d[6].d[0]" "b.out.d[6].f"
= "b.out.d[6].d[1]" "b.out.d[6].t"
= "b.out.d[5].d[0]" "b.out.d[5].f"
= "b.out.d[5].d[1]" "b.out.d[5].t"
= "b.out.d[4].d[0]" "b.out.d[4].f"
= "b.out.d[4].d[1]" "b.out.d[4].t"
= "b.out.d[3].d[0]" "b.out.d[3].f"
= "b.out.d[3].d[1]" "b.out.d[3].t"
= "b.out.d[2].d[0]" "b.out.d[2].f"
= "b.out.d[2].d[1]" "b.out.d[2].t"
= "b.out.d[1].d[0]" "b.out.d[1].f"
= "b.out.d[1].d[1]" "b.out.d[1].t"
= "b.out.d[0].d[0]" "b.out.d[0].f"
= "b.out.d[0].d[1]" "b.out.d[0].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.v" "b.b.in.v"
= "b.in.a" "b.b.in.a"
= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
= "b.in.d.d[5].f" "b.b.in.d.d[5].f"
= "b.in.d.d[5].t" "b.b.in.d.d[5].t"
= "b.in.d.d[5].d[0]" "b.b.in.d.d[5].d[0]"
= "b.in.d.d[5].d[1]" "b.b.in.d.d[5].d[1]"
= "b.in.d.d[6].f" "b.b.in.d.d[6].f"
= "b.in.d.d[6].t" "b.b.in.d.d[6].t"
= "b.in.d.d[6].d[0]" "b.b.in.d.d[6].d[0]"
= "b.in.d.d[6].d[1]" "b.b.in.d.d[6].d[1]"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
test/unit_tests/buffer_register_7/test.act
-52
View File
@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc buffer_register_7 (avMx1of2<7> in; Mx1of2<7> out; bool? out_v, flush){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
buffer_register<7> b(.in = in, .out = out, .out_v = out_v, .flush = flush, .reset_B = _reset_B);
}
// fifo_decoder_neurons_encoder_fifo e;
buffer_register_7 b;
test/unit_tests/buffer_register_7/test.prsim
-163
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@@ -1,163 +0,0 @@
watchall
set b.out_v 0
set b.flush 0
set-qdi-channel-neutral "b.in" 7
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] Flushing data'"
set b.flush 1
cycle
assert b.out.d[0].t 0
assert b.out.d[1].t 0
assert b.out.d[2].t 0
assert b.out.d[3].t 0
assert b.out.d[4].t 0
assert b.out.d[5].t 0
assert b.out.d[6].t 0
assert b.out.d[0].f 0
assert b.out.d[1].f 0
assert b.out.d[2].f 0
assert b.out.d[3].f 0
assert b.out.d[4].f 0
assert b.out.d[5].f 0
assert b.out.d[6].f 0
set b.out_v 0
set b.flush 0
cycle
system "echo '[] Sending in a 0'"
set-qdi-channel-valid "b.in" 7 0
cycle
# assert-qdi-channel-valid 'b.out' 7 127
assert b.in.a 0
assert b.in.v 1
assert-var-int "b.out" 7 0
system "echo '[] Sending in output valid'"
set b.out_v 1
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.out" 7 0
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 7
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.out" 7 0
system "echo '[] Flushing data'"
set b.flush 1
cycle
assert b.out.d[0].t 0
assert b.out.d[1].t 0
assert b.out.d[2].t 0
assert b.out.d[3].t 0
assert b.out.d[4].t 0
assert b.out.d[5].t 0
assert b.out.d[6].t 0
assert b.out.d[0].f 0
assert b.out.d[1].f 0
assert b.out.d[2].f 0
assert b.out.d[3].f 0
assert b.out.d[4].f 0
assert b.out.d[5].f 0
assert b.out.d[6].f 0
set b.out_v 0
cycle
set b.flush 0
cycle
system "echo '[] Sending in a 127'"
set-qdi-channel-valid "b.in" 7 127
cycle
# assert-qdi-channel-valid 'b.out' 7 127
assert b.in.a 0
assert b.in.v 1
assert-var-int "b.out" 7 127
system "echo '[] Sending in output valid'"
set b.out_v 1
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.out" 7 127
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 7
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.out" 7 127
system "echo '[] Flushing data'"
set b.flush 1
cycle
assert b.out.d[0].t 0
assert b.out.d[1].t 0
assert b.out.d[2].t 0
assert b.out.d[3].t 0
assert b.out.d[4].t 0
assert b.out.d[5].t 0
assert b.out.d[6].t 0
assert b.out.d[0].f 0
assert b.out.d[1].f 0
assert b.out.d[2].f 0
assert b.out.d[3].f 0
assert b.out.d[4].f 0
assert b.out.d[5].f 0
assert b.out.d[6].f 0
set b.out_v 0
cycle
set b.flush 0
cycle
system "echo '[] Sending in a 56'"
set-qdi-channel-valid "b.in" 7 56
cycle
assert b.in.a 0
assert b.in.v 1
assert-var-int "b.out" 7 56
system "echo '[] Sending in output valid'"
set b.out_v 1
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.out" 7 56
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 7
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.out" 7 56
system "echo '[] Resetting'"
set Reset 1
cycle
assert-var-int "b.out" 7 127
set Reset 0
cycle
assert-var-int "b.out" 7 127
test/unit_tests/decoder_2d_dly_8_16/run/prsim.out
-355
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@@ -1,355 +0,0 @@
b.b.addr_buf.vc.ct.in[1] b.b.dly.dly[9].__y b.b.addr_buf.out_a_B_buf_f.buf2._y b.b.addr_buf.vc.OR2_tf[6]._y b.b.addr_buf.vc.ct.in[0] b.b.addr_buf.vc.ct.C2Els[1]._y b.dly_cfg[2] b.in.d.d[4].f b.b.addr_buf._out_a_BX_f[0] b.in.d.d[1].f b.b.dly._a[1] b.in.d.d[1].t b.b.addr_buf.vc.ct.tmp[8] b.in.d.d[6].t b.b.addr_buf.vc.ct.in[6] b.b.addr_buf.in_v_buf._y b.b.addr_buf._in_v b.dly_cfg[3] b.b.dly.dly[10].y b.b.dly.dly[6]._y b.in.d.d[3].t b.b.dly.dly[7].y b.in.d.d[4].t b.b.addr_buf.vc.ct.in[4] b.b.dly._a[3] b.b.dly.dly[5].y b.in.d.d[3].f b.in.v b.b.addr_buf.vc.ct.tmp[9] b.b.dly.dly[9].___y b.b.addr_buf._out_a_BX_t[0] b.b.addr_buf.vc.ct.in[2] b.b.dly.dly[14].___y b.in.d.d[0].f b.b.dly.mu2[0]._y b.b.dly.dly[6].___y b.b.dly.mu2[3]._y b.b.dly.and2[3]._y b.in.d.d[5].t b.b.dly.dly[14].__y b.b.dly.mu2[2]._y b.in.d.d[0].t b.in.d.d[6].f b.b.addr_buf._out_a_B b.in.d.d[2].t b.b.addr_buf.vc.ct.tmp[7] b.b.dly.dly[7]._y b.b.dly.out b.b.dly.dly[4].__y b.b.dly.dly[12].__y b.b.dly.dly[1].y b.b.dly.dly[14]._y b.b.addr_buf.vc.ct.in[5] b.b.addr_buf.vc.OR2_tf[4]._y b.b.dly.dly[3].a b.b.dly.mu2[3].b b.in.d.d[5].f b.dly_cfg[1] b.b.dly.dly[7].a b.b.dly.dly[8].y b.b.dly.dly[3].___y b.b.dly._a[2] b.b.addr_buf.vc.ct.C3Els[1]._y b.b.dly.dly[1].a b.in.d.d[2].f b.b.addr_buf.vc.ct.in[3] b.b.dly.dly[3]._y b.b.dly.dly[10].__y b.b.dly.dly[1]._y b.b.dly.dly[11]._y b.b.dly.and2[1]._y b.b.dly.dly[9].y b.b.addr_buf.out_a_B_buf_t.buf2._y b.b.dly.dly[13]._y b.b.addr_buf.vc.OR2_tf[3]._y b.b.dly.dly[5].___y b.b.dly.dly[13].__y b.b.dly.dly[11].__y b.b.dly.dly[13].y b.b.dly.dly[4]._y b.b.dly.dly[11].y b.b.dly.dly[7].___y b.b.dly.dly[8].__y b.b.dly.dly[4].___y b.b.dly.dly[8]._y b.dly_cfg[0] b.b.dly.dly[12].___y b.b.dly.dly[12].y b.b.addr_buf.vc.OR2_tf[2]._y b.b.dly.dly[6].y b.b.dly.dly[2].y b.b.dly.mu2[1]._s b.b.dly.dly[4].y b.b.dly.dly[13].___y b.b.addr_buf.vc.OR2_tf[5]._y b.b.dly.dly[12]._y b.b.dly.dly[2].___y b.b.dly.mu2[2]._s b.b.dly.dly[10].___y b.b.dly.dly[6].__y b.b.dly.dly[3].y b.b.dly.dly[5].__y b.b.dly.mu2[0]._s b.b.addr_buf.vc.OR2_tf[0]._y b.b.dly.mu2[1]._y b.b.dly.mu2[3]._s b.b.dly.dly[1].___y b.b.dly.dly[2]._y b.b.dly.dly[7].__y b.b.dly.dly[8].___y b.b.addr_buf.vc.ct.C2Els[0]._y b.b.dly.dly[5]._y b.b.addr_buf.vc.ct.C3Els[0]._y b.b.dly.dly[1].__y b.b.addr_buf.vc.OR2_tf[1]._y b.b.dly.and2[2]._y b.b.dly.dly[11].___y b.b.dly.dly[2].__y b.b.dly.dly[3].__y b.b.dly.dly[9]._y b.b.dly.dly[10]._y
175726 b.in.d.d[0].f : 0
175726 b.dly_cfg[3] : 0
175726 b.dly_cfg[2] : 0
175726 b.in.d.d[1].f : 0
175726 b.in.d.d[3].f : 0
175726 b.b.dly.out : 0
175726 b.in.d.d[6].t : 0
175726 b.in.d.d[2].t : 0
175726 b.dly_cfg[1] : 1
175726 b.dly_cfg[0] : 1
175726 b.in.d.d[6].f : 0
175726 b.in.d.d[5].t : 0
175726 b.in.d.d[0].t : 0
175726 Reset : 0
175726 b.in.d.d[2].f : 0
175726 b.in.d.d[5].f : 0
175726 b.in.d.d[4].t : 0
175726 b.in.d.d[1].t : 0
175726 b.in.d.d[4].f : 0
175726 b.in.d.d[3].t : 0
175727 b.b.dly.mu2[3]._s : 1 [by b.dly_cfg[3]:=0]
175730 b.b.addr_buf.vc.OR2_tf[5]._y : 1 [by b.in.d.d[5].f:=0]
175734 b.b.addr_buf.vc.OR2_tf[6]._y : 1 [by b.in.d.d[6].f:=0]
175760 b.b.addr_buf.vc.OR2_tf[0]._y : 1 [by b.in.d.d[0].t:=0]
175763 b.b.addr_buf.vc.ct.in[0] : 0 [by b.b.addr_buf.vc.OR2_tf[0]._y:=1]
175768 b.b.dly.and2[2]._y : 1 [by b.dly_cfg[2]:=0]
175782 b.b.addr_buf.vc.ct.in[6] : 0 [by b.b.addr_buf.vc.OR2_tf[6]._y:=1]
175821 b.b.dly.mu2[1]._s : 0 [by b.dly_cfg[1]:=1]
175946 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
176061 b.b.dly.mu2[0]._s : 0 [by b.dly_cfg[0]:=1]
176644 b.b.addr_buf.vc.OR2_tf[2]._y : 1 [by b.in.d.d[2].f:=0]
178124 b.b.addr_buf.vc.OR2_tf[4]._y : 1 [by b.in.d.d[4].f:=0]
178543 b.b.dly.mu2[2]._s : 1 [by b.dly_cfg[2]:=0]
178941 b.b.addr_buf.vc.OR2_tf[3]._y : 1 [by b.in.d.d[3].t:=0]
179768 b.b.addr_buf.vc.ct.in[3] : 0 [by b.b.addr_buf.vc.OR2_tf[3]._y:=1]
182595 b.b.addr_buf.vc.ct.in[2] : 0 [by b.b.addr_buf.vc.OR2_tf[2]._y:=1]
182768 b.b.addr_buf.vc.ct.C2Els[1]._y : 1 [by b.b.addr_buf.vc.ct.in[2]:=0]
182952 b.b.addr_buf.vc.ct.tmp[8] : 0 [by b.b.addr_buf.vc.ct.C2Els[1]._y:=1]
187960 b.b.dly.mu2[0]._y : 1 [by b.b.dly.mu2[0]._s:=0]
187961 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
188034 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
188038 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
189459 b.b.addr_buf._out_a_B : 1 [by b.b.dly.out:=0]
189555 b.b.addr_buf.out_a_B_buf_t.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
189556 b.b.addr_buf._out_a_BX_f[0] : 1 [by b.b.addr_buf.out_a_B_buf_t.buf2._y:=0]
189595 b.b.addr_buf.out_a_B_buf_f.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
189613 b._reset_B : 1 [by Reset:=0]
189854 b.b.addr_buf.reset_buf._y : 0 [by b._reset_B:=1]
193813 b.b.addr_buf._reset_BX : 1 [by b.b.addr_buf.reset_buf._y:=0]
193825 b.b.addr_buf.reset_bufarray.buf2._y : 0 [by b.b.addr_buf._reset_BX:=1]
196923 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
197725 b.b.addr_buf._reset_BXX[0] : 1 [by b.b.addr_buf.reset_bufarray.buf2._y:=0]
197952 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
197953 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
198009 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
208641 b.b.addr_buf._out_a_BX_t[0] : 1 [by b.b.addr_buf.out_a_B_buf_f.buf2._y:=0]
217609 b.b.addr_buf.vc.ct.in[4] : 0 [by b.b.addr_buf.vc.OR2_tf[4]._y:=1]
222104 b.b.addr_buf.vc.OR2_tf[1]._y : 1 [by b.in.d.d[1].t:=0]
222105 b.b.addr_buf.vc.ct.in[1] : 0 [by b.b.addr_buf.vc.OR2_tf[1]._y:=1]
222142 b.b.addr_buf.vc.ct.C2Els[0]._y : 1 [by b.b.addr_buf.vc.ct.in[1]:=0]
222849 b.b.addr_buf.vc.ct.in[5] : 0 [by b.b.addr_buf.vc.OR2_tf[5]._y:=1]
222850 b.b.addr_buf.vc.ct.C3Els[0]._y : 1 [by b.b.addr_buf.vc.ct.in[5]:=0]
225326 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
226414 b.b.addr_buf.vc.ct.tmp[9] : 0 [by b.b.addr_buf.vc.ct.C3Els[0]._y:=1]
227018 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
227031 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
234688 b.b.dly.and2[3]._y : 1 [by b.dly_cfg[3]:=0]
235045 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
235070 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
235091 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
235092 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
243015 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
243016 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
243017 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
243178 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
244015 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
244020 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
244215 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
244601 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
244612 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
244623 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
244637 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
244655 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
244659 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
244740 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
244763 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
245517 b.b.addr_buf.vc.ct.tmp[7] : 0 [by b.b.addr_buf.vc.ct.C2Els[0]._y:=1]
245659 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
245887 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
245967 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
246730 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
246800 b.b.dly.mu2[2]._y : 1 [by b.b.dly._a[2]:=0]
247426 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
253972 b.b.addr_buf.vc.ct.C3Els[1]._y : 1 [by b.b.addr_buf.vc.ct.tmp[7]:=0]
253983 b.b.addr_buf._in_v : 0 [by b.b.addr_buf.vc.ct.C3Els[1]._y:=1]
253986 b.b.addr_buf.in_v_buf._y : 1 [by b.b.addr_buf._in_v:=0]
254040 b.in.v : 0 [by b.b.addr_buf.in_v_buf._y:=1]
276184 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
277332 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
278493 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
287145 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
287226 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
297222 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
298303 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
298395 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
306706 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
308450 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
309063 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
315205 b.b.dly.mu2[3]._y : 1 [by b.b.dly._a[3]:=0]
323085 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
323130 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
324127 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
325776 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
326301 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
327201 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
327253 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
327260 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
342872 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
349339 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
349341 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
349695 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
349828 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
349829 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
349833 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
350379 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
395942 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
395943 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
[] set Reset 1
395943 Reset : 1
408321 b._reset_B : 0 [by Reset:=1]
408400 b.b.addr_buf.reset_buf._y : 1 [by b._reset_B:=0]
410833 b.b.addr_buf._reset_BX : 0 [by b.b.addr_buf.reset_buf._y:=1]
410921 b.b.addr_buf.reset_bufarray.buf2._y : 1 [by b.b.addr_buf._reset_BX:=0]
418703 b.b.addr_buf._reset_BXX[0] : 0 [by b.b.addr_buf.reset_bufarray.buf2._y:=1]
[] set Reset 0
418703 Reset : 0
447030 b._reset_B : 1 [by Reset:=0]
447089 b.b.addr_buf.reset_buf._y : 0 [by b._reset_B:=1]
447119 b.b.addr_buf._reset_BX : 1 [by b.b.addr_buf.reset_buf._y:=0]
448586 b.b.addr_buf.reset_bufarray.buf2._y : 0 [by b.b.addr_buf._reset_BX:=1]
508090 b.b.addr_buf._reset_BXX[0] : 1 [by b.b.addr_buf.reset_bufarray.buf2._y:=0]
[] Sending packet in
508090 b.in.d.d[0].t : 1
508090 b.in.d.d[6].t : 1
508090 b.in.d.d[2].t : 1
508090 b.in.d.d[5].t : 1
508090 b.in.d.d[1].t : 1
508090 b.in.d.d[4].t : 1
508090 b.in.d.d[3].t : 1
508091 b.b.addr_buf.t_buf_func[4]._y : 0 [by b.in.d.d[4].t:=1]
508093 b.b.addr_buf.t_buf_func[1]._y : 0 [by b.in.d.d[1].t:=1]
508095 b.b.atree_x[2].in[1] : 1 [by b.b.addr_buf.t_buf_func[1]._y:=0]
508096 b.b.vtree_x.OR2_tf[1]._y : 0 [by b.b.atree_x[2].in[1]:=1]
508102 b.b.addr_buf.vc.OR2_tf[5]._y : 0 [by b.in.d.d[5].t:=1]
508104 b.b.addr_buf.vc.ct.in[5] : 1 [by b.b.addr_buf.vc.OR2_tf[5]._y:=0]
508128 b.b.addr_buf.vc.OR2_tf[4]._y : 0 [by b.in.d.d[4].t:=1]
508133 b.b.addr_buf.t_buf_func[2]._y : 0 [by b.in.d.d[2].t:=1]
508146 b.b.addr_buf.vc.ct.in[4] : 1 [by b.b.addr_buf.vc.OR2_tf[4]._y:=0]
508182 b.b.addr_buf.t_buf_func[3]._y : 0 [by b.in.d.d[3].t:=1]
508217 b.b.addr_buf.t_buf_func[6]._y : 0 [by b.in.d.d[6].t:=1]
508225 b.b.atree_y[8].in[3] : 1 [by b.b.addr_buf.t_buf_func[6]._y:=0]
508252 b.b.atree_x[4].in[2] : 1 [by b.b.addr_buf.t_buf_func[2]._y:=0]
508259 b.b.addr_buf.vc.OR2_tf[2]._y : 0 [by b.in.d.d[2].t:=1]
508264 b.b.addr_buf.vc.ct.in[2] : 1 [by b.b.addr_buf.vc.OR2_tf[2]._y:=0]
508279 b.b.vtree_y.OR2_tf[3]._y : 0 [by b.b.atree_y[8].in[3]:=1]
508323 b.b.addr_buf.vc.OR2_tf[1]._y : 0 [by b.in.d.d[1].t:=1]
508324 b.b.addr_buf.vc.ct.in[1] : 1 [by b.b.addr_buf.vc.OR2_tf[1]._y:=0]
508775 b.b.addr_buf.t_buf_func[0]._y : 0 [by b.in.d.d[0].t:=1]
508913 b.b.atree_x[1].in[0] : 1 [by b.b.addr_buf.t_buf_func[0]._y:=0]
508914 b.b.atree_x[7].and3s[0]._y : 0 [by b.b.atree_x[1].in[0]:=1]
508977 b.b.vtree_x.OR2_tf[0]._y : 0 [by b.b.atree_x[1].in[0]:=1]
508979 b.b.vtree_x.ct.in[0] : 1 [by b.b.vtree_x.OR2_tf[0]._y:=0]
509037 b.outx[7] : 1 [by b.b.atree_x[7].and3s[0]._y:=0]
509346 b.b.vtree_y.ct.in[3] : 1 [by b.b.vtree_y.OR2_tf[3]._y:=0]
509369 b.b.addr_buf.t_buf_func[5]._y : 0 [by b.in.d.d[5].t:=1]
509406 b.b.atree_y[4].in[2] : 1 [by b.b.addr_buf.t_buf_func[5]._y:=0]
509407 b.b.vtree_y.OR2_tf[2]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509416 b.b.vtree_y.ct.in[2] : 1 [by b.b.vtree_y.OR2_tf[2]._y:=0]
509417 b.b.atree_y[14].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509441 b.b.vtree_y.ct.C2Els[1]._y : 0 [by b.b.vtree_y.ct.in[2]:=1]
509457 b.b.atree_y[12].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509549 b.b.atree_y[15].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509597 b.b.vtree_x.ct.in[1] : 1 [by b.b.vtree_x.OR2_tf[1]._y:=0]
509602 b.b.atree_y[12].tmp[5] : 1 [by b.b.atree_y[12].and2s[1]._y:=0]
509848 b.b.atree_y[13].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
510078 b.b.atree_y[13].tmp[5] : 1 [by b.b.atree_y[13].and2s[1]._y:=0]
510818 b.b.atree_y[2].in[1] : 1 [by b.b.addr_buf.t_buf_func[4]._y:=0]
511509 b.b.vtree_y.OR2_tf[1]._y : 0 [by b.b.atree_y[2].in[1]:=1]
511523 b.b.vtree_y.ct.in[1] : 1 [by b.b.vtree_y.OR2_tf[1]._y:=0]
512962 b.b.vtree_y.ct.tmp[5] : 1 [by b.b.vtree_y.ct.C2Els[1]._y:=0]
513902 b.b.atree_y[1].in[0] : 1 [by b.b.addr_buf.t_buf_func[3]._y:=0]
513903 b.b.vtree_y.OR2_tf[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
513904 b.b.vtree_y.ct.in[0] : 1 [by b.b.vtree_y.OR2_tf[0]._y:=0]
513913 b.b.atree_y[11].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
514552 b.b.atree_y[11].tmp[4] : 1 [by b.b.atree_y[11].and2s[0]._y:=0]
515445 b.b.atree_y[15].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
515513 b.b.atree_y[3].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
515645 b.b.atree_y[3].tmp[4] : 1 [by b.b.atree_y[3].and2s[0]._y:=0]
517238 b.b.atree_y[15].tmp[4] : 1 [by b.b.atree_y[15].and2s[0]._y:=0]
519670 b.b.atree_y[14].tmp[5] : 1 [by b.b.atree_y[14].and2s[1]._y:=0]
520405 b.b.vtree_y.ct.C2Els[0]._y : 0 [by b.b.vtree_y.ct.in[0]:=1]
520406 b.b.vtree_y.ct.tmp[4] : 1 [by b.b.vtree_y.ct.C2Els[0]._y:=0]
520423 b.b.vtree_y.ct.C2Els[2]._y : 0 [by b.b.vtree_y.ct.tmp[4]:=1]
520575 b.b.C2el.c2 : 1 [by b.b.vtree_y.ct.C2Els[2]._y:=0]
520842 b.b.addr_buf.vc.OR2_tf[3]._y : 0 [by b.in.d.d[3].t:=1]
523825 b.b.addr_buf.vc.ct.in[3] : 1 [by b.b.addr_buf.vc.OR2_tf[3]._y:=0]
523828 b.b.addr_buf.vc.ct.C2Els[1]._y : 0 [by b.b.addr_buf.vc.ct.in[3]:=1]
524252 b.b.addr_buf.vc.ct.tmp[8] : 1 [by b.b.addr_buf.vc.ct.C2Els[1]._y:=0]
524805 b.b.addr_buf.vc.OR2_tf[6]._y : 0 [by b.in.d.d[6].t:=1]
524811 b.b.addr_buf.vc.ct.in[6] : 1 [by b.b.addr_buf.vc.OR2_tf[6]._y:=0]
525717 b.b.atree_y[15].tmp[5] : 1 [by b.b.atree_y[15].and2s[1]._y:=0]
527399 b.b.addr_buf.vc.ct.C3Els[0]._y : 0 [by b.b.addr_buf.vc.ct.in[6]:=1]
527474 b.b.addr_buf.vc.OR2_tf[0]._y : 0 [by b.in.d.d[0].t:=1]
528178 b.b.atree_y[15].and2s[2]._y : 0 [by b.b.atree_y[15].tmp[5]:=1]
528180 b.outy[15] : 1 [by b.b.atree_y[15].and2s[2]._y:=0]
528229 b.b.addr_buf.vc.ct.tmp[9] : 1 [by b.b.addr_buf.vc.ct.C3Els[0]._y:=0]
531414 b.b.atree_y[7].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
531608 b.b.atree_y[7].tmp[4] : 1 [by b.b.atree_y[7].and2s[0]._y:=0]
550406 b.b.addr_buf.vc.ct.in[0] : 1 [by b.b.addr_buf.vc.OR2_tf[0]._y:=0]
551009 b.b.addr_buf.vc.ct.C2Els[0]._y : 0 [by b.b.addr_buf.vc.ct.in[0]:=1]
551147 b.b.addr_buf.vc.ct.tmp[7] : 1 [by b.b.addr_buf.vc.ct.C2Els[0]._y:=0]
551164 b.b.addr_buf.vc.ct.C3Els[1]._y : 0 [by b.b.addr_buf.vc.ct.tmp[7]:=1]
551181 b.b.addr_buf._in_v : 1 [by b.b.addr_buf.vc.ct.C3Els[1]._y:=0]
551607 b.b.addr_buf.in_v_buf._y : 0 [by b.b.addr_buf._in_v:=1]
551608 b.in.v : 1 [by b.b.addr_buf.in_v_buf._y:=0]
558790 b.b.vtree_x.OR2_tf[2]._y : 0 [by b.b.atree_x[4].in[2]:=1]
558791 b.b.vtree_x.ct.in[2] : 1 [by b.b.vtree_x.OR2_tf[2]._y:=0]
559817 b.b.vtree_x.ct.C3Els[0]._y : 0 [by b.b.vtree_x.ct.in[2]:=1]
559818 b.b.C2el.c1 : 1 [by b.b.vtree_x.ct.C3Els[0]._y:=0]
559837 b.b.C2el._y : 0 [by b.b.C2el.c1:=1]
560005 b.b.C2el.y : 1 [by b.b.C2el._y:=0]
560166 b.b.addr_buf.inack_ctl._y : 0 [by b.b.C2el.y:=1]
560339 b.in.a : 1 [by b.b.addr_buf.inack_ctl._y:=0]
560544 b.b.dly.and2[0]._y : 0 [by b.b.C2el.y:=1]
562886 b.b.addr_buf._en : 0 [by b.in.a:=1]
562887 b.b.addr_buf.en_buf_f.buf2._y : 1 [by b.b.addr_buf._en:=0]
562887 b.b.addr_buf.en_buf_t.buf2._y : 1 [by b.b.addr_buf._en:=0]
563094 b.b.addr_buf._en_X_t[0] : 0 [by b.b.addr_buf.en_buf_t.buf2._y:=1]
563277 b.b.addr_buf._en_X_f[0] : 0 [by b.b.addr_buf.en_buf_f.buf2._y:=1]
575605 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
576438 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
576466 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
576473 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
576887 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
576891 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
578670 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
601544 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
601710 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
641580 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
650225 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
651158 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
652014 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
652153 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
678362 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
678557 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
678559 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
732008 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
732014 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
732268 b.b.dly.mu2[2]._y : 0 [by b.b.dly._a[2]:=1]
732276 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
732277 b.b.dly.mu2[3]._y : 0 [by b.b.dly._a[3]:=1]
732283 b.b.dly.out : 1 [by b.b.dly.mu2[3]._y:=0]
783319 b.b.addr_buf._out_a_B : 0 [by b.b.dly.out:=1]
783545 b.b.addr_buf.out_a_B_buf_f.buf2._y : 1 [by b.b.addr_buf._out_a_B:=0]
784364 b.b.addr_buf._out_a_BX_t[0] : 0 [by b.b.addr_buf.out_a_B_buf_f.buf2._y:=1]
784365 b.b.addr_buf.t_buf_func[0]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784366 b.b.addr_buf.t_buf_func[2]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784370 b.b.addr_buf.t_buf_func[1]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784379 b.b.addr_buf.t_buf_func[4]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784458 b.b.atree_x[1].in[0] : 0 [by b.b.addr_buf.t_buf_func[0]._y:=1]
784471 b.b.addr_buf.t_buf_func[6]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784472 b.b.atree_y[8].in[3] : 0 [by b.b.addr_buf.t_buf_func[6]._y:=1]
784473 b.b.atree_y[12].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
784473 b.b.vtree_y.OR2_tf[3]._y : 1 [by b.b.atree_y[8].in[3]:=0]
784474 b.b.vtree_y.ct.in[3] : 0 [by b.b.vtree_y.OR2_tf[3]._y:=1]
784479 b.b.atree_y[12].tmp[5] : 0 [by b.b.atree_y[12].and2s[1]._y:=1]
785137 b.b.atree_y[2].in[1] : 0 [by b.b.addr_buf.t_buf_func[4]._y:=1]
785144 b.b.vtree_y.OR2_tf[1]._y : 1 [by b.b.atree_y[2].in[1]:=0]
785159 b.b.atree_y[7].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
785172 b.b.atree_y[7].tmp[4] : 0 [by b.b.atree_y[7].and2s[0]._y:=1]
785174 b.b.vtree_x.OR2_tf[0]._y : 1 [by b.b.atree_x[1].in[0]:=0]
785209 b.b.vtree_y.ct.in[1] : 0 [by b.b.vtree_y.OR2_tf[1]._y:=1]
786018 b.b.atree_x[4].in[2] : 0 [by b.b.addr_buf.t_buf_func[2]._y:=1]
786122 b.b.vtree_x.OR2_tf[2]._y : 1 [by b.b.atree_x[4].in[2]:=0]
786163 b.b.vtree_x.ct.in[2] : 0 [by b.b.vtree_x.OR2_tf[2]._y:=1]
786212 b.b.atree_y[15].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
786213 b.b.atree_y[15].tmp[5] : 0 [by b.b.atree_y[15].and2s[1]._y:=1]
786214 b.b.atree_y[15].and2s[2]._y : 1 [by b.b.atree_y[15].tmp[5]:=0]
786298 b.b.vtree_x.ct.in[0] : 0 [by b.b.vtree_x.OR2_tf[0]._y:=1]
786409 b.b.addr_buf.out_a_B_buf_t.buf2._y : 1 [by b.b.addr_buf._out_a_B:=0]
787081 b.b.atree_x[7].and3s[0]._y : 1 [by b.b.atree_x[1].in[0]:=0]
787082 b.outx[7] : 0 [by b.b.atree_x[7].and3s[0]._y:=1]
787926 b.b.addr_buf.t_buf_func[3]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
788309 b.b.atree_x[2].in[1] : 0 [by b.b.addr_buf.t_buf_func[1]._y:=1]
791445 b.b.vtree_x.OR2_tf[1]._y : 1 [by b.b.atree_x[2].in[1]:=0]
792271 b.b.vtree_x.ct.in[1] : 0 [by b.b.vtree_x.OR2_tf[1]._y:=1]
794104 b.b.vtree_x.ct.C3Els[0]._y : 1 [by b.b.vtree_x.ct.in[1]:=0]
796624 b.b.atree_y[13].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
796682 b.b.atree_y[13].tmp[5] : 0 [by b.b.atree_y[13].and2s[1]._y:=1]
799581 b.b.addr_buf._out_a_BX_f[0] : 0 [by b.b.addr_buf.out_a_B_buf_t.buf2._y:=1]
805165 b.b.addr_buf.t_buf_func[5]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
806736 b.b.atree_y[3].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
807608 b.b.atree_y[4].in[2] : 0 [by b.b.addr_buf.t_buf_func[5]._y:=1]
807645 b.b.atree_y[11].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
807659 b.b.atree_y[11].tmp[4] : 0 [by b.b.atree_y[11].and2s[0]._y:=1]
807751 b.b.atree_y[1].in[0] : 0 [by b.b.addr_buf.t_buf_func[3]._y:=1]
808107 b.b.vtree_y.OR2_tf[0]._y : 1 [by b.b.atree_y[1].in[0]:=0]
810652 b.b.C2el.c1 : 0 [by b.b.vtree_x.ct.C3Els[0]._y:=1]
812671 b.b.atree_y[14].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
812776 b.b.atree_y[14].tmp[5] : 0 [by b.b.atree_y[14].and2s[1]._y:=1]
823509 b.b.atree_y[3].tmp[4] : 0 [by b.b.atree_y[3].and2s[0]._y:=1]
824626 b.b.atree_y[15].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
824735 b.b.atree_y[15].tmp[4] : 0 [by b.b.atree_y[15].and2s[0]._y:=1]
843945 b.b.vtree_y.ct.in[0] : 0 [by b.b.vtree_y.OR2_tf[0]._y:=1]
843946 b.b.vtree_y.ct.C2Els[0]._y : 1 [by b.b.vtree_y.ct.in[0]:=0]
843955 b.b.vtree_y.ct.tmp[4] : 0 [by b.b.vtree_y.ct.C2Els[0]._y:=1]
844807 b.b.vtree_y.OR2_tf[2]._y : 1 [by b.b.atree_y[4].in[2]:=0]
850592 b.outy[15] : 0 [by b.b.atree_y[15].and2s[2]._y:=1]
882760 b.b.vtree_y.ct.in[2] : 0 [by b.b.vtree_y.OR2_tf[2]._y:=1]
882761 b.b.vtree_y.ct.C2Els[1]._y : 1 [by b.b.vtree_y.ct.in[2]:=0]
919155 b.b.vtree_y.ct.tmp[5] : 0 [by b.b.vtree_y.ct.C2Els[1]._y:=1]
919156 b.b.vtree_y.ct.C2Els[2]._y : 1 [by b.b.vtree_y.ct.tmp[5]:=0]
922245 b.b.C2el.c2 : 0 [by b.b.vtree_y.ct.C2Els[2]._y:=1]
970971 b.b.C2el._y : 1 [by b.b.C2el.c2:=0]
971721 b.b.C2el.y : 0 [by b.b.C2el._y:=1]
978476 b.b.dly.and2[0]._y : 1 [by b.b.C2el.y:=0]
978527 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
978537 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
978857 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
986439 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
986440 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
986441 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
988171 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
989858 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
989873 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
1014147 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
1014601 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
1014917 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
1014918 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
1015301 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
1022764 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
1022784 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
1024107 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
1024194 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
1030916 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
1030928 b.b.dly.mu2[2]._y : 1 [by b.b.dly._a[2]:=0]
1031073 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
1031974 b.b.dly.mu2[3]._y : 1 [by b.b.dly._a[3]:=0]
1033323 b.b.dly.out : 0 [by b.b.dly.mu2[3]._y:=1]
1033542 b.b.addr_buf._out_a_B : 1 [by b.b.dly.out:=0]
1041873 b.b.addr_buf.out_a_B_buf_t.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
1041891 b.b.addr_buf._out_a_BX_f[0] : 1 [by b.b.addr_buf.out_a_B_buf_t.buf2._y:=0]
1065123 b.b.addr_buf.out_a_B_buf_f.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
1067317 b.b.addr_buf._out_a_BX_t[0] : 1 [by b.b.addr_buf.out_a_B_buf_f.buf2._y:=0]
test/unit_tests/decoder_2d_dly_8_16/run/prsim.pdf
BIN
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test/unit_tests/decoder_2d_dly_8_16/run/test.prs
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test/unit_tests/decoder_2d_dly_8_16/test.act
-47
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@@ -1,47 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc decoder_2d_dly_8_16(avMx1of2<3+4> in; bool? outx[8], outy[16], dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
decoder_2d_dly<3,4,8,16,4> b(.in = in, .outx = outx, .outy = outy, .dly_cfg = dly_cfg);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
decoder_2d_dly_8_16 b;
test/unit_tests/decoder_2d_dly_8_16/test.prsim
-59
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@@ -1,59 +0,0 @@
watchall
set-qdi-channel-neutral "b.in" 7
set b.b.addr_buf.out.a 0
set Reset 0
# Set delay config lines
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
system "echo '[] Sending packet in'"
set-qdi-channel-valid "b.in" 7 127
cycle
assert b.in.a 1
assert b.in.v 1
# system "echo '[]' Setting ack from DLY high"
# set b.b.addr_buf.out.a 1
cycle
assert b.outx[0] 0
assert b.outx[1] 0
assert b.outx[2] 0
assert b.outx[3] 0
assert b.outx[4] 0
assert b.outx[5] 0
assert b.outx[6] 0
assert b.outx[7] 0
assert b.outy[0] 0
assert b.outy[1] 0
assert b.outy[2] 0
assert b.outy[3] 0
assert b.outy[4] 0
assert b.outy[5] 0
assert b.outy[6] 0
assert b.outy[7] 0
assert b.outy[8] 0
assert b.outy[9] 0
assert b.outy[10] 0
assert b.outy[11] 0
assert b.outy[12] 0
assert b.outy[13] 0
assert b.outy[14] 0
assert b.outy[15] 0
test/unit_tests/decoder_2d_dly_and_2_4/run/test.prs
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@@ -1,3 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
test/unit_tests/decoder_2d_dly_and_2_4/test.act
-52
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@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc decoder_2d_dly_and_2_4(avMx1of2<1+2> in; bool? out[2*4], dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
decoder_2d_dly<1,2,2,4,4> de(.in = in, .dly_cfg = dly_cfg);
de.supply.vdd = Vdd;
de.supply.vss = GND;
de.reset_B = _reset_B;
and_grid<2,4> ag(.inx = de.outx, .iny = de.outy, .out = out);
ag.supply.vdd = Vdd;
ag.supply.vss = GND;
}
decoder_2d_dly_and_2_4 t;
test/unit_tests/decoder_2d_dly_and_2_4/test.prsim
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@@ -1,57 +0,0 @@
watchall
set-qdi-channel-neutral "t.in" 3
set Reset 0
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
set t.dly_cfg[2] 1
set t.dly_cfg[3] 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
system "echo '[] Sending packet in'"
set-qdi-channel-valid "t.in" 3 7
cycle
assert t.in.a 1
assert t.in.v 1
# system "echo '[]' Setting ack from DLY high"
# set b.b.addr_buf.out.a 1
# cycle
# assert b.outx[0] 0
# assert b.outx[1] 0
# assert b.outx[2] 0
# assert b.outx[3] 0
# assert b.outx[4] 0
# assert b.outx[5] 0
# assert b.outx[6] 0
# assert b.outx[7] 0
# assert b.outy[0] 0
# assert b.outy[1] 0
# assert b.outy[2] 0
# assert b.outy[3] 0
# assert b.outy[4] 0
# assert b.outy[5] 0
# assert b.outy[6] 0
# assert b.outy[7] 0
# assert b.outy[8] 0
# assert b.outy[9] 0
# assert b.outy[10] 0
# assert b.outy[11] 0
# assert b.outy[12] 0
# assert b.outy[13] 0
# assert b.outy[14] 0
# assert b.outy[15] 0
test/unit_tests/decoder_2d_hs/run/prsim.out
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@@ -1,460 +0,0 @@
e.in.d.d[2].t e.in.d.d[1].f e.in.d.d[0].f e.in.d.d[2].f e.decoder.addr_buf._in_v e.in.d.d[1].t e.decoder.addr_buf.vc.ct.in[0] e.decoder.addr_buf.vc.ct.in[1] e.in.d.d[0].t e.decoder.addr_buf.vc.ct.C3Els[0]._y e.decoder.addr_buf.vc.OR2_tf[0]._y e.in.v e.decoder.addr_buf.in_v_buf._y e.decoder.addr_buf.vc.ct.in[2] e.decoder.addr_buf.vc.OR2_tf[2]._y e.decoder.addr_buf.vc.OR2_tf[1]._y
162088 e.in.d.d[0].f : 0
162088 e.in.d.d[2].t : 0
162088 e.in.d.d[2].f : 0
162088 e.in.d.d[1].t : 0
162088 e.in.d.d[1].f : 0
162088 e.in.d.d[0].t : 0
162104 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1 [by e.in.d.d[1].f:=0]
162632 e.decoder.addr_buf.vc.ct.in[1] : 0 [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
164729 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1 [by e.in.d.d[2].f:=0]
166650 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1 [by e.in.d.d[0].t:=0]
167164 e.decoder.addr_buf.vc.ct.in[2] : 0 [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
193530 e.decoder.addr_buf.vc.ct.in[0] : 0 [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
217455 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1 [by e.decoder.addr_buf.vc.ct.in[0]:=0]
230496 e.decoder.addr_buf._in_v : 0 [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
230498 e.decoder.addr_buf.in_v_buf._y : 1 [by e.decoder.addr_buf._in_v:=0]
291456 e.in.v : 0 [by e.decoder.addr_buf.in_v_buf._y:=1]
[] Set reset 0
291456 Reset : 0
291459 e._reset_B : 1 [by Reset:=0]
291488 e.decoder.addr_buf.reset_buf._y : 0 [by e._reset_B:=1]
291805 e.decoder.addr_buf._reset_BX : 1 [by e.decoder.addr_buf.reset_buf._y:=0]
293406 e.decoder.addr_buf.reset_bufarray.buf1._y : 0 [by e.decoder.addr_buf._reset_BX:=1]
293559 e.decoder.addr_buf._reset_BXX[0] : 1 [by e.decoder.addr_buf.reset_bufarray.buf1._y:=0]
[] Sending in a 7 packet
293559 e.in.d.d[0].t : 1
293559 e.in.d.d[2].t : 1
293559 e.in.d.d[1].t : 1
293560 e.decoder.addr_buf.t_buf_func[2]._y : 0 [by e.in.d.d[2].t:=1]
293561 e.decoder.d_dr_y.in_tX[1].in : 1 [by e.decoder.addr_buf.t_buf_func[2]._y:=0]
293581 e.decoder.addr_buf.t_buf_func[1]._y : 0 [by e.in.d.d[1].t:=1]
293603 e.decoder.addr_buf.vc.OR2_tf[0]._y : 0 [by e.in.d.d[0].t:=1]
293740 e.decoder.d_dr_y.in_tX[0].in : 1 [by e.decoder.addr_buf.t_buf_func[1]._y:=0]
293776 e.decoder.addr_buf.vc.OR2_tf[1]._y : 0 [by e.in.d.d[1].t:=1]
293921 e.decoder.addr_buf.vc.ct.in[1] : 1 [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=0]
295027 e.decoder.d_dr_y.in_tX[0].buf1._y : 0 [by e.decoder.d_dr_y.in_tX[0].in:=1]
295142 e.decoder.d_dr_y.in_tX[1].buf1._y : 0 [by e.decoder.d_dr_y.in_tX[1].in:=1]
295972 e.decoder.vtree_y.OR2_tf[0]._y : 0 [by e.decoder.d_dr_y.in_tX[0].in:=1]
295973 e.decoder.vtree_y.ct.in[0] : 1 [by e.decoder.vtree_y.OR2_tf[0]._y:=0]
296320 e.decoder.addr_buf.t_buf_func[0]._y : 0 [by e.in.d.d[0].t:=1]
297859 e.decoder.d_dr_y.atree[1].in[0] : 1 [by e.decoder.d_dr_y.in_tX[0].buf1._y:=0]
301496 e.decoder.d_dr_y.atree[2].in[1] : 1 [by e.decoder.d_dr_y.in_tX[1].buf1._y:=0]
301658 e.decoder.d_dr_y.atree[3].and2s[0]._y : 0 [by e.decoder.d_dr_y.atree[2].in[1]:=1]
302906 e.decoder.vtree_y.OR2_tf[1]._y : 0 [by e.decoder.d_dr_y.in_tX[1].in:=1]
302920 e.decoder.vtree_y.ct.in[1] : 1 [by e.decoder.vtree_y.OR2_tf[1]._y:=0]
302927 e.decoder.vtree_y.ct.C2Els[0]._y : 0 [by e.decoder.vtree_y.ct.in[1]:=1]
303087 e.decoder.vtree_y.out : 1 [by e.decoder.vtree_y.ct.C2Els[0]._y:=0]
307242 e.decoder.addr_buf.vc.OR2_tf[2]._y : 0 [by e.in.d.d[2].t:=1]
309027 e.decoder.d_dr_y.out[3] : 1 [by e.decoder.d_dr_y.atree[3].and2s[0]._y:=0]
309028 e.decoder._and_grid.ybuf[3].buf1._y : 0 [by e.decoder.d_dr_y.out[3]:=1]
309029 e.decoder._and_grid.ands[6].b : 1 [by e.decoder._and_grid.ybuf[3].buf1._y:=0]
313279 e.decoder.addr_buf.vc.ct.in[0] : 1 [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=0]
328799 e.decoder.addr_buf.vc.ct.in[2] : 1 [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=0]
328800 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 0 [by e.decoder.addr_buf.vc.ct.in[2]:=1]
331043 e.decoder.addr_buf._in_v : 1 [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=0]
331230 e.decoder.addr_buf.in_v_buf._y : 0 [by e.decoder.addr_buf._in_v:=1]
331231 e.in.v : 1 [by e.decoder.addr_buf.in_v_buf._y:=0]
335604 e.decoder.d_dr_x.in_tX[0].in : 1 [by e.decoder.addr_buf.t_buf_func[0]._y:=0]
339786 e.decoder.d_dr_x.in_tX[0].buf1._y : 0 [by e.decoder.d_dr_x.in_tX[0].in:=1]
339787 e.decoder.d_dr_x.atree[1].in[0] : 1 [by e.decoder.d_dr_x.in_tX[0].buf1._y:=0]
340640 e.decoder.d_dr_x.atree[1].b._y : 0 [by e.decoder.d_dr_x.atree[1].in[0]:=1]
340645 e.decoder.d_dr_x.out[1] : 1 [by e.decoder.d_dr_x.atree[1].b._y:=0]
340646 e.decoder.d_dr_xX[1].buf2._y : 0 [by e.decoder.d_dr_x.out[1]:=1]
340663 e.decoder.pu_ANDs[1].a : 1 [by e.decoder.d_dr_xX[1].buf2._y:=0]
341536 e.decoder._and_grid.xbuf[1].buf1._y : 0 [by e.decoder.d_dr_x.out[1]:=1]
343236 e.decoder.pu_ANDs[1]._y : 0 [by e.decoder.pu_ANDs[1].a:=1]
343239 e.decoder.pu[1].a : 1 [by e.decoder.pu_ANDs[1]._y:=0]
349897 e.decoder._and_grid.ands[1].a : 1 [by e.decoder._and_grid.xbuf[1].buf1._y:=0]
350838 e.decoder._and_grid.ands[7]._y : 0 [by e.decoder._and_grid.ands[1].a:=1]
370386 e.decoder.vtree_x.OR2_tf[0]._y : 0 [by e.decoder.d_dr_x.in_tX[0].in:=1]
370387 e.decoder.vtree_x.ct.in[0] : 1 [by e.decoder.vtree_x.OR2_tf[0]._y:=0]
370429 e.decoder.vtree_x.ct.b._y : 0 [by e.decoder.vtree_x.ct.in[0]:=1]
373246 e.decoder.vtree_x.out : 1 [by e.decoder.vtree_x.ct.b._y:=0]
386979 e.decoder.valid_Cel._y : 0 [by e.decoder.vtree_x.out:=1]
387074 e.decoder.valid_Cel.y : 1 [by e.decoder.valid_Cel._y:=0]
387409 e.decoder.addr_buf.inack_ctl._y : 0 [by e.decoder.valid_Cel.y:=1]
387417 e.in.a : 1 [by e.decoder.addr_buf.inack_ctl._y:=0]
387451 e.decoder.addr_buf._en : 0 [by e.in.a:=1]
388369 e.decoder.addr_buf.en_buf_t.buf1._y : 1 [by e.decoder.addr_buf._en:=0]
388373 e.decoder.addr_buf._en_X_t[0] : 0 [by e.decoder.addr_buf.en_buf_t.buf1._y:=1]
401338 e.decoder.addr_buf.en_buf_f.buf1._y : 1 [by e.decoder.addr_buf._en:=0]
409800 e.out[7].r : 1 [by e.decoder._and_grid.ands[7]._y:=0]
412198 e.synapses[7].y : 0 [by e.out[7].r:=1]
447716 e.decoder.addr_buf._en_X_f[0] : 0 [by e.decoder.addr_buf.en_buf_f.buf1._y:=1]
[] Removing input
[] Synapse [7] gives ack
447716 e.in.d.d[0].t : 0
447716 e.out[7].a : 1
447716 e.in.d.d[2].t : 0
447716 e.in.d.d[1].t : 0
447719 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1 [by e.in.d.d[1].t:=0]
447764 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1 [by e.in.d.d[2].t:=0]
447897 e.decoder.addr_buf.vc.ct.in[1] : 0 [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
450931 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1 [by e.in.d.d[0].t:=0]
462830 e.decoder.addr_buf.vc.ct.in[0] : 0 [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
468741 e.decoder.addr_buf.vc.ct.in[2] : 0 [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
474692 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1 [by e.decoder.addr_buf.vc.ct.in[2]:=0]
494835 e.decoder._out_acksB[1] : 0 [by e.out[7].a:=1]
495662 e.decoder._ortree.in[1] : 1 [by e.decoder._out_acksB[1]:=0]
495835 e.decoder._ortree.or2s[0]._y : 0 [by e.decoder._ortree.in[1]:=1]
496019 e.decoder._ortree.out : 1 [by e.decoder._ortree.or2s[0]._y:=0]
496020 e.decoder.buf_ack_Cel._y : 0 [by e.decoder._ortree.out:=1]
496093 e.decoder.buf_ack_Cel.y : 1 [by e.decoder.buf_ack_Cel._y:=0]
496097 e.decoder.addr_buf._out_a_B : 0 [by e.decoder.buf_ack_Cel.y:=1]
496193 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 1 [by e.decoder.addr_buf._out_a_B:=0]
496329 e.decoder.addr_buf._out_a_BX_t[0] : 0 [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=1]
496330 e.decoder.addr_buf.t_buf_func[0]._y : 1 [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
496570 e.decoder.addr_buf.t_buf_func[2]._y : 1 [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
496582 e.decoder.d_dr_y.in_tX[1].in : 0 [by e.decoder.addr_buf.t_buf_func[2]._y:=1]
497611 e.decoder.vtree_y.OR2_tf[1]._y : 1 [by e.decoder.d_dr_y.in_tX[1].in:=0]
497612 e.decoder.vtree_y.ct.in[1] : 0 [by e.decoder.vtree_y.OR2_tf[1]._y:=1]
500289 e.decoder.d_dr_x.in_tX[0].in : 0 [by e.decoder.addr_buf.t_buf_func[0]._y:=1]
500345 e.decoder.d_dr_x.in_tX[0].buf1._y : 1 [by e.decoder.d_dr_x.in_tX[0].in:=0]
500346 e.decoder.d_dr_x.atree[1].in[0] : 0 [by e.decoder.d_dr_x.in_tX[0].buf1._y:=1]
500383 e.decoder.d_dr_x.atree[1].b._y : 1 [by e.decoder.d_dr_x.atree[1].in[0]:=0]
500482 e.decoder.d_dr_y.in_tX[1].buf1._y : 1 [by e.decoder.d_dr_y.in_tX[1].in:=0]
500483 e.decoder.d_dr_y.atree[2].in[1] : 0 [by e.decoder.d_dr_y.in_tX[1].buf1._y:=1]
504047 e.decoder.d_dr_y.atree[3].and2s[0]._y : 1 [by e.decoder.d_dr_y.atree[2].in[1]:=0]
505739 e.decoder.d_dr_y.out[3] : 0 [by e.decoder.d_dr_y.atree[3].and2s[0]._y:=1]
505752 e.decoder._and_grid.ybuf[3].buf1._y : 1 [by e.decoder.d_dr_y.out[3]:=0]
514177 e.decoder.addr_buf._in_v : 0 [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
514534 e.decoder.addr_buf.in_v_buf._y : 1 [by e.decoder.addr_buf._in_v:=0]
514559 e.in.v : 0 [by e.decoder.addr_buf.in_v_buf._y:=1]
515375 e.decoder.addr_buf.t_buf_func[1]._y : 1 [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
515396 e.decoder.d_dr_y.in_tX[0].in : 0 [by e.decoder.addr_buf.t_buf_func[1]._y:=1]
515397 e.decoder.d_dr_y.in_tX[0].buf1._y : 1 [by e.decoder.d_dr_y.in_tX[0].in:=0]
515398 e.decoder.d_dr_y.atree[1].in[0] : 0 [by e.decoder.d_dr_y.in_tX[0].buf1._y:=1]
522736 e.decoder._and_grid.ands[6].b : 0 [by e.decoder._and_grid.ybuf[3].buf1._y:=1]
522737 e.decoder._and_grid.ands[7]._y : 1 [by e.decoder._and_grid.ands[6].b:=0]
522898 e.out[7].r : 0 [by e.decoder._and_grid.ands[7]._y:=1]
523758 e.decoder.d_dr_x.out[1] : 0 [by e.decoder.d_dr_x.atree[1].b._y:=1]
523763 e.decoder._and_grid.xbuf[1].buf1._y : 1 [by e.decoder.d_dr_x.out[1]:=0]
523935 e.synapses[7].y : 1 [by e.out[7].r:=0]
523946 e.out[7].a : 0 [by e.synapses[7].y:=1]
524171 e.decoder._and_grid.ands[1].a : 0 [by e.decoder._and_grid.xbuf[1].buf1._y:=1]
524339 e.decoder.d_dr_xX[1].buf2._y : 1 [by e.decoder.d_dr_x.out[1]:=0]
525044 e.decoder.vtree_y.OR2_tf[0]._y : 1 [by e.decoder.d_dr_y.in_tX[0].in:=0]
525058 e.decoder.vtree_y.ct.in[0] : 0 [by e.decoder.vtree_y.OR2_tf[0]._y:=1]
525076 e.decoder.vtree_y.ct.C2Els[0]._y : 1 [by e.decoder.vtree_y.ct.in[0]:=0]
525080 e.decoder.vtree_y.out : 0 [by e.decoder.vtree_y.ct.C2Els[0]._y:=1]
525386 e.decoder.pu_ANDs[1].a : 0 [by e.decoder.d_dr_xX[1].buf2._y:=1]
525490 e.decoder.pu_ANDs[1]._y : 1 [by e.decoder.pu_ANDs[1].a:=0]
533385 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 1 [by e.decoder.addr_buf._out_a_B:=0]
534589 e.decoder.addr_buf._out_a_BX_f[0] : 0 [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=1]
545295 e.decoder.vtree_x.OR2_tf[0]._y : 1 [by e.decoder.d_dr_x.in_tX[0].in:=0]
553750 e.decoder.vtree_x.ct.in[0] : 0 [by e.decoder.vtree_x.OR2_tf[0]._y:=1]
553978 e.decoder.vtree_x.ct.b._y : 1 [by e.decoder.vtree_x.ct.in[0]:=0]
554821 e.decoder.vtree_x.out : 0 [by e.decoder.vtree_x.ct.b._y:=1]
556280 e.decoder.valid_Cel._y : 1 [by e.decoder.vtree_x.out:=0]
556350 e.decoder.valid_Cel.y : 0 [by e.decoder.valid_Cel._y:=1]
556934 e.decoder.pu[1].a : 0 [by e.decoder.pu_ANDs[1]._y:=1]
556945 e.decoder._out_acksB[1] : 1 [by e.decoder.pu[1].a:=0]
556948 e.decoder._ortree.in[1] : 0 [by e.decoder._out_acksB[1]:=1]
557002 e.decoder._ortree.or2s[0]._y : 1 [by e.decoder._ortree.in[1]:=0]
558150 e.decoder._ortree.out : 0 [by e.decoder._ortree.or2s[0]._y:=1]
559311 e.decoder.buf_ack_Cel._y : 1 [by e.decoder._ortree.out:=0]
567963 e.decoder.buf_ack_Cel.y : 0 [by e.decoder.buf_ack_Cel._y:=1]
568044 e.decoder.addr_buf._out_a_B : 1 [by e.decoder.buf_ack_Cel.y:=0]
579121 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 0 [by e.decoder.addr_buf._out_a_B:=1]
579213 e.decoder.addr_buf._out_a_BX_f[0] : 1 [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=0]
586027 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 0 [by e.decoder.addr_buf._out_a_B:=1]
594338 e.decoder.addr_buf._out_a_BX_t[0] : 1 [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=0]
606772 e.decoder.addr_buf.inack_ctl._y : 1 [by e.decoder.valid_Cel.y:=0]
608516 e.in.a : 0 [by e.decoder.addr_buf.inack_ctl._y:=1]
609129 e.decoder.addr_buf._en : 1 [by e.in.a:=0]
609174 e.decoder.addr_buf.en_buf_t.buf1._y : 0 [by e.decoder.addr_buf._en:=1]
610171 e.decoder.addr_buf._en_X_t[0] : 1 [by e.decoder.addr_buf.en_buf_t.buf1._y:=0]
623151 e.decoder.addr_buf.en_buf_f.buf1._y : 0 [by e.decoder.addr_buf._en:=1]
624800 e.decoder.addr_buf._en_X_f[0] : 1 [by e.decoder.addr_buf.en_buf_f.buf1._y:=0]
[] Sending in a 5 packet
624800 e.in.d.d[0].t : 1
624800 e.in.d.d[2].t : 1
624800 e.in.d.d[1].f : 1
624807 e.decoder.addr_buf.t_buf_func[2]._y : 0 [by e.in.d.d[2].t:=1]
624809 e.decoder.d_dr_y.in_tX[1].in : 1 [by e.decoder.addr_buf.t_buf_func[2]._y:=0]
624852 e.decoder.addr_buf.vc.OR2_tf[2]._y : 0 [by e.in.d.d[2].t:=1]
624853 e.decoder.addr_buf.vc.ct.in[2] : 1 [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=0]
624942 e.decoder.vtree_y.OR2_tf[1]._y : 0 [by e.decoder.d_dr_y.in_tX[1].in:=1]
624946 e.decoder.vtree_y.ct.in[1] : 1 [by e.decoder.vtree_y.OR2_tf[1]._y:=0]
625163 e.decoder.d_dr_y.in_tX[1].buf1._y : 0 [by e.decoder.d_dr_y.in_tX[1].in:=1]
625325 e.decoder.addr_buf.vc.OR2_tf[0]._y : 0 [by e.in.d.d[0].t:=1]
625700 e.decoder.addr_buf.t_buf_func[0]._y : 0 [by e.in.d.d[0].t:=1]
625701 e.decoder.d_dr_x.in_tX[0].in : 1 [by e.decoder.addr_buf.t_buf_func[0]._y:=0]
625709 e.decoder.d_dr_y.atree[2].in[1] : 1 [by e.decoder.d_dr_y.in_tX[1].buf1._y:=0]
625780 e.decoder.vtree_x.OR2_tf[0]._y : 0 [by e.decoder.d_dr_x.in_tX[0].in:=1]
628213 e.decoder.vtree_x.ct.in[0] : 1 [by e.decoder.vtree_x.OR2_tf[0]._y:=0]
628301 e.decoder.vtree_x.ct.b._y : 0 [by e.decoder.vtree_x.ct.in[0]:=1]
631267 e.decoder.addr_buf.f_buf_func[1]._y : 0 [by e.in.d.d[1].f:=1]
636083 e.decoder.vtree_x.out : 1 [by e.decoder.vtree_x.ct.b._y:=0]
638079 e.decoder.d_dr_x.in_tX[0].buf1._y : 0 [by e.decoder.d_dr_x.in_tX[0].in:=1]
638138 e.decoder.d_dr_x.atree[1].in[0] : 1 [by e.decoder.d_dr_x.in_tX[0].buf1._y:=0]
638168 e.decoder.d_dr_x.atree[1].b._y : 0 [by e.decoder.d_dr_x.atree[1].in[0]:=1]
639635 e.decoder.d_dr_x.out[1] : 1 [by e.decoder.d_dr_x.atree[1].b._y:=0]
640412 e.decoder.addr_buf.vc.OR2_tf[1]._y : 0 [by e.in.d.d[1].f:=1]
641097 e.decoder.addr_buf.vc.ct.in[1] : 1 [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=0]
659019 e.decoder.d_dr_xX[1].buf2._y : 0 [by e.decoder.d_dr_x.out[1]:=1]
659594 e.decoder.d_dr_y.in_fX[0].in : 1 [by e.decoder.addr_buf.f_buf_func[1]._y:=0]
659721 e.decoder.d_dr_y.in_fX[0].buf1._y : 0 [by e.decoder.d_dr_y.in_fX[0].in:=1]
659763 e.decoder.vtree_y.OR2_tf[0]._y : 0 [by e.decoder.d_dr_y.in_fX[0].in:=1]
659764 e.decoder.d_dr_y.atree[0].in[0] : 1 [by e.decoder.d_dr_y.in_fX[0].buf1._y:=0]
659775 e.decoder.vtree_y.ct.in[0] : 1 [by e.decoder.vtree_y.OR2_tf[0]._y:=0]
660008 e.decoder.vtree_y.ct.C2Els[0]._y : 0 [by e.decoder.vtree_y.ct.in[0]:=1]
660011 e.decoder.vtree_y.out : 1 [by e.decoder.vtree_y.ct.C2Els[0]._y:=0]
660049 e.decoder.valid_Cel._y : 0 [by e.decoder.vtree_y.out:=1]
660050 e.decoder.valid_Cel.y : 1 [by e.decoder.valid_Cel._y:=0]
661043 e.decoder.d_dr_y.atree[2].and2s[0]._y : 0 [by e.decoder.d_dr_y.atree[0].in[0]:=1]
670888 e.decoder.addr_buf.vc.ct.in[0] : 1 [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=0]
670980 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 0 [by e.decoder.addr_buf.vc.ct.in[0]:=1]
673707 e.decoder.addr_buf._in_v : 1 [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=0]
673709 e.decoder.addr_buf.in_v_buf._y : 0 [by e.decoder.addr_buf._in_v:=1]
673710 e.in.v : 1 [by e.decoder.addr_buf.in_v_buf._y:=0]
673795 e.decoder.d_dr_y.out[2] : 1 [by e.decoder.d_dr_y.atree[2].and2s[0]._y:=0]
673797 e.decoder._and_grid.ybuf[2].buf1._y : 0 [by e.decoder.d_dr_y.out[2]:=1]
673815 e.decoder._and_grid.ands[4].b : 1 [by e.decoder._and_grid.ybuf[2].buf1._y:=0]
675211 e.decoder.addr_buf.inack_ctl._y : 0 [by e.in.v:=1]
675330 e.in.a : 1 [by e.decoder.addr_buf.inack_ctl._y:=0]
675734 e.decoder.pu_ANDs[1].a : 1 [by e.decoder.d_dr_xX[1].buf2._y:=0]
675742 e.decoder.pu_ANDs[1]._y : 0 [by e.decoder.pu_ANDs[1].a:=1]
675796 e.decoder.pu[1].a : 1 [by e.decoder.pu_ANDs[1]._y:=0]
681050 e.decoder.addr_buf._en : 0 [by e.in.a:=1]
681055 e.decoder.addr_buf.en_buf_t.buf1._y : 1 [by e.decoder.addr_buf._en:=0]
682122 e.decoder.addr_buf._en_X_t[0] : 0 [by e.decoder.addr_buf.en_buf_t.buf1._y:=1]
699139 e.decoder._and_grid.xbuf[1].buf1._y : 0 [by e.decoder.d_dr_x.out[1]:=1]
699140 e.decoder._and_grid.ands[1].a : 1 [by e.decoder._and_grid.xbuf[1].buf1._y:=0]
699278 e.decoder._and_grid.ands[5]._y : 0 [by e.decoder._and_grid.ands[1].a:=1]
699279 e.out[5].r : 1 [by e.decoder._and_grid.ands[5]._y:=0]
699343 e.synapses[5].y : 0 [by e.out[5].r:=1]
731588 e.decoder.addr_buf.en_buf_f.buf1._y : 1 [by e.decoder.addr_buf._en:=0]
731711 e.decoder.addr_buf._en_X_f[0] : 0 [by e.decoder.addr_buf.en_buf_f.buf1._y:=1]
[] Removing input
[] Synapse [5] gives ack
731711 e.in.d.d[0].t : 0
731711 e.out[5].a : 1
731711 e.in.d.d[2].t : 0
731711 e.in.d.d[1].f : 0
731713 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1 [by e.in.d.d[0].t:=0]
731748 e.decoder._out_acksB[1] : 0 [by e.out[5].a:=1]
731759 e.decoder._ortree.in[1] : 1 [by e.decoder._out_acksB[1]:=0]
731760 e.decoder._ortree.or2s[0]._y : 0 [by e.decoder._ortree.in[1]:=1]
731762 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1 [by e.in.d.d[1].f:=0]
731769 e.decoder._ortree.out : 1 [by e.decoder._ortree.or2s[0]._y:=0]
731787 e.decoder.addr_buf.vc.ct.in[1] : 0 [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
731854 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1 [by e.in.d.d[2].t:=0]
732155 e.decoder.addr_buf.vc.ct.in[0] : 0 [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
735375 e.decoder.addr_buf.vc.ct.in[2] : 0 [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
735520 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1 [by e.decoder.addr_buf.vc.ct.in[2]:=0]
742022 e.decoder.buf_ack_Cel._y : 0 [by e.decoder._ortree.out:=1]
742252 e.decoder.buf_ack_Cel.y : 1 [by e.decoder.buf_ack_Cel._y:=0]
742943 e.decoder.addr_buf._out_a_B : 0 [by e.decoder.buf_ack_Cel.y:=1]
742957 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 1 [by e.decoder.addr_buf._out_a_B:=0]
744486 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 1 [by e.decoder.addr_buf._out_a_B:=0]
744568 e.decoder.addr_buf._out_a_BX_f[0] : 0 [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=1]
744579 e.decoder.addr_buf.f_buf_func[1]._y : 1 [by e.decoder.addr_buf._out_a_BX_f[0]:=0]
744580 e.decoder.d_dr_y.in_fX[0].in : 0 [by e.decoder.addr_buf.f_buf_func[1]._y:=1]
744581 e.decoder.d_dr_y.in_fX[0].buf1._y : 1 [by e.decoder.d_dr_y.in_fX[0].in:=0]
745220 e.decoder.d_dr_y.atree[0].in[0] : 0 [by e.decoder.d_dr_y.in_fX[0].buf1._y:=1]
747013 e.decoder.d_dr_y.atree[2].and2s[0]._y : 1 [by e.decoder.d_dr_y.atree[0].in[0]:=0]
747145 e.decoder.d_dr_y.out[2] : 0 [by e.decoder.d_dr_y.atree[2].and2s[0]._y:=1]
747146 e.decoder._and_grid.ybuf[2].buf1._y : 1 [by e.decoder.d_dr_y.out[2]:=0]
747163 e.decoder._and_grid.ands[4].b : 0 [by e.decoder._and_grid.ybuf[2].buf1._y:=1]
747315 e.decoder._and_grid.ands[5]._y : 1 [by e.decoder._and_grid.ands[4].b:=0]
750298 e.out[5].r : 0 [by e.decoder._and_grid.ands[5]._y:=1]
750301 e.synapses[5].y : 1 [by e.out[5].r:=0]
750725 e.out[5].a : 0 [by e.synapses[5].y:=1]
751081 e.decoder.vtree_y.OR2_tf[0]._y : 1 [by e.decoder.d_dr_y.in_fX[0].in:=0]
751087 e.decoder.vtree_y.ct.in[0] : 0 [by e.decoder.vtree_y.OR2_tf[0]._y:=1]
751688 e.decoder.addr_buf._in_v : 0 [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
754276 e.decoder.addr_buf.in_v_buf._y : 1 [by e.decoder.addr_buf._in_v:=0]
756737 e.in.v : 0 [by e.decoder.addr_buf.in_v_buf._y:=1]
761998 e.decoder.addr_buf._out_a_BX_t[0] : 0 [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=1]
762828 e.decoder.addr_buf.t_buf_func[0]._y : 1 [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
762830 e.decoder.d_dr_x.in_tX[0].in : 0 [by e.decoder.addr_buf.t_buf_func[0]._y:=1]
763024 e.decoder.d_dr_x.in_tX[0].buf1._y : 1 [by e.decoder.d_dr_x.in_tX[0].in:=0]
763162 e.decoder.d_dr_x.atree[1].in[0] : 0 [by e.decoder.d_dr_x.in_tX[0].buf1._y:=1]
763179 e.decoder.d_dr_x.atree[1].b._y : 1 [by e.decoder.d_dr_x.atree[1].in[0]:=0]
763196 e.decoder.d_dr_x.out[1] : 0 [by e.decoder.d_dr_x.atree[1].b._y:=1]
763197 e.decoder.d_dr_xX[1].buf2._y : 1 [by e.decoder.d_dr_x.out[1]:=0]
763198 e.decoder.pu_ANDs[1].a : 0 [by e.decoder.d_dr_xX[1].buf2._y:=1]
763433 e.decoder.vtree_x.OR2_tf[0]._y : 1 [by e.decoder.d_dr_x.in_tX[0].in:=0]
763434 e.decoder.vtree_x.ct.in[0] : 0 [by e.decoder.vtree_x.OR2_tf[0]._y:=1]
763453 e.decoder.vtree_x.ct.b._y : 1 [by e.decoder.vtree_x.ct.in[0]:=0]
763621 e.decoder.vtree_x.out : 0 [by e.decoder.vtree_x.ct.b._y:=1]
763622 e.decoder._and_grid.xbuf[1].buf1._y : 1 [by e.decoder.d_dr_x.out[1]:=0]
764161 e.decoder._and_grid.ands[1].a : 0 [by e.decoder._and_grid.xbuf[1].buf1._y:=1]
764224 e.decoder.pu_ANDs[1]._y : 1 [by e.decoder.pu_ANDs[1].a:=0]
764385 e.decoder.pu[1].a : 0 [by e.decoder.pu_ANDs[1]._y:=1]
764558 e.decoder._out_acksB[1] : 1 [by e.decoder.pu[1].a:=0]
767105 e.decoder._ortree.in[1] : 0 [by e.decoder._out_acksB[1]:=1]
782166 e.decoder._ortree.or2s[0]._y : 1 [by e.decoder._ortree.in[1]:=0]
782167 e.decoder._ortree.out : 0 [by e.decoder._ortree.or2s[0]._y:=1]
784930 e.decoder.addr_buf.t_buf_func[2]._y : 1 [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
784931 e.decoder.d_dr_y.in_tX[1].in : 0 [by e.decoder.addr_buf.t_buf_func[2]._y:=1]
785138 e.decoder.vtree_y.OR2_tf[1]._y : 1 [by e.decoder.d_dr_y.in_tX[1].in:=0]
785321 e.decoder.d_dr_y.in_tX[1].buf1._y : 1 [by e.decoder.d_dr_y.in_tX[1].in:=0]
785349 e.decoder.d_dr_y.atree[2].in[1] : 0 [by e.decoder.d_dr_y.in_tX[1].buf1._y:=1]
785971 e.decoder.vtree_y.ct.in[1] : 0 [by e.decoder.vtree_y.OR2_tf[1]._y:=1]
785978 e.decoder.vtree_y.ct.C2Els[0]._y : 1 [by e.decoder.vtree_y.ct.in[1]:=0]
786392 e.decoder.vtree_y.out : 0 [by e.decoder.vtree_y.ct.C2Els[0]._y:=1]
786396 e.decoder.valid_Cel._y : 1 [by e.decoder.vtree_y.out:=0]
788175 e.decoder.valid_Cel.y : 0 [by e.decoder.valid_Cel._y:=1]
788341 e.decoder.addr_buf.inack_ctl._y : 1 [by e.decoder.valid_Cel.y:=0]
811049 e.decoder.buf_ack_Cel._y : 1 [by e.decoder.valid_Cel.y:=0]
819694 e.decoder.buf_ack_Cel.y : 0 [by e.decoder.buf_ack_Cel._y:=1]
820627 e.decoder.addr_buf._out_a_B : 1 [by e.decoder.buf_ack_Cel.y:=0]
820766 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 0 [by e.decoder.addr_buf._out_a_B:=1]
821483 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 0 [by e.decoder.addr_buf._out_a_B:=1]
821678 e.decoder.addr_buf._out_a_BX_f[0] : 1 [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=0]
828211 e.in.a : 0 [by e.decoder.addr_buf.inack_ctl._y:=1]
828213 e.decoder.addr_buf._en : 1 [by e.in.a:=0]
828219 e.decoder.addr_buf.en_buf_t.buf1._y : 0 [by e.decoder.addr_buf._en:=1]
828473 e.decoder.addr_buf._en_X_t[0] : 1 [by e.decoder.addr_buf.en_buf_t.buf1._y:=0]
846975 e.decoder.addr_buf._out_a_BX_t[0] : 1 [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=0]
881662 e.decoder.addr_buf.en_buf_f.buf1._y : 0 [by e.decoder.addr_buf._en:=1]
881670 e.decoder.addr_buf._en_X_f[0] : 1 [by e.decoder.addr_buf.en_buf_f.buf1._y:=0]
[] Sending in a 1 packet
881670 e.in.d.d[0].t : 1
881670 e.in.d.d[2].f : 1
881670 e.in.d.d[1].f : 1
881671 e.decoder.addr_buf.vc.OR2_tf[0]._y : 0 [by e.in.d.d[0].t:=1]
881672 e.decoder.addr_buf.vc.ct.in[0] : 1 [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=0]
881676 e.decoder.addr_buf.t_buf_func[0]._y : 0 [by e.in.d.d[0].t:=1]
881682 e.decoder.d_dr_x.in_tX[0].in : 1 [by e.decoder.addr_buf.t_buf_func[0]._y:=0]
881684 e.decoder.d_dr_x.in_tX[0].buf1._y : 0 [by e.decoder.d_dr_x.in_tX[0].in:=1]
881699 e.decoder.d_dr_x.atree[1].in[0] : 1 [by e.decoder.d_dr_x.in_tX[0].buf1._y:=0]
881896 e.decoder.addr_buf.vc.OR2_tf[1]._y : 0 [by e.in.d.d[1].f:=1]
882003 e.decoder.addr_buf.vc.ct.in[1] : 1 [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=0]
882489 e.decoder.addr_buf.f_buf_func[1]._y : 0 [by e.in.d.d[1].f:=1]
882582 e.decoder.d_dr_y.in_fX[0].in : 1 [by e.decoder.addr_buf.f_buf_func[1]._y:=0]
884234 e.decoder.d_dr_y.in_fX[0].buf1._y : 0 [by e.decoder.d_dr_y.in_fX[0].in:=1]
884760 e.decoder.addr_buf.f_buf_func[2]._y : 0 [by e.in.d.d[2].f:=1]
884992 e.decoder.d_dr_y.atree[0].in[0] : 1 [by e.decoder.d_dr_y.in_fX[0].buf1._y:=0]
885244 e.decoder.vtree_x.OR2_tf[0]._y : 0 [by e.decoder.d_dr_x.in_tX[0].in:=1]
885960 e.decoder.vtree_x.ct.in[0] : 1 [by e.decoder.vtree_x.OR2_tf[0]._y:=0]
885961 e.decoder.vtree_x.ct.b._y : 0 [by e.decoder.vtree_x.ct.in[0]:=1]
886521 e.decoder.vtree_y.OR2_tf[0]._y : 0 [by e.decoder.d_dr_y.in_fX[0].in:=1]
886522 e.decoder.vtree_y.ct.in[0] : 1 [by e.decoder.vtree_y.OR2_tf[0]._y:=0]
887383 e.decoder.d_dr_y.in_fX[1].in : 1 [by e.decoder.addr_buf.f_buf_func[2]._y:=0]
887701 e.decoder.vtree_x.out : 1 [by e.decoder.vtree_x.ct.b._y:=0]
899535 e.decoder.d_dr_y.in_fX[1].buf1._y : 0 [by e.decoder.d_dr_y.in_fX[1].in:=1]
899536 e.decoder.d_dr_y.atree[0].in[1] : 1 [by e.decoder.d_dr_y.in_fX[1].buf1._y:=0]
899542 e.decoder.d_dr_y.atree[0].and2s[0]._y : 0 [by e.decoder.d_dr_y.atree[0].in[1]:=1]
899543 e.decoder.d_dr_y.out[0] : 1 [by e.decoder.d_dr_y.atree[0].and2s[0]._y:=0]
902500 e.decoder.d_dr_x.atree[1].b._y : 0 [by e.decoder.d_dr_x.atree[1].in[0]:=1]
915582 e.decoder.vtree_y.OR2_tf[1]._y : 0 [by e.decoder.d_dr_y.in_fX[1].in:=1]
915604 e.decoder.vtree_y.ct.in[1] : 1 [by e.decoder.vtree_y.OR2_tf[1]._y:=0]
924099 e.decoder.d_dr_x.out[1] : 1 [by e.decoder.d_dr_x.atree[1].b._y:=0]
924106 e.decoder._and_grid.xbuf[1].buf1._y : 0 [by e.decoder.d_dr_x.out[1]:=1]
924119 e.decoder._and_grid.ands[1].a : 1 [by e.decoder._and_grid.xbuf[1].buf1._y:=0]
924164 e.decoder.d_dr_xX[1].buf2._y : 0 [by e.decoder.d_dr_x.out[1]:=1]
925288 e.decoder.pu_ANDs[1].a : 1 [by e.decoder.d_dr_xX[1].buf2._y:=0]
925392 e.decoder.pu_ANDs[1]._y : 0 [by e.decoder.pu_ANDs[1].a:=1]
925433 e.decoder.pu[1].a : 1 [by e.decoder.pu_ANDs[1]._y:=0]
932706 e.decoder.addr_buf.vc.OR2_tf[2]._y : 0 [by e.in.d.d[2].f:=1]
932707 e.decoder.addr_buf.vc.ct.in[2] : 1 [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=0]
932708 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 0 [by e.decoder.addr_buf.vc.ct.in[2]:=1]
938112 e.decoder.vtree_y.ct.C2Els[0]._y : 0 [by e.decoder.vtree_y.ct.in[1]:=1]
939032 e.decoder._and_grid.ybuf[0].buf1._y : 0 [by e.decoder.d_dr_y.out[0]:=1]
939033 e.decoder._and_grid.ands[0].b : 1 [by e.decoder._and_grid.ybuf[0].buf1._y:=0]
951284 e.decoder.vtree_y.out : 1 [by e.decoder.vtree_y.ct.C2Els[0]._y:=0]
954420 e.decoder.valid_Cel._y : 0 [by e.decoder.vtree_y.out:=1]
955246 e.decoder.valid_Cel.y : 1 [by e.decoder.valid_Cel._y:=0]
958858 e.decoder._and_grid.ands[1]._y : 0 [by e.decoder._and_grid.ands[0].b:=1]
960691 e.out[1].r : 1 [by e.decoder._and_grid.ands[1]._y:=0]
977239 e.synapses[1].y : 0 [by e.out[1].r:=1]
997086 e.decoder.addr_buf._in_v : 1 [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=0]
997144 e.decoder.addr_buf.in_v_buf._y : 0 [by e.decoder.addr_buf._in_v:=1]
999587 e.in.v : 1 [by e.decoder.addr_buf.in_v_buf._y:=0]
1016360 e.decoder.addr_buf.inack_ctl._y : 0 [by e.in.v:=1]
1053559 e.in.a : 1 [by e.decoder.addr_buf.inack_ctl._y:=0]
1053573 e.decoder.addr_buf._en : 0 [by e.in.a:=1]
1053929 e.decoder.addr_buf.en_buf_f.buf1._y : 1 [by e.decoder.addr_buf._en:=0]
1054034 e.decoder.addr_buf._en_X_f[0] : 0 [by e.decoder.addr_buf.en_buf_f.buf1._y:=1]
1089411 e.decoder.addr_buf.en_buf_t.buf1._y : 1 [by e.decoder.addr_buf._en:=0]
1089520 e.decoder.addr_buf._en_X_t[0] : 0 [by e.decoder.addr_buf.en_buf_t.buf1._y:=1]
[] Synapse [5] gives ack
1089520 e.out[1].a : 1
1089521 e.decoder._out_acksB[1] : 0 [by e.out[1].a:=1]
1089530 e.decoder._ortree.in[1] : 1 [by e.decoder._out_acksB[1]:=0]
1127483 e.decoder._ortree.or2s[0]._y : 0 [by e.decoder._ortree.in[1]:=1]
1127484 e.decoder._ortree.out : 1 [by e.decoder._ortree.or2s[0]._y:=0]
1163878 e.decoder.buf_ack_Cel._y : 0 [by e.decoder._ortree.out:=1]
1163879 e.decoder.buf_ack_Cel.y : 1 [by e.decoder.buf_ack_Cel._y:=0]
1166968 e.decoder.addr_buf._out_a_B : 0 [by e.decoder.buf_ack_Cel.y:=1]
1167718 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 1 [by e.decoder.addr_buf._out_a_B:=0]
1174473 e.decoder.addr_buf._out_a_BX_t[0] : 0 [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=1]
1174524 e.decoder.addr_buf.t_buf_func[0]._y : 1 [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
1174534 e.decoder.d_dr_x.in_tX[0].in : 0 [by e.decoder.addr_buf.t_buf_func[0]._y:=1]
1174854 e.decoder.d_dr_x.in_tX[0].buf1._y : 1 [by e.decoder.d_dr_x.in_tX[0].in:=0]
1174855 e.decoder.d_dr_x.atree[1].in[0] : 0 [by e.decoder.d_dr_x.in_tX[0].buf1._y:=1]
1174856 e.decoder.d_dr_x.atree[1].b._y : 1 [by e.decoder.d_dr_x.atree[1].in[0]:=0]
1176586 e.decoder.d_dr_x.out[1] : 0 [by e.decoder.d_dr_x.atree[1].b._y:=1]
1176601 e.decoder.d_dr_xX[1].buf2._y : 1 [by e.decoder.d_dr_x.out[1]:=0]
1178273 e.decoder._and_grid.xbuf[1].buf1._y : 1 [by e.decoder.d_dr_x.out[1]:=0]
1178727 e.decoder._and_grid.ands[1].a : 0 [by e.decoder._and_grid.xbuf[1].buf1._y:=1]
1179043 e.decoder._and_grid.ands[1]._y : 1 [by e.decoder._and_grid.ands[1].a:=0]
1179044 e.out[1].r : 0 [by e.decoder._and_grid.ands[1]._y:=1]
1179427 e.synapses[1].y : 1 [by e.out[1].r:=0]
1182116 e.decoder.vtree_x.OR2_tf[0]._y : 1 [by e.decoder.d_dr_x.in_tX[0].in:=0]
1182136 e.decoder.vtree_x.ct.in[0] : 0 [by e.decoder.vtree_x.OR2_tf[0]._y:=1]
1183459 e.decoder.vtree_x.ct.b._y : 1 [by e.decoder.vtree_x.ct.in[0]:=0]
1183546 e.decoder.vtree_x.out : 0 [by e.decoder.vtree_x.ct.b._y:=1]
1186890 e.out[1].a : 0 [by e.synapses[1].y:=1]
1200875 e.decoder.pu_ANDs[1].a : 0 [by e.decoder.d_dr_xX[1].buf2._y:=1]
1207597 e.decoder.pu_ANDs[1]._y : 1 [by e.decoder.pu_ANDs[1].a:=0]
1207609 e.decoder.pu[1].a : 0 [by e.decoder.pu_ANDs[1]._y:=1]
1207754 e.decoder._out_acksB[1] : 1 [by e.decoder.pu[1].a:=0]
1208655 e.decoder._ortree.in[1] : 0 [by e.decoder._out_acksB[1]:=1]
1210004 e.decoder._ortree.or2s[0]._y : 1 [by e.decoder._ortree.in[1]:=0]
1210223 e.decoder._ortree.out : 0 [by e.decoder._ortree.or2s[0]._y:=1]
1215694 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 1 [by e.decoder.addr_buf._out_a_B:=0]
1224025 e.decoder.addr_buf._out_a_BX_f[0] : 0 [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=1]
1224043 e.decoder.addr_buf.f_buf_func[2]._y : 1 [by e.decoder.addr_buf._out_a_BX_f[0]:=0]
1226237 e.decoder.d_dr_y.in_fX[1].in : 0 [by e.decoder.addr_buf.f_buf_func[2]._y:=1]
1226357 e.decoder.vtree_y.OR2_tf[1]._y : 1 [by e.decoder.d_dr_y.in_fX[1].in:=0]
1232672 e.decoder.vtree_y.ct.in[1] : 0 [by e.decoder.vtree_y.OR2_tf[1]._y:=1]
1255606 e.decoder.addr_buf.f_buf_func[1]._y : 1 [by e.decoder.addr_buf._out_a_BX_f[0]:=0]
1257670 e.decoder.d_dr_y.in_fX[0].in : 0 [by e.decoder.addr_buf.f_buf_func[1]._y:=1]
1257677 e.decoder.vtree_y.OR2_tf[0]._y : 1 [by e.decoder.d_dr_y.in_fX[0].in:=0]
1257678 e.decoder.vtree_y.ct.in[0] : 0 [by e.decoder.vtree_y.OR2_tf[0]._y:=1]
1257802 e.decoder.vtree_y.ct.C2Els[0]._y : 1 [by e.decoder.vtree_y.ct.in[0]:=0]
1258262 e.decoder.d_dr_y.in_fX[0].buf1._y : 1 [by e.decoder.d_dr_y.in_fX[0].in:=0]
1259314 e.decoder.d_dr_y.atree[0].in[0] : 0 [by e.decoder.d_dr_y.in_fX[0].buf1._y:=1]
1259674 e.decoder.d_dr_y.atree[0].and2s[0]._y : 1 [by e.decoder.d_dr_y.atree[0].in[0]:=0]
1263732 e.decoder.vtree_y.out : 0 [by e.decoder.vtree_y.ct.C2Els[0]._y:=1]
1264209 e.decoder.d_dr_y.in_fX[1].buf1._y : 1 [by e.decoder.d_dr_y.in_fX[1].in:=0]
1264829 e.decoder.valid_Cel._y : 1 [by e.decoder.vtree_y.out:=0]
1264833 e.decoder.valid_Cel.y : 0 [by e.decoder.valid_Cel._y:=1]
1269868 e.decoder.d_dr_y.out[0] : 0 [by e.decoder.d_dr_y.atree[0].and2s[0]._y:=1]
1276497 e.decoder.buf_ack_Cel._y : 1 [by e.decoder.valid_Cel.y:=0]
1284101 e.decoder.d_dr_y.atree[0].in[1] : 0 [by e.decoder.d_dr_y.in_fX[1].buf1._y:=1]
1294158 e.decoder.buf_ack_Cel.y : 0 [by e.decoder.buf_ack_Cel._y:=1]
1297539 e.decoder.addr_buf._out_a_B : 1 [by e.decoder.buf_ack_Cel.y:=0]
1297795 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 0 [by e.decoder.addr_buf._out_a_B:=1]
1297832 e.decoder.addr_buf._out_a_BX_f[0] : 1 [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=0]
1307787 e.decoder._and_grid.ybuf[0].buf1._y : 1 [by e.decoder.d_dr_y.out[0]:=0]
1307799 e.decoder._and_grid.ands[0].b : 0 [by e.decoder._and_grid.ybuf[0].buf1._y:=1]
1312469 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 0 [by e.decoder.addr_buf._out_a_B:=1]
1312478 e.decoder.addr_buf._out_a_BX_t[0] : 1 [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=0]
[] Removing input
1312478 e.in.d.d[0].t : 0
1312478 e.in.d.d[2].f : 0
1312478 e.in.d.d[1].f : 0
1312720 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1 [by e.in.d.d[2].f:=0]
1312905 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1 [by e.in.d.d[0].t:=0]
1313313 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1 [by e.in.d.d[1].f:=0]
1314465 e.decoder.addr_buf.vc.ct.in[0] : 0 [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
1350406 e.decoder.addr_buf.vc.ct.in[1] : 0 [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
1359456 e.decoder.addr_buf.vc.ct.in[2] : 0 [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
1359716 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1 [by e.decoder.addr_buf.vc.ct.in[2]:=0]
1368704 e.decoder.addr_buf._in_v : 0 [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
1368705 e.decoder.addr_buf.in_v_buf._y : 1 [by e.decoder.addr_buf._in_v:=0]
1404755 e.in.v : 0 [by e.decoder.addr_buf.in_v_buf._y:=1]
1405139 e.decoder.addr_buf.inack_ctl._y : 1 [by e.in.v:=0]
1405158 e.in.a : 0 [by e.decoder.addr_buf.inack_ctl._y:=1]
1405167 e.decoder.addr_buf._en : 1 [by e.in.a:=0]
1405355 e.decoder.addr_buf.en_buf_t.buf1._y : 0 [by e.decoder.addr_buf._en:=1]
1427121 e.decoder.addr_buf.en_buf_f.buf1._y : 0 [by e.decoder.addr_buf._en:=1]
1430721 e.decoder.addr_buf._en_X_f[0] : 1 [by e.decoder.addr_buf.en_buf_f.buf1._y:=0]
1451131 e.decoder.addr_buf._en_X_t[0] : 1 [by e.decoder.addr_buf.en_buf_t.buf1._y:=0]
test/unit_tests/decoder_2d_hs/run/test.prs
-1190
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test/unit_tests/decoder_2d_hs/test.act
-73
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@@ -1,73 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc decoder_2d_hs_2x4 (avMx1of2<3> in; a1of1 out[8]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
decoder_2d_hs<1,2,2,4> decoder(.in = in, .out = out,
.reset_B = _reset_B, .supply = supply);
// model the synapse as having automatic pulldown of ack.
INV_X1 synapses[8];
PULLDOWN_X4 synapses2[8];
(i:8:
synapses[i].a = decoder.out[i].r;
synapses2[i].a = synapses[i].y;
synapses2[i].y = decoder.out[i].a;
synapses[i].vss = supply.vss;
synapses[i].vdd = supply.vdd;
synapses2[i].vss = supply.vss;
synapses2[i].vdd = supply.vdd;
)
}
// fifo_decoder_neurons_encoder_fifo e;
decoder_2d_hs_2x4 e;
test/unit_tests/decoder_2d_hs/test.prsim
-153
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@@ -1,153 +0,0 @@
watchall
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
set-qdi-channel-neutral "e.in" 3
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a 7 packet'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [5] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
test/unit_tests/decoder_2d_hybrid/run/prsim.out
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test/unit_tests/decoder_2d_hybrid/run/prsim.pdf
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test/unit_tests/decoder_2d_hybrid/run/test.prs
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test/unit_tests/decoder_2d_hybrid/test.act
-74
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .out = out, .dly_cfg = dly_cfg, .hs_en = hs_en,
.reset_B = _reset_B, .supply = supply);
// model the synapse as having automatic pulldown of ack.
INV_X1 synapses[8];
PULLDOWN_X4 synapses2[8];
(i:8:
synapses[i].a = decoder.out[i].r;
synapses2[i].a = synapses[i].y;
synapses2[i].y = decoder.out[i].a;
synapses[i].vss = supply.vss;
synapses[i].vdd = supply.vdd;
synapses2[i].vss = supply.vss;
synapses2[i].vdd = supply.vdd;
)
}
// fifo_decoder_neurons_encoder_fifo e;
decoder_2d_hybrid_2x4 e;
test/unit_tests/decoder_2d_hybrid/test.prsim
-341
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@@ -1,341 +0,0 @@
watchall
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
set e.dly_cfg[0] 0
set e.dly_cfg[1] 0
set e.dly_cfg[2] 0
set e.dly_cfg[3] 0
set e.hs_en 1
set-qdi-channel-neutral "e.in" 3
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a 7 packet'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [1] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input, enabling delays'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Enabling delays'"
cycle
set e.dly_cfg[0] 1
set e.dly_cfg[1] 1
set e.dly_cfg[2] 1
set e.dly_cfg[3] 1
system "echo '[] Sending in a 7 packet, with delays'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [1] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input, disabling handshaking'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
set e.hs_en 0
cycle
system "echo '[] Sending in a 0, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 0
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in a 7, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in a 5, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
test/unit_tests/delayprog_4/run/prsim.out
+118 -256
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@@ -1,272 +1,134 @@
t.s[2] t.dp.dly[4].__y t.dp.dly[3].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.dp.dly[9].___y t.dp.dly[0].___y t.s[0] t.dp.dly[6].___y t.dp.dly[4].___y t.dp.and2[2]._y t.dp.dly[3].__y t.dp.dly[11].__y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp.dly[8].___y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[10].___y t.dp.dly[11].y t.dp.dly[8].__y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[11].___y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[12].___y t.dp.dly[8].y t.dp.dly[1].y t.dp.dly[5].__y t.dp.dly[1].a t.in t.dp.dly[7].a t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[9].y t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[7].y t.dp.dly[6].__y t.dp.dly[0].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.dly[13].___y t.out t.dp.mu2[3].b t.dp.mu2[1]._s t.dp.dly[10].y t.dp.dly[1].__y t.dp.dly[13].y t.dp.dly[12].y t.dp.dly[13]._y t.dp.dly[12].__y t.dp.dly[8]._y t.dp.dly[14].__y t.dp.dly[10].__y t.dp.mu2[2]._y t.dp.dly[5].___y t.dp.dly[9].__y t.dp.dly[3].y t.dp.dly[14].___y t.dp.dly[7].__y t.dp.dly[0].y t.dp.dly[2].__y t.dp.dly[3]._y t.dp.dly[3].___y t.dp.dly[2].___y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[13].__y t.dp.dly[1].___y t.dp.dly[4]._y t.dp.dly[7].___y t.dp.mu2[1]._y t.dp.dly[0].__y t.dp.dly[10]._y
t.s[2] t.dp.dly[2].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.a t.s[0] t.dp.and2[2]._y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[11].y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[9].a t.dp.dly[1].y t.dp.dly[1].a t.dp.dly[4].a t.y t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[10].a t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[8].a t.dp.dly[0].a t.dp.dly[7].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.mu2[1]._s t.dp.dly[11].a t.dp.dly[14].a t.dp.dly[13].a t.dp.dly[13]._y t.dp.dly[7].y t.dp.dly[8]._y t.dp.mu2[2]._y t.dp.dly[3].y t.dp.dly[14].y t.dp.dly[0].y t.dp.dly[3]._y t.dp.dly[13].y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[10].y t.dp.dly[9].y t.dp.dly[4]._y t.dp.dly[12].y t.dp.dly[8].y t.dp.mu2[1]._y t.dp.dly[12].a t.dp.dly[10]._y
0
0 t.in : 0
0 t.a : 0
0 t.s[3] : 1
0 t.s[1] : 1
0 t.s[0] : 1
0 t.s[2] : 1
1 t.dp.and2[0]._y : 1 [by t.in:=0]
1 t.dp.and2[0]._y : 1 [by t.a:=0]
2 t.dp.mu2[0]._s : 0 [by t.s[0]:=1]
1138 t.dp.dly[0].a : 0 [by t.dp.and2[0]._y:=1]
1252 t.dp.dly[0]._y : 1 [by t.dp.dly[0].a:=0]
4753 t.dp.mu2[2]._s : 0 [by t.s[2]:=1]
7092 t.dp.mu2[3]._s : 0 [by t.s[3]:=1]
10467 t.dp.mu2[1]._s : 0 [by t.s[1]:=1]
66618 t.dp.dly[0].__y : 0 [by t.dp.dly[0]._y:=1]
68344 t.dp.dly[0].___y : 1 [by t.dp.dly[0].__y:=0]
68383 t.dp.dly[0].y : 0 [by t.dp.dly[0].___y:=1]
68398 t.dp.mu2[0]._y : 1 [by t.dp.dly[0].y:=0]
68889 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
68902 t.dp.and2[1]._y : 1 [by t.dp._a[1]:=0]
68942 t.dp.dly[1].a : 0 [by t.dp.and2[1]._y:=1]
69357 t.dp.dly[1]._y : 1 [by t.dp.dly[1].a:=0]
69377 t.dp.dly[1].__y : 0 [by t.dp.dly[1]._y:=1]
75438 t.dp.dly[1].___y : 1 [by t.dp.dly[1].__y:=0]
75485 t.dp.dly[1].y : 0 [by t.dp.dly[1].___y:=1]
75501 t.dp.dly[2]._y : 1 [by t.dp.dly[1].y:=0]
119599 t.dp.dly[2].__y : 0 [by t.dp.dly[2]._y:=1]
133323 t.dp.dly[2].___y : 1 [by t.dp.dly[2].__y:=0]
133327 t.dp.dly[2].y : 0 [by t.dp.dly[2].___y:=1]
142456 t.dp.mu2[1]._y : 1 [by t.dp.dly[2].y:=0]
142471 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
185719 t.dp.and2[2]._y : 1 [by t.dp._a[2]:=0]
222650 t.dp.dly[3].a : 0 [by t.dp.and2[2]._y:=1]
222705 t.dp.dly[3]._y : 1 [by t.dp.dly[3].a:=0]
274358 t.dp.dly[3].__y : 0 [by t.dp.dly[3]._y:=1]
304138 t.dp.dly[3].___y : 1 [by t.dp.dly[3].__y:=0]
317987 t.dp.dly[3].y : 0 [by t.dp.dly[3].___y:=1]
342799 t.dp.dly[4]._y : 1 [by t.dp.dly[3].y:=0]
357142 t.dp.dly[4].__y : 0 [by t.dp.dly[4]._y:=1]
357564 t.dp.dly[4].___y : 1 [by t.dp.dly[4].__y:=0]
406278 t.dp.dly[4].y : 0 [by t.dp.dly[4].___y:=1]
406279 t.dp.dly[5]._y : 1 [by t.dp.dly[4].y:=0]
406280 t.dp.dly[5].__y : 0 [by t.dp.dly[5]._y:=1]
426485 t.dp.dly[5].___y : 1 [by t.dp.dly[5].__y:=0]
426767 t.dp.dly[5].y : 0 [by t.dp.dly[5].___y:=1]
427535 t.dp.dly[6]._y : 1 [by t.dp.dly[5].y:=0]
427538 t.dp.dly[6].__y : 0 [by t.dp.dly[6]._y:=1]
449979 t.dp.dly[6].___y : 1 [by t.dp.dly[6].__y:=0]
450530 t.dp.dly[6].y : 0 [by t.dp.dly[6].___y:=1]
451601 t.dp.mu2[2]._y : 1 [by t.dp.dly[6].y:=0]
452555 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
453636 t.dp.and2[3]._y : 1 [by t.dp._a[3]:=0]
508106 t.dp.dly[7].a : 0 [by t.dp.and2[3]._y:=1]
509088 t.dp.dly[7]._y : 1 [by t.dp.dly[7].a:=0]
509106 t.dp.dly[7].__y : 0 [by t.dp.dly[7]._y:=1]
513119 t.dp.dly[7].___y : 1 [by t.dp.dly[7].__y:=0]
517122 t.dp.dly[7].y : 0 [by t.dp.dly[7].___y:=1]
562023 t.dp.dly[8]._y : 1 [by t.dp.dly[7].y:=0]
583607 t.dp.dly[8].__y : 0 [by t.dp.dly[8]._y:=1]
588367 t.dp.dly[8].___y : 1 [by t.dp.dly[8].__y:=0]
588869 t.dp.dly[8].y : 0 [by t.dp.dly[8].___y:=1]
589072 t.dp.dly[9]._y : 1 [by t.dp.dly[8].y:=0]
590926 t.dp.dly[9].__y : 0 [by t.dp.dly[9]._y:=1]
591065 t.dp.dly[9].___y : 1 [by t.dp.dly[9].__y:=0]
627411 t.dp.dly[9].y : 0 [by t.dp.dly[9].___y:=1]
627480 t.dp.dly[10]._y : 1 [by t.dp.dly[9].y:=0]
627491 t.dp.dly[10].__y : 0 [by t.dp.dly[10]._y:=1]
679277 t.dp.dly[10].___y : 1 [by t.dp.dly[10].__y:=0]
679481 t.dp.dly[10].y : 0 [by t.dp.dly[10].___y:=1]
679496 t.dp.dly[11]._y : 1 [by t.dp.dly[10].y:=0]
679497 t.dp.dly[11].__y : 0 [by t.dp.dly[11]._y:=1]
679534 t.dp.dly[11].___y : 1 [by t.dp.dly[11].__y:=0]
680273 t.dp.dly[11].y : 0 [by t.dp.dly[11].___y:=1]
680385 t.dp.dly[12]._y : 1 [by t.dp.dly[11].y:=0]
727897 t.dp.dly[12].__y : 0 [by t.dp.dly[12]._y:=1]
727937 t.dp.dly[12].___y : 1 [by t.dp.dly[12].__y:=0]
728194 t.dp.dly[12].y : 0 [by t.dp.dly[12].___y:=1]
728281 t.dp.dly[13]._y : 1 [by t.dp.dly[12].y:=0]
728575 t.dp.dly[13].__y : 0 [by t.dp.dly[13]._y:=1]
728576 t.dp.dly[13].___y : 1 [by t.dp.dly[13].__y:=0]
730382 t.dp.dly[13].y : 0 [by t.dp.dly[13].___y:=1]
732389 t.dp.dly[14]._y : 1 [by t.dp.dly[13].y:=0]
733598 t.dp.dly[14].__y : 0 [by t.dp.dly[14]._y:=1]
734188 t.dp.dly[14].___y : 1 [by t.dp.dly[14].__y:=0]
734366 t.dp.mu2[3].b : 0 [by t.dp.dly[14].___y:=1]
735169 t.dp.mu2[3]._y : 1 [by t.dp.mu2[3].b:=0]
735333 t.out : 0 [by t.dp.mu2[3]._y:=1]
66618 t.dp.dly[0].y : 0 [by t.dp.dly[0]._y:=1]
68344 t.dp.mu2[0]._y : 1 [by t.dp.dly[0].y:=0]
68383 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
68398 t.dp.and2[1]._y : 1 [by t.dp._a[1]:=0]
68889 t.dp.dly[1].a : 0 [by t.dp.and2[1]._y:=1]
68902 t.dp.dly[1]._y : 1 [by t.dp.dly[1].a:=0]
68942 t.dp.dly[1].y : 0 [by t.dp.dly[1]._y:=1]
69357 t.dp.mu2[1]._y : 1 [by t.dp.dly[1].y:=0]
69377 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
75438 t.dp.and2[2]._y : 1 [by t.dp._a[2]:=0]
75485 t.dp.dly[2].a : 0 [by t.dp.and2[2]._y:=1]
75501 t.dp.dly[2]._y : 1 [by t.dp.dly[2].a:=0]
119599 t.dp.dly[2].y : 0 [by t.dp.dly[2]._y:=1]
133323 t.dp.dly[3]._y : 1 [by t.dp.dly[2].y:=0]
133327 t.dp.dly[3].y : 0 [by t.dp.dly[3]._y:=1]
142456 t.dp.mu2[2]._y : 1 [by t.dp.dly[3].y:=0]
142471 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
185719 t.dp.and2[3]._y : 1 [by t.dp._a[3]:=0]
222650 t.dp.dly[4].a : 0 [by t.dp.and2[3]._y:=1]
222705 t.dp.dly[4]._y : 1 [by t.dp.dly[4].a:=0]
274358 t.dp.dly[4].y : 0 [by t.dp.dly[4]._y:=1]
304138 t.dp.dly[5]._y : 1 [by t.dp.dly[4].y:=0]
317987 t.dp.dly[5].y : 0 [by t.dp.dly[5]._y:=1]
342799 t.dp.dly[6]._y : 1 [by t.dp.dly[5].y:=0]
357142 t.dp.dly[6].y : 0 [by t.dp.dly[6]._y:=1]
357564 t.dp.mu2[3]._y : 1 [by t.dp.dly[6].y:=0]
406278 t.y : 0 [by t.dp.mu2[3]._y:=1]
[] setting high
735333 t.in : 1
737528 t.dp.and2[0]._y : 0 [by t.in:=1]
737550 t.dp.dly[0].a : 1 [by t.dp.and2[0]._y:=0]
738397 t.dp.dly[0]._y : 0 [by t.dp.dly[0].a:=1]
768525 t.dp.dly[0].__y : 1 [by t.dp.dly[0]._y:=0]
768658 t.dp.dly[0].___y : 0 [by t.dp.dly[0].__y:=1]
784320 t.dp.dly[0].y : 1 [by t.dp.dly[0].___y:=0]
784679 t.dp.mu2[0]._y : 0 [by t.dp.dly[0].y:=1]
798795 t.dp._a[1] : 1 [by t.dp.mu2[0]._y:=0]
799016 t.dp.and2[1]._y : 0 [by t.dp._a[1]:=1]
799023 t.dp.dly[1].a : 1 [by t.dp.and2[1]._y:=0]
799053 t.dp.dly[1]._y : 0 [by t.dp.dly[1].a:=1]
805766 t.dp.dly[1].__y : 1 [by t.dp.dly[1]._y:=0]
863227 t.dp.dly[1].___y : 0 [by t.dp.dly[1].__y:=1]
863318 t.dp.dly[1].y : 1 [by t.dp.dly[1].___y:=0]
865507 t.dp.dly[2]._y : 0 [by t.dp.dly[1].y:=1]
865514 t.dp.dly[2].__y : 1 [by t.dp.dly[2]._y:=0]
868301 t.dp.dly[2].___y : 0 [by t.dp.dly[2].__y:=1]
868407 t.dp.dly[2].y : 1 [by t.dp.dly[2].___y:=0]
868485 t.dp.mu2[1]._y : 0 [by t.dp.dly[2].y:=1]
868760 t.dp._a[2] : 1 [by t.dp.mu2[1]._y:=0]
887756 t.dp.and2[2]._y : 0 [by t.dp._a[2]:=1]
888211 t.dp.dly[3].a : 1 [by t.dp.and2[2]._y:=0]
888223 t.dp.dly[3]._y : 0 [by t.dp.dly[3].a:=1]
888627 t.dp.dly[3].__y : 1 [by t.dp.dly[3]._y:=0]
888639 t.dp.dly[3].___y : 0 [by t.dp.dly[3].__y:=1]
894555 t.dp.dly[3].y : 1 [by t.dp.dly[3].___y:=0]
898831 t.dp.dly[4]._y : 0 [by t.dp.dly[3].y:=1]
901730 t.dp.dly[4].__y : 1 [by t.dp.dly[4]._y:=0]
906025 t.dp.dly[4].___y : 0 [by t.dp.dly[4].__y:=1]
906027 t.dp.dly[4].y : 1 [by t.dp.dly[4].___y:=0]
910562 t.dp.dly[5]._y : 0 [by t.dp.dly[4].y:=1]
911811 t.dp.dly[5].__y : 1 [by t.dp.dly[5]._y:=0]
915310 t.dp.dly[5].___y : 0 [by t.dp.dly[5].__y:=1]
915476 t.dp.dly[5].y : 1 [by t.dp.dly[5].___y:=0]
915551 t.dp.dly[6]._y : 0 [by t.dp.dly[5].y:=1]
915896 t.dp.dly[6].__y : 1 [by t.dp.dly[6]._y:=0]
916034 t.dp.dly[6].___y : 0 [by t.dp.dly[6].__y:=1]
921297 t.dp.dly[6].y : 1 [by t.dp.dly[6].___y:=0]
921299 t.dp.mu2[2]._y : 0 [by t.dp.dly[6].y:=1]
965216 t.dp._a[3] : 1 [by t.dp.mu2[2]._y:=0]
965217 t.dp.and2[3]._y : 0 [by t.dp._a[3]:=1]
965765 t.dp.dly[7].a : 1 [by t.dp.and2[3]._y:=0]
965776 t.dp.dly[7]._y : 0 [by t.dp.dly[7].a:=1]
966146 t.dp.dly[7].__y : 1 [by t.dp.dly[7]._y:=0]
966213 t.dp.dly[7].___y : 0 [by t.dp.dly[7].__y:=1]
968854 t.dp.dly[7].y : 1 [by t.dp.dly[7].___y:=0]
968870 t.dp.dly[8]._y : 0 [by t.dp.dly[7].y:=1]
973432 t.dp.dly[8].__y : 1 [by t.dp.dly[8]._y:=0]
973960 t.dp.dly[8].___y : 0 [by t.dp.dly[8].__y:=1]
976395 t.dp.dly[8].y : 1 [by t.dp.dly[8].___y:=0]
1003275 t.dp.dly[9]._y : 0 [by t.dp.dly[8].y:=1]
1027200 t.dp.dly[9].__y : 1 [by t.dp.dly[9]._y:=0]
1040241 t.dp.dly[9].___y : 0 [by t.dp.dly[9].__y:=1]
1040243 t.dp.dly[9].y : 1 [by t.dp.dly[9].___y:=0]
1101201 t.dp.dly[10]._y : 0 [by t.dp.dly[9].y:=1]
1101204 t.dp.dly[10].__y : 1 [by t.dp.dly[10]._y:=0]
1101233 t.dp.dly[10].___y : 0 [by t.dp.dly[10].__y:=1]
1101550 t.dp.dly[10].y : 1 [by t.dp.dly[10].___y:=0]
1103151 t.dp.dly[11]._y : 0 [by t.dp.dly[10].y:=1]
1103304 t.dp.dly[11].__y : 1 [by t.dp.dly[11]._y:=0]
1103348 t.dp.dly[11].___y : 0 [by t.dp.dly[11].__y:=1]
1106109 t.dp.dly[11].y : 1 [by t.dp.dly[11].___y:=0]
1119792 t.dp.dly[12]._y : 0 [by t.dp.dly[11].y:=1]
1119793 t.dp.dly[12].__y : 1 [by t.dp.dly[12]._y:=0]
1120010 t.dp.dly[12].___y : 0 [by t.dp.dly[12].__y:=1]
1120032 t.dp.dly[12].y : 1 [by t.dp.dly[12].___y:=0]
1120033 t.dp.dly[13]._y : 0 [by t.dp.dly[12].y:=1]
1121614 t.dp.dly[13].__y : 1 [by t.dp.dly[13]._y:=0]
1130959 t.dp.dly[13].___y : 0 [by t.dp.dly[13].__y:=1]
1131118 t.dp.dly[13].y : 1 [by t.dp.dly[13].___y:=0]
1150794 t.dp.dly[14]._y : 0 [by t.dp.dly[13].y:=1]
1152081 t.dp.dly[14].__y : 1 [by t.dp.dly[14]._y:=0]
1154313 t.dp.dly[14].___y : 0 [by t.dp.dly[14].__y:=1]
1154458 t.dp.mu2[3].b : 1 [by t.dp.dly[14].___y:=0]
1157290 t.dp.mu2[3]._y : 0 [by t.dp.mu2[3].b:=1]
1163644 t.out : 1 [by t.dp.mu2[3]._y:=0]
406278 t.a : 1
406279 t.dp.and2[0]._y : 0 [by t.a:=1]
406280 t.dp.dly[0].a : 1 [by t.dp.and2[0]._y:=0]
426485 t.dp.dly[0]._y : 0 [by t.dp.dly[0].a:=1]
426767 t.dp.dly[0].y : 1 [by t.dp.dly[0]._y:=0]
427535 t.dp.mu2[0]._y : 0 [by t.dp.dly[0].y:=1]
427538 t.dp._a[1] : 1 [by t.dp.mu2[0]._y:=0]
449979 t.dp.and2[1]._y : 0 [by t.dp._a[1]:=1]
450530 t.dp.dly[1].a : 1 [by t.dp.and2[1]._y:=0]
451601 t.dp.dly[1]._y : 0 [by t.dp.dly[1].a:=1]
452555 t.dp.dly[1].y : 1 [by t.dp.dly[1]._y:=0]
453636 t.dp.mu2[1]._y : 0 [by t.dp.dly[1].y:=1]
508106 t.dp._a[2] : 1 [by t.dp.mu2[1]._y:=0]
509088 t.dp.and2[2]._y : 0 [by t.dp._a[2]:=1]
509106 t.dp.dly[2].a : 1 [by t.dp.and2[2]._y:=0]
513119 t.dp.dly[2]._y : 0 [by t.dp.dly[2].a:=1]
517122 t.dp.dly[2].y : 1 [by t.dp.dly[2]._y:=0]
562023 t.dp.dly[3]._y : 0 [by t.dp.dly[2].y:=1]
583607 t.dp.dly[3].y : 1 [by t.dp.dly[3]._y:=0]
588367 t.dp.mu2[2]._y : 0 [by t.dp.dly[3].y:=1]
588869 t.dp._a[3] : 1 [by t.dp.mu2[2]._y:=0]
589072 t.dp.and2[3]._y : 0 [by t.dp._a[3]:=1]
590926 t.dp.dly[4].a : 1 [by t.dp.and2[3]._y:=0]
591065 t.dp.dly[4]._y : 0 [by t.dp.dly[4].a:=1]
627411 t.dp.dly[4].y : 1 [by t.dp.dly[4]._y:=0]
627480 t.dp.dly[5]._y : 0 [by t.dp.dly[4].y:=1]
627491 t.dp.dly[5].y : 1 [by t.dp.dly[5]._y:=0]
679277 t.dp.dly[6]._y : 0 [by t.dp.dly[5].y:=1]
679481 t.dp.dly[6].y : 1 [by t.dp.dly[6]._y:=0]
679496 t.dp.mu2[3]._y : 0 [by t.dp.dly[6].y:=1]
679497 t.y : 1 [by t.dp.mu2[3]._y:=0]
[] setting low
1163644 t.in : 0
1163645 t.dp.and2[0]._y : 1 [by t.in:=0]
1202929 t.dp.dly[0].a : 0 [by t.dp.and2[0]._y:=1]
1203091 t.dp.dly[0]._y : 1 [by t.dp.dly[0].a:=0]
1210460 t.dp.dly[0].__y : 0 [by t.dp.dly[0]._y:=1]
1210474 t.dp.dly[0].___y : 1 [by t.dp.dly[0].__y:=0]
1210481 t.dp.dly[0].y : 0 [by t.dp.dly[0].___y:=1]
1210641 t.dp.mu2[0]._y : 1 [by t.dp.dly[0].y:=0]
1232198 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
1232199 t.dp.and2[1]._y : 1 [by t.dp._a[1]:=0]
1232200 t.dp.dly[1].a : 0 [by t.dp.and2[1]._y:=1]
1232201 t.dp.dly[1]._y : 1 [by t.dp.dly[1].a:=0]
1234444 t.dp.dly[1].__y : 0 [by t.dp.dly[1]._y:=1]
1234631 t.dp.dly[1].___y : 1 [by t.dp.dly[1].__y:=0]
1234632 t.dp.dly[1].y : 0 [by t.dp.dly[1].___y:=1]
1238814 t.dp.dly[2]._y : 1 [by t.dp.dly[1].y:=0]
1273596 t.dp.dly[2].__y : 0 [by t.dp.dly[2]._y:=1]
1273597 t.dp.dly[2].___y : 1 [by t.dp.dly[2].__y:=0]
1274450 t.dp.dly[2].y : 0 [by t.dp.dly[2].___y:=1]
1274455 t.dp.mu2[1]._y : 1 [by t.dp.dly[2].y:=0]
1275346 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
1275347 t.dp.and2[2]._y : 1 [by t.dp._a[2]:=0]
1275364 t.dp.dly[3].a : 0 [by t.dp.and2[2]._y:=1]
1277937 t.dp.dly[3]._y : 1 [by t.dp.dly[3].a:=0]
1286298 t.dp.dly[3].__y : 0 [by t.dp.dly[3]._y:=1]
1286301 t.dp.dly[3].___y : 1 [by t.dp.dly[3].__y:=0]
1287242 t.dp.dly[3].y : 0 [by t.dp.dly[3].___y:=1]
1346204 t.dp.dly[4]._y : 1 [by t.dp.dly[3].y:=0]
1346205 t.dp.dly[4].__y : 0 [by t.dp.dly[4]._y:=1]
1346247 t.dp.dly[4].___y : 1 [by t.dp.dly[4].__y:=0]
1349064 t.dp.dly[4].y : 0 [by t.dp.dly[4].___y:=1]
1362797 t.dp.dly[5]._y : 1 [by t.dp.dly[4].y:=0]
1362892 t.dp.dly[5].__y : 0 [by t.dp.dly[5]._y:=1]
1363227 t.dp.dly[5].___y : 1 [by t.dp.dly[5].__y:=0]
1363235 t.dp.dly[5].y : 0 [by t.dp.dly[5].___y:=1]
1363269 t.dp.dly[6]._y : 1 [by t.dp.dly[5].y:=0]
1377156 t.dp.dly[6].__y : 0 [by t.dp.dly[6]._y:=1]
1378074 t.dp.dly[6].___y : 1 [by t.dp.dly[6].__y:=0]
1378078 t.dp.dly[6].y : 0 [by t.dp.dly[6].___y:=1]
1424456 t.dp.mu2[2]._y : 1 [by t.dp.dly[6].y:=0]
1426854 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
1430069 t.dp.and2[3]._y : 1 [by t.dp._a[3]:=0]
1477188 t.dp.dly[7].a : 0 [by t.dp.and2[3]._y:=1]
1477236 t.dp.dly[7]._y : 1 [by t.dp.dly[7].a:=0]
1477239 t.dp.dly[7].__y : 0 [by t.dp.dly[7]._y:=1]
1477417 t.dp.dly[7].___y : 1 [by t.dp.dly[7].__y:=0]
1498394 t.dp.dly[7].y : 0 [by t.dp.dly[7].___y:=1]
1510293 t.dp.dly[8]._y : 1 [by t.dp.dly[7].y:=0]
1516244 t.dp.dly[8].__y : 0 [by t.dp.dly[8]._y:=1]
1555729 t.dp.dly[8].___y : 1 [by t.dp.dly[8].__y:=0]
1556556 t.dp.dly[8].y : 0 [by t.dp.dly[8].___y:=1]
1556729 t.dp.dly[9]._y : 1 [by t.dp.dly[8].y:=0]
1556913 t.dp.dly[9].__y : 0 [by t.dp.dly[9]._y:=1]
1556914 t.dp.dly[9].___y : 1 [by t.dp.dly[9].__y:=0]
1556987 t.dp.dly[9].y : 0 [by t.dp.dly[9].___y:=1]
1556991 t.dp.dly[10]._y : 1 [by t.dp.dly[9].y:=0]
1594279 t.dp.dly[10].__y : 0 [by t.dp.dly[10]._y:=1]
1594375 t.dp.dly[10].___y : 1 [by t.dp.dly[10].__y:=0]
1594511 t.dp.dly[10].y : 0 [by t.dp.dly[10].___y:=1]
1594512 t.dp.dly[11]._y : 1 [by t.dp.dly[10].y:=0]
1613558 t.dp.dly[11].__y : 0 [by t.dp.dly[11]._y:=1]
1613799 t.dp.dly[11].___y : 1 [by t.dp.dly[11].__y:=0]
1617758 t.dp.dly[11].y : 0 [by t.dp.dly[11].___y:=1]
1617770 t.dp.dly[12]._y : 1 [by t.dp.dly[11].y:=0]
1621670 t.dp.dly[12].__y : 0 [by t.dp.dly[12]._y:=1]
1622699 t.dp.dly[12].___y : 1 [by t.dp.dly[12].__y:=0]
1622700 t.dp.dly[12].y : 0 [by t.dp.dly[12].___y:=1]
1622756 t.dp.dly[13]._y : 1 [by t.dp.dly[12].y:=0]
1667762 t.dp.dly[13].__y : 0 [by t.dp.dly[13]._y:=1]
1667763 t.dp.dly[13].___y : 1 [by t.dp.dly[13].__y:=0]
1667800 t.dp.dly[13].y : 0 [by t.dp.dly[13].___y:=1]
1691175 t.dp.dly[14]._y : 1 [by t.dp.dly[13].y:=0]
1691176 t.dp.dly[14].__y : 0 [by t.dp.dly[14]._y:=1]
1694740 t.dp.dly[14].___y : 1 [by t.dp.dly[14].__y:=0]
1696432 t.dp.mu2[3].b : 0 [by t.dp.dly[14].___y:=1]
1696445 t.dp.mu2[3]._y : 1 [by t.dp.mu2[3].b:=0]
1713429 t.out : 0 [by t.dp.mu2[3]._y:=1]
679497 t.a : 0
679534 t.dp.and2[0]._y : 1 [by t.a:=0]
680273 t.dp.dly[0].a : 0 [by t.dp.and2[0]._y:=1]
680385 t.dp.dly[0]._y : 1 [by t.dp.dly[0].a:=0]
727897 t.dp.dly[0].y : 0 [by t.dp.dly[0]._y:=1]
727937 t.dp.mu2[0]._y : 1 [by t.dp.dly[0].y:=0]
728194 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
728281 t.dp.and2[1]._y : 1 [by t.dp._a[1]:=0]
728575 t.dp.dly[1].a : 0 [by t.dp.and2[1]._y:=1]
728576 t.dp.dly[1]._y : 1 [by t.dp.dly[1].a:=0]
730382 t.dp.dly[1].y : 0 [by t.dp.dly[1]._y:=1]
732389 t.dp.mu2[1]._y : 1 [by t.dp.dly[1].y:=0]
733598 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
734188 t.dp.and2[2]._y : 1 [by t.dp._a[2]:=0]
734366 t.dp.dly[2].a : 0 [by t.dp.and2[2]._y:=1]
735169 t.dp.dly[2]._y : 1 [by t.dp.dly[2].a:=0]
735333 t.dp.dly[2].y : 0 [by t.dp.dly[2]._y:=1]
737528 t.dp.dly[3]._y : 1 [by t.dp.dly[2].y:=0]
737550 t.dp.dly[3].y : 0 [by t.dp.dly[3]._y:=1]
738397 t.dp.mu2[2]._y : 1 [by t.dp.dly[3].y:=0]
768525 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
768658 t.dp.and2[3]._y : 1 [by t.dp._a[3]:=0]
784320 t.dp.dly[4].a : 0 [by t.dp.and2[3]._y:=1]
784679 t.dp.dly[4]._y : 1 [by t.dp.dly[4].a:=0]
798795 t.dp.dly[4].y : 0 [by t.dp.dly[4]._y:=1]
799016 t.dp.dly[5]._y : 1 [by t.dp.dly[4].y:=0]
799023 t.dp.dly[5].y : 0 [by t.dp.dly[5]._y:=1]
799053 t.dp.dly[6]._y : 1 [by t.dp.dly[5].y:=0]
805766 t.dp.dly[6].y : 0 [by t.dp.dly[6]._y:=1]
863227 t.dp.mu2[3]._y : 1 [by t.dp.dly[6].y:=0]
863318 t.y : 0 [by t.dp.mu2[3]._y:=1]
[] setting configs low
1713429 t.s[0] : 0
1713429 t.s[3] : 0
1713429 t.s[2] : 0
1713429 t.s[1] : 0
1713430 t.dp.mu2[1]._s : 1 [by t.s[1]:=0]
1713450 t.dp.mu2[2]._s : 1 [by t.s[2]:=0]
1713454 t.dp.mu2[3]._s : 1 [by t.s[3]:=0]
1713786 t.dp.mu2[0]._s : 1 [by t.s[0]:=0]
863318 t.s[0] : 0
863318 t.s[3] : 0
863318 t.s[2] : 0
863318 t.s[1] : 0
863325 t.dp.mu2[3]._s : 1 [by t.s[3]:=0]
863424 t.dp.mu2[1]._s : 1 [by t.s[1]:=0]
865507 t.dp.mu2[0]._s : 1 [by t.s[0]:=0]
866105 t.dp.mu2[2]._s : 1 [by t.s[2]:=0]
[] setting high
1713786 t.in : 1
1723434 t.dp.mu2[0]._y : 0 [by t.in:=1]
1723435 t.dp._a[1] : 1 [by t.dp.mu2[0]._y:=0]
1723436 t.dp.mu2[1]._y : 0 [by t.dp._a[1]:=1]
1723597 t.dp._a[2] : 1 [by t.dp.mu2[1]._y:=0]
1724634 t.dp.mu2[2]._y : 0 [by t.dp._a[2]:=1]
1724639 t.dp._a[3] : 1 [by t.dp.mu2[2]._y:=0]
1725220 t.dp.mu2[3]._y : 0 [by t.dp._a[3]:=1]
1725628 t.out : 1 [by t.dp.mu2[3]._y:=0]
866105 t.a : 1
866183 t.dp.mu2[0]._y : 0 [by t.a:=1]
866458 t.dp._a[1] : 1 [by t.dp.mu2[0]._y:=0]
885454 t.dp.mu2[1]._y : 0 [by t.dp._a[1]:=1]
885909 t.dp._a[2] : 1 [by t.dp.mu2[1]._y:=0]
885921 t.dp.mu2[2]._y : 0 [by t.dp._a[2]:=1]
886325 t.dp._a[3] : 1 [by t.dp.mu2[2]._y:=0]
886337 t.dp.mu2[3]._y : 0 [by t.dp._a[3]:=1]
892253 t.y : 1 [by t.dp.mu2[3]._y:=0]
[] setting low
1725628 t.in : 0
1725639 t.dp.mu2[0]._y : 1 [by t.in:=0]
1726686 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
1726700 t.dp.mu2[1]._y : 1 [by t.dp._a[1]:=0]
1726718 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
1726722 t.dp.mu2[2]._y : 1 [by t.dp._a[2]:=0]
1726826 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
1758270 t.dp.mu2[3]._y : 1 [by t.dp._a[3]:=0]
1759474 t.out : 0 [by t.dp.mu2[3]._y:=1]
892253 t.a : 0
896529 t.dp.mu2[0]._y : 1 [by t.a:=0]
899428 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
903723 t.dp.mu2[1]._y : 1 [by t.dp._a[1]:=0]
903725 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
908260 t.dp.mu2[2]._y : 1 [by t.dp._a[2]:=0]
909509 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
913008 t.dp.mu2[3]._y : 1 [by t.dp._a[3]:=0]
913174 t.y : 0 [by t.dp.mu2[3]._y:=1]
test/unit_tests/delayprog_4/run/prsim.pdf
BIN
View File
Binary file not shown.
test/unit_tests/delayprog_4/run/test.prs
+43 -111
View File
@@ -1,6 +1,11 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
= "t.y" "t.dp.y"
= "t.a" "t.dp.a"
= "t.dp.a" "t.dp.mu2[0].a"
= "t.dp.a" "t.dp.and2[0].a"
= "t.dp.a" "t.dp._a[0]"
"t.dp.and2[0].a"&"t.dp.and2[0].b"->"t.dp.and2[0]._y"-
~("t.dp.and2[0].a"&"t.dp.and2[0].b")->"t.dp.and2[0]._y"+
"t.dp.and2[0]._y"->"t.dp.and2[0].y"-
@@ -97,140 +102,72 @@
~("t.dp.mu2[3]._y")->"t.dp.mu2[3].y"+
"t.dp.dly[0].a"->"t.dp.dly[0]._y"-
~("t.dp.dly[0].a")->"t.dp.dly[0]._y"+
"t.dp.dly[0]._y"->"t.dp.dly[0].__y"-
~("t.dp.dly[0]._y")->"t.dp.dly[0].__y"+
"t.dp.dly[0].__y"->"t.dp.dly[0].___y"-
~("t.dp.dly[0].__y")->"t.dp.dly[0].___y"+
"t.dp.dly[0].___y"->"t.dp.dly[0].y"-
~("t.dp.dly[0].___y")->"t.dp.dly[0].y"+
"t.dp.dly[0]._y"->"t.dp.dly[0].y"-
~("t.dp.dly[0]._y")->"t.dp.dly[0].y"+
"t.dp.dly[1].a"->"t.dp.dly[1]._y"-
~("t.dp.dly[1].a")->"t.dp.dly[1]._y"+
"t.dp.dly[1]._y"->"t.dp.dly[1].__y"-
~("t.dp.dly[1]._y")->"t.dp.dly[1].__y"+
"t.dp.dly[1].__y"->"t.dp.dly[1].___y"-
~("t.dp.dly[1].__y")->"t.dp.dly[1].___y"+
"t.dp.dly[1].___y"->"t.dp.dly[1].y"-
~("t.dp.dly[1].___y")->"t.dp.dly[1].y"+
"t.dp.dly[1]._y"->"t.dp.dly[1].y"-
~("t.dp.dly[1]._y")->"t.dp.dly[1].y"+
"t.dp.dly[2].a"->"t.dp.dly[2]._y"-
~("t.dp.dly[2].a")->"t.dp.dly[2]._y"+
"t.dp.dly[2]._y"->"t.dp.dly[2].__y"-
~("t.dp.dly[2]._y")->"t.dp.dly[2].__y"+
"t.dp.dly[2].__y"->"t.dp.dly[2].___y"-
~("t.dp.dly[2].__y")->"t.dp.dly[2].___y"+
"t.dp.dly[2].___y"->"t.dp.dly[2].y"-
~("t.dp.dly[2].___y")->"t.dp.dly[2].y"+
"t.dp.dly[2]._y"->"t.dp.dly[2].y"-
~("t.dp.dly[2]._y")->"t.dp.dly[2].y"+
"t.dp.dly[3].a"->"t.dp.dly[3]._y"-
~("t.dp.dly[3].a")->"t.dp.dly[3]._y"+
"t.dp.dly[3]._y"->"t.dp.dly[3].__y"-
~("t.dp.dly[3]._y")->"t.dp.dly[3].__y"+
"t.dp.dly[3].__y"->"t.dp.dly[3].___y"-
~("t.dp.dly[3].__y")->"t.dp.dly[3].___y"+
"t.dp.dly[3].___y"->"t.dp.dly[3].y"-
~("t.dp.dly[3].___y")->"t.dp.dly[3].y"+
"t.dp.dly[3]._y"->"t.dp.dly[3].y"-
~("t.dp.dly[3]._y")->"t.dp.dly[3].y"+
"t.dp.dly[4].a"->"t.dp.dly[4]._y"-
~("t.dp.dly[4].a")->"t.dp.dly[4]._y"+
"t.dp.dly[4]._y"->"t.dp.dly[4].__y"-
~("t.dp.dly[4]._y")->"t.dp.dly[4].__y"+
"t.dp.dly[4].__y"->"t.dp.dly[4].___y"-
~("t.dp.dly[4].__y")->"t.dp.dly[4].___y"+
"t.dp.dly[4].___y"->"t.dp.dly[4].y"-
~("t.dp.dly[4].___y")->"t.dp.dly[4].y"+
"t.dp.dly[4]._y"->"t.dp.dly[4].y"-
~("t.dp.dly[4]._y")->"t.dp.dly[4].y"+
"t.dp.dly[5].a"->"t.dp.dly[5]._y"-
~("t.dp.dly[5].a")->"t.dp.dly[5]._y"+
"t.dp.dly[5]._y"->"t.dp.dly[5].__y"-
~("t.dp.dly[5]._y")->"t.dp.dly[5].__y"+
"t.dp.dly[5].__y"->"t.dp.dly[5].___y"-
~("t.dp.dly[5].__y")->"t.dp.dly[5].___y"+
"t.dp.dly[5].___y"->"t.dp.dly[5].y"-
~("t.dp.dly[5].___y")->"t.dp.dly[5].y"+
"t.dp.dly[5]._y"->"t.dp.dly[5].y"-
~("t.dp.dly[5]._y")->"t.dp.dly[5].y"+
"t.dp.dly[6].a"->"t.dp.dly[6]._y"-
~("t.dp.dly[6].a")->"t.dp.dly[6]._y"+
"t.dp.dly[6]._y"->"t.dp.dly[6].__y"-
~("t.dp.dly[6]._y")->"t.dp.dly[6].__y"+
"t.dp.dly[6].__y"->"t.dp.dly[6].___y"-
~("t.dp.dly[6].__y")->"t.dp.dly[6].___y"+
"t.dp.dly[6].___y"->"t.dp.dly[6].y"-
~("t.dp.dly[6].___y")->"t.dp.dly[6].y"+
"t.dp.dly[6]._y"->"t.dp.dly[6].y"-
~("t.dp.dly[6]._y")->"t.dp.dly[6].y"+
"t.dp.dly[7].a"->"t.dp.dly[7]._y"-
~("t.dp.dly[7].a")->"t.dp.dly[7]._y"+
"t.dp.dly[7]._y"->"t.dp.dly[7].__y"-
~("t.dp.dly[7]._y")->"t.dp.dly[7].__y"+
"t.dp.dly[7].__y"->"t.dp.dly[7].___y"-
~("t.dp.dly[7].__y")->"t.dp.dly[7].___y"+
"t.dp.dly[7].___y"->"t.dp.dly[7].y"-
~("t.dp.dly[7].___y")->"t.dp.dly[7].y"+
"t.dp.dly[7]._y"->"t.dp.dly[7].y"-
~("t.dp.dly[7]._y")->"t.dp.dly[7].y"+
"t.dp.dly[8].a"->"t.dp.dly[8]._y"-
~("t.dp.dly[8].a")->"t.dp.dly[8]._y"+
"t.dp.dly[8]._y"->"t.dp.dly[8].__y"-
~("t.dp.dly[8]._y")->"t.dp.dly[8].__y"+
"t.dp.dly[8].__y"->"t.dp.dly[8].___y"-
~("t.dp.dly[8].__y")->"t.dp.dly[8].___y"+
"t.dp.dly[8].___y"->"t.dp.dly[8].y"-
~("t.dp.dly[8].___y")->"t.dp.dly[8].y"+
"t.dp.dly[8]._y"->"t.dp.dly[8].y"-
~("t.dp.dly[8]._y")->"t.dp.dly[8].y"+
"t.dp.dly[9].a"->"t.dp.dly[9]._y"-
~("t.dp.dly[9].a")->"t.dp.dly[9]._y"+
"t.dp.dly[9]._y"->"t.dp.dly[9].__y"-
~("t.dp.dly[9]._y")->"t.dp.dly[9].__y"+
"t.dp.dly[9].__y"->"t.dp.dly[9].___y"-
~("t.dp.dly[9].__y")->"t.dp.dly[9].___y"+
"t.dp.dly[9].___y"->"t.dp.dly[9].y"-
~("t.dp.dly[9].___y")->"t.dp.dly[9].y"+
"t.dp.dly[9]._y"->"t.dp.dly[9].y"-
~("t.dp.dly[9]._y")->"t.dp.dly[9].y"+
"t.dp.dly[10].a"->"t.dp.dly[10]._y"-
~("t.dp.dly[10].a")->"t.dp.dly[10]._y"+
"t.dp.dly[10]._y"->"t.dp.dly[10].__y"-
~("t.dp.dly[10]._y")->"t.dp.dly[10].__y"+
"t.dp.dly[10].__y"->"t.dp.dly[10].___y"-
~("t.dp.dly[10].__y")->"t.dp.dly[10].___y"+
"t.dp.dly[10].___y"->"t.dp.dly[10].y"-
~("t.dp.dly[10].___y")->"t.dp.dly[10].y"+
"t.dp.dly[10]._y"->"t.dp.dly[10].y"-
~("t.dp.dly[10]._y")->"t.dp.dly[10].y"+
"t.dp.dly[11].a"->"t.dp.dly[11]._y"-
~("t.dp.dly[11].a")->"t.dp.dly[11]._y"+
"t.dp.dly[11]._y"->"t.dp.dly[11].__y"-
~("t.dp.dly[11]._y")->"t.dp.dly[11].__y"+
"t.dp.dly[11].__y"->"t.dp.dly[11].___y"-
~("t.dp.dly[11].__y")->"t.dp.dly[11].___y"+
"t.dp.dly[11].___y"->"t.dp.dly[11].y"-
~("t.dp.dly[11].___y")->"t.dp.dly[11].y"+
"t.dp.dly[11]._y"->"t.dp.dly[11].y"-
~("t.dp.dly[11]._y")->"t.dp.dly[11].y"+
"t.dp.dly[12].a"->"t.dp.dly[12]._y"-
~("t.dp.dly[12].a")->"t.dp.dly[12]._y"+
"t.dp.dly[12]._y"->"t.dp.dly[12].__y"-
~("t.dp.dly[12]._y")->"t.dp.dly[12].__y"+
"t.dp.dly[12].__y"->"t.dp.dly[12].___y"-
~("t.dp.dly[12].__y")->"t.dp.dly[12].___y"+
"t.dp.dly[12].___y"->"t.dp.dly[12].y"-
~("t.dp.dly[12].___y")->"t.dp.dly[12].y"+
"t.dp.dly[12]._y"->"t.dp.dly[12].y"-
~("t.dp.dly[12]._y")->"t.dp.dly[12].y"+
"t.dp.dly[13].a"->"t.dp.dly[13]._y"-
~("t.dp.dly[13].a")->"t.dp.dly[13]._y"+
"t.dp.dly[13]._y"->"t.dp.dly[13].__y"-
~("t.dp.dly[13]._y")->"t.dp.dly[13].__y"+
"t.dp.dly[13].__y"->"t.dp.dly[13].___y"-
~("t.dp.dly[13].__y")->"t.dp.dly[13].___y"+
"t.dp.dly[13].___y"->"t.dp.dly[13].y"-
~("t.dp.dly[13].___y")->"t.dp.dly[13].y"+
"t.dp.dly[13]._y"->"t.dp.dly[13].y"-
~("t.dp.dly[13]._y")->"t.dp.dly[13].y"+
"t.dp.dly[14].a"->"t.dp.dly[14]._y"-
~("t.dp.dly[14].a")->"t.dp.dly[14]._y"+
"t.dp.dly[14]._y"->"t.dp.dly[14].__y"-
~("t.dp.dly[14]._y")->"t.dp.dly[14].__y"+
"t.dp.dly[14].__y"->"t.dp.dly[14].___y"-
~("t.dp.dly[14].__y")->"t.dp.dly[14].___y"+
"t.dp.dly[14].___y"->"t.dp.dly[14].y"-
~("t.dp.dly[14].___y")->"t.dp.dly[14].y"+
= "t.dp.dly[14].y" "t.dp.mu2[3].b"
= "t.dp.dly[14].a" "t.dp.dly[13].y"
= "t.dp.dly[13].a" "t.dp.dly[12].y"
= "t.dp.dly[12].a" "t.dp.dly[11].y"
= "t.dp.dly[11].a" "t.dp.dly[10].y"
= "t.dp.dly[10].a" "t.dp.dly[9].y"
= "t.dp.dly[9].a" "t.dp.dly[8].y"
= "t.dp.dly[8].a" "t.dp.dly[7].y"
= "t.dp.dly[7].a" "t.dp.and2[3].y"
= "t.dp.dly[6].y" "t.dp.mu2[2].b"
"t.dp.dly[14]._y"->"t.dp.dly[14].y"-
~("t.dp.dly[14]._y")->"t.dp.dly[14].y"+
= "t.dp.dly[6].y" "t.dp.mu2[3].b"
= "t.dp.dly[6].a" "t.dp.dly[5].y"
= "t.dp.dly[5].a" "t.dp.dly[4].y"
= "t.dp.dly[4].a" "t.dp.dly[3].y"
= "t.dp.dly[3].a" "t.dp.and2[2].y"
= "t.dp.dly[2].y" "t.dp.mu2[1].b"
= "t.dp.dly[2].a" "t.dp.dly[1].y"
= "t.dp.dly[4].a" "t.dp.and2[3].y"
= "t.dp.dly[3].y" "t.dp.mu2[2].b"
= "t.dp.dly[3].a" "t.dp.dly[2].y"
= "t.dp.dly[2].a" "t.dp.and2[2].y"
= "t.dp.dly[1].y" "t.dp.mu2[1].b"
= "t.dp.dly[1].a" "t.dp.and2[1].y"
= "t.dp.dly[0].y" "t.dp.mu2[0].b"
= "t.dp.dly[0].a" "t.dp.and2[0].y"
@@ -243,15 +180,10 @@
= "t.dp._a[3]" "t.dp.mu2[3].a"
= "t.dp._a[3]" "t.dp.and2[3].a"
= "t.dp._a[3]" "t.dp.mu2[2].y"
= "t.dp.out" "t.dp.mu2[3].y"
= "t.dp.out" "t.dp._a[4]"
= "t.dp.in" "t.dp.mu2[0].a"
= "t.dp.in" "t.dp.and2[0].a"
= "t.dp.in" "t.dp._a[0]"
= "t.dp.y" "t.dp.mu2[3].y"
= "t.dp.y" "t.dp._a[4]"
= "Vdd" "t.dp.supply.vdd"
= "GND" "t.dp.supply.vss"
= "t.out" "t.dp.out"
= "t.in" "t.dp.in"
= "t.s[0]" "t.dp.s[0]"
= "t.s[1]" "t.dp.s[1]"
= "t.s[2]" "t.dp.s[2]"
test/unit_tests/delayprog_4/test.act
+2 -2
View File
@@ -31,8 +31,8 @@ import globals;
open tmpl::dataflow_neuro;
defproc delayprog_4 (bool? s[4], in; bool! out){
delayprog<4> dp(.in=in, .out=out, .s = s);
defproc delayprog_4 (bool? s[4], a; bool! y){
delayprog<4> dp(.a=a, .y=y, .s = s);
dp.supply.vss = GND;
dp.supply.vdd = Vdd;
test/unit_tests/delayprog_4/test.prsim
+11 -11
View File
@@ -2,7 +2,7 @@ watchall
system "echo '0'"
set t.in 0
set t.a 0
set t.s[0] 1
set t.s[1] 1
set t.s[2] 1
@@ -11,17 +11,17 @@ set t.s[3] 1
cycle
mode run
# assert t.out 0
assert t.y 0
system "echo '[] setting high'"
set t.in 1
set t.a 1
cycle
assert t.out 1
assert t.y 1
system "echo '[] setting low'"
set t.in 0
set t.a 0
cycle
assert t.out 0
assert t.y 0
system "echo '[] setting configs low'"
set t.s[0] 0
@@ -29,14 +29,14 @@ set t.s[1] 0
set t.s[2] 0
set t.s[3] 0
cycle
assert t.out 0
assert t.y 0
system "echo '[] setting high'"
set t.in 1
set t.a 1
cycle
assert t.out 1
assert t.y 1
system "echo '[] setting low'"
set t.in 0
set t.a 0
cycle
assert t.out 0
assert t.y 0
test/unit_tests/demux_7/run/prsim.out
+80 -80
View File
@@ -1,4 +1,4 @@
my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.cond.v my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.ct.in[4] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.vc.ct.tmp[9] my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.ct.tmp[8] my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.ct.in[5] my_demux.my_demux.vc.ct.in[1] my_demux.my_demux.vc.ct.in[6] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.ct.in[2] my_demux.my_demux.vc.ct.tmp[7] my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_v my_demux.my_demux.vc.ct.C3Els[0]._y my_demux.my_demux.vc.ct.in[0] my_demux.out2.v my_demux.my_demux.vc.ct.C3Els[1]._y my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.ct.C2Els[0]._y my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux.vc.ct.in[3] my_demux.my_demux._out_v my_demux.in.v my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.ct.C2Els[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y
my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.tmp[9] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux.vc.tmp[7] my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.C2Els[1]._y my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.tmp[6] my_demux.my_demux.vc.tmp[1] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.C2Els[0]._y my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux.vc.tmp[8] my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_c_v_ my_demux.out2.v my_demux.my_demux._in_v my_demux.my_demux.vc.tmp[4] my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.tmp[0] my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.my_demux.vc.tmp[5] my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux._out_v my_demux.my_demux.vc.C3Els[0]._y my_demux.in.v my_demux.my_demux.vc.C3Els[1]._y my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.tmp[3] my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.vc.tmp[2] my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y
119199 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
119199 my_demux.my_demux.c_buf_f.in : 0
119199 my_demux.my_demux.c_buf_t.in : 0
@@ -26,7 +26,7 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
119286 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
119311 my_demux.my_demux._out1_a_B : 1 [by my_demux.out1.a:=0]
119333 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux._out1_a_B:=1]
119378 my_demux.my_demux.vc.ct.in[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
119378 my_demux.my_demux.vc.tmp[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
119403 my_demux.my_demux._out_v : 0 [by my_demux.my_demux.out_or._y:=1]
119456 my_demux.my_demux.vc.OR2_tf[6]._y : 1 [by my_demux.my_demux.out1_f_buf_func[6].n1:=0]
119493 my_demux.my_demux.vc.OR2_tf[2]._y : 1 [by my_demux.my_demux.out1_f_buf_func[2].n1:=0]
@@ -36,35 +36,35 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
119757 my_demux.my_demux.out1_en_buf_t.buf2._y : 0 [by my_demux.my_demux._en:=1]
119790 my_demux.my_demux._c_f_buf[0] : 0 [by my_demux.my_demux.c_buf_f.buf2._y:=1]
119848 my_demux.my_demux._en1_X_t[0] : 1 [by my_demux.my_demux.out1_en_buf_t.buf2._y:=0]
119852 my_demux.my_demux.vc.ct.in[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
119852 my_demux.my_demux.vc.tmp[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
119938 my_demux.my_demux.c_f_c_t_or._y : 1 [by my_demux.my_demux.c_buf_t.in:=0]
120039 my_demux.my_demux._c_t_buf[0] : 0 [by my_demux.my_demux.c_buf_t.buf2._y:=1]
120158 my_demux.my_demux.out1_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux._out1_a_B:=1]
120165 my_demux.my_demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
120408 my_demux.my_demux.vc.OR2_tf[3]._y : 1 [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
121005 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
121111 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
121111 my_demux.my_demux.vc.tmp[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
121206 my_demux.my_demux.vc.OR2_tf[4]._y : 1 [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
121284 my_demux.my_demux.vc.ct.in[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
121481 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
121756 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[0]:=0]
121284 my_demux.my_demux.vc.tmp[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
121481 my_demux.my_demux.vc.tmp[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
121756 my_demux.my_demux.vc.C2Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[0]:=0]
122127 my_demux.my_demux._c_v : 0 [by my_demux.my_demux.c_f_c_t_or._y:=1]
123195 my_demux.my_demux.vc.ct.in[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
123650 my_demux.my_demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.vc.ct.in[3]:=0]
123662 my_demux.my_demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
123195 my_demux.my_demux.vc.tmp[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
123650 my_demux.my_demux.vc.C2Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[3]:=0]
123662 my_demux.my_demux.vc.tmp[8] : 0 [by my_demux.my_demux.vc.C2Els[1]._y:=1]
126256 my_demux.my_demux._en2_X_t[0] : 1 [by my_demux.my_demux.out2_en_buf_t.buf2._y:=0]
133652 my_demux.my_demux.out2_en_buf_f.buf2._y : 0 [by my_demux.my_demux._en:=1]
134056 my_demux.my_demux._en2_X_f[0] : 1 [by my_demux.my_demux.out2_en_buf_f.buf2._y:=0]
135118 my_demux.my_demux.vc.ct.in[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
135130 my_demux.my_demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[6]:=0]
140752 my_demux.my_demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
141046 my_demux.my_demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
145322 my_demux.my_demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.vc.ct.tmp[9]:=0]
148221 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
135118 my_demux.my_demux.vc.tmp[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
135130 my_demux.my_demux.vc.C3Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[6]:=0]
140752 my_demux.my_demux.vc.tmp[7] : 0 [by my_demux.my_demux.vc.C2Els[0]._y:=1]
141046 my_demux.my_demux.vc.tmp[9] : 0 [by my_demux.my_demux.vc.C3Els[0]._y:=1]
145322 my_demux.my_demux.vc.C3Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[9]:=0]
148221 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.C3Els[1]._y:=1]
148223 my_demux.my_demux.c_el._y : 1 [by my_demux.my_demux._in_v:=0]
149461 my_demux.my_demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
152516 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
152758 my_demux.cond.v : 0 [by my_demux.my_demux.c_el._y:=1]
152758 my_demux.my_demux._in_c_v_ : 0 [by my_demux.my_demux.c_el._y:=1]
153765 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
166711 my_demux.my_demux._out2_a_B : 1 [by my_demux.out2.a:=0]
166877 my_demux.my_demux.out2_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux._out2_a_B:=1]
@@ -94,7 +94,7 @@ Output neutral checked
226364 my_demux.my_demux.vc.OR2_tf[4]._y : 0 [by my_demux.my_demux.out1_t_buf_func[4].n1:=1]
226415 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
226718 my_demux.my_demux.vc.OR2_tf[6]._y : 0 [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
226720 my_demux.my_demux.vc.ct.in[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
226720 my_demux.my_demux.vc.tmp[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
226876 my_demux.my_demux.vc.OR2_tf[3]._y : 0 [by my_demux.my_demux.out1_t_buf_func[3].n1:=1]
226896 my_demux.my_demux.c_buf_t.buf2._y : 0 [by my_demux.my_demux.c_buf_t.in:=1]
226899 my_demux.my_demux._c_t_buf[0] : 1 [by my_demux.my_demux.c_buf_t.buf2._y:=0]
@@ -109,30 +109,30 @@ Output neutral checked
228500 my_demux.my_demux.out1_t_buf_func[2]._y : 0 [by my_demux.my_demux._c_t_buf[0]:=1]
228783 my_demux.my_demux.vc.OR2_tf[2]._y : 0 [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
228989 my_demux.my_demux.vc.OR2_tf[5]._y : 0 [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
229148 my_demux.my_demux.vc.ct.in[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
229148 my_demux.my_demux.vc.tmp[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
229660 my_demux.my_demux.out1_t_buf_func[5]._y : 0 [by my_demux.my_demux._c_t_buf[0]:=1]
230081 my_demux.my_demux.out1_t_buf_func[2].y : 1 [by my_demux.my_demux.out1_t_buf_func[2]._y:=0]
230910 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
232197 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
238128 my_demux.my_demux.vc.ct.in[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
239456 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
232197 my_demux.my_demux.vc.tmp[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
238128 my_demux.my_demux.vc.tmp[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
239456 my_demux.my_demux.vc.tmp[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
240582 my_demux.my_demux.out1_t_buf_func[6]._y : 0 [by my_demux.my_demux._c_t_buf[0]:=1]
240727 my_demux.my_demux.out1_t_buf_func[6].y : 1 [by my_demux.my_demux.out1_t_buf_func[6]._y:=0]
241688 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[1]:=1]
244520 my_demux.my_demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
241688 my_demux.my_demux.vc.C2Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[1]:=1]
244520 my_demux.my_demux.vc.tmp[7] : 1 [by my_demux.my_demux.vc.C2Els[0]._y:=0]
249336 my_demux.my_demux.out1_t_buf_func[5].y : 1 [by my_demux.my_demux.out1_t_buf_func[5]._y:=0]
250289 my_demux.my_demux.vc.ct.in[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
250289 my_demux.my_demux.vc.tmp[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
253239 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
256643 my_demux.my_demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[4]:=1]
256644 my_demux.my_demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
287834 my_demux.my_demux.vc.ct.in[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
327118 my_demux.my_demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.vc.ct.in[3]:=1]
327280 my_demux.my_demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
334649 my_demux.my_demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.vc.ct.tmp[8]:=1]
334663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
256643 my_demux.my_demux.vc.C3Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[4]:=1]
256644 my_demux.my_demux.vc.tmp[9] : 1 [by my_demux.my_demux.vc.C3Els[0]._y:=0]
287834 my_demux.my_demux.vc.tmp[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
327118 my_demux.my_demux.vc.C2Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[3]:=1]
327280 my_demux.my_demux.vc.tmp[8] : 1 [by my_demux.my_demux.vc.C2Els[1]._y:=0]
334649 my_demux.my_demux.vc.C3Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[8]:=1]
334663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.C3Els[1]._y:=0]
334670 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
334823 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
334824 my_demux.cond.v : 1 [by my_demux.my_demux.c_el._y:=0]
334824 my_demux.my_demux._in_c_v_ : 1 [by my_demux.my_demux.c_el._y:=0]
356227 my_demux.in.v : 1 [by my_demux.my_demux.in_v_buf._y:=0]
356227 my_demux.out1.v : 1
356228 my_demux.my_demux.out_or._y : 0 [by my_demux.out1.v:=1]
@@ -158,25 +158,25 @@ Output neutral checked
393460 my_demux.my_demux.vc.OR2_tf[4]._y : 1 [by my_demux.my_demux.out1_t_buf_func[4].n1:=0]
393462 my_demux.my_demux.vc.OR2_tf[2]._y : 1 [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
393501 my_demux.my_demux.vc.OR2_tf[3]._y : 1 [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
393596 my_demux.my_demux.vc.ct.in[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
393596 my_demux.my_demux.vc.tmp[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
394400 my_demux.my_demux.vc.OR2_tf[5]._y : 1 [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
394735 my_demux.my_demux.vc.ct.in[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
394735 my_demux.my_demux.vc.tmp[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
396032 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
396040 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
396277 my_demux.my_demux.vc.ct.in[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
396040 my_demux.my_demux.vc.tmp[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
396277 my_demux.my_demux.vc.tmp[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
401820 my_demux.my_demux.vc.OR2_tf[6]._y : 1 [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
401854 my_demux.my_demux.vc.ct.in[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
407195 my_demux.my_demux.vc.ct.in[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
408113 my_demux.my_demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.vc.ct.in[2]:=0]
408117 my_demux.my_demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
415741 my_demux.my_demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[6]:=0]
401854 my_demux.my_demux.vc.tmp[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
407195 my_demux.my_demux.vc.tmp[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
408113 my_demux.my_demux.vc.C2Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[2]:=0]
408117 my_demux.my_demux.vc.tmp[8] : 0 [by my_demux.my_demux.vc.C2Els[1]._y:=1]
415741 my_demux.my_demux.vc.C3Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[6]:=0]
452421 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
454819 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
458034 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[1]:=0]
462119 my_demux.my_demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
505153 my_demux.my_demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
505201 my_demux.my_demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.vc.ct.tmp[7]:=0]
505204 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
454819 my_demux.my_demux.vc.tmp[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
458034 my_demux.my_demux.vc.C2Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[1]:=0]
462119 my_demux.my_demux.vc.tmp[9] : 0 [by my_demux.my_demux.vc.C3Els[0]._y:=1]
505153 my_demux.my_demux.vc.tmp[7] : 0 [by my_demux.my_demux.vc.C2Els[0]._y:=1]
505201 my_demux.my_demux.vc.C3Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[7]:=0]
505204 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.C3Els[1]._y:=1]
505382 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
526359 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
First Cond Checked
@@ -214,7 +214,7 @@ Output neutral checked
585101 my_demux.my_demux._c_v : 0 [by my_demux.my_demux.c_f_c_t_or._y:=1]
585114 my_demux.my_demux.c_el._y : 1 [by my_demux.my_demux._c_v:=0]
586919 my_demux.my_demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
602098 my_demux.cond.v : 0 [by my_demux.my_demux.c_el._y:=1]
602098 my_demux.my_demux._in_c_v_ : 0 [by my_demux.my_demux.c_el._y:=1]
606729 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux._out1_a_B:=1]
607086 my_demux.my_demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
628359 my_demux.my_demux.out_or._y : 1 [by my_demux.out1.v:=0]
@@ -241,46 +241,46 @@ Output neutral checked
639106 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_f_buf_func[1].n1:=1]
639116 my_demux.my_demux.c_buf_f.buf2._y : 0 [by my_demux.my_demux.c_buf_f.in:=1]
639120 my_demux.my_demux.vc.OR2_tf[6]._y : 0 [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
639190 my_demux.my_demux.vc.ct.in[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
639190 my_demux.my_demux.vc.tmp[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
639206 my_demux.my_demux.vc.OR2_tf[5]._y : 0 [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
639330 my_demux.my_demux.vc.OR2_tf[2]._y : 0 [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
639341 my_demux.my_demux.vc.ct.in[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
639949 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
639341 my_demux.my_demux.vc.tmp[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
639949 my_demux.my_demux.vc.tmp[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
640149 my_demux.my_demux.c_f_c_t_or._y : 0 [by my_demux.my_demux.c_buf_f.in:=1]
640152 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
640306 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_f_buf_func[0].n1:=1]
640360 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
640360 my_demux.my_demux.vc.tmp[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
640575 my_demux.my_demux._c_f_buf[0] : 1 [by my_demux.my_demux.c_buf_f.buf2._y:=0]
640656 my_demux.my_demux.out2_t_buf_func[6]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
640667 my_demux.my_demux.out2_f_buf_func[3]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
641280 my_demux.my_demux.out2_f_buf_func[3].y : 1 [by my_demux.my_demux.out2_f_buf_func[3]._y:=0]
641508 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[0]:=1]
641508 my_demux.my_demux.vc.C2Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[0]:=1]
641736 my_demux.my_demux.out2_t_buf_func[2]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
641781 my_demux.my_demux.out2_t_buf_func[2].y : 1 [by my_demux.my_demux.out2_t_buf_func[2]._y:=0]
642400 my_demux.my_demux.out2_t_buf_func[6].y : 1 [by my_demux.my_demux.out2_t_buf_func[6]._y:=0]
647557 my_demux.my_demux.vc.OR2_tf[3]._y : 0 [by my_demux.my_demux.out1_f_buf_func[3].n1:=1]
648554 my_demux.my_demux.vc.ct.in[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
648554 my_demux.my_demux.vc.tmp[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
648886 my_demux.my_demux.out2_f_buf_func[4]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
649227 my_demux.my_demux.out2_t_buf_func[5]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
649411 my_demux.my_demux.out2_f_buf_func[4].y : 1 [by my_demux.my_demux.out2_f_buf_func[4]._y:=0]
650127 my_demux.my_demux.out2_t_buf_func[5].y : 1 [by my_demux.my_demux.out2_t_buf_func[5]._y:=0]
650203 my_demux.my_demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.vc.ct.in[3]:=1]
650255 my_demux.my_demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
650203 my_demux.my_demux.vc.C2Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[3]:=1]
650255 my_demux.my_demux.vc.tmp[8] : 1 [by my_demux.my_demux.vc.C2Els[1]._y:=0]
651652 my_demux.my_demux.out2_f_buf_func[0]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
651659 my_demux.my_demux.out2_f_buf_func[0].y : 1 [by my_demux.my_demux.out2_f_buf_func[0]._y:=0]
655530 my_demux.my_demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
655530 my_demux.my_demux.vc.tmp[7] : 1 [by my_demux.my_demux.vc.C2Els[0]._y:=0]
658558 my_demux.my_demux.out2_f_buf_func[1]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
670546 my_demux.my_demux.vc.OR2_tf[4]._y : 0 [by my_demux.my_demux.out1_f_buf_func[4].n1:=1]
674170 my_demux.my_demux.out2_f_buf_func[1].y : 1 [by my_demux.my_demux.out2_f_buf_func[1]._y:=0]
677013 my_demux.my_demux.vc.ct.in[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
689628 my_demux.my_demux.vc.ct.in[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
689630 my_demux.my_demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[5]:=1]
689984 my_demux.my_demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
690117 my_demux.my_demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.vc.ct.tmp[9]:=1]
690118 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
677013 my_demux.my_demux.vc.tmp[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
689628 my_demux.my_demux.vc.tmp[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
689630 my_demux.my_demux.vc.C3Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[5]:=1]
689984 my_demux.my_demux.vc.tmp[9] : 1 [by my_demux.my_demux.vc.C3Els[0]._y:=0]
690117 my_demux.my_demux.vc.C3Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[9]:=1]
690118 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.C3Els[1]._y:=0]
690122 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
690664 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
690665 my_demux.cond.v : 1 [by my_demux.my_demux.c_el._y:=0]
690665 my_demux.my_demux._in_c_v_ : 1 [by my_demux.my_demux.c_el._y:=0]
735685 my_demux.in.v : 1 [by my_demux.my_demux.in_v_buf._y:=0]
735685 my_demux.out2.v : 1
748063 my_demux.my_demux.out_or._y : 0 [by my_demux.out2.v:=1]
@@ -305,26 +305,26 @@ Output neutral checked
817979 my_demux.my_demux.out1_f_buf_func[3].n1 : 0
817982 my_demux.my_demux.vc.OR2_tf[3]._y : 1 [by my_demux.my_demux.out1_f_buf_func[3].n1:=0]
817991 my_demux.my_demux.vc.OR2_tf[5]._y : 1 [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
817992 my_demux.my_demux.vc.ct.in[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
818020 my_demux.my_demux.vc.ct.in[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
817992 my_demux.my_demux.vc.tmp[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
818020 my_demux.my_demux.vc.tmp[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
818022 my_demux.my_demux.vc.OR2_tf[2]._y : 1 [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
818106 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_f_buf_func[0].n1:=0]
818148 my_demux.my_demux.vc.OR2_tf[6]._y : 1 [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
818198 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
818198 my_demux.my_demux.vc.tmp[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
818212 my_demux.my_demux.vc.OR2_tf[4]._y : 1 [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
818214 my_demux.my_demux.vc.ct.in[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
818214 my_demux.my_demux.vc.tmp[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
819258 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_f_buf_func[1].n1:=0]
819259 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
820760 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[1]:=0]
820762 my_demux.my_demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
820875 my_demux.my_demux.vc.ct.in[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
820893 my_demux.my_demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[6]:=0]
821012 my_demux.my_demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
830774 my_demux.my_demux.vc.ct.in[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
836494 my_demux.my_demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.vc.ct.in[2]:=0]
836502 my_demux.my_demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
836556 my_demux.my_demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.vc.ct.tmp[8]:=0]
887094 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
819259 my_demux.my_demux.vc.tmp[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
820760 my_demux.my_demux.vc.C2Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[1]:=0]
820762 my_demux.my_demux.vc.tmp[7] : 0 [by my_demux.my_demux.vc.C2Els[0]._y:=1]
820875 my_demux.my_demux.vc.tmp[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
820893 my_demux.my_demux.vc.C3Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[6]:=0]
821012 my_demux.my_demux.vc.tmp[9] : 0 [by my_demux.my_demux.vc.C3Els[0]._y:=1]
830774 my_demux.my_demux.vc.tmp[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
836494 my_demux.my_demux.vc.C2Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[2]:=0]
836502 my_demux.my_demux.vc.tmp[8] : 0 [by my_demux.my_demux.vc.C2Els[1]._y:=1]
836556 my_demux.my_demux.vc.C3Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[8]:=0]
887094 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.C3Els[1]._y:=1]
887099 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
888166 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
Second Cond Checked
test/unit_tests/demux_7/run/prsim.pdf
BIN
View File
Binary file not shown.
test/unit_tests/demux_7/run/test.prs
+48 -69
View File
@@ -330,7 +330,6 @@
= "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.vc.in.d[6].d[0]"
= "my_demux.my_demux.in.d.d[6].d[1]" "my_demux.my_demux.vc.in.d[6].d[1]"
= "my_demux.my_demux.in.a" "my_demux.my_demux.en_ctl.c1"
= "my_demux.my_demux.in.a" "my_demux.my_demux.cond.a"
= "my_demux.my_demux.in.a" "my_demux.my_demux.inack_ctl.y"
= "my_demux.my_demux.in.v" "my_demux.my_demux.in_v_buf.y"
= "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.out2_f_buf_func[6].n1"
@@ -427,6 +426,8 @@
~("my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b")->"my_demux.my_demux.out_or._y"+
"my_demux.my_demux.out_or._y"->"my_demux.my_demux.out_or.y"-
~("my_demux.my_demux.out_or._y")->"my_demux.my_demux.out_or.y"+
= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.c_el.y"
= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.inack_ctl.c2"
= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_a_B_buf_f.out[0]"
= "my_demux.my_demux._out1_a_BX_t[1]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
= "my_demux.my_demux._out1_a_BX_t[2]" "my_demux.my_demux.out1_a_B_buf_f.out[2]"
@@ -853,20 +854,12 @@
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out2_en_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[6].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_f_buf_func[6].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[5].vdd"
@@ -937,59 +930,22 @@
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.en_ctl.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.inack_ctl.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
~"my_demux.my_demux.vc.ct.C2Els[0].c1"&~"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"+
"my_demux.my_demux.vc.ct.C2Els[0].c1"&"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"-
"my_demux.my_demux.vc.ct.C2Els[0]._y"->"my_demux.my_demux.vc.ct.C2Els[0].y"-
~("my_demux.my_demux.vc.ct.C2Els[0]._y")->"my_demux.my_demux.vc.ct.C2Els[0].y"+
~"my_demux.my_demux.vc.ct.C2Els[1].c1"&~"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"+
"my_demux.my_demux.vc.ct.C2Els[1].c1"&"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"-
"my_demux.my_demux.vc.ct.C2Els[1]._y"->"my_demux.my_demux.vc.ct.C2Els[1].y"-
~("my_demux.my_demux.vc.ct.C2Els[1]._y")->"my_demux.my_demux.vc.ct.C2Els[1].y"+
~"my_demux.my_demux.vc.ct.C3Els[0].c1"&~"my_demux.my_demux.vc.ct.C3Els[0].c2"&~"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"+
"my_demux.my_demux.vc.ct.C3Els[0].c1"&"my_demux.my_demux.vc.ct.C3Els[0].c2"&"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"-
"my_demux.my_demux.vc.ct.C3Els[0]._y"->"my_demux.my_demux.vc.ct.C3Els[0].y"-
~("my_demux.my_demux.vc.ct.C3Els[0]._y")->"my_demux.my_demux.vc.ct.C3Els[0].y"+
~"my_demux.my_demux.vc.ct.C3Els[1].c1"&~"my_demux.my_demux.vc.ct.C3Els[1].c2"&~"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"+
"my_demux.my_demux.vc.ct.C3Els[1].c1"&"my_demux.my_demux.vc.ct.C3Els[1].c2"&"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"-
"my_demux.my_demux.vc.ct.C3Els[1]._y"->"my_demux.my_demux.vc.ct.C3Els[1].y"-
~("my_demux.my_demux.vc.ct.C3Els[1]._y")->"my_demux.my_demux.vc.ct.C3Els[1].y"+
= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C3Els[1].c1"
= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C2Els[0].y"
= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C3Els[1].c2"
= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C2Els[1].y"
= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[1].c3"
= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[0].y"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[1].vdd"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[0].vdd"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[1].vdd"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[0].vdd"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[1].vss"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[0].vss"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[1].vss"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[0].vss"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.C2Els[0].c1"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.tmp[0]"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.C2Els[0].c2"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.tmp[1]"
= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.C2Els[1].c1"
= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.tmp[2]"
= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.C2Els[1].c2"
= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.tmp[3]"
= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.C3Els[0].c1"
= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.tmp[4]"
= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.C3Els[0].c2"
= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.tmp[5]"
= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.C3Els[0].c3"
= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.tmp[6]"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.C3Els[1].y"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.tmp[10]"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
~"my_demux.my_demux.vc.C2Els[0].c1"&~"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"+
"my_demux.my_demux.vc.C2Els[0].c1"&"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"-
"my_demux.my_demux.vc.C2Els[0]._y"->"my_demux.my_demux.vc.C2Els[0].y"-
~("my_demux.my_demux.vc.C2Els[0]._y")->"my_demux.my_demux.vc.C2Els[0].y"+
~"my_demux.my_demux.vc.C2Els[1].c1"&~"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"+
"my_demux.my_demux.vc.C2Els[1].c1"&"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"-
"my_demux.my_demux.vc.C2Els[1]._y"->"my_demux.my_demux.vc.C2Els[1].y"-
~("my_demux.my_demux.vc.C2Els[1]._y")->"my_demux.my_demux.vc.C2Els[1].y"+
~"my_demux.my_demux.vc.C3Els[0].c1"&~"my_demux.my_demux.vc.C3Els[0].c2"&~"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"+
"my_demux.my_demux.vc.C3Els[0].c1"&"my_demux.my_demux.vc.C3Els[0].c2"&"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"-
"my_demux.my_demux.vc.C3Els[0]._y"->"my_demux.my_demux.vc.C3Els[0].y"-
~("my_demux.my_demux.vc.C3Els[0]._y")->"my_demux.my_demux.vc.C3Els[0].y"+
~"my_demux.my_demux.vc.C3Els[1].c1"&~"my_demux.my_demux.vc.C3Els[1].c2"&~"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"+
"my_demux.my_demux.vc.C3Els[1].c1"&"my_demux.my_demux.vc.C3Els[1].c2"&"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"-
"my_demux.my_demux.vc.C3Els[1]._y"->"my_demux.my_demux.vc.C3Els[1].y"-
~("my_demux.my_demux.vc.C3Els[1]._y")->"my_demux.my_demux.vc.C3Els[1].y"+
"my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
"my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
@@ -1018,8 +974,30 @@
~("my_demux.my_demux.vc.OR2_tf[6].a"|"my_demux.my_demux.vc.OR2_tf[6].b")->"my_demux.my_demux.vc.OR2_tf[6]._y"+
"my_demux.my_demux.vc.OR2_tf[6]._y"->"my_demux.my_demux.vc.OR2_tf[6].y"-
~("my_demux.my_demux.vc.OR2_tf[6]._y")->"my_demux.my_demux.vc.OR2_tf[6].y"+
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.ct.supply.vss"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.ct.supply.vdd"
= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.C2Els[0].c1"
= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.C2Els[0].c2"
= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.C2Els[1].c1"
= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.C2Els[1].c2"
= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.C3Els[0].c1"
= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.C3Els[0].c2"
= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.C3Els[0].c3"
= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C3Els[1].c1"
= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C2Els[0].y"
= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C3Els[1].c2"
= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C2Els[1].y"
= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[1].c3"
= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[0].y"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[0].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[0].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[6].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[5].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[4].vdd"
@@ -1027,6 +1005,10 @@
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[2].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[0].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[0].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[6].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[5].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[4].vss"
@@ -1034,7 +1016,6 @@
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[2].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.ct.out"
= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
@@ -1091,6 +1072,8 @@
= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.OR2_tf[0].a"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.C3Els[1].y"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.tmp[10]"
"my_demux.my_demux.out2_a_B_buf_f.buf2.a"->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"-
~("my_demux.my_demux.out2_a_B_buf_f.buf2.a")->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"+
"my_demux.my_demux.out2_a_B_buf_f.buf2._y"->"my_demux.my_demux.out2_a_B_buf_f.buf2.y"-
@@ -1127,9 +1110,6 @@
= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
= "my_demux.my_demux.cond.v" "my_demux.my_demux.c_el.y"
= "my_demux.my_demux.cond.v" "my_demux.my_demux.inack_ctl.c2"
= "my_demux.my_demux.cond.v" "my_demux.my_demux._in_c_v_"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_f_c_t_or.b"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_buf_f.in"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
@@ -1406,7 +1386,6 @@
= "my_demux.in.d.d[6].t" "my_demux.my_demux.in.d.d[6].t"
= "my_demux.in.d.d[6].d[0]" "my_demux.my_demux.in.d.d[6].d[0]"
= "my_demux.in.d.d[6].d[1]" "my_demux.my_demux.in.d.d[6].d[1]"
= "my_demux.in.a" "my_demux.cond.a"
= "my_demux.in.d.d[6].d[0]" "my_demux.in.d.d[6].f"
= "my_demux.in.d.d[6].d[1]" "my_demux.in.d.d[6].t"
= "my_demux.in.d.d[5].d[0]" "my_demux.in.d.d[5].f"
test/unit_tests/demux_7/test.prsim
-3
View File
@@ -18,7 +18,6 @@ mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 7
assert my_demux.cond.v 0
cycle
system "echo 'Output neutral checked'"
@@ -29,7 +28,6 @@ set-qdi-channel-valid "my_demux.in" 7 127
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert my_demux.cond.v 1
assert-qdi-channel-valid "my_demux.out1" 7 127
set my_demux.out1.v 1
@@ -70,7 +68,6 @@ set-qdi-channel-valid "my_demux.in" 7 100
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert my_demux.cond.v 1
assert-qdi-channel-valid "my_demux.out2" 7 100
set my_demux.out2.v 1
test/unit_tests/demux_bit_7/run/prsim.out
-336
View File
@@ -1,336 +0,0 @@
my_demux.in.d.d[5].t my_demux.my_demux.demux._en2_X_t[0] my_demux.in.d.d[2].f my_demux.my_demux.demux._out1_a_BX_f[0] my_demux.my_demux.demux._out2_a_BX_t[0] my_demux.in.d.d[5].f my_demux.my_demux.demux._out1_a_B my_demux.my_demux.demux._en1_X_t[0] my_demux.my_demux.demux._out_v my_demux.in.d.d[1].f my_demux.my_demux.demux._out2_a_BX_f[0] my_demux.my_demux.demux._en1_X_f[0] my_demux.in.d.d[6].f my_demux.in.d.d[2].t my_demux.my_demux.demux.vc.OR2_tf[2]._y my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y my_demux.in.d.d[0].f my_demux.my_demux.demux._c_f_buf[0] my_demux.my_demux.demux.vc.ct.in[1] my_demux.my_demux.demux._out1_a_BX_t[0] my_demux.my_demux.demux._c_t_buf[0] my_demux.out1.a my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[8] my_demux.in.d.d[4].f my_demux.in.d.d[4].t my_demux.my_demux.demux._in_c_v_ my_demux.my_demux.demux.out_or._y my_demux.my_demux.demux._c_v my_demux.my_demux.demux._en2_X_f[0] my_demux.my_demux.demux.vc.ct.in[6] my_demux.in.d.d[6].t my_demux.in.d.d[1].t my_demux.in.d.d[0].t my_demux.my_demux.demux._out2_a_B my_demux.in.d.d[3].f my_demux.out2.a my_demux.in.v my_demux.my_demux.demux.vc.OR2_tf[1]._y my_demux.my_demux.demux.vc.ct.C3Els[0]._y my_demux.my_demux.demux.vc.ct.C2Els[1]._y my_demux.my_demux.demux._en my_demux.in.d.d[3].t my_demux.my_demux.demux.vc.ct.tmp[9] my_demux.my_demux.demux.vc.ct.in[5] my_demux.my_demux.demux.vc.ct.in[4] my_demux.my_demux.demux.vc.ct.in[2] my_demux.out2.v my_demux.my_demux.demux.vc.ct.C3Els[1]._y my_demux.my_demux.demux.vc.ct.C2Els[0]._y my_demux.my_demux.demux.vc.OR2_tf[0]._y my_demux.my_demux.demux.vc.ct.in[3] my_demux.my_demux.demux.c_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[7] my_demux.my_demux.demux.vc.OR2_tf[6]._y my_demux.my_demux.demux.vc.ct.in[0] my_demux.my_demux.demux._in_v my_demux.my_demux.demux.c_buf_t.buf2._y my_demux.out1.v my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.demux.vc.OR2_tf[5]._y my_demux.my_demux.demux.c_el._y my_demux.my_demux.demux.out2_en_buf_t.buf2._y my_demux.my_demux.demux.in_v_buf._y my_demux.my_demux.demux.vc.OR2_tf[4]._y my_demux.my_demux.demux.c_f_c_t_or._y my_demux.my_demux.demux.out1_en_buf_f.buf2._y my_demux.my_demux.demux.out2_en_buf_f.buf2._y my_demux.my_demux.demux.out1_en_buf_t.buf2._y my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.OR2_tf[3]._y
119199 my_demux.in.d.d[0].f : 0
119199 my_demux.in.d.d[0].t : 0
119199 my_demux.in.d.d[1].f : 0
119199 my_demux.in.d.d[3].f : 0
119199 my_demux.in.d.d[7].f : 0
119199 my_demux.in.d.d[6].t : 0
119199 my_demux.out2.v : 0
119199 my_demux.out2.a : 0
119199 my_demux.out1.v : 0
119199 my_demux.in.d.d[2].t : 0
119199 my_demux.in.d.d[6].f : 0
119199 my_demux.out1.a : 0
119199 my_demux.in.d.d[5].t : 0
119199 my_demux.in.d.d[7].t : 0
119199 my_demux.in.d.d[2].f : 0
119199 my_demux.in.d.d[5].f : 0
119199 my_demux.in.d.d[4].t : 0
119199 my_demux.in.d.d[1].t : 0
119199 my_demux.in.d.d[4].f : 0
119199 my_demux.in.d.d[3].t : 0
119200 my_demux.my_demux.demux.c_buf_f.buf2._y : 1 [by my_demux.in.d.d[0].f:=0]
119200 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1 [by my_demux.in.d.d[5].f:=0]
119236 my_demux.my_demux.demux.c_buf_t.buf2._y : 1 [by my_demux.in.d.d[0].t:=0]
119239 my_demux.my_demux.demux.out_or._y : 1 [by my_demux.out1.v:=0]
119286 my_demux.my_demux.demux._out1_a_B : 1 [by my_demux.out1.a:=0]
119308 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
119311 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1 [by my_demux.in.d.d[0].t:=0]
119378 my_demux.my_demux.demux.vc.ct.in[5] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
119403 my_demux.my_demux.demux._out_v : 0 [by my_demux.my_demux.demux.out_or._y:=1]
119456 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1 [by my_demux.in.d.d[6].f:=0]
119493 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1 [by my_demux.in.d.d[2].f:=0]
119536 my_demux.my_demux.demux._en : 1 [by my_demux.my_demux.demux._out_v:=0]
119543 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
119566 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
119757 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
119790 my_demux.my_demux.demux._c_f_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
119848 my_demux.my_demux.demux._en1_X_t[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
119852 my_demux.my_demux.demux.vc.ct.in[2] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
119938 my_demux.my_demux.demux.c_f_c_t_or._y : 1 [by my_demux.in.d.d[0].t:=0]
120039 my_demux.my_demux.demux._c_t_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
120155 my_demux.my_demux.demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
120408 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1 [by my_demux.in.d.d[3].t:=0]
120415 my_demux.my_demux.demux.vc.ct.in[3] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
121005 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1 [by my_demux.in.d.d[1].t:=0]
121111 my_demux.my_demux.demux.vc.ct.in[1] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
121206 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1 [by my_demux.in.d.d[4].f:=0]
121284 my_demux.my_demux.demux.vc.ct.in[4] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
121481 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
121756 my_demux.my_demux.demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
122127 my_demux.my_demux.demux._c_v : 0 [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
123202 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
126256 my_demux.my_demux.demux._en2_X_t[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
133652 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
134107 my_demux.my_demux.demux._en2_X_f[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
135118 my_demux.my_demux.demux.vc.ct.in[6] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
135130 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
135534 my_demux.my_demux.demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
142198 my_demux.my_demux.demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
149439 my_demux.my_demux.demux.vc.ct.in[0] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
149451 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
155367 my_demux.my_demux.demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
159643 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.tmp[7]:=0]
162542 my_demux.my_demux.demux._in_v : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
162544 my_demux.my_demux.demux.c_el._y : 1 [by my_demux.my_demux.demux._in_v:=0]
166711 my_demux.my_demux.demux._out2_a_B : 1 [by my_demux.out2.a:=0]
166837 my_demux.my_demux.demux.in_v_buf._y : 1 [by my_demux.my_demux.demux._in_v:=0]
167003 my_demux.in.v : 0 [by my_demux.my_demux.demux.in_v_buf._y:=1]
167079 my_demux.my_demux.demux._in_c_v_ : 0 [by my_demux.my_demux.demux.c_el._y:=1]
167960 my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._out2_a_B:=1]
168035 my_demux.my_demux.demux._out2_a_BX_f[0] : 1 [by my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y:=0]
170210 my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._out2_a_B:=1]
170555 my_demux.my_demux.demux._out2_a_BX_t[0] : 1 [by my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y:=0]
177027 my_demux.my_demux.demux._en1_X_f[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
System initialized
177027 Reset : 0
177165 my_demux._reset_B : 1 [by Reset:=0]
182428 my_demux.my_demux.demux.reset_buf._y : 0 [by my_demux._reset_B:=1]
182430 my_demux.my_demux.demux._reset_BX : 1 [by my_demux.my_demux.demux.reset_buf._y:=0]
226347 my_demux.my_demux.demux.reset_bufarray.buf4._y : 0 [by my_demux.my_demux.demux._reset_BX:=1]
226348 my_demux.my_demux.demux._reset_BXX[0] : 1 [by my_demux.my_demux.demux.reset_bufarray.buf4._y:=0]
System reset completed
Output neutral checked
226348 my_demux.in.d.d[0].t : 1
226348 my_demux.in.d.d[7].t : 1
226348 my_demux.in.d.d[2].t : 1
226348 my_demux.in.d.d[6].t : 1
226348 my_demux.in.d.d[5].t : 1
226348 my_demux.in.d.d[1].t : 1
226348 my_demux.in.d.d[4].t : 1
226348 my_demux.in.d.d[3].t : 1
226359 my_demux.my_demux.demux.c_f_c_t_or._y : 0 [by my_demux.in.d.d[0].t:=1]
226364 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0 [by my_demux.in.d.d[5].t:=1]
226415 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0 [by my_demux.in.d.d[2].t:=1]
226718 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0 [by my_demux.in.d.d[0].t:=1]
226720 my_demux.my_demux.demux.vc.ct.in[0] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
226876 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0 [by my_demux.in.d.d[4].t:=1]
226896 my_demux.my_demux.demux.c_buf_t.buf2._y : 0 [by my_demux.in.d.d[0].t:=1]
226899 my_demux.my_demux.demux._c_t_buf[0] : 1 [by my_demux.my_demux.demux.c_buf_t.buf2._y:=0]
226928 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
226929 my_demux.out1.d.d[0].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=0]
226943 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
227052 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
227074 my_demux.out1.d.d[3].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=0]
227160 my_demux.out1.d.d[4].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=0]
227216 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
227217 my_demux.out1.d.d[1].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=0]
228500 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
228783 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0 [by my_demux.in.d.d[3].t:=1]
228989 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0 [by my_demux.in.d.d[6].t:=1]
229148 my_demux.my_demux.demux.vc.ct.in[6] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
229660 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
230081 my_demux.out1.d.d[2].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=0]
230910 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0 [by my_demux.in.d.d[1].t:=1]
232197 my_demux.my_demux.demux.vc.ct.in[1] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
234429 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
234574 my_demux.my_demux.demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
238128 my_demux.my_demux.demux.vc.ct.in[3] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
239456 my_demux.my_demux.demux.vc.ct.in[2] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
240582 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
242288 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
242289 my_demux.my_demux.demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
246936 my_demux.out1.d.d[6].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=0]
249336 my_demux.out1.d.d[5].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=0]
250289 my_demux.my_demux.demux.vc.ct.in[5] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
253239 my_demux.my_demux.demux._c_v : 1 [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
287834 my_demux.my_demux.demux.vc.ct.in[4] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
327118 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[4]:=1]
327280 my_demux.my_demux.demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
334649 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
334663 my_demux.my_demux.demux._in_v : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
334670 my_demux.my_demux.demux.in_v_buf._y : 0 [by my_demux.my_demux.demux._in_v:=1]
334823 my_demux.my_demux.demux.c_el._y : 0 [by my_demux.my_demux.demux._in_v:=1]
334824 my_demux.my_demux.demux._in_c_v_ : 1 [by my_demux.my_demux.demux.c_el._y:=0]
356227 my_demux.in.v : 1 [by my_demux.my_demux.demux.in_v_buf._y:=0]
356227 my_demux.out1.v : 1
356228 my_demux.my_demux.demux.out_or._y : 0 [by my_demux.out1.v:=1]
356229 my_demux.my_demux.demux._out_v : 1 [by my_demux.my_demux.demux.out_or._y:=0]
358472 my_demux.my_demux.demux.inack_ctl._y : 0 [by my_demux.my_demux.demux._out_v:=1]
358659 my_demux.in.a : 1 [by my_demux.my_demux.demux.inack_ctl._y:=0]
358660 my_demux.my_demux.demux._en : 0 [by my_demux.in.a:=1]
358661 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
358666 my_demux.my_demux.demux._en2_X_t[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
359513 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
360404 my_demux.my_demux.demux._en1_X_f[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
362842 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
362843 my_demux.my_demux.demux._en2_X_f[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
393442 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
393459 my_demux.my_demux.demux._en1_X_t[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
393459 my_demux.in.d.d[0].t : 0
393459 my_demux.in.d.d[7].t : 0
393459 my_demux.in.d.d[2].t : 0
393459 my_demux.in.d.d[6].t : 0
393459 my_demux.in.d.d[5].t : 0
393459 my_demux.in.d.d[1].t : 0
393459 my_demux.in.d.d[4].t : 0
393459 my_demux.in.d.d[3].t : 0
393460 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1 [by my_demux.in.d.d[5].t:=0]
393462 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1 [by my_demux.in.d.d[0].t:=0]
393501 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1 [by my_demux.in.d.d[1].t:=0]
393509 my_demux.my_demux.demux.vc.ct.in[1] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
393555 my_demux.my_demux.demux.vc.ct.in[5] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
393797 my_demux.my_demux.demux.vc.ct.in[0] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
393831 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
394400 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1 [by my_demux.in.d.d[2].t:=0]
395318 my_demux.my_demux.demux.vc.ct.in[2] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
396032 my_demux.my_demux.demux.c_buf_t.buf2._y : 1 [by my_demux.in.d.d[0].t:=0]
396036 my_demux.my_demux.demux._c_t_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
396276 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1 [by my_demux.in.d.d[4].t:=0]
401820 my_demux.my_demux.demux.c_f_c_t_or._y : 1 [by my_demux.in.d.d[0].t:=0]
404218 my_demux.my_demux.demux._c_v : 0 [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
407192 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1 [by my_demux.in.d.d[3].t:=0]
407718 my_demux.my_demux.demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
410407 my_demux.my_demux.demux.vc.ct.in[3] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
442654 my_demux.my_demux.demux.vc.ct.in[4] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
452421 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1 [by my_demux.in.d.d[6].t:=0]
452469 my_demux.my_demux.demux.vc.ct.in[6] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
452472 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
452650 my_demux.my_demux.demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
457526 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
478503 my_demux.my_demux.demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
490402 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.tmp[8]:=0]
496353 my_demux.my_demux.demux._in_v : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
497180 my_demux.my_demux.demux.c_el._y : 1 [by my_demux.my_demux.demux._in_v:=0]
497353 my_demux.my_demux.demux._in_c_v_ : 0 [by my_demux.my_demux.demux.c_el._y:=1]
535838 my_demux.my_demux.demux.in_v_buf._y : 1 [by my_demux.my_demux.demux._in_v:=0]
536022 my_demux.in.v : 0 [by my_demux.my_demux.demux.in_v_buf._y:=1]
First Cond Checked
536022 my_demux.out1.a : 1
536023 my_demux.my_demux.demux._out1_a_B : 0 [by my_demux.out1.a:=1]
536027 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._out1_a_B:=0]
536096 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._out1_a_B:=0]
536192 my_demux.my_demux.demux._out1_a_BX_t[0] : 0 [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=1]
536193 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
536204 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
536205 my_demux.out1.d.d[5].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=1]
536328 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
536384 my_demux.out1.d.d[0].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=1]
536433 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
537222 my_demux.out1.d.d[1].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=1]
540092 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
540093 my_demux.out1.d.d[6].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=1]
540151 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
540188 my_demux.out1.d.d[4].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=1]
555238 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
573315 my_demux.my_demux.demux._out1_a_BX_f[0] : 0 [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=1]
578613 my_demux.out1.d.d[2].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=1]
581439 my_demux.out1.d.d[3].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=1]
System reset completed
Output neutral checked
581439 my_demux.out1.a : 0
581439 my_demux.out1.v : 0
581440 my_demux.my_demux.demux._out1_a_B : 1 [by my_demux.out1.a:=0]
581453 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
583132 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
583489 my_demux.my_demux.demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
585003 my_demux.my_demux.demux.out_or._y : 1 [by my_demux.out1.v:=0]
585028 my_demux.my_demux.demux._out_v : 0 [by my_demux.my_demux.demux.out_or._y:=1]
585049 my_demux.my_demux.demux.inack_ctl._y : 1 [by my_demux.my_demux.demux._out_v:=0]
585050 my_demux.in.a : 0 [by my_demux.my_demux.demux.inack_ctl._y:=1]
594698 my_demux.my_demux.demux._en : 1 [by my_demux.in.a:=0]
594699 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
594699 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
594704 my_demux.my_demux.demux._en2_X_f[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
594859 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
595267 my_demux.my_demux.demux._en2_X_t[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
595280 my_demux.my_demux.demux._en1_X_t[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
595735 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
595746 my_demux.my_demux.demux._en1_X_f[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
598437 my_demux.my_demux.demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
598437 my_demux.in.d.d[0].f : 1
598437 my_demux.in.d.d[7].f : 1
598437 my_demux.in.d.d[2].t : 1
598437 my_demux.in.d.d[6].t : 1
598437 my_demux.in.d.d[5].t : 1
598437 my_demux.in.d.d[1].f : 1
598437 my_demux.in.d.d[4].f : 1
598437 my_demux.in.d.d[3].f : 1
598441 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0 [by my_demux.in.d.d[2].t:=1]
598451 my_demux.my_demux.demux.c_buf_f.buf2._y : 0 [by my_demux.in.d.d[0].f:=1]
598455 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0 [by my_demux.in.d.d[0].f:=1]
598525 my_demux.my_demux.demux.vc.ct.in[0] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
598541 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0 [by my_demux.in.d.d[6].t:=1]
598665 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0 [by my_demux.in.d.d[3].f:=1]
598676 my_demux.my_demux.demux.vc.ct.in[3] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
599284 my_demux.my_demux.demux.vc.ct.in[2] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
599287 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
599341 my_demux.my_demux.demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
599484 my_demux.my_demux.demux.c_f_c_t_or._y : 0 [by my_demux.in.d.d[0].f:=1]
599641 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0 [by my_demux.in.d.d[1].f:=1]
599910 my_demux.my_demux.demux._c_f_buf[0] : 1 [by my_demux.my_demux.demux.c_buf_f.buf2._y:=0]
599991 my_demux.my_demux.demux.out2_t_buf_func[5]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
600002 my_demux.my_demux.demux.out2_f_buf_func[1]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
600604 my_demux.out2.d.d[5].t : 1 [by my_demux.my_demux.demux.out2_t_buf_func[5]._y:=0]
600632 my_demux.my_demux.demux._c_v : 1 [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
600802 my_demux.my_demux.demux.vc.ct.in[1] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
600847 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
601654 my_demux.my_demux.demux.out2_f_buf_func[4]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
601844 my_demux.my_demux.demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
603303 my_demux.out2.d.d[4].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[4]._y:=0]
606892 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0 [by my_demux.in.d.d[4].f:=1]
607417 my_demux.my_demux.demux.vc.ct.in[4] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
608221 my_demux.my_demux.demux.out2_f_buf_func[3]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
608562 my_demux.my_demux.demux.out2_t_buf_func[2]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
608614 my_demux.out2.d.d[2].t : 1 [by my_demux.my_demux.demux.out2_t_buf_func[2]._y:=0]
609121 my_demux.out2.d.d[3].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[3]._y:=0]
610987 my_demux.my_demux.demux.out2_t_buf_func[6]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
610994 my_demux.out2.d.d[6].t : 1 [by my_demux.my_demux.demux.out2_t_buf_func[6]._y:=0]
614024 my_demux.out2.d.d[1].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[1]._y:=0]
617893 my_demux.my_demux.demux.out2_f_buf_func[0]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
629881 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0 [by my_demux.in.d.d[5].t:=1]
633505 my_demux.out2.d.d[0].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[0]._y:=0]
636348 my_demux.my_demux.demux.vc.ct.in[5] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
648963 my_demux.my_demux.demux.vc.ct.in[6] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
648965 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[6]:=1]
649319 my_demux.my_demux.demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
649452 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
649453 my_demux.my_demux.demux._in_v : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
649457 my_demux.my_demux.demux.in_v_buf._y : 0 [by my_demux.my_demux.demux._in_v:=1]
649999 my_demux.my_demux.demux.c_el._y : 0 [by my_demux.my_demux.demux._in_v:=1]
650000 my_demux.my_demux.demux._in_c_v_ : 1 [by my_demux.my_demux.demux.c_el._y:=0]
695020 my_demux.in.v : 1 [by my_demux.my_demux.demux.in_v_buf._y:=0]
695020 my_demux.out2.v : 1
707398 my_demux.my_demux.demux.out_or._y : 0 [by my_demux.out2.v:=1]
707477 my_demux.my_demux.demux._out_v : 1 [by my_demux.my_demux.demux.out_or._y:=0]
709910 my_demux.my_demux.demux.inack_ctl._y : 0 [by my_demux.my_demux.demux._out_v:=1]
709998 my_demux.in.a : 1 [by my_demux.my_demux.demux.inack_ctl._y:=0]
717780 my_demux.my_demux.demux._en : 0 [by my_demux.in.a:=1]
717810 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
717839 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
719247 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
719932 my_demux.my_demux.demux._en1_X_f[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
737223 my_demux.my_demux.demux._en1_X_t[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
746107 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
762822 my_demux.my_demux.demux._en2_X_f[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
777314 my_demux.my_demux.demux._en2_X_t[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
777314 my_demux.in.d.d[0].f : 0
777314 my_demux.in.d.d[6].t : 0
777314 my_demux.in.d.d[2].t : 0
777314 my_demux.in.d.d[5].t : 0
777314 my_demux.in.d.d[1].f : 0
777314 my_demux.in.d.d[4].f : 0
777314 my_demux.in.d.d[3].f : 0
777315 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1 [by my_demux.in.d.d[3].f:=0]
777317 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1 [by my_demux.in.d.d[1].f:=0]
777326 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1 [by my_demux.in.d.d[6].t:=0]
777352 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1 [by my_demux.in.d.d[4].f:=0]
777354 my_demux.my_demux.demux.vc.ct.in[4] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
777357 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1 [by my_demux.in.d.d[0].f:=0]
777358 my_demux.my_demux.demux.vc.ct.in[0] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
777409 my_demux.my_demux.demux.vc.ct.in[1] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
777441 my_demux.my_demux.demux.c_f_c_t_or._y : 1 [by my_demux.in.d.d[0].f:=0]
777443 my_demux.my_demux.demux._c_v : 0 [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
777483 my_demux.my_demux.demux.c_buf_f.buf2._y : 1 [by my_demux.in.d.d[0].f:=0]
777501 my_demux.my_demux.demux._c_f_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
777547 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1 [by my_demux.in.d.d[5].t:=0]
777666 my_demux.my_demux.demux.vc.ct.in[5] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
778593 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1 [by my_demux.in.d.d[2].t:=0]
778910 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[1]:=0]
778918 my_demux.my_demux.demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
780053 my_demux.my_demux.demux.vc.ct.in[6] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
780107 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
784313 my_demux.my_demux.demux.vc.ct.in[2] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
790067 my_demux.my_demux.demux.vc.ct.in[3] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
790072 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
791139 my_demux.my_demux.demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
830645 my_demux.my_demux.demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
830646 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.tmp[9]:=0]
830784 my_demux.my_demux.demux._in_v : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
830785 my_demux.my_demux.demux.in_v_buf._y : 1 [by my_demux.my_demux.demux._in_v:=0]
830848 my_demux.my_demux.demux.c_el._y : 1 [by my_demux.my_demux.demux._in_v:=0]
830850 my_demux.my_demux.demux._in_c_v_ : 0 [by my_demux.my_demux.demux.c_el._y:=1]
830908 my_demux.in.v : 0 [by my_demux.my_demux.demux.in_v_buf._y:=1]
Second Cond Checked
test/unit_tests/demux_bit_7/run/test.prs
-1692
View File
File diff suppressed because it is too large Load Diff
test/unit_tests/demux_bit_7/test.act
-49
View File
@@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc demux_bit_7 (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
demux_bit<7,0> my_demux(.in=in, .out1=out1,.out2 = out2);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
my_demux.supply.vss = GND;
my_demux.supply.vdd = Vdd;
my_demux.reset_B = _reset_B;
}
demux_bit_7 my_demux;
test/unit_tests/demux_bit_7/test.prsim
-77
View File
@@ -1,77 +0,0 @@
watchall
set-qdi-channel-neutral "my_demux.in" 8
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
set my_demux.in.d.d[0].t 0
set my_demux.in.d.d[0].f 0
cycle
system "echo 'System initialized'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 8
cycle
system "echo 'Output neutral checked'"
set-qdi-channel-valid "my_demux.in" 8 255
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out1" 7 127
assert-qdi-channel-neutral "my_demux.out2" 7
set my_demux.out1.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 8
cycle
set my_demux.out1.a 1
system "echo 'First Cond Checked'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 8
cycle
system "echo 'Output neutral checked'"
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
cycle
set-qdi-channel-valid "my_demux.in" 8 100
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out2" 7 100
set my_demux.out2.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 7
cycle
system "echo 'Second Cond Checked'"
test/unit_tests/demux_td_2/run/prsim.out
+26 -26
View File
@@ -1,4 +1,4 @@
my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_en_buf_t.buf1._y my_demux.my_demux.token_a_out my_demux.my_demux._out_v my_demux.my_demux._in_v my_demux.my_demux._c_d_buf[0] my_demux.my_demux._en my_demux.my_demux.cond_inv_f my_demux.my_demux._out1_a_B my_demux.my_demux.invout_f.a my_demux.my_demux._out1_a_BX_t[0] my_demux.in.v my_demux.my_demux._c_v my_demux.my_demux.invout_t.a my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.v my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.cond_inv_t my_demux.out1.a my_demux.my_demux.vc.ct.in[1] my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out_or._y my_demux.my_demux._en1_X_t[0] my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.in_v_buf._y my_demux.token.a my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux._in_c_v_ my_demux.my_demux.c_buf_tk_inv._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_f.buf1._y my_demux.my_demux.vc.ct.C2Els[0]._y my_demux.my_demux.c_buf_d_inv.buf1._y my_demux.my_demux._c_tk_buf my_demux.my_demux.out1_a_B_buf_f.buf1._y my_demux.my_demux.c_el._y my_demux.my_demux.out1_a_B_buf_t.buf1._y
my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_en_buf_t.buf1._y my_demux.my_demux.token_a_out my_demux.my_demux._out_v my_demux.my_demux._in_v my_demux.my_demux._c_d_buf[0] my_demux.my_demux._en my_demux.my_demux.vc.OR2_tf[1].y my_demux.my_demux.cond_inv_f my_demux.my_demux._out1_a_B my_demux.my_demux.invout_f.a my_demux.my_demux._out1_a_BX_t[0] my_demux.in.v my_demux.my_demux._c_v my_demux.my_demux.invout_t.a my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.v my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.cond_inv_t my_demux.out1.a my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out_or._y my_demux.my_demux._en1_X_t[0] my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[0].y my_demux.token.a my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux._in_c_v_ my_demux.my_demux.c_buf_tk_inv._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_f.buf1._y my_demux.my_demux.c_buf_d_inv.buf1._y my_demux.my_demux._c_tk_buf my_demux.my_demux.vc.myctree.C2Els[0]._y my_demux.my_demux.out1_a_B_buf_f.buf1._y my_demux.my_demux.c_el._y my_demux.my_demux.out1_a_B_buf_t.buf1._y
83058 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
83058 my_demux.my_demux.invout_f.a : 0
83058 my_demux.my_demux.invout_t.a : 0
@@ -13,7 +13,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
83113 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
92187 my_demux.my_demux.token_a_out : 1 [by my_demux.token.a:=0]
96782 my_demux.my_demux.cond_inv_t : 1 [by my_demux.my_demux.invout_t.a:=0]
96962 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
96962 my_demux.my_demux.vc.OR2_tf[1].y : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
112853 my_demux.my_demux._out_v : 0 [by my_demux.my_demux.out_or._y:=1]
119989 my_demux.my_demux._out1_a_B : 1 [by my_demux.out1.a:=0]
120411 my_demux.my_demux.out1_a_B_buf_f.buf1._y : 0 [by my_demux.my_demux._out1_a_B:=1]
@@ -29,9 +29,9 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
127989 my_demux.my_demux._c_d_buf[0] : 1 [by my_demux.my_demux.c_buf_d_inv.buf1._y:=0]
129035 my_demux.my_demux._en1_X_t[0] : 1 [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
134715 my_demux.my_demux._c_v : 0 [by my_demux.my_demux.c_f_c_t_or._y:=1]
146511 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
147465 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[0]:=0]
148546 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
146511 my_demux.my_demux.vc.OR2_tf[0].y : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
147465 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1 [by my_demux.my_demux.vc.OR2_tf[0].y:=0]
148546 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
149528 my_demux.my_demux.c_el._y : 1 [by my_demux.my_demux._in_v:=0]
149546 my_demux.my_demux._in_c_v_ : 0 [by my_demux.my_demux.c_el._y:=1]
149640 my_demux.my_demux._en1_X_f[0] : 1 [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
@@ -39,7 +39,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
172716 my_demux.my_demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=0]
203016 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
207019 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
[]System initialized
System initialized
207019 Reset : 0
251920 my_demux._reset_B : 1 [by Reset:=0]
273504 my_demux.my_demux.reset_buf._y : 0 [by my_demux._reset_B:=1]
@@ -48,25 +48,25 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
278766 my_demux.my_demux.reset_bufarray.buf1._y : 0 [by my_demux.my_demux._reset_BX:=1]
278905 my_demux.my_demux._reset_BXX[0] : 1 [by my_demux.my_demux.reset_bufarray.buf1._y:=0]
280321 my_demux.my_demux._reset_BXt : 1 [by my_demux.my_demux.reset_buf_token._y:=0]
[]System reset completed
System reset completed
[]Output neutral checked
Output neutral checked
280321 my_demux.my_demux.invout_t.a : 1
280321 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
280321 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
280332 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
280333 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
280333 my_demux.my_demux.vc.OR2_tf[1].y : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
280336 my_demux.my_demux.out1_t_buf_func[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
280373 my_demux.my_demux.out1_t_buf_func[0].y : 1 [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
280390 my_demux.my_demux.c_f_c_t_or._y : 0 [by my_demux.my_demux.invout_t.a:=1]
280525 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
280637 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
280637 my_demux.my_demux.vc.OR2_tf[0].y : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
281129 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
316667 my_demux.my_demux.cond_inv_t : 0 [by my_demux.my_demux.invout_t.a:=1]
316707 my_demux.my_demux.c_buf_tk_inv._y : 1 [by my_demux.my_demux.cond_inv_t:=0]
316964 my_demux.my_demux._c_tk_buf : 0 [by my_demux.my_demux.c_buf_tk_inv._y:=1]
328149 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[0]:=1]
328236 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
328149 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0 [by my_demux.my_demux.vc.OR2_tf[0].y:=1]
328236 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
328237 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
328530 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
330043 my_demux.my_demux._in_c_v_ : 1 [by my_demux.my_demux.c_el._y:=0]
@@ -86,11 +86,11 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
367396 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
367396 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
367755 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
381871 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
381871 my_demux.my_demux.vc.OR2_tf[1].y : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
383058 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
383279 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
383286 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[0]:=0]
383316 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
383279 my_demux.my_demux.vc.OR2_tf[0].y : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
383286 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1 [by my_demux.my_demux.vc.OR2_tf[0].y:=0]
383316 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
390029 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
447490 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
447490 my_demux.out1.a : 1
@@ -103,7 +103,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
450375 my_demux.my_demux._out1_a_BX_f[0] : 0 [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=1]
450606 my_demux.my_demux.out1_t_buf_func[1].y : 0 [by my_demux.my_demux.out1_t_buf_func[1]._y:=1]
468950 my_demux.my_demux.out1_t_buf_func[0].y : 0 [by my_demux.my_demux.out1_t_buf_func[0]._y:=1]
[]First Cond Checked
First Cond Checked
468950 my_demux.my_demux.invout_t.a : 0
468950 my_demux.out1.v : 0
468950 my_demux.out1.a : 0
@@ -128,7 +128,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
484418 my_demux.my_demux._en1_X_f[0] : 1 [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
527786 my_demux.my_demux.out1_en_buf_t.buf1._y : 0 [by my_demux.my_demux._en:=1]
527797 my_demux.my_demux._en1_X_t[0] : 1 [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
[]System initialized
System initialized
527797 my_demux.my_demux.invout_f.a : 1
527797 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
527797 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
@@ -138,15 +138,15 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
528325 my_demux.my_demux.out1_t_buf_func[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
530248 my_demux.my_demux.out1_t_buf_func[1].y : 1 [by my_demux.my_demux.out1_t_buf_func[1]._y:=0]
530438 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
530440 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
530440 my_demux.my_demux.vc.OR2_tf[1].y : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
532359 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
541366 my_demux.my_demux.out1_t_buf_func[0].y : 1 [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
552092 my_demux.my_demux.c_buf_d_inv.buf1._y : 1 [by my_demux.my_demux.cond_inv_f:=0]
552095 my_demux.my_demux._c_d_buf[0] : 0 [by my_demux.my_demux.c_buf_d_inv.buf1._y:=1]
554744 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
593317 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
593346 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[0]:=1]
593663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
593317 my_demux.my_demux.vc.OR2_tf[0].y : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
593346 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0 [by my_demux.my_demux.vc.OR2_tf[0].y:=1]
593663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
593707 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
593816 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
595264 my_demux.my_demux.token_buf._y : 0 [by my_demux.my_demux._in_v:=1]
@@ -172,12 +172,12 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
677919 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
677919 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
677933 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
677940 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
677940 my_demux.my_demux.vc.OR2_tf[0].y : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
678081 my_demux.my_demux.token_a_out : 1 [by my_demux.token.a:=0]
685288 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
685448 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
707005 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[1]:=0]
707006 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
685448 my_demux.my_demux.vc.OR2_tf[1].y : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
707005 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1 [by my_demux.my_demux.vc.OR2_tf[1].y:=0]
707006 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
707007 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
707008 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
707008 my_demux.my_demux.invout_f.a : 0
test/unit_tests/demux_td_2/run/prsim.pdf
BIN
View File
Binary file not shown.
test/unit_tests/demux_td_2/run/test.prs
+17 -31
View File
@@ -239,30 +239,19 @@
= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token_buf.y"
= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.out_or.b"
= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token.r"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_d_inv.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_d_inv.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_bufarray.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_bufarray.supply.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.token_buf.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.outt_a_inv.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[1].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[1].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[0].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[0].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_inv.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.in_v_buf.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_el.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_tk_inv.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_f.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_t.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_f_c_t_or.vdd"
@@ -272,15 +261,12 @@
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.inack_ctl.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out_or.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.token_buf.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.outt_a_inv.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[1].vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[1].vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[0].vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[0].vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_inv.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.in_v_buf.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_el.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_tk_inv.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_f.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_t.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_f_c_t_or.vss"
@@ -291,20 +277,18 @@
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
"my_demux.my_demux.invout_f.a"->"my_demux.my_demux.invout_f.y"-
~("my_demux.my_demux.invout_f.a")->"my_demux.my_demux.invout_f.y"+
~"my_demux.my_demux.vc.ct.C2Els[0].c1"&~"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"+
"my_demux.my_demux.vc.ct.C2Els[0].c1"&"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"-
"my_demux.my_demux.vc.ct.C2Els[0]._y"->"my_demux.my_demux.vc.ct.C2Els[0].y"-
~("my_demux.my_demux.vc.ct.C2Els[0]._y")->"my_demux.my_demux.vc.ct.C2Els[0].y"+
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[0].vdd"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[0].vss"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.C2Els[0].c1"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.tmp[0]"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.C2Els[0].c2"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.tmp[1]"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.C2Els[0].y"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.tmp[2]"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
~"my_demux.my_demux.vc.myctree.C2Els[0].c1"&~"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"+
"my_demux.my_demux.vc.myctree.C2Els[0].c1"&"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"-
"my_demux.my_demux.vc.myctree.C2Els[0]._y"->"my_demux.my_demux.vc.myctree.C2Els[0].y"-
~("my_demux.my_demux.vc.myctree.C2Els[0]._y")->"my_demux.my_demux.vc.myctree.C2Els[0].y"+
= "my_demux.my_demux.vc.myctree.supply.vdd" "my_demux.my_demux.vc.myctree.C2Els[0].vdd"
= "my_demux.my_demux.vc.myctree.supply.vss" "my_demux.my_demux.vc.myctree.C2Els[0].vss"
= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.C2Els[0].c1"
= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.tmp[0]"
= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.C2Els[0].c2"
= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.tmp[1]"
= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.C2Els[0].y"
= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.tmp[2]"
"my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
"my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
@@ -313,13 +297,15 @@
~("my_demux.my_demux.vc.OR2_tf[1].a"|"my_demux.my_demux.vc.OR2_tf[1].b")->"my_demux.my_demux.vc.OR2_tf[1]._y"+
"my_demux.my_demux.vc.OR2_tf[1]._y"->"my_demux.my_demux.vc.OR2_tf[1].y"-
~("my_demux.my_demux.vc.OR2_tf[1]._y")->"my_demux.my_demux.vc.OR2_tf[1].y"+
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.ct.supply.vss"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.ct.supply.vdd"
= "my_demux.my_demux.vc.OR2_tf[1].y" "my_demux.my_demux.vc.myctree.in[1]"
= "my_demux.my_demux.vc.OR2_tf[0].y" "my_demux.my_demux.vc.myctree.in[0]"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.myctree.supply.vss"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.myctree.supply.vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.ct.out"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.myctree.out"
= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
test/unit_tests/demux_td_2/test.prsim
+5 -5
View File
@@ -7,11 +7,11 @@ set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo '[]System initialized'"
system "echo 'System initialized'"
set Reset 0
cycle
system "echo '[]System reset completed'"
system "echo 'System reset completed'"
status X
mode run
@@ -19,7 +19,7 @@ assert-qdi-channel-neutral "my_demux.out1" 2
assert-qdi-channel-neutral "my_demux.in" 2
cycle
system "echo '[]Output neutral checked'"
system "echo 'Output neutral checked'"
set my_demux.cond.d.d[0].t 1
set my_demux.cond.d.d[0].f 0
@@ -46,7 +46,7 @@ assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
system "echo '[]First Cond Checked'"
system "echo 'First Cond Checked'"
set my_demux.out1.a 0
set my_demux.out1.v 0
@@ -56,7 +56,7 @@ set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo '[]System initialized'"
system "echo 'System initialized'"
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 1
test/unit_tests/dropper_static/run/prsim.out
-383
View File
@@ -1,383 +0,0 @@
b.b.and_f[0].b b.b.vt.ct.C2Els[0]._y b.b.and_f[3].a b.b.and_f[5].y b.b.and_t[1].a b.b.vt.OR2_tf[6]._y b.b.and_t[6].a b.b.and_f[2].y b.b.and_t[0].y b.b.vt.OR2_tf[4]._y b.b.and_f[2].a b.b.and_t[5].a b.b.and_f[5].a b.b.and_t[1].y b.drop b.b.and_t[4].y b.b.vt.ct.tmp[9] b.b.and_t[4].a b.b.and_f[6].a b.b.and_f[4].y b.b.vt.ct.tmp[7] b.b.vt.ct.in[2] b.b.and_t[0]._y b.b.vt.ct.in[5] b.b.vt.ct.C2Els[1]._y b.out.a b.b.and_t[3].a b.b.and_f[6].y b.in.v b.b.and_f[1].a b.b.and_f[0].c b.b.and_t[2].a b.b.and_t[6].y b.b.and_t[0].a b.b.and_f[1]._y b.b.sb_dropB.buf4._y b.b.and_t[3]._y b.b.or2.b b.b.vt.out b.b.and_f[4].a b.b.vt.OR2_tf[2]._y b.b.and_t[3].y b.b.and_f[1].y b.b._dropB b.b.vt.ct.in[0] b.b.and_t[6]._y b.b.vt.ct.tmp[8] b.b.and_t[2].y b.in.a b.b.and_f[0].a b.b.and_f[3].y b.b.or2.y b.b.vt.ct.in[1] b.b.and_t[5]._y b.b.and_f[0].y b.b.vt.ct.in[6] b.b.and_f[5]._y b.b.and_f[4]._y b.b.and2._y b.b.vt.ct.in[4] b.b.and_f[3]._y b.b.and_t[5].y b.b.vt.ct.in[3] b.b.ack_Cel._y b.b.vt.OR2_tf[3]._y b.b.vt.OR2_tf[5]._y b.b.and_t[4]._y b.b.and_t[2]._y b.b.vt.OR2_tf[1]._y b.b.and_f[0]._y b.b.and_t[1]._y b.b.and_f[2]._y b.b.vt.ct.C3Els[0]._y b.b.vt.ct.C3Els[1]._y b.b.in_v_buf._y b.b.or2._y b.b.vt.OR2_tf[0]._y b.b.and_f[6]._y b.b.sb_in_v.buf4._y
1 b.b.and_f[0].a : 0
1 b.drop : 0
1 b.b.and_f[1].a : 0
1 b.b.and_f[3].a : 0
1 b.out.a : 0
1 b.b.and_t[6].a : 0
1 b.b.and_t[2].a : 0
1 b.b.and_f[6].a : 0
1 b.b.and_t[5].a : 0
1 b.b.and_t[0].a : 0
1 b.b.and_f[2].a : 0
1 b.b.and_f[5].a : 0
1 b.b.and_t[4].a : 0
1 b.b.and_t[1].a : 0
1 b.b.and_f[4].a : 0
1 b.b.and_t[3].a : 0
1 b.out.v : 0
3 b.b._dropB : 1 [by b.drop:=0]
5 b.b.vt.OR2_tf[4]._y : 1 [by b.b.and_f[4].a:=0]
14 b.b.vt.OR2_tf[0]._y : 1 [by b.b.and_t[0].a:=0]
16 b.b.vt.OR2_tf[3]._y : 1 [by b.b.and_t[3].a:=0]
16 b.b.and_t[5]._y : 1 [by b.b.and_t[5].a:=0]
17 b.b.and_t[1]._y : 1 [by b.b.and_t[1].a:=0]
21 b.b.and_f[5]._y : 1 [by b.b.and_f[5].a:=0]
40 b.b.vt.OR2_tf[6]._y : 1 [by b.b.and_f[6].a:=0]
41 b.b.and_f[2]._y : 1 [by b.b.and_f[2].a:=0]
48 b.b.and_t[4]._y : 1 [by b.b.and_t[4].a:=0]
69 b.b.vt.ct.in[0] : 0 [by b.b.vt.OR2_tf[0]._y:=1]
115 b.b.and_t[6]._y : 1 [by b.b.and_t[6].a:=0]
116 b.b.and_t[6].y : 0 [by b.b.and_t[6]._y:=1]
416 b.b.vt.OR2_tf[2]._y : 1 [by b.b.and_f[2].a:=0]
417 b.b.vt.ct.in[2] : 0 [by b.b.vt.OR2_tf[2]._y:=1]
463 b.b.and_f[2].y : 0 [by b.b.and_f[2]._y:=1]
492 b.b.and_t[0]._y : 1 [by b.b.and_t[0].a:=0]
1138 b.b.and_f[3]._y : 1 [by b.b.and_f[3].a:=0]
1420 b.b.and_f[3].y : 0 [by b.b.and_f[3]._y:=1]
1727 b.b.and_f[6]._y : 1 [by b.b.and_f[6].a:=0]
2495 b.b.and_f[6].y : 0 [by b.b.and_f[6]._y:=1]
4754 b.b.and_f[1]._y : 1 [by b.b.and_f[1].a:=0]
4757 b.b.and_f[1].y : 0 [by b.b.and_f[1]._y:=1]
6062 b.b.vt.OR2_tf[5]._y : 1 [by b.b.and_f[5].a:=0]
7093 b.b.and_f[0]._y : 1 [by b.b.and_f[0].a:=0]
7644 b.b.and_f[0].y : 0 [by b.b.and_f[0]._y:=1]
9130 b.b.and_t[3]._y : 1 [by b.b.and_t[3].a:=0]
10201 b.b.and_t[3].y : 0 [by b.b.and_t[3]._y:=1]
10468 b.b.and2._y : 1 [by b.drop:=0]
11422 b.b.or2.b : 0 [by b.b.and2._y:=1]
12503 b.b.or2._y : 1 [by b.b.or2.b:=0]
13725 b.b.and_f[4]._y : 1 [by b.b.and_f[4].a:=0]
13866 b.b.and_t[1].y : 0 [by b.b.and_t[1]._y:=1]
14383 b.b.vt.ct.in[6] : 0 [by b.b.vt.OR2_tf[6]._y:=1]
14707 b.b.and_f[4].y : 0 [by b.b.and_f[4]._y:=1]
20697 b.b.and_t[0].y : 0 [by b.b.and_t[0]._y:=1]
24833 b.b.and_f[5].y : 0 [by b.b.and_f[5]._y:=1]
28503 b.b.vt.ct.in[5] : 0 [by b.b.vt.OR2_tf[5]._y:=1]
29796 b.b.and_t[5].y : 0 [by b.b.and_t[5]._y:=1]
36936 b.b.vt.ct.in[4] : 0 [by b.b.vt.OR2_tf[4]._y:=1]
36954 b.b.vt.ct.C3Els[0]._y : 1 [by b.b.vt.ct.in[4]:=0]
40967 b.b.vt.ct.tmp[9] : 0 [by b.b.vt.ct.C3Els[0]._y:=1]
43251 b.b.sb_dropB.buf4._y : 0 [by b.b._dropB:=1]
44099 b.b.vt.OR2_tf[1]._y : 1 [by b.b.and_t[1].a:=0]
47254 b.b.and_f[0].b : 1 [by b.b.sb_dropB.buf4._y:=0]
48762 b.b.and_t[4].y : 0 [by b.b.and_t[4]._y:=1]
51669 b.b.vt.ct.in[3] : 0 [by b.b.vt.OR2_tf[3]._y:=1]
65367 b.b.and_t[2]._y : 1 [by b.b.and_t[2].a:=0]
66973 b.b.or2.y : 0 [by b.b.or2._y:=1]
70127 b.b.and_t[2].y : 0 [by b.b.and_t[2]._y:=1]
73253 b.b.vt.ct.C2Els[1]._y : 1 [by b.b.vt.ct.in[3]:=0]
73755 b.b.vt.ct.tmp[8] : 0 [by b.b.vt.ct.C2Els[1]._y:=1]
89000 b.b.vt.ct.in[1] : 0 [by b.b.vt.OR2_tf[1]._y:=1]
89203 b.b.vt.ct.C2Els[0]._y : 1 [by b.b.vt.ct.in[1]:=0]
91057 b.b.vt.ct.tmp[7] : 0 [by b.b.vt.ct.C2Els[0]._y:=1]
91196 b.b.vt.ct.C3Els[1]._y : 1 [by b.b.vt.ct.tmp[7]:=0]
127542 b.b.vt.out : 0 [by b.b.vt.ct.C3Els[1]._y:=1]
127611 b.b.in_v_buf._y : 1 [by b.b.vt.out:=0]
127622 b.in.v : 0 [by b.b.in_v_buf._y:=1]
127826 b.b.ack_Cel._y : 1 [by b.in.v:=0]
127841 b.in.a : 0 [by b.b.ack_Cel._y:=1]
179408 b.b.sb_in_v.buf4._y : 1 [by b.in.v:=0]
179409 b.b.and_f[0].c : 0 [by b.b.sb_in_v.buf4._y:=1]
[] Set reset 0
179409 Reset : 0
179446 b._reset_B : 1 [by Reset:=0]
[] Sending in valid data
179446 b.b.and_t[0].a : 1
179446 b.b.and_f[6].a : 1
179446 b.b.and_t[2].a : 1
179446 b.b.and_t[5].a : 1
179446 b.b.and_f[1].a : 1
179446 b.b.and_f[4].a : 1
179446 b.b.and_t[3].a : 1
179486 b.b.vt.OR2_tf[5]._y : 0 [by b.b.and_t[5].a:=1]
179487 b.b.vt.ct.in[5] : 1 [by b.b.vt.OR2_tf[5]._y:=0]
179533 b.b.vt.OR2_tf[4]._y : 0 [by b.b.and_f[4].a:=1]
179558 b.b.vt.OR2_tf[6]._y : 0 [by b.b.and_f[6].a:=1]
179703 b.b.vt.OR2_tf[1]._y : 0 [by b.b.and_f[1].a:=1]
179740 b.b.vt.OR2_tf[3]._y : 0 [by b.b.and_t[3].a:=1]
180185 b.b.vt.OR2_tf[0]._y : 0 [by b.b.and_t[0].a:=1]
180330 b.b.vt.ct.in[3] : 1 [by b.b.vt.OR2_tf[3]._y:=0]
180363 b.b.vt.ct.in[0] : 1 [by b.b.vt.OR2_tf[0]._y:=0]
180912 b.b.vt.ct.in[1] : 1 [by b.b.vt.OR2_tf[1]._y:=0]
181339 b.b.vt.ct.in[4] : 1 [by b.b.vt.OR2_tf[4]._y:=0]
181565 b.b.vt.ct.in[6] : 1 [by b.b.vt.OR2_tf[6]._y:=0]
181715 b.b.vt.ct.C2Els[0]._y : 0 [by b.b.vt.ct.in[1]:=1]
181729 b.b.vt.ct.C3Els[0]._y : 0 [by b.b.vt.ct.in[6]:=1]
181751 b.b.vt.ct.tmp[9] : 1 [by b.b.vt.ct.C3Els[0]._y:=0]
183910 b.b.vt.ct.tmp[7] : 1 [by b.b.vt.ct.C2Els[0]._y:=0]
226958 b.b.vt.OR2_tf[2]._y : 0 [by b.b.and_t[2].a:=1]
227805 b.b.vt.ct.in[2] : 1 [by b.b.vt.OR2_tf[2]._y:=0]
257933 b.b.vt.ct.C2Els[1]._y : 0 [by b.b.vt.ct.in[2]:=1]
258066 b.b.vt.ct.tmp[8] : 1 [by b.b.vt.ct.C2Els[1]._y:=0]
273728 b.b.vt.ct.C3Els[1]._y : 0 [by b.b.vt.ct.tmp[8]:=1]
274087 b.b.vt.out : 1 [by b.b.vt.ct.C3Els[1]._y:=0]
288203 b.b.in_v_buf._y : 0 [by b.b.vt.out:=1]
288424 b.in.v : 1 [by b.b.in_v_buf._y:=0]
288431 b.b.sb_in_v.buf4._y : 0 [by b.in.v:=1]
288461 b.b.and_f[0].c : 1 [by b.b.sb_in_v.buf4._y:=0]
288468 b.b.and_t[2]._y : 0 [by b.b.and_f[0].c:=1]
288546 b.b.and_t[2].y : 1 [by b.b.and_t[2]._y:=0]
288552 b.b.and_f[4]._y : 0 [by b.b.and_f[0].c:=1]
288567 b.b.and_t[5]._y : 0 [by b.b.and_f[0].c:=1]
288827 b.b.and_f[4].y : 1 [by b.b.and_f[4]._y:=0]
290650 b.b.and_t[0]._y : 0 [by b.b.and_f[0].c:=1]
291105 b.b.and_t[0].y : 1 [by b.b.and_t[0]._y:=0]
291248 b.b.and_t[3]._y : 0 [by b.b.and_f[0].c:=1]
291260 b.b.and_t[3].y : 1 [by b.b.and_t[3]._y:=0]
295174 b.b.and_f[6]._y : 0 [by b.b.and_f[0].c:=1]
295578 b.b.and_f[6].y : 1 [by b.b.and_f[6]._y:=0]
307563 b.b.and_t[5].y : 1 [by b.b.and_t[5]._y:=0]
345922 b.b.and_f[1]._y : 0 [by b.b.and_f[0].c:=1]
345934 b.b.and_f[1].y : 1 [by b.b.and_f[1]._y:=0]
345934 b.out.a : 1
351850 b.b.or2._y : 0 [by b.out.a:=1]
356126 b.b.or2.y : 1 [by b.b.or2._y:=0]
359025 b.b.ack_Cel._y : 0 [by b.b.or2.y:=1]
363320 b.in.a : 1 [by b.b.ack_Cel._y:=0]
[] Removing data
363320 b.b.and_t[0].a : 0
363320 b.b.and_f[6].a : 0
363320 b.b.and_t[2].a : 0
363320 b.b.and_t[5].a : 0
363320 b.b.and_f[1].a : 0
363320 b.b.and_f[4].a : 0
363320 b.b.and_t[3].a : 0
363321 b.b.vt.OR2_tf[4]._y : 1 [by b.b.and_f[4].a:=0]
363322 b.b.vt.OR2_tf[1]._y : 1 [by b.b.and_f[1].a:=0]
363322 b.b.and_t[0]._y : 1 [by b.b.and_t[0].a:=0]
363331 b.b.vt.OR2_tf[3]._y : 1 [by b.b.and_t[3].a:=0]
363347 b.b.vt.ct.in[3] : 0 [by b.b.vt.OR2_tf[3]._y:=1]
363389 b.b.vt.ct.in[1] : 0 [by b.b.vt.OR2_tf[1]._y:=1]
363395 b.b.vt.OR2_tf[2]._y : 1 [by b.b.and_t[2].a:=0]
363458 b.b.vt.OR2_tf[5]._y : 1 [by b.b.and_t[5].a:=0]
363486 b.b.and_t[2]._y : 1 [by b.b.and_t[2].a:=0]
363665 b.b.and_t[5]._y : 1 [by b.b.and_t[5].a:=0]
363691 b.b.vt.ct.in[4] : 0 [by b.b.vt.OR2_tf[4]._y:=1]
363868 b.b.and_t[3]._y : 1 [by b.b.and_t[3].a:=0]
363986 b.b.vt.ct.in[5] : 0 [by b.b.vt.OR2_tf[5]._y:=1]
364569 b.b.and_f[6]._y : 1 [by b.b.and_f[6].a:=0]
365921 b.b.and_t[2].y : 0 [by b.b.and_t[2]._y:=1]
365963 b.b.and_t[0].y : 0 [by b.b.and_t[0]._y:=1]
366819 b.b.vt.OR2_tf[6]._y : 1 [by b.b.and_f[6].a:=0]
366821 b.b.vt.ct.in[6] : 0 [by b.b.vt.OR2_tf[6]._y:=1]
367855 b.b.vt.OR2_tf[0]._y : 1 [by b.b.and_t[0].a:=0]
367858 b.b.vt.ct.in[0] : 0 [by b.b.vt.OR2_tf[0]._y:=1]
367887 b.b.vt.ct.C2Els[0]._y : 1 [by b.b.vt.ct.in[0]:=0]
367957 b.b.vt.ct.in[2] : 0 [by b.b.vt.OR2_tf[2]._y:=1]
368204 b.b.vt.ct.tmp[7] : 0 [by b.b.vt.ct.C2Els[0]._y:=1]
368583 b.b.and_f[1]._y : 1 [by b.b.and_f[1].a:=0]
368736 b.b.and_f[1].y : 0 [by b.b.and_f[1]._y:=1]
369558 b.b.vt.ct.C2Els[1]._y : 1 [by b.b.vt.ct.in[2]:=0]
369602 b.b.vt.ct.tmp[8] : 0 [by b.b.vt.ct.C2Els[1]._y:=1]
377610 b.b.and_f[6].y : 0 [by b.b.and_f[6]._y:=1]
387793 b.b.and_t[3].y : 0 [by b.b.and_t[3]._y:=1]
390545 b.b.and_t[5].y : 0 [by b.b.and_t[5]._y:=1]
407237 b.b.and_f[4]._y : 1 [by b.b.and_f[4].a:=0]
409998 b.b.and_f[4].y : 0 [by b.b.and_f[4]._y:=1]
427779 b.b.vt.ct.C3Els[0]._y : 1 [by b.b.vt.ct.in[6]:=0]
441462 b.b.vt.ct.tmp[9] : 0 [by b.b.vt.ct.C3Els[0]._y:=1]
441463 b.b.vt.ct.C3Els[1]._y : 1 [by b.b.vt.ct.tmp[9]:=0]
441680 b.b.vt.out : 0 [by b.b.vt.ct.C3Els[1]._y:=1]
441702 b.b.in_v_buf._y : 1 [by b.b.vt.out:=0]
441703 b.in.v : 0 [by b.b.in_v_buf._y:=1]
443284 b.b.sb_in_v.buf4._y : 1 [by b.in.v:=0]
452629 b.b.and_f[0].c : 0 [by b.b.sb_in_v.buf4._y:=1]
452629 b.out.a : 0
452788 b.b.or2._y : 1 [by b.out.a:=0]
472464 b.b.or2.y : 0 [by b.b.or2._y:=1]
473751 b.b.ack_Cel._y : 1 [by b.b.or2.y:=0]
475983 b.in.a : 0 [by b.b.ack_Cel._y:=1]
[] Sending in valid data
475983 b.b.and_t[0].a : 1
475983 b.b.and_f[6].a : 1
475983 b.b.and_t[2].a : 1
475983 b.b.and_t[5].a : 1
475983 b.b.and_f[1].a : 1
475983 b.b.and_f[4].a : 1
475983 b.b.and_f[3].a : 1
475984 b.b.vt.OR2_tf[5]._y : 0 [by b.b.and_t[5].a:=1]
475998 b.b.vt.ct.in[5] : 1 [by b.b.vt.OR2_tf[5]._y:=0]
476128 b.b.vt.OR2_tf[0]._y : 0 [by b.b.and_t[0].a:=1]
476135 b.b.vt.ct.in[0] : 1 [by b.b.vt.OR2_tf[0]._y:=0]
476145 b.b.vt.OR2_tf[4]._y : 0 [by b.b.and_f[4].a:=1]
476305 b.b.vt.ct.in[4] : 1 [by b.b.vt.OR2_tf[4]._y:=0]
478815 b.b.vt.OR2_tf[6]._y : 0 [by b.b.and_f[6].a:=1]
482337 b.b.vt.OR2_tf[2]._y : 0 [by b.b.and_t[2].a:=1]
482338 b.b.vt.ct.in[2] : 1 [by b.b.vt.OR2_tf[2]._y:=0]
483352 b.b.vt.OR2_tf[3]._y : 0 [by b.b.and_f[3].a:=1]
483353 b.b.vt.ct.in[3] : 1 [by b.b.vt.OR2_tf[3]._y:=0]
483354 b.b.vt.ct.C2Els[1]._y : 0 [by b.b.vt.ct.in[3]:=1]
485597 b.b.vt.ct.tmp[8] : 1 [by b.b.vt.ct.C2Els[1]._y:=0]
500372 b.b.vt.ct.in[6] : 1 [by b.b.vt.OR2_tf[6]._y:=0]
500559 b.b.vt.ct.C3Els[0]._y : 0 [by b.b.vt.ct.in[6]:=1]
500560 b.b.vt.ct.tmp[9] : 1 [by b.b.vt.ct.C3Els[0]._y:=0]
515267 b.b.vt.OR2_tf[1]._y : 0 [by b.b.and_f[1].a:=1]
519449 b.b.vt.ct.in[1] : 1 [by b.b.vt.OR2_tf[1]._y:=0]
554231 b.b.vt.ct.C2Els[0]._y : 0 [by b.b.vt.ct.in[1]:=1]
554232 b.b.vt.ct.tmp[7] : 1 [by b.b.vt.ct.C2Els[0]._y:=0]
555085 b.b.vt.ct.C3Els[1]._y : 0 [by b.b.vt.ct.tmp[7]:=1]
555090 b.b.vt.out : 1 [by b.b.vt.ct.C3Els[1]._y:=0]
555981 b.b.in_v_buf._y : 0 [by b.b.vt.out:=1]
555982 b.in.v : 1 [by b.b.in_v_buf._y:=0]
555999 b.b.sb_in_v.buf4._y : 0 [by b.in.v:=1]
558572 b.b.and_f[0].c : 1 [by b.b.sb_in_v.buf4._y:=0]
558573 b.b.and_t[0]._y : 0 [by b.b.and_f[0].c:=1]
558575 b.b.and_f[1]._y : 0 [by b.b.and_f[0].c:=1]
558614 b.b.and_t[2]._y : 0 [by b.b.and_f[0].c:=1]
558670 b.b.and_f[1].y : 1 [by b.b.and_f[1]._y:=0]
558949 b.b.and_t[2].y : 1 [by b.b.and_t[2]._y:=0]
559513 b.b.and_f[3]._y : 0 [by b.b.and_f[0].c:=1]
559521 b.b.and_f[3].y : 1 [by b.b.and_f[3]._y:=0]
561389 b.b.and_t[5]._y : 0 [by b.b.and_f[0].c:=1]
561423 b.b.and_t[5].y : 1 [by b.b.and_t[5]._y:=0]
566933 b.b.and_f[6]._y : 0 [by b.b.and_f[0].c:=1]
572306 b.b.and_t[0].y : 1 [by b.b.and_t[0]._y:=0]
580820 b.b.and_f[6].y : 1 [by b.b.and_f[6]._y:=0]
617534 b.b.and_f[4]._y : 0 [by b.b.and_f[0].c:=1]
618452 b.b.and_f[4].y : 1 [by b.b.and_f[4]._y:=0]
618452 b.out.a : 1
618456 b.b.or2._y : 0 [by b.out.a:=1]
664834 b.b.or2.y : 1 [by b.b.or2._y:=0]
667232 b.b.ack_Cel._y : 0 [by b.b.or2.y:=1]
670447 b.in.a : 1 [by b.b.ack_Cel._y:=0]
[] Removing data
670447 b.b.and_t[0].a : 0
670447 b.b.and_f[6].a : 0
670447 b.b.and_t[2].a : 0
670447 b.b.and_t[5].a : 0
670447 b.b.and_f[1].a : 0
670447 b.b.and_f[4].a : 0
670447 b.b.and_f[3].a : 0
670448 b.b.vt.OR2_tf[4]._y : 1 [by b.b.and_f[4].a:=0]
670450 b.b.and_f[6]._y : 1 [by b.b.and_f[6].a:=0]
670451 b.b.vt.OR2_tf[3]._y : 1 [by b.b.and_f[3].a:=0]
670495 b.b.vt.OR2_tf[0]._y : 1 [by b.b.and_t[0].a:=0]
670496 b.b.vt.ct.in[0] : 0 [by b.b.vt.OR2_tf[0]._y:=1]
670520 b.b.and_f[3]._y : 1 [by b.b.and_f[3].a:=0]
670546 b.b.and_f[6].y : 0 [by b.b.and_f[6]._y:=1]
670587 b.b.vt.ct.in[3] : 0 [by b.b.vt.OR2_tf[3]._y:=1]
670620 b.b.vt.OR2_tf[1]._y : 1 [by b.b.and_f[1].a:=0]
670625 b.b.vt.OR2_tf[6]._y : 1 [by b.b.and_f[6].a:=0]
670631 b.b.and_f[4]._y : 1 [by b.b.and_f[4].a:=0]
670643 b.b.and_f[4].y : 0 [by b.b.and_f[4]._y:=1]
670861 b.b.vt.ct.in[1] : 0 [by b.b.vt.OR2_tf[1]._y:=1]
671274 b.b.and_f[1]._y : 1 [by b.b.and_f[1].a:=0]
672303 b.b.and_f[1].y : 0 [by b.b.and_f[1]._y:=1]
674584 b.b.vt.ct.in[6] : 0 [by b.b.vt.OR2_tf[6]._y:=1]
674761 b.b.vt.ct.C2Els[0]._y : 1 [by b.b.vt.ct.in[1]:=0]
674762 b.b.vt.ct.tmp[7] : 0 [by b.b.vt.ct.C2Els[0]._y:=1]
676398 b.b.and_t[5]._y : 1 [by b.b.and_t[5].a:=0]
676454 b.b.and_t[5].y : 0 [by b.b.and_t[5]._y:=1]
682346 b.b.vt.OR2_tf[2]._y : 1 [by b.b.and_t[2].a:=0]
689566 b.b.and_f[3].y : 0 [by b.b.and_f[3]._y:=1]
691424 b.b.and_t[2]._y : 1 [by b.b.and_t[2].a:=0]
691425 b.b.and_t[2].y : 0 [by b.b.and_t[2]._y:=1]
707736 b.b.vt.ct.in[4] : 0 [by b.b.vt.OR2_tf[4]._y:=1]
709932 b.b.vt.OR2_tf[5]._y : 1 [by b.b.and_t[5].a:=0]
709969 b.b.vt.ct.in[5] : 0 [by b.b.vt.OR2_tf[5]._y:=1]
717566 b.b.and_t[0]._y : 1 [by b.b.and_t[0].a:=0]
717567 b.b.and_t[0].y : 0 [by b.b.and_t[0]._y:=1]
727352 b.b.vt.ct.in[2] : 0 [by b.b.vt.OR2_tf[2]._y:=1]
730916 b.b.vt.ct.C2Els[1]._y : 1 [by b.b.vt.ct.in[2]:=0]
732608 b.b.vt.ct.tmp[8] : 0 [by b.b.vt.ct.C2Els[1]._y:=1]
733344 b.b.vt.ct.C3Els[0]._y : 1 [by b.b.vt.ct.in[5]:=0]
733357 b.b.vt.ct.tmp[9] : 0 [by b.b.vt.ct.C3Els[0]._y:=1]
750341 b.b.vt.ct.C3Els[1]._y : 1 [by b.b.vt.ct.tmp[9]:=0]
750698 b.b.vt.out : 0 [by b.b.vt.ct.C3Els[1]._y:=1]
750723 b.b.in_v_buf._y : 1 [by b.b.vt.out:=0]
750744 b.in.v : 0 [by b.b.in_v_buf._y:=1]
750745 b.b.sb_in_v.buf4._y : 1 [by b.in.v:=0]
760393 b.b.and_f[0].c : 0 [by b.b.sb_in_v.buf4._y:=1]
760393 b.out.a : 0
760394 b.b.or2._y : 1 [by b.out.a:=0]
760395 b.b.or2.y : 0 [by b.b.or2._y:=1]
760556 b.b.ack_Cel._y : 1 [by b.b.or2.y:=0]
761593 b.in.a : 0 [by b.b.ack_Cel._y:=1]
[] Enabling drop
761593 b.drop : 1
761598 b.b._dropB : 0 [by b.drop:=1]
762179 b.b.sb_dropB.buf4._y : 1 [by b.b._dropB:=0]
762587 b.b.and_f[0].b : 0 [by b.b.sb_dropB.buf4._y:=1]
[] Sending in valid data
762587 b.b.and_t[0].a : 1
762587 b.b.and_f[6].a : 1
762587 b.b.and_t[2].a : 1
762587 b.b.and_t[5].a : 1
762587 b.b.and_f[1].a : 1
762587 b.b.and_f[4].a : 1
762587 b.b.and_t[3].a : 1
762591 b.b.vt.OR2_tf[1]._y : 0 [by b.b.and_f[1].a:=1]
762598 b.b.vt.OR2_tf[0]._y : 0 [by b.b.and_t[0].a:=1]
762601 b.b.vt.OR2_tf[2]._y : 0 [by b.b.and_t[2].a:=1]
762605 b.b.vt.OR2_tf[5]._y : 0 [by b.b.and_t[5].a:=1]
762691 b.b.vt.OR2_tf[4]._y : 0 [by b.b.and_f[4].a:=1]
762829 b.b.vt.ct.in[2] : 1 [by b.b.vt.OR2_tf[2]._y:=0]
763448 b.b.vt.ct.in[5] : 1 [by b.b.vt.OR2_tf[5]._y:=0]
763634 b.b.vt.OR2_tf[6]._y : 0 [by b.b.and_f[6].a:=1]
763704 b.b.vt.ct.in[6] : 1 [by b.b.vt.OR2_tf[6]._y:=0]
763795 b.b.vt.ct.in[1] : 1 [by b.b.vt.OR2_tf[1]._y:=0]
764150 b.b.vt.ct.in[4] : 1 [by b.b.vt.OR2_tf[4]._y:=0]
771053 b.b.vt.ct.in[0] : 1 [by b.b.vt.OR2_tf[0]._y:=0]
771064 b.b.vt.ct.C2Els[0]._y : 0 [by b.b.vt.ct.in[0]:=1]
771067 b.b.vt.ct.tmp[7] : 1 [by b.b.vt.ct.C2Els[0]._y:=0]
794031 b.b.vt.OR2_tf[3]._y : 0 [by b.b.and_t[3].a:=1]
794085 b.b.vt.ct.in[3] : 1 [by b.b.vt.OR2_tf[3]._y:=0]
795233 b.b.vt.ct.C2Els[1]._y : 0 [by b.b.vt.ct.in[3]:=1]
796394 b.b.vt.ct.tmp[8] : 1 [by b.b.vt.ct.C2Els[1]._y:=0]
814572 b.b.vt.ct.C3Els[0]._y : 0 [by b.b.vt.ct.in[4]:=1]
823224 b.b.vt.ct.tmp[9] : 1 [by b.b.vt.ct.C3Els[0]._y:=0]
823305 b.b.vt.ct.C3Els[1]._y : 0 [by b.b.vt.ct.tmp[9]:=1]
834382 b.b.vt.out : 1 [by b.b.vt.ct.C3Els[1]._y:=0]
852365 b.b.in_v_buf._y : 0 [by b.b.vt.out:=1]
852457 b.in.v : 1 [by b.b.in_v_buf._y:=0]
854201 b.b.sb_in_v.buf4._y : 0 [by b.in.v:=1]
854814 b.b.and_f[0].c : 1 [by b.b.sb_in_v.buf4._y:=0]
860768 b.b.and2._y : 0 [by b.in.v:=1]
874790 b.b.or2.b : 1 [by b.b.and2._y:=0]
874835 b.b.or2._y : 0 [by b.b.or2.b:=1]
875832 b.b.or2.y : 1 [by b.b.or2._y:=0]
877481 b.b.ack_Cel._y : 0 [by b.b.or2.y:=1]
878006 b.in.a : 1 [by b.b.ack_Cel._y:=0]
[] Removing data
878006 b.b.and_t[0].a : 0
878006 b.b.and_f[6].a : 0
878006 b.b.and_t[2].a : 0
878006 b.b.and_t[5].a : 0
878006 b.b.and_f[1].a : 0
878006 b.b.and_f[4].a : 0
878006 b.b.and_t[3].a : 0
878008 b.b.vt.OR2_tf[4]._y : 1 [by b.b.and_f[4].a:=0]
878013 b.b.vt.OR2_tf[2]._y : 1 [by b.b.and_t[2].a:=0]
878014 b.b.vt.ct.in[2] : 0 [by b.b.vt.OR2_tf[2]._y:=1]
878058 b.b.vt.OR2_tf[6]._y : 1 [by b.b.and_f[6].a:=0]
878062 b.b.vt.ct.in[6] : 0 [by b.b.vt.OR2_tf[6]._y:=1]
878141 b.b.vt.ct.in[4] : 0 [by b.b.vt.OR2_tf[4]._y:=1]
878360 b.b.vt.OR2_tf[3]._y : 1 [by b.b.and_t[3].a:=0]
878906 b.b.vt.OR2_tf[0]._y : 1 [by b.b.and_t[0].a:=0]
878906 b.b.vt.ct.in[3] : 0 [by b.b.vt.OR2_tf[3]._y:=1]
878907 b.b.vt.ct.C2Els[1]._y : 1 [by b.b.vt.ct.in[3]:=0]
884473 b.b.vt.OR2_tf[1]._y : 1 [by b.b.and_f[1].a:=0]
884552 b.b.vt.ct.in[1] : 0 [by b.b.vt.OR2_tf[1]._y:=1]
891285 b.b.vt.ct.tmp[8] : 0 [by b.b.vt.ct.C2Els[1]._y:=1]
893618 b.b.vt.OR2_tf[5]._y : 1 [by b.b.and_t[5].a:=0]
896051 b.b.vt.ct.in[5] : 0 [by b.b.vt.OR2_tf[5]._y:=1]
896139 b.b.vt.ct.C3Els[0]._y : 1 [by b.b.vt.ct.in[5]:=0]
903921 b.b.vt.ct.tmp[9] : 0 [by b.b.vt.ct.C3Els[0]._y:=1]
924469 b.b.vt.ct.in[0] : 0 [by b.b.vt.OR2_tf[0]._y:=1]
952796 b.b.vt.ct.C2Els[0]._y : 1 [by b.b.vt.ct.in[0]:=0]
952855 b.b.vt.ct.tmp[7] : 0 [by b.b.vt.ct.C2Els[0]._y:=1]
952885 b.b.vt.ct.C3Els[1]._y : 1 [by b.b.vt.ct.tmp[7]:=0]
954352 b.b.vt.out : 0 [by b.b.vt.ct.C3Els[1]._y:=1]
1013856 b.b.in_v_buf._y : 1 [by b.b.vt.out:=0]
1033240 b.in.v : 0 [by b.b.in_v_buf._y:=1]
1033925 b.b.and2._y : 1 [by b.in.v:=0]
1034052 b.b.or2.b : 0 [by b.b.and2._y:=1]
1034221 b.b.or2._y : 1 [by b.b.or2.b:=0]
1034264 b.b.or2.y : 0 [by b.b.or2._y:=1]
1034276 b.b.ack_Cel._y : 1 [by b.b.or2.y:=0]
1035555 b.in.a : 0 [by b.b.ack_Cel._y:=1]
1049955 b.b.sb_in_v.buf4._y : 1 [by b.in.v:=0]
1050188 b.b.and_f[0].c : 0 [by b.b.sb_in_v.buf4._y:=1]
test/unit_tests/dropper_static/run/test.prs
-717
View File
@@ -1,717 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
= "b.b._dropB" "b.b.sb_dropB.in"
= "b.b._dropB" "b.b.inv.y"
"b.b.in_v_buf.a"->"b.b.in_v_buf._y"-
~("b.b.in_v_buf.a")->"b.b.in_v_buf._y"+
"b.b.in_v_buf._y"->"b.b.in_v_buf.y"-
~("b.b.in_v_buf._y")->"b.b.in_v_buf.y"+
"b.b.sb_dropB.buf4.a"->"b.b.sb_dropB.buf4._y"-
~("b.b.sb_dropB.buf4.a")->"b.b.sb_dropB.buf4._y"+
"b.b.sb_dropB.buf4._y"->"b.b.sb_dropB.buf4.y"-
~("b.b.sb_dropB.buf4._y")->"b.b.sb_dropB.buf4.y"+
= "b.b.sb_dropB.supply.vdd" "b.b.sb_dropB.buf4.vdd"
= "b.b.sb_dropB.supply.vss" "b.b.sb_dropB.buf4.vss"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[13]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[12]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[11]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[10]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[9]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[8]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[7]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[6]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[5]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[4]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[3]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[2]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[1]"
= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.buf4.y"
= "b.b.sb_dropB.in" "b.b.sb_dropB.buf4.a"
= "b.b.supply.vss" "b.b.sb_in_v.supply.vss"
= "b.b.supply.vdd" "b.b.sb_in_v.supply.vdd"
= "b.b.supply.vss" "b.b.sb_dropB.supply.vss"
= "b.b.supply.vdd" "b.b.sb_dropB.supply.vdd"
= "b.b.supply.vss" "b.b.vt.supply.vss"
= "b.b.supply.vdd" "b.b.vt.supply.vdd"
= "b.b.supply.vdd" "b.b.and_t[6].vdd"
= "b.b.supply.vdd" "b.b.and_t[5].vdd"
= "b.b.supply.vdd" "b.b.and_t[4].vdd"
= "b.b.supply.vdd" "b.b.and_t[3].vdd"
= "b.b.supply.vdd" "b.b.and_t[2].vdd"
= "b.b.supply.vdd" "b.b.and_t[1].vdd"
= "b.b.supply.vdd" "b.b.and_t[0].vdd"
= "b.b.supply.vdd" "b.b.or2.vdd"
= "b.b.supply.vdd" "b.b.and2.vdd"
= "b.b.supply.vdd" "b.b.in_v_buf.vdd"
= "b.b.supply.vdd" "b.b.inv.vdd"
= "b.b.supply.vss" "b.b.and_t[6].vss"
= "b.b.supply.vss" "b.b.and_t[5].vss"
= "b.b.supply.vss" "b.b.and_t[4].vss"
= "b.b.supply.vss" "b.b.and_t[3].vss"
= "b.b.supply.vss" "b.b.and_t[2].vss"
= "b.b.supply.vss" "b.b.and_t[1].vss"
= "b.b.supply.vss" "b.b.and_t[0].vss"
= "b.b.supply.vss" "b.b.or2.vss"
= "b.b.supply.vss" "b.b.and2.vss"
= "b.b.supply.vss" "b.b.in_v_buf.vss"
= "b.b.supply.vss" "b.b.inv.vss"
= "b.b.cond" "b.b.and2.a"
= "b.b.cond" "b.b._drop"
= "b.b.cond" "b.b.inv.a"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.a" "b.b.or2.a"
= "b.b.out.d.d[6].d[0]" "b.b.and_f[6].y"
= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
= "b.b.out.d.d[6].d[1]" "b.b.and_t[6].y"
= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
= "b.b.out.d.d[5].d[0]" "b.b.and_f[5].y"
= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
= "b.b.out.d.d[5].d[1]" "b.b.and_t[5].y"
= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
= "b.b.out.d.d[4].d[0]" "b.b.and_f[4].y"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.and_t[4].y"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.and_f[3].y"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.and_t[3].y"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.and_f[2].y"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.and_t[2].y"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.and_f[1].y"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.and_t[1].y"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.and_f[0].y"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.and_t[0].y"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[0].f" "b.b.vt.in.d[0].f"
= "b.b.in.d.d[0].t" "b.b.vt.in.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.vt.in.d[0].d[0]"
= "b.b.in.d.d[0].d[1]" "b.b.vt.in.d[0].d[1]"
= "b.b.in.d.d[1].f" "b.b.vt.in.d[1].f"
= "b.b.in.d.d[1].t" "b.b.vt.in.d[1].t"
= "b.b.in.d.d[1].d[0]" "b.b.vt.in.d[1].d[0]"
= "b.b.in.d.d[1].d[1]" "b.b.vt.in.d[1].d[1]"
= "b.b.in.d.d[2].f" "b.b.vt.in.d[2].f"
= "b.b.in.d.d[2].t" "b.b.vt.in.d[2].t"
= "b.b.in.d.d[2].d[0]" "b.b.vt.in.d[2].d[0]"
= "b.b.in.d.d[2].d[1]" "b.b.vt.in.d[2].d[1]"
= "b.b.in.d.d[3].f" "b.b.vt.in.d[3].f"
= "b.b.in.d.d[3].t" "b.b.vt.in.d[3].t"
= "b.b.in.d.d[3].d[0]" "b.b.vt.in.d[3].d[0]"
= "b.b.in.d.d[3].d[1]" "b.b.vt.in.d[3].d[1]"
= "b.b.in.d.d[4].f" "b.b.vt.in.d[4].f"
= "b.b.in.d.d[4].t" "b.b.vt.in.d[4].t"
= "b.b.in.d.d[4].d[0]" "b.b.vt.in.d[4].d[0]"
= "b.b.in.d.d[4].d[1]" "b.b.vt.in.d[4].d[1]"
= "b.b.in.d.d[5].f" "b.b.vt.in.d[5].f"
= "b.b.in.d.d[5].t" "b.b.vt.in.d[5].t"
= "b.b.in.d.d[5].d[0]" "b.b.vt.in.d[5].d[0]"
= "b.b.in.d.d[5].d[1]" "b.b.vt.in.d[5].d[1]"
= "b.b.in.d.d[6].f" "b.b.vt.in.d[6].f"
= "b.b.in.d.d[6].t" "b.b.vt.in.d[6].t"
= "b.b.in.d.d[6].d[0]" "b.b.vt.in.d[6].d[0]"
= "b.b.in.d.d[6].d[1]" "b.b.vt.in.d[6].d[1]"
= "b.b.in.a" "b.b.ack_Cel.y"
= "b.b.in.v" "b.b.sb_in_v.in"
= "b.b.in.v" "b.b.ack_Cel.c2"
= "b.b.in.v" "b.b.and2.b"
= "b.b.in.v" "b.b.in_v_buf.y"
= "b.b.in.v" "b.b._in_vX"
= "b.b.in.d.d[6].d[0]" "b.b.and_f[6].a"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.and_t[6].a"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.and_f[5].a"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.and_t[5].a"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.and_f[4].a"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.and_t[4].a"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.and_f[3].a"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.and_t[3].a"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.and_f[2].a"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.and_t[2].a"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.and_f[1].a"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.and_t[1].a"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.and_f[0].a"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.and_t[0].a"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
"b.b.or2.a"|"b.b.or2.b"->"b.b.or2._y"-
~("b.b.or2.a"|"b.b.or2.b")->"b.b.or2._y"+
"b.b.or2._y"->"b.b.or2.y"-
~("b.b.or2._y")->"b.b.or2.y"+
= "b.b.or2.y" "b.b.ack_Cel.c1"
= "b.b.or2.b" "b.b.and2.y"
"b.b.and2.a"&"b.b.and2.b"->"b.b.and2._y"-
~("b.b.and2.a"&"b.b.and2.b")->"b.b.and2._y"+
"b.b.and2._y"->"b.b.and2.y"-
~("b.b.and2._y")->"b.b.and2.y"+
"b.b.sb_in_v.buf4.a"->"b.b.sb_in_v.buf4._y"-
~("b.b.sb_in_v.buf4.a")->"b.b.sb_in_v.buf4._y"+
"b.b.sb_in_v.buf4._y"->"b.b.sb_in_v.buf4.y"-
~("b.b.sb_in_v.buf4._y")->"b.b.sb_in_v.buf4.y"+
= "b.b.sb_in_v.supply.vdd" "b.b.sb_in_v.buf4.vdd"
= "b.b.sb_in_v.supply.vss" "b.b.sb_in_v.buf4.vss"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[13]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[12]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[11]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[10]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[9]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[8]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[7]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[6]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[5]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[4]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[3]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[2]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[1]"
= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.buf4.y"
= "b.b.sb_in_v.in" "b.b.sb_in_v.buf4.a"
"b.b.and_f[0].a"&"b.b.and_f[0].b"&"b.b.and_f[0].c"->"b.b.and_f[0]._y"-
~("b.b.and_f[0].a"&"b.b.and_f[0].b"&"b.b.and_f[0].c")->"b.b.and_f[0]._y"+
"b.b.and_f[0]._y"->"b.b.and_f[0].y"-
~("b.b.and_f[0]._y")->"b.b.and_f[0].y"+
"b.b.and_f[1].a"&"b.b.and_f[1].b"&"b.b.and_f[1].c"->"b.b.and_f[1]._y"-
~("b.b.and_f[1].a"&"b.b.and_f[1].b"&"b.b.and_f[1].c")->"b.b.and_f[1]._y"+
"b.b.and_f[1]._y"->"b.b.and_f[1].y"-
~("b.b.and_f[1]._y")->"b.b.and_f[1].y"+
"b.b.and_f[2].a"&"b.b.and_f[2].b"&"b.b.and_f[2].c"->"b.b.and_f[2]._y"-
~("b.b.and_f[2].a"&"b.b.and_f[2].b"&"b.b.and_f[2].c")->"b.b.and_f[2]._y"+
"b.b.and_f[2]._y"->"b.b.and_f[2].y"-
~("b.b.and_f[2]._y")->"b.b.and_f[2].y"+
"b.b.and_f[3].a"&"b.b.and_f[3].b"&"b.b.and_f[3].c"->"b.b.and_f[3]._y"-
~("b.b.and_f[3].a"&"b.b.and_f[3].b"&"b.b.and_f[3].c")->"b.b.and_f[3]._y"+
"b.b.and_f[3]._y"->"b.b.and_f[3].y"-
~("b.b.and_f[3]._y")->"b.b.and_f[3].y"+
"b.b.and_f[4].a"&"b.b.and_f[4].b"&"b.b.and_f[4].c"->"b.b.and_f[4]._y"-
~("b.b.and_f[4].a"&"b.b.and_f[4].b"&"b.b.and_f[4].c")->"b.b.and_f[4]._y"+
"b.b.and_f[4]._y"->"b.b.and_f[4].y"-
~("b.b.and_f[4]._y")->"b.b.and_f[4].y"+
"b.b.and_f[5].a"&"b.b.and_f[5].b"&"b.b.and_f[5].c"->"b.b.and_f[5]._y"-
~("b.b.and_f[5].a"&"b.b.and_f[5].b"&"b.b.and_f[5].c")->"b.b.and_f[5]._y"+
"b.b.and_f[5]._y"->"b.b.and_f[5].y"-
~("b.b.and_f[5]._y")->"b.b.and_f[5].y"+
"b.b.and_f[6].a"&"b.b.and_f[6].b"&"b.b.and_f[6].c"->"b.b.and_f[6]._y"-
~("b.b.and_f[6].a"&"b.b.and_f[6].b"&"b.b.and_f[6].c")->"b.b.and_f[6]._y"+
"b.b.and_f[6]._y"->"b.b.and_f[6].y"-
~("b.b.and_f[6]._y")->"b.b.and_f[6].y"+
= "b.b.and_f[6].b" "b.b.and_t[6].b"
= "b.b.and_f[6].b" "b.b.and_t[5].b"
= "b.b.and_f[6].b" "b.b.and_t[4].b"
= "b.b.and_f[6].b" "b.b.and_t[3].b"
= "b.b.and_f[6].b" "b.b.and_t[2].b"
= "b.b.and_f[6].b" "b.b.and_t[1].b"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[13]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[12]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[11]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[10]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[9]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[8]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[7]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[6]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[5]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[4]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[3]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[2]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[1]"
= "b.b.and_f[6].b" "b.b.sb_dropB.out[0]"
= "b.b.and_f[6].b" "b.b.and_t[0].b"
= "b.b.and_f[6].b" "b.b.and_f[0].b"
= "b.b.and_f[6].b" "b.b.and_f[1].b"
= "b.b.and_f[6].b" "b.b.and_f[2].b"
= "b.b.and_f[6].b" "b.b.and_f[3].b"
= "b.b.and_f[6].b" "b.b.and_f[4].b"
= "b.b.and_f[6].b" "b.b.and_f[5].b"
= "b.b.and_f[6].c" "b.b.and_t[6].c"
= "b.b.and_f[6].c" "b.b.and_t[5].c"
= "b.b.and_f[6].c" "b.b.and_t[4].c"
= "b.b.and_f[6].c" "b.b.and_t[3].c"
= "b.b.and_f[6].c" "b.b.and_t[2].c"
= "b.b.and_f[6].c" "b.b.and_t[1].c"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[13]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[12]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[11]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[10]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[9]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[8]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[7]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[6]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[5]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[4]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[3]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[2]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[1]"
= "b.b.and_f[6].c" "b.b.sb_in_v.out[0]"
= "b.b.and_f[6].c" "b.b.and_t[0].c"
= "b.b.and_f[6].c" "b.b.and_f[0].c"
= "b.b.and_f[6].c" "b.b.and_f[1].c"
= "b.b.and_f[6].c" "b.b.and_f[2].c"
= "b.b.and_f[6].c" "b.b.and_f[3].c"
= "b.b.and_f[6].c" "b.b.and_f[4].c"
= "b.b.and_f[6].c" "b.b.and_f[5].c"
"b.b.and_t[0].a"&"b.b.and_t[0].b"&"b.b.and_t[0].c"->"b.b.and_t[0]._y"-
~("b.b.and_t[0].a"&"b.b.and_t[0].b"&"b.b.and_t[0].c")->"b.b.and_t[0]._y"+
"b.b.and_t[0]._y"->"b.b.and_t[0].y"-
~("b.b.and_t[0]._y")->"b.b.and_t[0].y"+
"b.b.and_t[1].a"&"b.b.and_t[1].b"&"b.b.and_t[1].c"->"b.b.and_t[1]._y"-
~("b.b.and_t[1].a"&"b.b.and_t[1].b"&"b.b.and_t[1].c")->"b.b.and_t[1]._y"+
"b.b.and_t[1]._y"->"b.b.and_t[1].y"-
~("b.b.and_t[1]._y")->"b.b.and_t[1].y"+
"b.b.and_t[2].a"&"b.b.and_t[2].b"&"b.b.and_t[2].c"->"b.b.and_t[2]._y"-
~("b.b.and_t[2].a"&"b.b.and_t[2].b"&"b.b.and_t[2].c")->"b.b.and_t[2]._y"+
"b.b.and_t[2]._y"->"b.b.and_t[2].y"-
~("b.b.and_t[2]._y")->"b.b.and_t[2].y"+
"b.b.and_t[3].a"&"b.b.and_t[3].b"&"b.b.and_t[3].c"->"b.b.and_t[3]._y"-
~("b.b.and_t[3].a"&"b.b.and_t[3].b"&"b.b.and_t[3].c")->"b.b.and_t[3]._y"+
"b.b.and_t[3]._y"->"b.b.and_t[3].y"-
~("b.b.and_t[3]._y")->"b.b.and_t[3].y"+
"b.b.and_t[4].a"&"b.b.and_t[4].b"&"b.b.and_t[4].c"->"b.b.and_t[4]._y"-
~("b.b.and_t[4].a"&"b.b.and_t[4].b"&"b.b.and_t[4].c")->"b.b.and_t[4]._y"+
"b.b.and_t[4]._y"->"b.b.and_t[4].y"-
~("b.b.and_t[4]._y")->"b.b.and_t[4].y"+
"b.b.and_t[5].a"&"b.b.and_t[5].b"&"b.b.and_t[5].c"->"b.b.and_t[5]._y"-
~("b.b.and_t[5].a"&"b.b.and_t[5].b"&"b.b.and_t[5].c")->"b.b.and_t[5]._y"+
"b.b.and_t[5]._y"->"b.b.and_t[5].y"-
~("b.b.and_t[5]._y")->"b.b.and_t[5].y"+
"b.b.and_t[6].a"&"b.b.and_t[6].b"&"b.b.and_t[6].c"->"b.b.and_t[6]._y"-
~("b.b.and_t[6].a"&"b.b.and_t[6].b"&"b.b.and_t[6].c")->"b.b.and_t[6]._y"+
"b.b.and_t[6]._y"->"b.b.and_t[6].y"-
~("b.b.and_t[6]._y")->"b.b.and_t[6].y"+
"b.b.inv.a"->"b.b.inv.y"-
~("b.b.inv.a")->"b.b.inv.y"+
~"b.b.vt.ct.C2Els[0].c1"&~"b.b.vt.ct.C2Els[0].c2"->"b.b.vt.ct.C2Els[0]._y"+
"b.b.vt.ct.C2Els[0].c1"&"b.b.vt.ct.C2Els[0].c2"->"b.b.vt.ct.C2Els[0]._y"-
"b.b.vt.ct.C2Els[0]._y"->"b.b.vt.ct.C2Els[0].y"-
~("b.b.vt.ct.C2Els[0]._y")->"b.b.vt.ct.C2Els[0].y"+
~"b.b.vt.ct.C2Els[1].c1"&~"b.b.vt.ct.C2Els[1].c2"->"b.b.vt.ct.C2Els[1]._y"+
"b.b.vt.ct.C2Els[1].c1"&"b.b.vt.ct.C2Els[1].c2"->"b.b.vt.ct.C2Els[1]._y"-
"b.b.vt.ct.C2Els[1]._y"->"b.b.vt.ct.C2Els[1].y"-
~("b.b.vt.ct.C2Els[1]._y")->"b.b.vt.ct.C2Els[1].y"+
~"b.b.vt.ct.C3Els[0].c1"&~"b.b.vt.ct.C3Els[0].c2"&~"b.b.vt.ct.C3Els[0].c3"->"b.b.vt.ct.C3Els[0]._y"+
"b.b.vt.ct.C3Els[0].c1"&"b.b.vt.ct.C3Els[0].c2"&"b.b.vt.ct.C3Els[0].c3"->"b.b.vt.ct.C3Els[0]._y"-
"b.b.vt.ct.C3Els[0]._y"->"b.b.vt.ct.C3Els[0].y"-
~("b.b.vt.ct.C3Els[0]._y")->"b.b.vt.ct.C3Els[0].y"+
~"b.b.vt.ct.C3Els[1].c1"&~"b.b.vt.ct.C3Els[1].c2"&~"b.b.vt.ct.C3Els[1].c3"->"b.b.vt.ct.C3Els[1]._y"+
"b.b.vt.ct.C3Els[1].c1"&"b.b.vt.ct.C3Els[1].c2"&"b.b.vt.ct.C3Els[1].c3"->"b.b.vt.ct.C3Els[1]._y"-
"b.b.vt.ct.C3Els[1]._y"->"b.b.vt.ct.C3Els[1].y"-
~("b.b.vt.ct.C3Els[1]._y")->"b.b.vt.ct.C3Els[1].y"+
= "b.b.vt.ct.tmp[7]" "b.b.vt.ct.C3Els[1].c1"
= "b.b.vt.ct.tmp[7]" "b.b.vt.ct.C2Els[0].y"
= "b.b.vt.ct.tmp[8]" "b.b.vt.ct.C3Els[1].c2"
= "b.b.vt.ct.tmp[8]" "b.b.vt.ct.C2Els[1].y"
= "b.b.vt.ct.tmp[9]" "b.b.vt.ct.C3Els[1].c3"
= "b.b.vt.ct.tmp[9]" "b.b.vt.ct.C3Els[0].y"
= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C3Els[1].vdd"
= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C3Els[0].vdd"
= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C2Els[1].vdd"
= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C2Els[0].vdd"
= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C3Els[1].vss"
= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C3Els[0].vss"
= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C2Els[1].vss"
= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C2Els[0].vss"
= "b.b.vt.ct.in[0]" "b.b.vt.ct.C2Els[0].c1"
= "b.b.vt.ct.in[0]" "b.b.vt.ct.tmp[0]"
= "b.b.vt.ct.in[1]" "b.b.vt.ct.C2Els[0].c2"
= "b.b.vt.ct.in[1]" "b.b.vt.ct.tmp[1]"
= "b.b.vt.ct.in[2]" "b.b.vt.ct.C2Els[1].c1"
= "b.b.vt.ct.in[2]" "b.b.vt.ct.tmp[2]"
= "b.b.vt.ct.in[3]" "b.b.vt.ct.C2Els[1].c2"
= "b.b.vt.ct.in[3]" "b.b.vt.ct.tmp[3]"
= "b.b.vt.ct.in[4]" "b.b.vt.ct.C3Els[0].c1"
= "b.b.vt.ct.in[4]" "b.b.vt.ct.tmp[4]"
= "b.b.vt.ct.in[5]" "b.b.vt.ct.C3Els[0].c2"
= "b.b.vt.ct.in[5]" "b.b.vt.ct.tmp[5]"
= "b.b.vt.ct.in[6]" "b.b.vt.ct.C3Els[0].c3"
= "b.b.vt.ct.in[6]" "b.b.vt.ct.tmp[6]"
= "b.b.vt.ct.out" "b.b.vt.ct.C3Els[1].y"
= "b.b.vt.ct.out" "b.b.vt.ct.tmp[10]"
= "b.b.vt.ct.in[0]" "b.b.vt.OR2_tf[0].y"
= "b.b.vt.ct.in[1]" "b.b.vt.OR2_tf[1].y"
= "b.b.vt.ct.in[2]" "b.b.vt.OR2_tf[2].y"
= "b.b.vt.ct.in[3]" "b.b.vt.OR2_tf[3].y"
= "b.b.vt.ct.in[4]" "b.b.vt.OR2_tf[4].y"
= "b.b.vt.ct.in[5]" "b.b.vt.OR2_tf[5].y"
= "b.b.vt.ct.in[6]" "b.b.vt.OR2_tf[6].y"
"b.b.vt.OR2_tf[0].a"|"b.b.vt.OR2_tf[0].b"->"b.b.vt.OR2_tf[0]._y"-
~("b.b.vt.OR2_tf[0].a"|"b.b.vt.OR2_tf[0].b")->"b.b.vt.OR2_tf[0]._y"+
"b.b.vt.OR2_tf[0]._y"->"b.b.vt.OR2_tf[0].y"-
~("b.b.vt.OR2_tf[0]._y")->"b.b.vt.OR2_tf[0].y"+
"b.b.vt.OR2_tf[1].a"|"b.b.vt.OR2_tf[1].b"->"b.b.vt.OR2_tf[1]._y"-
~("b.b.vt.OR2_tf[1].a"|"b.b.vt.OR2_tf[1].b")->"b.b.vt.OR2_tf[1]._y"+
"b.b.vt.OR2_tf[1]._y"->"b.b.vt.OR2_tf[1].y"-
~("b.b.vt.OR2_tf[1]._y")->"b.b.vt.OR2_tf[1].y"+
"b.b.vt.OR2_tf[2].a"|"b.b.vt.OR2_tf[2].b"->"b.b.vt.OR2_tf[2]._y"-
~("b.b.vt.OR2_tf[2].a"|"b.b.vt.OR2_tf[2].b")->"b.b.vt.OR2_tf[2]._y"+
"b.b.vt.OR2_tf[2]._y"->"b.b.vt.OR2_tf[2].y"-
~("b.b.vt.OR2_tf[2]._y")->"b.b.vt.OR2_tf[2].y"+
"b.b.vt.OR2_tf[3].a"|"b.b.vt.OR2_tf[3].b"->"b.b.vt.OR2_tf[3]._y"-
~("b.b.vt.OR2_tf[3].a"|"b.b.vt.OR2_tf[3].b")->"b.b.vt.OR2_tf[3]._y"+
"b.b.vt.OR2_tf[3]._y"->"b.b.vt.OR2_tf[3].y"-
~("b.b.vt.OR2_tf[3]._y")->"b.b.vt.OR2_tf[3].y"+
"b.b.vt.OR2_tf[4].a"|"b.b.vt.OR2_tf[4].b"->"b.b.vt.OR2_tf[4]._y"-
~("b.b.vt.OR2_tf[4].a"|"b.b.vt.OR2_tf[4].b")->"b.b.vt.OR2_tf[4]._y"+
"b.b.vt.OR2_tf[4]._y"->"b.b.vt.OR2_tf[4].y"-
~("b.b.vt.OR2_tf[4]._y")->"b.b.vt.OR2_tf[4].y"+
"b.b.vt.OR2_tf[5].a"|"b.b.vt.OR2_tf[5].b"->"b.b.vt.OR2_tf[5]._y"-
~("b.b.vt.OR2_tf[5].a"|"b.b.vt.OR2_tf[5].b")->"b.b.vt.OR2_tf[5]._y"+
"b.b.vt.OR2_tf[5]._y"->"b.b.vt.OR2_tf[5].y"-
~("b.b.vt.OR2_tf[5]._y")->"b.b.vt.OR2_tf[5].y"+
"b.b.vt.OR2_tf[6].a"|"b.b.vt.OR2_tf[6].b"->"b.b.vt.OR2_tf[6]._y"-
~("b.b.vt.OR2_tf[6].a"|"b.b.vt.OR2_tf[6].b")->"b.b.vt.OR2_tf[6]._y"+
"b.b.vt.OR2_tf[6]._y"->"b.b.vt.OR2_tf[6].y"-
~("b.b.vt.OR2_tf[6]._y")->"b.b.vt.OR2_tf[6].y"+
= "b.b.vt.supply.vss" "b.b.vt.ct.supply.vss"
= "b.b.vt.supply.vdd" "b.b.vt.ct.supply.vdd"
= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[6].vdd"
= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[5].vdd"
= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[4].vdd"
= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[3].vdd"
= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[2].vdd"
= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[1].vdd"
= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[0].vdd"
= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[6].vss"
= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[5].vss"
= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[4].vss"
= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[3].vss"
= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[2].vss"
= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[1].vss"
= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[0].vss"
= "b.b.vt.out" "b.b.vt.ct.out"
= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
= "b.b.vt.in.d[6].d[0]" "b.b.vt.OR2_tf[6].b"
= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
= "b.b.vt.in.d[6].d[1]" "b.b.vt.OR2_tf[6].a"
= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
= "b.b.vt.in.d[5].d[0]" "b.b.vt.OR2_tf[5].b"
= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
= "b.b.vt.in.d[5].d[1]" "b.b.vt.OR2_tf[5].a"
= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
= "b.b.vt.in.d[4].d[0]" "b.b.vt.OR2_tf[4].b"
= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
= "b.b.vt.in.d[4].d[1]" "b.b.vt.OR2_tf[4].a"
= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
= "b.b.vt.in.d[3].d[0]" "b.b.vt.OR2_tf[3].b"
= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
= "b.b.vt.in.d[3].d[1]" "b.b.vt.OR2_tf[3].a"
= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
= "b.b.vt.in.d[2].d[0]" "b.b.vt.OR2_tf[2].b"
= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
= "b.b.vt.in.d[2].d[1]" "b.b.vt.OR2_tf[2].a"
= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
= "b.b.vt.in.d[1].d[0]" "b.b.vt.OR2_tf[1].b"
= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
= "b.b.vt.in.d[1].d[1]" "b.b.vt.OR2_tf[1].a"
= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
= "b.b.vt.in.d[0].d[0]" "b.b.vt.OR2_tf[0].b"
= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
= "b.b.vt.in.d[0].d[1]" "b.b.vt.OR2_tf[0].a"
= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
= "b.b.vt.out" "b.b.in_v_buf.a"
~"b.b.ack_Cel.c1"&~"b.b.ack_Cel.c2"->"b.b.ack_Cel._y"+
"b.b.ack_Cel.c1"&"b.b.ack_Cel.c2"->"b.b.ack_Cel._y"-
"b.b.ack_Cel._y"->"b.b.ack_Cel.y"-
~("b.b.ack_Cel._y")->"b.b.ack_Cel.y"+
= "b.supply.vss" "b.b.supply.vss"
= "b.supply.vdd" "b.b.supply.vdd"
= "Vdd" "b.supply.vdd"
= "GND" "b.supply.vss"
= "b.drop" "b.b.cond"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.v" "b.b.out.v"
= "b.out.a" "b.b.out.a"
= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
= "b.out.d.d[5].f" "b.b.out.d.d[5].f"
= "b.out.d.d[5].t" "b.b.out.d.d[5].t"
= "b.out.d.d[5].d[0]" "b.b.out.d.d[5].d[0]"
= "b.out.d.d[5].d[1]" "b.b.out.d.d[5].d[1]"
= "b.out.d.d[6].f" "b.b.out.d.d[6].f"
= "b.out.d.d[6].t" "b.b.out.d.d[6].t"
= "b.out.d.d[6].d[0]" "b.b.out.d.d[6].d[0]"
= "b.out.d.d[6].d[1]" "b.b.out.d.d[6].d[1]"
= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.v" "b.b.in.v"
= "b.in.a" "b.b.in.a"
= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
= "b.in.d.d[5].f" "b.b.in.d.d[5].f"
= "b.in.d.d[5].t" "b.b.in.d.d[5].t"
= "b.in.d.d[5].d[0]" "b.b.in.d.d[5].d[0]"
= "b.in.d.d[5].d[1]" "b.b.in.d.d[5].d[1]"
= "b.in.d.d[6].f" "b.b.in.d.d[6].f"
= "b.in.d.d[6].t" "b.b.in.d.d[6].t"
= "b.in.d.d[6].d[0]" "b.b.in.d.d[6].d[0]"
= "b.in.d.d[6].d[1]" "b.b.in.d.d[6].d[1]"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
test/unit_tests/dropper_static/test.act
-52
View File
@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc dropper_static_7 (avMx1of2<7> in; avMx1of2<7> out; bool? drop){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
dropper_static<7, true> b(.in = in, .out = out, .cond = drop, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
dropper_static_7 b;
test/unit_tests/dropper_static/test.prsim
-73
View File
@@ -1,73 +0,0 @@
watchall
set-qdi-channel-neutral "b.in" 7
set b.out.a 0
set b.out.v 0
set b.drop 0
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
status X
assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending in valid data'"
set-qdi-channel-valid "b.in" 7 45
cycle
assert-qdi-channel-valid "b.out" 7 45
assert b.in.v 1
cycle
set b.out.a 1
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing data'"
set-qdi-channel-neutral "b.in" 7
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 0
set b.out.a 0
cycle
assert b.in.a 0
system "echo '[] Sending in valid data'"
set-qdi-channel-valid "b.in" 7 37
cycle
assert-qdi-channel-valid "b.out" 7 37
assert b.in.v 1
cycle
set b.out.a 1
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing data'"
set-qdi-channel-neutral "b.in" 7
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 0
set b.out.a 0
cycle
assert b.in.a 0
system "echo '[] Enabling drop'"
set b.drop 1
cycle
system "echo '[] Sending in valid data'"
set-qdi-channel-valid "b.in" 7 45
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 1
assert b.in.a 1
system "echo '[] Removing data'"
set-qdi-channel-neutral "b.in" 7
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 0
assert b.in.a 0
test/unit_tests/encoder1d_7/run/prsim.in
-268
View File
@@ -1,268 +0,0 @@
random_seed 99
initialize
load-scm "helper.scm"
random
set GND 0
set Vdd 1
set Reset 1
mode reset
cycle
status U
watchall
system "echo '[] Set Reset 1'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 0
set e.out.v 0
set Reset 1
cycle
status X
system "echo '[] Set Reset 0'"
set Reset 0
cycle
status X
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 6 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 1
cycle
assert-qdi-channel-valid "e.out" 3 6
assert e.in[6].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[6].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
test/unit_tests/encoder1d_7/run/prsim.out
-3073
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File diff suppressed because it is too large Load Diff
test/unit_tests/encoder1d_7/run/test.prs
-3110
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File diff suppressed because it is too large Load Diff
test/unit_tests/encoder1d_7/test.act
-54
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@@ -1,54 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder1d_simple_test(a1of1 in[7]; avMx1of2<3> out){
power supply;
supply.vss = GND;
supply.vdd = Vdd;
bool _reset_B;
prs {
Reset => _reset_B-
}
encoder1d_simple<3,7> e(.in = in, .supply = supply, .reset_B = _reset_B);
fifo<3, 5> fifo_post(.in = e.out, .out = out, .supply = supply, .reset_B = _reset_B);
}
encoder1d_simple_test e;
test/unit_tests/encoder1d_7/test.prsim
-257
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@@ -1,257 +0,0 @@
watchall
system "echo '[] Set Reset 1'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 0
set e.out.v 0
set Reset 1
cycle
status X
system "echo '[] Set Reset 0'"
set Reset 0
cycle
status X
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 6 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 1
cycle
assert-qdi-channel-valid "e.out" 3 6
assert e.in[6].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[6].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
test/unit_tests/encoder1d_bd/run/prsim.in
-92
View File
@@ -1,92 +0,0 @@
initialize
load-scm "helper.scm"
random
set GND 0
set Vdd 1
set Reset 1
mode reset
cycle
status U
watchall
set c.dly_cfg[0] 1
set c.dly_cfg[1] 1
set c.dly_cfg[2] 1
set c.dly_cfg[3] 1
set c.in[0].r 0
set c.in[1].r 0
set c.in[2].r 0
set c.in[3].r 0
set c.in[4].r 0
set c.in[5].r 0
set c.in[6].r 0
set c.out.a 0
set Reset 1
cycle
status X
system "echo '[] Set reset 0'"
mode run
set Reset 0
cycle
system "echo '[] Reset finished'"
status X
assert-bd-channel-neutral "c.out" 3
assert c.in[0].a 0
assert c.in[1].a 0
assert c.in[2].a 0
assert c.in[3].a 0
assert c.in[4].a 0
assert c.in[5].a 0
assert c.in[6].a 0
system "echo '[] Spiking 3'"
set c.in[3].r 1
cycle
assert c.in[3].a 1
set c.in[3].r 0
cycle
assert c.in[3].a 0
system "echo '[] Spiking 6'"
set c.in[6].r 1
cycle
assert c.in[6].a 1
set c.in[6].r 0
cycle
assert c.in[6].a 0
system "echo '[] Receive 3'"
assert-bd-channel-valid "c.out" 3 3
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 3
set c.out.a 0
cycle
system "echo '[] Receive 6'"
assert-bd-channel-valid "c.out" 3 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 6
set c.out.a 0
cycle
test/unit_tests/encoder1d_bd/run/prsim.out
-3470
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File diff suppressed because one or more lines are too long
test/unit_tests/encoder1d_bd/run/test.prs
-4957
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File diff suppressed because it is too large Load Diff
test/unit_tests/encoder1d_bd/test.act
-61
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@@ -1,61 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
pint N = 7;
pint Nc = std::ceil_log2(N);
pint N_BUFFERS = 5;
pint N_BD_DLY_CFG = 4;
defproc _encoder1d_bd (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
.reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
_encoder1d_bd c;
test/unit_tests/encoder1d_bd/test.prsim
-82
View File
@@ -1,82 +0,0 @@
watchall
set c.dly_cfg[0] 1
set c.dly_cfg[1] 1
set c.dly_cfg[2] 1
set c.dly_cfg[3] 1
set c.in[0].r 0
set c.in[1].r 0
set c.in[2].r 0
set c.in[3].r 0
set c.in[4].r 0
set c.in[5].r 0
set c.in[6].r 0
set c.out.a 0
set Reset 1
cycle
status X
system "echo '[] Set reset 0'"
mode run
set Reset 0
cycle
system "echo '[] Reset finished'"
status X
assert-bd-channel-neutral "c.out" 3
assert c.in[0].a 0
assert c.in[1].a 0
assert c.in[2].a 0
assert c.in[3].a 0
assert c.in[4].a 0
assert c.in[5].a 0
assert c.in[6].a 0
system "echo '[] Spiking 3'"
set c.in[3].r 1
cycle
assert c.in[3].a 1
set c.in[3].r 0
cycle
assert c.in[3].a 0
system "echo '[] Spiking 6'"
set c.in[6].r 1
cycle
assert c.in[6].a 1
set c.in[6].r 0
cycle
assert c.in[6].a 0
system "echo '[] Receive 3'"
assert-bd-channel-valid "c.out" 3 3
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 3
set c.out.a 0
cycle
system "echo '[] Receive 6'"
assert-bd-channel-valid "c.out" 3 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 6
set c.out.a 0
cycle

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