alexmadison ec03f8abe4 added reg reset sig		2022-04-21 14:33:41 +02:00
..
andtree_5	…
andtree_15	…
append_5_3_2	…
arbiter	…
arbiter_2	…
arbiter_handshake_adv	…
arbiter_handshake_simple	…
arbiter_tree_simple_nosim	…
arbiter_tree_test	…
arbtree_5	…
async_instantiate	…
bd-fifo-register-fifo-bd	…
bd2qdi_5	…
buf_15	…
buf_s_5	…
buffer_register_7	…
buffer_token	…
ctree_15	…
decoder_2d_dly_8_16	…
decoder_2d_dly_and_2_4	…
decoder_2d_hs	…
decoder_2d_hybrid	…
delayprog_4	…
demux_7	…
demux_bit_7	…
demux_td_2	…
demux_td_2_SIGN	…
dropper_static	…
encoder1d_7	encoder1d passed unit tests	2022-04-11 19:49:22 +02:00
encoder2D_2x2	…
encoder2D_8x7	…
encoder2D_8x8	…
encoder_7	…
fifo-decoder-neurons-encoder-fifo	…
fifo-decoder_hs-neurons-encoder-fifo	…
fifo-decoder_hybrid-neurons-encoder-fifo	…
fifo-register-fifo	…
fifo3_8bit	…
fifo_demux_bit_7_fifo	…
fifo_t_5	…
fifo_t_15	…
flipflop	…
fork_15	…
line_end_pull_up	…
merge_t_2_adv	…
merge_t_2_simple	…
nrn_hs_2D_array_3x5	…
ortree_15	…
qdi2bd_5	…
registerA_w	…
registerA_w_array	…
registerA_wr_array	…
register_write	…
register_wrw	…
sigbuf_15	…
std_instantiate	…
texel_dualcore	added reg reset sig	2022-04-21 14:33:41 +02:00
texel_dualcore_innovus	texel prs for innovus generated	2022-04-21 14:31:35 +02:00
texel_in30	…
texel_in30_noNrn	texel30 with manual neurons passing tests	2022-04-08 18:36:58 +02:00
texel_small	texel small testt working	2022-04-12 17:48:59 +02:00
vtree_5	…
vtree_15	…
.DS_Store	…
buf_15.v	…
buf_15_friendly2.v	…
buff.v	…
helper.scm	added set bd channel without setting r	2022-04-10 13:59:27 +02:00
init.prs	…
init_qdi.prsim	…