Michele 6f1a970cfd register_rw (formerly register_rw_v2) compiles

2022-03-09 16:44:44 +01:00

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andtree_5

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andtree_15

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arbiter

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arbiter_2

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arbiter_handshake_adv

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arbiter_handshake_simple

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arbiter_tree_simple_nosim

arbiter_test redone without fifos

2022-03-08 11:36:25 +01:00

arbiter_tree_test

started register_v2 with reading and writing abilities

2022-03-09 13:05:08 +01:00

arbtree_5

arbtree init, using or2s for now

2022-03-03 10:47:37 +01:00

async_instantiate

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buf_15

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buf_s_5

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buffer_token

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ctree_15

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decoder_2d_dly_8_16

decoder 2d dly init

2022-03-02 15:55:26 +01:00

decoder_2d_dly_and_2_4

decoder dly with and grid unit test

2022-03-03 17:10:55 +01:00

delayprog_4

programmable delay tested

2022-03-01 15:26:43 +01:00

demux_7

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demux_td_2

demux_td reviewed and supplies added

2022-03-08 10:11:52 +01:00

demux_td_2_SIGN

finished and simmed demuxtd

2022-03-01 17:56:30 +01:00

encoder2D_7

encoder sim still not working

2022-03-08 18:49:04 +01:00

encoder_7

renamed encoder to dualrail_encoder

2022-03-04 14:53:14 +01:00

fifo3_8bit

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fifo_t_5

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fifo_t_15

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flipflop

register_write works

2022-03-07 16:36:01 +01:00

fork_15

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line_end_pull_up

Added stuff for line end pull U/D

2022-03-04 12:33:49 +01:00

merge_t_2_adv

merge tested with concurrent inputs work

2022-03-01 17:36:49 +01:00

merge_t_2_simple

merge with simple test is working

2022-03-01 17:14:10 +01:00

ortree_15

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register_write

started register_v2 with reading and writing abilities

2022-03-09 13:05:08 +01:00

register_wrw

register_rw (formerly register_rw_v2) compiles

2022-03-09 16:44:44 +01:00

sigbuf_15

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std_instantiate

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vtree_5

added a vtree_5 test

2022-03-05 20:29:02 +01:00

vtree_15

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buf_15_friendly2.v

encoder sim still not working

2022-03-08 18:49:04 +01:00

buf_15.v

Added stuff for line end pull U/D

2022-03-04 12:33:49 +01:00

helper.scm

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init_qdi.prsim

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init.prs

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