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andtree_5
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added and tree
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2022-03-01 12:22:36 +01:00 |
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andtree_15
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added and tree
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2022-03-01 12:22:36 +01:00 |
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arbiter
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pushed merge in primitives.act
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2022-02-28 18:58:32 +01:00 |
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arbiter_2
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started demuxtd
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2022-02-28 09:46:26 +01:00 |
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arbiter_handshake_adv
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fifo_test_adv works
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2022-02-28 11:11:30 +01:00 |
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arbiter_handshake_simple
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fifo_test_adv works
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2022-02-28 11:11:30 +01:00 |
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arbiter_tree_simple_nosim
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arbiter_test redone without fifos
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2022-03-08 11:36:25 +01:00 |
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arbiter_tree_test
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started register_v2 with reading and writing abilities
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2022-03-09 13:05:08 +01:00 |
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arbtree_5
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arbtree init, using or2s for now
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2022-03-03 10:47:37 +01:00 |
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async_instantiate
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prepared things for having unit test ready
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2022-02-21 13:01:45 +01:00 |
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buf_15
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Changed printout to be more serious
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2022-02-22 19:23:33 +01:00 |
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buf_s_5
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unit tests working
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2022-03-01 09:58:20 +01:00 |
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buffer_token
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started demuxtd
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2022-02-28 09:46:26 +01:00 |
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ctree_15
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differentiated between ctree and vtree, all primitives updated
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2022-03-01 09:44:51 +01:00 |
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decoder_2d_dly_8_16
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decoder 2d dly init
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2022-03-02 15:55:26 +01:00 |
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decoder_2d_dly_and_2_4
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decoder dly with and grid unit test
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2022-03-03 17:10:55 +01:00 |
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delayprog_4
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programmable delay tested
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2022-03-01 15:26:43 +01:00 |
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demux_7
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Demux Simmed, fixed treegates
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2022-02-25 15:13:21 +01:00 |
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demux_td_2
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demux_td reviewed and supplies added
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2022-03-08 10:11:52 +01:00 |
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demux_td_2_SIGN
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finished and simmed demuxtd
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2022-03-01 17:56:30 +01:00 |
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encoder2D_2x2
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encoder8x8sim
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2022-03-18 11:39:30 +01:00 |
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encoder2D_8x7
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encoder2d revd mdsn
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2022-03-22 16:29:30 +01:00 |
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encoder2D_8x8
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encoder2d revd mdsn
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2022-03-22 16:29:30 +01:00 |
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encoder_7
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renamed encoder to dualrail_encoder
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2022-03-04 14:53:14 +01:00 |
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fifo3_8bit
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prepared things for having unit test ready
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2022-02-21 13:01:45 +01:00 |
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fifo_t_5
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fifo t 5 unit tests checked
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2022-02-28 15:52:20 +01:00 |
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fifo_t_15
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fifo_test_adv works
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2022-02-28 11:11:30 +01:00 |
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flipflop
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register_write works
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2022-03-07 16:36:01 +01:00 |
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fork_15
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Demux Simmed, fixed treegates
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2022-02-25 15:13:21 +01:00 |
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line_end_pull_up
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Added stuff for line end pull U/D
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2022-03-04 12:33:49 +01:00 |
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merge_t_2_adv
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merge tested with concurrent inputs work
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2022-03-01 17:36:49 +01:00 |
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merge_t_2_simple
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merge with simple test is working
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2022-03-01 17:14:10 +01:00 |
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ortree_15
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we have liftoff - lisp code still needs fixing
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2022-02-22 11:25:55 +01:00 |
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register_write
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started register_v2 with reading and writing abilities
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2022-03-09 13:05:08 +01:00 |
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register_wrw
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continued register_rw
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2022-03-15 08:16:59 +01:00 |
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sigbuf_15
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we have liftoff - lisp code still needs fixing
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2022-02-22 11:25:55 +01:00 |
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std_instantiate
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Added std test
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2022-02-21 13:07:14 +01:00 |
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vtree_5
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added a vtree_5 test
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2022-03-05 20:29:02 +01:00 |
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vtree_15
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differentiated between ctree and vtree, all primitives updated
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2022-03-01 09:44:51 +01:00 |
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buf_15.v
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Added stuff for line end pull U/D
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2022-03-04 12:33:49 +01:00 |
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buf_15_friendly2.v
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encoder sim still not working
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2022-03-08 18:49:04 +01:00 |
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helper.scm
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added bd helpers
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2022-02-23 11:43:28 +01:00 |
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init.prs
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attempting to complete the buffer
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2022-02-22 13:52:54 +01:00 |
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init_qdi.prsim
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Async buffer test fully working
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2022-02-22 18:04:21 +01:00 |
9ad12dc951