Greatorex b9219f266f Encoder Simmed

2022-03-18 10:06:43 +01:00

..

andtree_5

added and tree

2022-03-01 12:22:36 +01:00

andtree_15

added and tree

2022-03-01 12:22:36 +01:00

arbiter

pushed merge in primitives.act

2022-02-28 18:58:32 +01:00

arbiter_2

started demuxtd

2022-02-28 09:46:26 +01:00

arbiter_handshake_adv

fifo_test_adv works

2022-02-28 11:11:30 +01:00

arbiter_handshake_simple

fifo_test_adv works

2022-02-28 11:11:30 +01:00

arbiter_tree_simple_nosim

arbiter_test redone without fifos

2022-03-08 11:36:25 +01:00

arbiter_tree_test

started register_v2 with reading and writing abilities

2022-03-09 13:05:08 +01:00

arbtree_5

arbtree init, using or2s for now

2022-03-03 10:47:37 +01:00

async_instantiate

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

buf_15

Changed printout to be more serious

2022-02-22 19:23:33 +01:00

buf_s_5

unit tests working

2022-03-01 09:58:20 +01:00

buffer_token

started demuxtd

2022-02-28 09:46:26 +01:00

ctree_15

differentiated between ctree and vtree, all primitives updated

2022-03-01 09:44:51 +01:00

decoder_2d_dly_8_16

decoder 2d dly init

2022-03-02 15:55:26 +01:00

decoder_2d_dly_and_2_4

decoder dly with and grid unit test

2022-03-03 17:10:55 +01:00

delayprog_4

programmable delay tested

2022-03-01 15:26:43 +01:00

demux_7

Demux Simmed, fixed treegates

2022-02-25 15:13:21 +01:00

demux_td_2

demux_td reviewed and supplies added

2022-03-08 10:11:52 +01:00

demux_td_2_SIGN

finished and simmed demuxtd

2022-03-01 17:56:30 +01:00

encoder2D_7

Encoder Simmed

2022-03-18 10:06:43 +01:00

encoder_7

renamed encoder to dualrail_encoder

2022-03-04 14:53:14 +01:00

fifo3_8bit

prepared things for having unit test ready

2022-02-21 13:01:45 +01:00

fifo_t_5

fifo t 5 unit tests checked

2022-02-28 15:52:20 +01:00

fifo_t_15

fifo_test_adv works

2022-02-28 11:11:30 +01:00

flipflop

register_write works

2022-03-07 16:36:01 +01:00

fork_15

Demux Simmed, fixed treegates

2022-02-25 15:13:21 +01:00

line_end_pull_up

Added stuff for line end pull U/D

2022-03-04 12:33:49 +01:00

merge_t_2_adv

merge tested with concurrent inputs work

2022-03-01 17:36:49 +01:00

merge_t_2_simple

merge with simple test is working

2022-03-01 17:14:10 +01:00

ortree_15

we have liftoff - lisp code still needs fixing

2022-02-22 11:25:55 +01:00

register_write

started register_v2 with reading and writing abilities

2022-03-09 13:05:08 +01:00

register_wrw

register_rw continued

2022-03-09 20:02:41 +01:00

sigbuf_15

we have liftoff - lisp code still needs fixing

2022-02-22 11:25:55 +01:00

std_instantiate

Added std test

2022-02-21 13:07:14 +01:00

vtree_5

added a vtree_5 test

2022-03-05 20:29:02 +01:00

vtree_15

differentiated between ctree and vtree, all primitives updated

2022-03-01 09:44:51 +01:00

buf_15_friendly2.v

encoder sim still not working

2022-03-08 18:49:04 +01:00

buf_15.v

Added stuff for line end pull U/D

2022-03-04 12:33:49 +01:00

helper.scm

added bd helpers

2022-02-23 11:43:28 +01:00

init_qdi.prsim

Async buffer test fully working

2022-02-22 18:04:21 +01:00

init.prs

attempting to complete the buffer

2022-02-22 13:52:54 +01:00