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actlib_dataflow_neuro/test/unit_tests
History
alexmadison fa5f83f061 register rw passed initial tests
2022-04-02 18:31:45 +02:00
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andtree_5
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andtree_15
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append_5_3_2
append unit test with fifos
2022-03-25 18:57:35 +01:00
arbiter
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arbiter_2
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arbiter_handshake_adv
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arbiter_handshake_simple
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arbiter_tree_simple_nosim
arbiter_test redone without fifos
2022-03-08 11:36:25 +01:00
arbiter_tree_test
started register_v2 with reading and writing abilities
2022-03-09 13:05:08 +01:00
arbtree_5
Auto stash before rebase of "origin/dev"
2022-03-30 15:03:55 +02:00
async_instantiate
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bd2qdi_5
bd2qdi ole backseat reved
2022-03-25 15:43:46 +01:00
buf_15
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buf_s_5
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buffer_register_7
buffer register unit tests init
2022-04-01 20:47:04 +02:00
buffer_token
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ctree_15
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decoder_2d_dly_8_16
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decoder_2d_dly_and_2_4
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decoder_2d_hs
synapse handshake unit tests working
2022-03-31 11:23:51 +02:00
decoder_2d_hybrid
decoder 2d hybrid unit tests working
2022-03-31 18:00:08 +02:00
delayprog_4
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demux_7
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demux_td_2
demux_td reviewed and supplies added
2022-03-08 10:11:52 +01:00
demux_td_2_SIGN
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encoder2D_2x2
encoder8x8sim
2022-03-18 11:39:30 +01:00
encoder2D_8x7
encoder2d revd mdsn
2022-03-22 16:29:30 +01:00
encoder2D_8x8
encoder2d revd mdsn
2022-03-22 16:29:30 +01:00
encoder_7
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fifo3_8bit
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fifo_t_5
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fifo_t_15
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fifo-decoder_hs-neurons-encoder-fifo
nrn_hs fifo etc unit test working
2022-03-31 16:20:23 +02:00
fifo-decoder_hybrid-neurons-encoder-fifo
hybrid decoder in fifo train working
2022-03-31 18:06:47 +02:00
fifo-decoder-neurons-encoder-fifo
renamed encoder inputs from x to inx
2022-03-30 10:14:29 +02:00
flipflop
flipflop updated
2022-03-30 16:03:01 +02:00
fork_15
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line_end_pull_up
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merge_t_2_adv
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merge_t_2_simple
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nrn_hs_2D_array_3x5
unit test for hs
2022-03-29 11:25:14 +02:00
ortree_15
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qdi2bd_5
qdi2bd ready for rev
2022-03-25 17:15:03 +01:00
register_write
pushing register
2022-03-30 15:01:50 +02:00
register_wrw
pushing register
2022-03-30 15:01:50 +02:00
registerA_w
registerA_w unit test working
2022-04-01 20:46:45 +02:00
registerA_w_array
register write array unit tests working
2022-04-02 17:16:20 +02:00
registerA_wr_array
register rw passed initial tests
2022-04-02 18:31:45 +02:00
sigbuf_15
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std_instantiate
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vtree_5
added a vtree_5 test
2022-03-05 20:29:02 +01:00
vtree_15
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.DS_Store
Auto stash before rebase of "origin/dev"
2022-03-30 15:03:55 +02:00
buf_15_friendly2.v
encoder sim still not working
2022-03-08 18:49:04 +01:00
buf_15.v
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helper.scm
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init_qdi.prsim
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init.prs
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