alexmadison
|
5647d4affe
|
added TBUF_X4
|
2022-04-10 19:02:03 +02:00 |
|
alexmadison
|
b162cff991
|
added a comment to mux2
|
2022-04-01 20:46:03 +02:00 |
|
alexmadison
|
a53bd58e29
|
added Ole dly4 as per hugh
|
2022-03-30 16:50:05 +02:00 |
 M. Mastella
|
edb0443c01
|
Added new version of Register_rw (still not properly working)
|
2022-03-14 17:15:27 +01:00 |
|
M. Mastella
|
e49866323c
|
register_write works
|
2022-03-07 16:36:01 +01:00 |
Michele
|
72ec59cbcf
|
added flip flop from XFAB
|
2022-03-04 19:02:34 +01:00 |
|
Michele
|
e8fa8e43a6
|
Changed FF in std. Started test (spoiler: is not working)
|
2022-03-04 13:11:34 +01:00 |
|
Michele
|
397c832b7b
|
Added Flip Flop to std.act (still need to try it)
|
2022-03-04 11:43:33 +01:00 |
|
alexmadison
|
3bba9fefa4
|
made buf with dly sorry
|
2022-03-02 15:48:54 +01:00 |
|
alexmadison
|
31d2f35042
|
i am a moron re dly cells
|
2022-03-02 15:47:36 +01:00 |
|
alexmadison
|
79a96ed511
|
added DLY4 cell
|
2022-03-01 15:28:22 +01:00 |
 Greatorex
|
6dd5df58a1
|
pushing in the meanwhile
|
2022-02-21 18:27:41 +01:00 |
|
alexmadison
|
ded1742b72
|
added some 3/4 cells and changed mux cells
|
2022-02-21 17:50:23 +01:00 |
|
M. Mastella
|
df97903436
|
test celement tree is working
|
2022-02-21 16:44:08 +01:00 |
|
alexmadison
|
30ffd8b16f
|
removed clock buffers
|
2022-02-21 15:53:40 +01:00 |
|
Greatorex
|
5fc6eaab9e
|
Added std test
|
2022-02-21 13:07:14 +01:00 |
|
Greatorex
|
aa92b8bea4
|
Auto stash before merge of "dev" and "origin/dev"
|
2022-02-21 10:32:18 +01:00 |
 Ole Richter
|
48b691d7d4
|
added license, moved cell libs into repo
added buffer (not tested),
|
2022-02-21 00:33:58 +01:00 |