alexmadison
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8e38a0fb01
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put fake PRs in tiehi/los lol
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2022-06-29 15:58:58 +02:00 |
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alexmadison
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b994b60690
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inverted TBUFs
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2022-05-08 17:03:38 +02:00 |
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alexmadison
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82aae3d337
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added bufx32
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2022-04-21 14:56:57 +02:00 |
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alexmadison
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1e7133cafe
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reverted hughs madness
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2022-04-21 14:55:18 +02:00 |
 Greatorex
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cd1947a2ce
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Auto stash before merge of "dev" and "origin/dev"
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2022-04-15 12:48:50 +02:00 |
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alexmadison
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5647d4affe
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added TBUF_X4
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2022-04-10 19:02:03 +02:00 |
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alexmadison
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b162cff991
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added a comment to mux2
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2022-04-01 20:46:03 +02:00 |
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alexmadison
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a53bd58e29
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added Ole dly4 as per hugh
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2022-03-30 16:50:05 +02:00 |
 M. Mastella
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edb0443c01
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Added new version of Register_rw (still not properly working)
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2022-03-14 17:15:27 +01:00 |
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M. Mastella
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e49866323c
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register_write works
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2022-03-07 16:36:01 +01:00 |
Michele
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72ec59cbcf
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added flip flop from XFAB
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2022-03-04 19:02:34 +01:00 |
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Michele
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e8fa8e43a6
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Changed FF in std. Started test (spoiler: is not working)
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2022-03-04 13:11:34 +01:00 |
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Michele
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397c832b7b
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Added Flip Flop to std.act (still need to try it)
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2022-03-04 11:43:33 +01:00 |
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alexmadison
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3bba9fefa4
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made buf with dly sorry
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2022-03-02 15:48:54 +01:00 |
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alexmadison
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31d2f35042
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i am a moron re dly cells
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2022-03-02 15:47:36 +01:00 |
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alexmadison
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79a96ed511
|
added DLY4 cell
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2022-03-01 15:28:22 +01:00 |
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Greatorex
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6dd5df58a1
|
pushing in the meanwhile
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2022-02-21 18:27:41 +01:00 |
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alexmadison
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ded1742b72
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added some 3/4 cells and changed mux cells
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2022-02-21 17:50:23 +01:00 |
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M. Mastella
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df97903436
|
test celement tree is working
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2022-02-21 16:44:08 +01:00 |
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alexmadison
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30ffd8b16f
|
removed clock buffers
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2022-02-21 15:53:40 +01:00 |
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Greatorex
|
5fc6eaab9e
|
Added std test
|
2022-02-21 13:07:14 +01:00 |
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Greatorex
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aa92b8bea4
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Auto stash before merge of "dev" and "origin/dev"
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2022-02-21 10:32:18 +01:00 |
 Ole Richter
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48b691d7d4
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added license, moved cell libs into repo
added buffer (not tested),
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2022-02-21 00:33:58 +01:00 |