bics/actlib_dataflow_neuro
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Author SHA1 Message Date
alexmadison f91fa9b158 all times fix 2022-03-08 10:48:43 +01:00
alexmadison 2a4d8c8dee added sig names on rhs, ty maxime 2022-03-08 10:24:42 +01:00
alexmadison a78eec5777 demux_td reviewed and supplies added 2022-03-08 10:11:52 +01:00
alexmadison c3f0059bfa encoder2d compiling 2022-03-07 16:22:00 +01:00
alexmadison a411231628 added some supplies 2022-03-07 16:21:45 +01:00
alexmadison 9b3bdc3f6c rejigged A cell in encoder2d 2022-03-04 15:09:49 +01:00
alexmadison a53110dda4 renamed encoder to dualrail_encoder 2022-03-04 14:53:14 +01:00
alexmadison 2882bc0f24 encoder unit test 2022-03-04 14:32:02 +01:00
alexmadison 4a4c4eeb14 merged encoder 2022-03-04 14:27:38 +01:00
alexmadison f55322bc7c encoder init 2022-03-04 14:10:15 +01:00
alexmadison 382714d11e decoder dly with and grid unit test 2022-03-03 17:10:55 +01:00
alexmadison c8412606b3 merged 2022-03-03 17:10:16 +01:00
alexmadison 893f71db92 AND grid init 2022-03-03 17:09:00 +01:00
alexmadison da5948f493 added N=1 cases 2022-03-03 17:05:56 +01:00
alexmadison 6fc3e4b99c removed arbiter tree 2022-03-03 11:56:59 +01:00
alexmadison af52c688a3 arbiter tree with arbiters, not tested 2022-03-03 11:56:34 +01:00
alexmadison d0a2fff096 arbiter init with or2s 2022-03-03 10:52:29 +01:00
alexmadison 7f40b48b49 arbtree init, using or2s for now 2022-03-03 10:47:37 +01:00
alexmadison 9c27248e12 decoder 2d dly init 2022-03-02 15:55:26 +01:00
alexmadison 3bba9fefa4 made buf with dly sorry 2022-03-02 15:48:54 +01:00
alexmadison 31d2f35042 i am a moron re dly cells 2022-03-02 15:47:36 +01:00
alexmadison c61a570f80 fixed wiring bug in prog delay 2022-03-02 15:11:22 +01:00
alexmadison 6bece2f459 renamed gates in or tree 2022-03-02 13:51:12 +01:00
alexmadison 659cd2479c oops accidentally hit all trees 2022-03-02 13:50:04 +01:00
alexmadison c5e582ff3e renamed vars in atree 2022-03-02 13:48:57 +01:00
alexmadison e52ec9ed61 renamed var in vtree for consciences 2022-03-02 11:51:45 +01:00
alexmadison c580d21efe fixed supply in fifo_t 2022-03-02 11:24:28 +01:00
alexmadison 1b7e39bc00 coders.act file init 2022-03-02 09:48:41 +01:00
alexmadison 8060051da0 Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-03-02 09:48:11 +01:00
alexmadison b456ea40fd changed delayprog to outin vs ya naming scheme 2022-03-02 09:48:05 +01:00
alexmadison 79a96ed511 added DLY4 cell 2022-03-01 15:28:22 +01:00
alexmadison 233c9a7d10 cleaned up minor 2022-03-01 15:27:27 +01:00
alexmadison 00869fc16e programmable delay tested 2022-03-01 15:26:43 +01:00
alexmadison 8268379572 bug to prev bug 2022-03-01 14:00:47 +01:00
alexmadison 18f84bc652 Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-03-01 13:55:47 +01:00
alexmadison 05f46ccf33 added try except for assert printing 2022-03-01 13:55:45 +01:00
alexmadison fc4ccea3c0 added and tree 2022-03-01 12:22:36 +01:00
alexmadison c947b28b03 added yours truely to the authors 2022-03-01 10:18:32 +01:00
alexmadison aeed4e5527 changed c->v tree in buf_s 2022-03-01 10:15:23 +01:00
alexmadison a8b1710f65 merged buf_s into primitives 2022-03-01 10:09:08 +01:00
alexmadison 66cbbe3da7 unit tests working 2022-03-01 09:58:20 +01:00
alexmadison 84b2831d89 buf_s_5 unit tests 2022-02-28 18:27:22 +01:00
alexmadison 3fc4b1fb1a buf_s_tempalte init 2022-02-28 18:27:03 +01:00
alexmadison 5bae88d56f added flag to plot all times 2022-02-28 17:56:12 +01:00
alexmadison 225d481ae1 fifo t 5 unit tests checked 2022-02-28 15:52:20 +01:00
alexmadison 94109bb157 plotting in ex bugs 2022-02-28 15:44:24 +01:00
alexmadison e21e132d8b Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-02-28 13:57:32 +01:00
alexmadison 73ae3b0f19 added assert plots 2022-02-28 13:57:28 +01:00
alexmadison ee59fc9a44 fixed a plotting bug oops 2022-02-28 10:52:07 +01:00
alexmadison 6db6a2072b minor qol to plotting 2022-02-28 10:46:41 +01:00
alexmadison 1510746bfa merged w michele 2022-02-28 10:44:23 +01:00
alexmadison 9e4f090af2 added times and alternative colours 2022-02-28 10:21:43 +01:00
alexmadison be33d19762 renamed reset sigs in A_2C2N cells 2022-02-23 18:39:28 +01:00
alexmadison 1dcca99453 renamed RB cells2 2022-02-23 18:34:13 +01:00
alexmadison 9fb7aae0a4 renamed RB cells 2022-02-23 18:33:36 +01:00
alexmadison 68fea3633e Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-02-23 14:59:58 +01:00
alexmadison 97f7489100 minor plotting qol changes 2022-02-23 14:59:56 +01:00
alexmadison 3405e471d1 added png output 2022-02-23 12:49:07 +01:00
alexmadison 84ea663fd8 Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-02-23 12:27:40 +01:00
alexmadison 404c403e83 init prsim plotter 2022-02-23 12:23:10 +01:00
alexmadison 296411da8c what 2022-02-21 17:53:23 +01:00
alexmadison ded1742b72 added some 3/4 cells and changed mux cells 2022-02-21 17:50:23 +01:00
alexmadison 5928dc9f42 init rewriting tree gates 2022-02-21 15:54:10 +01:00
alexmadison 30ffd8b16f removed clock buffers 2022-02-21 15:53:40 +01:00