alexmadison
|
fdf05371f3
|
added sigbufs to register
|
2022-04-12 16:37:59 +02:00 |
|
alexmadison
|
a5a378fe6c
|
trying to fix possible lockup in reg lol
|
2022-04-12 10:24:26 +02:00 |
|
alexmadison
|
81032c1296
|
texel working with replaced encoder
|
2022-04-11 15:31:05 +02:00 |
|
alexmadison
|
cc2487be1c
|
added monitor decoders
|
2022-04-08 17:55:12 +02:00 |
|
alexmadison
|
ec091708a8
|
changed cells to lowercase
|
2022-04-08 12:13:43 +02:00 |
|
alexmadison
|
fa5f83f061
|
register rw passed initial tests
|
2022-04-02 18:31:45 +02:00 |
|
alexmadison
|
be3cc7a2d7
|
register rw compiling:
|
2022-04-02 18:09:09 +02:00 |
|
alexmadison
|
b59a57c324
|
changed write bit selectors from ands to Cels, to avoid selector hazards
|
2022-04-02 17:37:56 +02:00 |
|
alexmadison
|
eda9e2a98b
|
register write array unit tests working
|
2022-04-02 17:16:20 +02:00 |
|
alexmadison
|
a7fc0d2cba
|
write register array compiling
|
2022-04-01 20:45:04 +02:00 |
|
alexmadison
|
596a6f9c9f
|
register A cell init, compiling not tested
|
2022-04-01 18:10:49 +02:00 |
|
alexmadison
|
ab248d608e
|
init and unit tests for register buffer
|
2022-04-01 16:58:12 +02:00 |
 Greatorex
|
7db428b827
|
register added again
|
2022-03-30 15:04:35 +02:00 |
Michele
|
04d12338b7
|
continued register_rw
|
2022-03-15 08:16:59 +01:00 |
 M. Mastella
|
edb0443c01
|
Added new version of Register_rw (still not properly working)
|
2022-03-14 17:15:27 +01:00 |
|
Michele
|
cc2234a1b1
|
moved the ack of the register
|
2022-03-09 20:18:20 +01:00 |
|
Michele
|
4dcd975554
|
register_rw continued
|
2022-03-09 20:02:41 +01:00 |
|
Michele
|
6f1a970cfd
|
register_rw (formerly register_rw_v2) compiles
|
2022-03-09 16:44:44 +01:00 |
|
M. Mastella
|
c8ac3cf37d
|
started register_v2 with reading and writing abilities
|
2022-03-09 13:05:08 +01:00 |
|
M. Mastella
|
e49866323c
|
register_write works
|
2022-03-07 16:36:01 +01:00 |
|
Michele
|
ad318259a5
|
continued registers.c
|
2022-03-07 07:15:53 +01:00 |
|
Michele
|
932e967f3d
|
encoder in register works
|
2022-03-05 20:33:38 +01:00 |
|
Michele
|
aa67bd6168
|
register simulates correctly up to the fake clock generation
|
2022-03-05 20:28:50 +01:00 |
|
Michele
|
78a8f72d25
|
register compiles
|
2022-03-05 09:19:19 +01:00 |
|
Michele
|
7fe31f0ed8
|
started testing the register_w (doesn't compile)
|
2022-03-04 21:17:30 +01:00 |
|
Michele
|
b5fa707c4e
|
forgot proc in defproc
|
2022-03-04 19:04:11 +01:00 |
|
Michele
|
9c6a591dc7
|
started registers
|
2022-03-04 11:44:00 +01:00 |