alexmadison
|
ea3f91d6de
|
chips init
|
2022-04-04 17:14:08 +02:00 |
|
alexmadison
|
560ae9c5f0
|
added data slice primitive
|
2022-04-04 17:13:49 +02:00 |
 Greatorex
|
31b3853558
|
added more demuxs
|
2022-04-04 17:10:05 +02:00 |
|
alexmadison
|
55ed8bb839
|
added buffered dr decoder
|
2022-04-04 15:37:31 +02:00 |
|
alexmadison
|
5e4a8ee15c
|
dropper static with unit tests
|
2022-04-04 15:13:39 +02:00 |
|
alexmadison
|
afe332e8ba
|
fifo reg fifo unit test working
|
2022-04-04 09:49:51 +02:00 |
|
alexmadison
|
fa5f83f061
|
register rw passed initial tests
|
2022-04-02 18:31:45 +02:00 |
|
alexmadison
|
be3cc7a2d7
|
register rw compiling:
|
2022-04-02 18:09:09 +02:00 |
|
alexmadison
|
b59a57c324
|
changed write bit selectors from ands to Cels, to avoid selector hazards
|
2022-04-02 17:37:56 +02:00 |
|
alexmadison
|
eda9e2a98b
|
register write array unit tests working
|
2022-04-02 17:16:20 +02:00 |
|
alexmadison
|
e995a78efb
|
dunno what i changed buti it was probably good
|
2022-04-01 20:54:27 +02:00 |
|
alexmadison
|
87010c256b
|
buffer register unit tests init
|
2022-04-01 20:47:04 +02:00 |
|
alexmadison
|
0a957fc130
|
registerA_w unit test working
|
2022-04-01 20:46:45 +02:00 |
|
alexmadison
|
b162cff991
|
added a comment to mux2
|
2022-04-01 20:46:03 +02:00 |
|
alexmadison
|
732526f0e3
|
added cells needed for register
|
2022-04-01 20:45:37 +02:00 |
|
alexmadison
|
a7fc0d2cba
|
write register array compiling
|
2022-04-01 20:45:04 +02:00 |
|
alexmadison
|
596a6f9c9f
|
register A cell init, compiling not tested
|
2022-04-01 18:10:49 +02:00 |
|
alexmadison
|
ab248d608e
|
init and unit tests for register buffer
|
2022-04-01 16:58:12 +02:00 |
|
alexmadison
|
df1aae7690
|
added S cells for register
|
2022-04-01 16:57:44 +02:00 |
|
alexmadison
|
82537e07de
|
added pullup down as wrappers on teh A cells
|
2022-03-31 18:10:08 +02:00 |
|
alexmadison
|
e05196bb7e
|
hybrid decoder in fifo train working
|
2022-03-31 18:06:47 +02:00 |
|
alexmadison
|
c840273ae6
|
decoder 2d hybrid unit tests working
|
2022-03-31 18:00:08 +02:00 |
|
alexmadison
|
2c491a6e37
|
replaced Pullup/downs with A cell naming scheme
|
2022-03-31 16:44:09 +02:00 |
|
alexmadison
|
6751e2807c
|
comments
|
2022-03-31 16:23:01 +02:00 |
|
alexmadison
|
7b7cd4653e
|
nrn_hs fifo etc unit test working
|
2022-03-31 16:20:23 +02:00 |
|
alexmadison
|
89b8dacd29
|
changed line pull downs to be isochronic as fuk
|
2022-03-31 16:19:20 +02:00 |
|
alexmadison
|
6ecee7f0c7
|
added comments
|
2022-03-31 15:24:51 +02:00 |
|
alexmadison
|
f1ae79cd5a
|
added buffering of dualrail decoder output lines to pull downs
|
2022-03-31 15:22:50 +02:00 |
|
alexmadison
|
6dfc941993
|
added Cel to buf out ack, so that ack can't be removed before the bufs output data is fully invalidated
|
2022-03-31 15:10:47 +02:00 |
|
alexmadison
|
1d5d4738a2
|
cleaned up coders a bit
|
2022-03-31 13:20:18 +02:00 |
|
alexmadison
|
2e4cdd5029
|
vastly improved lazy synapse handshakes
|
2022-03-31 12:44:00 +02:00 |
|
alexmadison
|
cd5d41d7f8
|
synapse handshake unit tests working
|
2022-03-31 11:23:51 +02:00 |
|
alexmadison
|
e779ee55b9
|
added delays to out req-ack buffers, seems to work
|
2022-03-30 19:53:27 +02:00 |
|
alexmadison
|
a53bd58e29
|
added Ole dly4 as per hugh
|
2022-03-30 16:50:05 +02:00 |
 M. Mastella
|
8c4f081090
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-30 16:03:07 +02:00 |
|
M. Mastella
|
f468913472
|
flipflop updated
|
2022-03-30 16:03:01 +02:00 |
|
alexmadison
|
21c78e4461
|
fixed bug in delay fifo
|
2022-03-30 15:47:01 +02:00 |
|
alexmadison
|
4cbe8cb3d1
|
XMerge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
|
2022-03-30 15:16:19 +02:00 |
|
alexmadison
|
f9cdb2e914
|
added pulldown2
|
2022-03-30 15:16:15 +02:00 |
|
Greatorex
|
44f0cd871d
|
Merge branch 'HEAD' into dev
|
2022-03-30 15:10:25 +02:00 |
|
Greatorex
|
e09b4a0f7e
|
Merge branch 'dev' into HEAD
|
2022-03-30 15:09:59 +02:00 |
|
Greatorex
|
7db428b827
|
register added again
|
2022-03-30 15:04:35 +02:00 |
|
Greatorex
|
ba17fc0d1b
|
Auto stash before rebase of "origin/dev"
|
2022-03-30 15:03:55 +02:00 |
|
Greatorex
|
fbcd679b4c
|
pushing register
|
2022-03-30 15:01:50 +02:00 |
|
alexmadison
|
87f552b1d0
|
decoder hs wip
|
2022-03-30 14:06:14 +02:00 |
|
alexmadison
|
cff6eba344
|
decoder_2d_hs init
|
2022-03-30 13:18:07 +02:00 |
|
alexmadison
|
d10d78347c
|
refactored decoder into decoder dualrail
|
2022-03-30 11:01:21 +02:00 |
|
alexmadison
|
1707f1043a
|
renamed encoder inputs from x to inx
|
2022-03-30 10:14:29 +02:00 |
|
alexmadison
|
870da14ccd
|
let delay fifos have N= 0, simplified nrn grids thusly
|
2022-03-29 19:07:04 +02:00 |
|
alexmadison
|
8b60b23214
|
omg its working
|
2022-03-29 18:35:58 +02:00 |