actlib_dataflow_neuro/test/unit_tests
alexmadison a70c9a1b6d removed extra supply vss lines from tiehi/lows 2022-06-29 18:25:44 +02:00
..
andtree_5
andtree_15
append_5_3_2
arbiter
arbiter_2
arbiter_handshake_adv
arbiter_handshake_simple
arbiter_tree_simple_nosim
arbiter_tree_test
arbtree_5
async_instantiate
bd-fifo-register-fifo-bd
bd2qdi_5
buf_15
buf_s_5
buffer_register_7
buffer_token
ctree_15
decoder_2d_dly_8_16
decoder_2d_dly_and_2_4
decoder_2d_hs
decoder_2d_hybrid
delayprog_4
demux_7
demux_bit_7
demux_td_2
demux_td_2_SIGN
dropper_static
encoder1d_7
encoder1d_bd encoder1d with bd simmed 2022-04-21 16:09:13 +02:00
encoder2D_2x2
encoder2D_8x7
encoder2D_8x8
encoder_7
fifo-decoder-neurons-encoder-fifo
fifo-decoder_hs-neurons-encoder-fifo
fifo-decoder_hybrid-neurons-encoder-fifo
fifo-register-fifo
fifo3_8bit
fifo_demux_bit_7_fifo Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00
fifo_t_5
fifo_t_15
flipflop
fork_15
line_end_pull_up
merge_t_2_adv
merge_t_2_simple
nrn_hs_2D_array_3x5
nrn_hs_2d Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00
ortree_15
qdi2bd_5
registerA_w
registerA_w_array
registerA_wr_array
register_write
register_wrw
sadc_encoder renamed to sadc_encoder 2022-06-29 13:36:14 +02:00
sigbuf_15
std_instantiate
texel_dualcore added reset sigs to neuron syn cores 2022-05-02 18:49:57 +02:00
texel_dualcore_glue removed extra supply vss lines from tiehi/lows 2022-06-29 18:25:44 +02:00
texel_dualcore_glue_mapper test merge of sram rw output working 2022-05-10 15:34:04 +02:00
texel_dualcore_glue_small tdc glue small for testing 2022-06-23 17:54:10 +02:00
texel_dualcore_innovus regenned texel dualcore innovus fairly finaly?? 2022-05-02 19:45:34 +02:00
texel_encoder1d_bd_sadc added sadc encoder with inputs low active for dynapse sadcs 2022-06-29 13:18:42 +02:00
texel_in30
texel_in30_noNrn
texel_small Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00
vtree_5
vtree_15
.DS_Store
buf_15.v
buf_15_friendly2.v
buff.v
helper.scm
init.prs
init_qdi.prsim
nrn_hs_2d.v Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00
nrn_hs_2d_clean.v Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00
texel_small.net Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00
texel_small.v Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00
texel_small_clean.v Auto stash before merge of "dev" and "origin/dev" 2022-04-15 12:48:50 +02:00