bics/actlib_dataflow_neuro
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b21b84e78d8894e4f174f337e03505556c5e2f88
actlib_dataflow_neuro/test/unit_tests
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alexmadison b21b84e78d added some watches
2022-07-06 15:46:41 +02:00
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andtree_5
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andtree_15
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append_5_3_2
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arbiter
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arbiter_2
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arbiter_handshake_adv
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arbiter_handshake_simple
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arbiter_tree_simple_nosim
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arbiter_tree_test
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arbtree_5
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async_instantiate
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bd2qdi_5
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bd-fifo-register-fifo-bd
bd fifo register unit test working...
2022-04-05 10:02:37 +02:00
buf_15
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buf_s_5
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buffer_register_7
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buffer_token
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ctree_15
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decoder_2d_dly_8_16
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decoder_2d_dly_and_2_4
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decoder_2d_hs
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decoder_2d_hybrid
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delayprog_4
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demux_7
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demux_bit_7
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demux_td_2
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demux_td_2_SIGN
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dropper_static
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encoder1d_7
encoder1d passed unit tests
2022-04-11 19:49:22 +02:00
encoder1d_bd
encoder1d with bd simmed
2022-04-21 16:09:13 +02:00
encoder2D_2x2
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encoder2D_8x7
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encoder2D_8x8
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encoder_7
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fifo3_8bit
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fifo_demux_bit_7_fifo
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00
fifo_t_5
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fifo_t_15
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fifo-decoder_hs-neurons-encoder-fifo
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fifo-decoder_hybrid-neurons-encoder-fifo
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fifo-decoder-neurons-encoder-fifo
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fifo-register-fifo
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flipflop
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fork_15
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line_end_pull_up
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merge_t_2_adv
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merge_t_2_simple
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nrn_hs_2d
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00
nrn_hs_2D_array_3x5
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ortree_15
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qdi2bd_5
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register_write
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register_wrw
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registerA_w
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registerA_w_array
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registerA_wr_array
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sadc_encoder
removed inverted inputs from sadc encoder, regenned with proper reset sigs I hope
2022-07-01 17:26:55 +02:00
sadc_hs
added tests for dynapse sadc hs
2022-07-05 10:53:17 +02:00
sigbuf_15
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std_instantiate
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texel_dualcore
added reset sigs to neuron syn cores
2022-05-02 18:49:57 +02:00
texel_dualcore_glue
removed extra supply vss lines from tiehi/lows
2022-06-29 18:25:44 +02:00
texel_dualcore_glue_mapper
test merge of sram rw output working
2022-05-10 15:34:04 +02:00
texel_dualcore_glue_noread
added some watches
2022-07-06 15:46:41 +02:00
texel_dualcore_glue_slimreg
generated a tdc_glue with only 8 registers
2022-07-06 14:06:19 +02:00
texel_dualcore_glue_small
tdc glue small for testing
2022-06-23 17:54:10 +02:00
texel_dualcore_innovus
regenned texel dualcore innovus fairly finaly??
2022-05-02 19:45:34 +02:00
texel_encoder1d_bd_sadc
added sadc encoder with inputs low active for dynapse sadcs
2022-06-29 13:18:42 +02:00
texel_in30
added monitor decoders
2022-04-08 17:55:12 +02:00
texel_in30_noNrn
texel30 with manual neurons passing tests
2022-04-08 18:36:58 +02:00
texel_small
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00
vtree_5
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vtree_15
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.DS_Store
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buf_15_friendly2.v
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buf_15.v
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buff.v
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helper.scm
added set bd channel without setting r
2022-04-10 13:59:27 +02:00
init_qdi.prsim
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init.prs
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nrn_hs_2d_clean.v
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00
nrn_hs_2d.v
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00
texel_small_clean.v
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00
texel_small.net
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00
texel_small.v
Auto stash before merge of "dev" and "origin/dev"
2022-04-15 12:48:50 +02:00