Commit Graph

264 Commits

Author SHA1 Message Date
Michele ad318259a5 continued registers.c 2022-03-07 07:15:53 +01:00
Michele 932e967f3d encoder in register works 2022-03-05 20:33:38 +01:00
Michele aa67bd6168 register simulates correctly up to the fake clock generation 2022-03-05 20:28:50 +01:00
Michele 78a8f72d25 register compiles 2022-03-05 09:19:19 +01:00
Michele 7fe31f0ed8 started testing the register_w (doesn't compile) 2022-03-04 21:17:30 +01:00
Michele c30a46d6d8 I think the encoder2D compiles now 2022-03-04 21:11:34 +01:00
Michele b5fa707c4e forgot proc in defproc 2022-03-04 19:04:11 +01:00
Michele 72ec59cbcf added flip flop from XFAB 2022-03-04 19:02:34 +01:00
Michele 250f5bcc58 Added A_2C2P_RB_X1 because the encoder needs it 2022-03-04 19:02:12 +01:00
alexmadison 9b3bdc3f6c rejigged A cell in encoder2d 2022-03-04 15:09:49 +01:00
alexmadison a53110dda4 renamed encoder to dualrail_encoder 2022-03-04 14:53:14 +01:00
alexmadison 4a4c4eeb14 merged encoder 2022-03-04 14:27:38 +01:00
alexmadison f55322bc7c encoder init 2022-03-04 14:10:15 +01:00
Michele 18cf090b45 Merge remote-tracking branch 'origin/dev' into dev 2022-03-04 13:11:44 +01:00
Michele e8fa8e43a6 Changed FF in std. Started test (spoiler: is not working) 2022-03-04 13:11:34 +01:00
Greatorex 828fccfb38 Merge remote-tracking branch 'origin/dev' into dev 2022-03-04 12:34:00 +01:00
Greatorex 1abcc9dc55 Added stuff for line end pull U/D 2022-03-04 12:33:49 +01:00
Michele 9c6a591dc7 started registers 2022-03-04 11:44:00 +01:00
Michele b6c70f7f5e fixed vdd and vss in encoder sigbuf 2022-03-04 11:43:49 +01:00
Michele 397c832b7b Added Flip Flop to std.act (still need to try it) 2022-03-04 11:43:33 +01:00
Michele 15d3fd1b9b Added sigbuf_1output for signals that cannot have array outputs 2022-03-03 19:23:13 +01:00
Michele a4889ae844 fixed conflict with Madison commit 2022-03-03 17:54:29 +01:00
Michele d64afd8c50 Merge remote-tracking branch 'origin/dev' into dev 2022-03-03 17:53:40 +01:00
Michele ba096bf6b2 wired up most of the stuff in encoder (missing dual rail tree)
Obv not simulated yet and not sure all wires are correct. still need to repass through them
2022-03-03 17:52:42 +01:00
alexmadison c8412606b3 merged 2022-03-03 17:10:16 +01:00
alexmadison 893f71db92 AND grid init 2022-03-03 17:09:00 +01:00
alexmadison da5948f493 added N=1 cases 2022-03-03 17:05:56 +01:00
Michele 0e9f2ae506 started encoder on the coders.act 2022-03-03 15:10:31 +01:00
Michele f7cd7006d0 removed arbiter_tree from primitives because is already in coders 2022-03-03 12:15:17 +01:00
Michele 3e1b63c201 continued handshaking tree, not finished 2022-03-03 12:11:20 +01:00
Michele b49b9d98c3 started arbiter tree 2022-03-03 12:11:20 +01:00
alexmadison 6fc3e4b99c removed arbiter tree 2022-03-03 11:56:59 +01:00
alexmadison af52c688a3 arbiter tree with arbiters, not tested 2022-03-03 11:56:34 +01:00
alexmadison d0a2fff096 arbiter init with or2s 2022-03-03 10:52:29 +01:00
alexmadison 9c27248e12 decoder 2d dly init 2022-03-02 15:55:26 +01:00
alexmadison 3bba9fefa4 made buf with dly sorry 2022-03-02 15:48:54 +01:00
alexmadison 31d2f35042 i am a moron re dly cells 2022-03-02 15:47:36 +01:00
alexmadison c61a570f80 fixed wiring bug in prog delay 2022-03-02 15:11:22 +01:00
alexmadison 6bece2f459 renamed gates in or tree 2022-03-02 13:51:12 +01:00
alexmadison 659cd2479c oops accidentally hit all trees 2022-03-02 13:50:04 +01:00
alexmadison c5e582ff3e renamed vars in atree 2022-03-02 13:48:57 +01:00
alexmadison e52ec9ed61 renamed var in vtree for consciences 2022-03-02 11:51:45 +01:00
alexmadison c580d21efe fixed supply in fifo_t 2022-03-02 11:24:28 +01:00
alexmadison 1b7e39bc00 coders.act file init 2022-03-02 09:48:41 +01:00
alexmadison 8060051da0 Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-03-02 09:48:11 +01:00
alexmadison b456ea40fd changed delayprog to outin vs ya naming scheme 2022-03-02 09:48:05 +01:00
Michele 9f5bbc487d some more supplies added, need still to run all the codes 2022-03-01 19:02:10 +01:00
Michele c99ed439a6 added supply also to sigbuf in fifo 2022-03-01 18:57:06 +01:00
Michele d507deba84 Merge remote-tracking branch 'origin/dev' into dev 2022-03-01 18:51:10 +01:00
Michele 3d273b164d added power supply to sigbuf in fifo_t 2022-03-01 18:51:06 +01:00
Greatorex b15d8c11e9 Merge remote-tracking branch 'origin/dev' into dev 2022-03-01 17:56:39 +01:00
Greatorex ba5e695be5 finished and simmed demuxtd 2022-03-01 17:56:30 +01:00
Michele 357df7f66e merge tested with concurrent inputs work 2022-03-01 17:36:49 +01:00
Michele 018b308f61 Merge remote-tracking branch 'origin/dev' into dev 2022-03-01 17:14:15 +01:00
Michele 97784db492 merge with simple test is working 2022-03-01 17:14:10 +01:00
alexmadison 79a96ed511 added DLY4 cell 2022-03-01 15:28:22 +01:00
alexmadison 233c9a7d10 cleaned up minor 2022-03-01 15:27:27 +01:00
alexmadison 00869fc16e programmable delay tested 2022-03-01 15:26:43 +01:00
Michele 0a8496d4f7 Merge remote-tracking branch 'origin/dev' into dev 2022-03-01 13:26:32 +01:00
Michele 340a20e49e Added merge, syntax clean but violating dual rail 2022-03-01 13:26:29 +01:00
alexmadison fc4ccea3c0 added and tree 2022-03-01 12:22:36 +01:00
alexmadison c947b28b03 added yours truely to the authors 2022-03-01 10:18:32 +01:00
alexmadison aeed4e5527 changed c->v tree in buf_s 2022-03-01 10:15:23 +01:00
alexmadison a8b1710f65 merged buf_s into primitives 2022-03-01 10:09:08 +01:00
Michele 8b40e70058 differentiated between ctree and vtree, all primitives updated 2022-03-01 09:44:51 +01:00
Michele 92b0b36325 pushed merge in primitives.act 2022-02-28 18:58:32 +01:00
alexmadison 3fc4b1fb1a buf_s_tempalte init 2022-02-28 18:27:03 +01:00
Michele c96a154833 Merge remote-tracking branch 'origin/dev' into dev 2022-02-28 11:11:51 +01:00
Michele 2afec288a8 fifo_test_adv works 2022-02-28 11:11:30 +01:00
Greatorex 705adcfc87 started demuxtd 2022-02-28 09:46:26 +01:00
Michele b94715b6d9 buffer_t and fifo_t_15 work 2022-02-28 09:39:36 +01:00
M. Mastella c06912d446 Merge remote-tracking branch 'origin/dev' into dev 2022-02-25 19:16:44 +01:00
M. Mastella 72bccc295b started token buffer and token fifo. conmtinued arbiter tb 2022-02-25 19:16:40 +01:00
Greatorex e9f0f4ac0f Added Demux 2022-02-25 15:16:38 +01:00
Greatorex dbb7107da0 Demux Simmed, fixed treegates 2022-02-25 15:13:21 +01:00
Michele 8057bf54d3 Continued test arbiter_handshake, no results 2022-02-24 19:02:37 +01:00
Michele 0bdaa87cd2 changed mk_excllo from _y to y.
Weird behaviour of in2.r (it raises without reason)
2022-02-24 18:37:10 +01:00
Michele 4819635e35 continued arbitrer_handshake test (still doesn't work) 2022-02-24 16:47:24 +01:00
M. Mastella 739aadbc4d Merged with Hugh mux (mux doesn't compile 2022-02-23 19:02:56 +01:00
M. Mastella 6f53a76dbc Added arbiter_handshake 2022-02-23 19:01:54 +01:00
alexmadison be33d19762 renamed reset sigs in A_2C2N cells 2022-02-23 18:39:28 +01:00
alexmadison 1dcca99453 renamed RB cells2 2022-02-23 18:34:13 +01:00
alexmadison 9fb7aae0a4 renamed RB cells 2022-02-23 18:33:36 +01:00
Greatorex d98ddf37c5 Errors on demux fixed 2022-02-23 16:02:11 +01:00
Greatorex 10446c43c8 Finished demux again 2022-02-23 15:51:22 +01:00
Greatorex d545221e88 Merge remote-tracking branch 'origin/dev' into dev 2022-02-23 15:49:43 +01:00
Greatorex 5f74b285a4 Finished demux 2022-02-23 15:49:36 +01:00
M. Mastella 97b0be5af0 trying arbiter 2022-02-23 15:30:01 +01:00
M. Mastella f2a388fb09 Auto stash before merge of "dev" and "origin/dev" 2022-02-23 12:51:02 +01:00
M. Mastella 4bf13b4859 Merge remote-tracking branch 'origin/dev' into dev 2022-02-23 11:36:27 +01:00
M. Mastella 84cc93d2e1 Added merge empty func 2022-02-23 11:36:15 +01:00
Greatorex 04baa491eb Fixed buffer again in FORK 2022-02-23 11:35:16 +01:00
Greatorex 6dbc87c455 Merge remote-tracking branch 'origin/dev' into dev 2022-02-23 11:34:02 +01:00
Greatorex 39e863aa92 Fixed Buffer and Started MUX 2022-02-23 11:32:16 +01:00
M. Mastella 864460a68a Fork template done (basic simulation works) 2022-02-23 11:26:11 +01:00
M. Mastella 53d11963fb Async buffer test fully working 2022-02-22 18:04:21 +01:00
Greatorex 7e86815e28 attempting to complete the buffer 2022-02-22 13:52:54 +01:00
Greatorex 0772df30a5 we have liftoff - lisp code still needs fixing
ctree/ortree/sigbuf all tests working
2022-02-22 11:25:55 +01:00
Greatorex 90a429181e ctree test works, wrong folder name - is simmed in primitive_instantiate 2022-02-22 11:10:51 +01:00
Greatorex 6dd5df58a1 pushing in the meanwhile 2022-02-21 18:27:41 +01:00
Greatorex 0a5a271409 Trying to get ortree test working 2022-02-21 17:59:41 +01:00
alexmadison 296411da8c what 2022-02-21 17:53:23 +01:00
alexmadison ded1742b72 added some 3/4 cells and changed mux cells 2022-02-21 17:50:23 +01:00
Greatorex b076513813 Added Ortree maybe 2022-02-21 16:59:47 +01:00
M. Mastella df97903436 test celement tree is working 2022-02-21 16:44:08 +01:00
alexmadison 5928dc9f42 init rewriting tree gates 2022-02-21 15:54:10 +01:00
alexmadison 30ffd8b16f removed clock buffers 2022-02-21 15:53:40 +01:00
Greatorex 5fc6eaab9e Added std test 2022-02-21 13:07:14 +01:00
M. Mastella ca0e5df048 prepared things for having unit test ready 2022-02-21 13:01:45 +01:00
M. Mastella 6dc79383da Merge remote-tracking branch 'origin/dev' into dev 2022-02-21 10:44:40 +01:00
M. Mastella 38e21ac99e testing_facility for async works (we removed a namespace layer though) 2022-02-21 10:44:36 +01:00
Greatorex aa92b8bea4 Auto stash before merge of "dev" and "origin/dev" 2022-02-21 10:32:18 +01:00
M. Mastella f9361e7d66 cell_lib_async.act is now error-free 2022-02-21 10:28:19 +01:00
Ole Richter 48b691d7d4 added license, moved cell libs into repo
added buffer (not tested),
2022-02-21 00:33:58 +01:00