Michele
|
ad318259a5
|
continued registers.c
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2022-03-07 07:15:53 +01:00 |
|
Michele
|
932e967f3d
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encoder in register works
|
2022-03-05 20:33:38 +01:00 |
|
Michele
|
aa67bd6168
|
register simulates correctly up to the fake clock generation
|
2022-03-05 20:28:50 +01:00 |
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Michele
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78a8f72d25
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register compiles
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2022-03-05 09:19:19 +01:00 |
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Michele
|
7fe31f0ed8
|
started testing the register_w (doesn't compile)
|
2022-03-04 21:17:30 +01:00 |
|
Michele
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c30a46d6d8
|
I think the encoder2D compiles now
|
2022-03-04 21:11:34 +01:00 |
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Michele
|
b5fa707c4e
|
forgot proc in defproc
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2022-03-04 19:04:11 +01:00 |
|
Michele
|
72ec59cbcf
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added flip flop from XFAB
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2022-03-04 19:02:34 +01:00 |
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Michele
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250f5bcc58
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Added A_2C2P_RB_X1 because the encoder needs it
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2022-03-04 19:02:12 +01:00 |
alexmadison
|
9b3bdc3f6c
|
rejigged A cell in encoder2d
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2022-03-04 15:09:49 +01:00 |
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alexmadison
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a53110dda4
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renamed encoder to dualrail_encoder
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2022-03-04 14:53:14 +01:00 |
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alexmadison
|
4a4c4eeb14
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merged encoder
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2022-03-04 14:27:38 +01:00 |
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alexmadison
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f55322bc7c
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encoder init
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2022-03-04 14:10:15 +01:00 |
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Michele
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18cf090b45
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-04 13:11:44 +01:00 |
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Michele
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e8fa8e43a6
|
Changed FF in std. Started test (spoiler: is not working)
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2022-03-04 13:11:34 +01:00 |
 Greatorex
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828fccfb38
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-04 12:34:00 +01:00 |
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Greatorex
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1abcc9dc55
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Added stuff for line end pull U/D
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2022-03-04 12:33:49 +01:00 |
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Michele
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9c6a591dc7
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started registers
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2022-03-04 11:44:00 +01:00 |
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Michele
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b6c70f7f5e
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fixed vdd and vss in encoder sigbuf
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2022-03-04 11:43:49 +01:00 |
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Michele
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397c832b7b
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Added Flip Flop to std.act (still need to try it)
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2022-03-04 11:43:33 +01:00 |
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Michele
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15d3fd1b9b
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Added sigbuf_1output for signals that cannot have array outputs
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2022-03-03 19:23:13 +01:00 |
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Michele
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a4889ae844
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fixed conflict with Madison commit
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2022-03-03 17:54:29 +01:00 |
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Michele
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d64afd8c50
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-03 17:53:40 +01:00 |
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Michele
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ba096bf6b2
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wired up most of the stuff in encoder (missing dual rail tree)
Obv not simulated yet and not sure all wires are correct. still need to repass through them
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2022-03-03 17:52:42 +01:00 |
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alexmadison
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c8412606b3
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merged
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2022-03-03 17:10:16 +01:00 |
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alexmadison
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893f71db92
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AND grid init
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2022-03-03 17:09:00 +01:00 |
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alexmadison
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da5948f493
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added N=1 cases
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2022-03-03 17:05:56 +01:00 |
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Michele
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0e9f2ae506
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started encoder on the coders.act
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2022-03-03 15:10:31 +01:00 |
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Michele
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f7cd7006d0
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removed arbiter_tree from primitives because is already in coders
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2022-03-03 12:15:17 +01:00 |
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Michele
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3e1b63c201
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continued handshaking tree, not finished
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2022-03-03 12:11:20 +01:00 |
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Michele
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b49b9d98c3
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started arbiter tree
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2022-03-03 12:11:20 +01:00 |
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alexmadison
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6fc3e4b99c
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removed arbiter tree
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2022-03-03 11:56:59 +01:00 |
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alexmadison
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af52c688a3
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arbiter tree with arbiters, not tested
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2022-03-03 11:56:34 +01:00 |
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alexmadison
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d0a2fff096
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arbiter init with or2s
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2022-03-03 10:52:29 +01:00 |
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alexmadison
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9c27248e12
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decoder 2d dly init
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2022-03-02 15:55:26 +01:00 |
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alexmadison
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3bba9fefa4
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made buf with dly sorry
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2022-03-02 15:48:54 +01:00 |
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alexmadison
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31d2f35042
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i am a moron re dly cells
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2022-03-02 15:47:36 +01:00 |
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alexmadison
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c61a570f80
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fixed wiring bug in prog delay
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2022-03-02 15:11:22 +01:00 |
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alexmadison
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6bece2f459
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renamed gates in or tree
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2022-03-02 13:51:12 +01:00 |
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alexmadison
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659cd2479c
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oops accidentally hit all trees
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2022-03-02 13:50:04 +01:00 |
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alexmadison
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c5e582ff3e
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renamed vars in atree
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2022-03-02 13:48:57 +01:00 |
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alexmadison
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e52ec9ed61
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renamed var in vtree for consciences
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2022-03-02 11:51:45 +01:00 |
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alexmadison
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c580d21efe
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fixed supply in fifo_t
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2022-03-02 11:24:28 +01:00 |
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alexmadison
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1b7e39bc00
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coders.act file init
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2022-03-02 09:48:41 +01:00 |
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alexmadison
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8060051da0
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Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
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2022-03-02 09:48:11 +01:00 |
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alexmadison
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b456ea40fd
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changed delayprog to outin vs ya naming scheme
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2022-03-02 09:48:05 +01:00 |
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Michele
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9f5bbc487d
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some more supplies added, need still to run all the codes
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2022-03-01 19:02:10 +01:00 |
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Michele
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c99ed439a6
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added supply also to sigbuf in fifo
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2022-03-01 18:57:06 +01:00 |
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Michele
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d507deba84
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-01 18:51:10 +01:00 |
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Michele
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3d273b164d
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added power supply to sigbuf in fifo_t
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2022-03-01 18:51:06 +01:00 |
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Greatorex
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b15d8c11e9
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-01 17:56:39 +01:00 |
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Greatorex
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ba5e695be5
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finished and simmed demuxtd
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2022-03-01 17:56:30 +01:00 |
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Michele
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357df7f66e
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merge tested with concurrent inputs work
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2022-03-01 17:36:49 +01:00 |
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Michele
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018b308f61
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-01 17:14:15 +01:00 |
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Michele
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97784db492
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merge with simple test is working
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2022-03-01 17:14:10 +01:00 |
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alexmadison
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79a96ed511
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added DLY4 cell
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2022-03-01 15:28:22 +01:00 |
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alexmadison
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233c9a7d10
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cleaned up minor
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2022-03-01 15:27:27 +01:00 |
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alexmadison
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00869fc16e
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programmable delay tested
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2022-03-01 15:26:43 +01:00 |
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Michele
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0a8496d4f7
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Merge remote-tracking branch 'origin/dev' into dev
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2022-03-01 13:26:32 +01:00 |
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Michele
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340a20e49e
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Added merge, syntax clean but violating dual rail
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2022-03-01 13:26:29 +01:00 |
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alexmadison
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fc4ccea3c0
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added and tree
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2022-03-01 12:22:36 +01:00 |
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alexmadison
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c947b28b03
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added yours truely to the authors
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2022-03-01 10:18:32 +01:00 |
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alexmadison
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aeed4e5527
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changed c->v tree in buf_s
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2022-03-01 10:15:23 +01:00 |
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alexmadison
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a8b1710f65
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merged buf_s into primitives
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2022-03-01 10:09:08 +01:00 |
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Michele
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8b40e70058
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differentiated between ctree and vtree, all primitives updated
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2022-03-01 09:44:51 +01:00 |
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Michele
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92b0b36325
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pushed merge in primitives.act
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2022-02-28 18:58:32 +01:00 |
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alexmadison
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3fc4b1fb1a
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buf_s_tempalte init
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2022-02-28 18:27:03 +01:00 |
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Michele
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c96a154833
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Merge remote-tracking branch 'origin/dev' into dev
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2022-02-28 11:11:51 +01:00 |
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Michele
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2afec288a8
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fifo_test_adv works
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2022-02-28 11:11:30 +01:00 |
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Greatorex
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705adcfc87
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started demuxtd
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2022-02-28 09:46:26 +01:00 |
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Michele
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b94715b6d9
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buffer_t and fifo_t_15 work
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2022-02-28 09:39:36 +01:00 |
 M. Mastella
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c06912d446
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Merge remote-tracking branch 'origin/dev' into dev
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2022-02-25 19:16:44 +01:00 |
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M. Mastella
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72bccc295b
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started token buffer and token fifo. conmtinued arbiter tb
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2022-02-25 19:16:40 +01:00 |
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Greatorex
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e9f0f4ac0f
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Added Demux
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2022-02-25 15:16:38 +01:00 |
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Greatorex
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dbb7107da0
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Demux Simmed, fixed treegates
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2022-02-25 15:13:21 +01:00 |
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Michele
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8057bf54d3
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Continued test arbiter_handshake, no results
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2022-02-24 19:02:37 +01:00 |
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Michele
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0bdaa87cd2
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changed mk_excllo from _y to y.
Weird behaviour of in2.r (it raises without reason)
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2022-02-24 18:37:10 +01:00 |
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Michele
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4819635e35
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continued arbitrer_handshake test (still doesn't work)
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2022-02-24 16:47:24 +01:00 |
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M. Mastella
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739aadbc4d
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Merged with Hugh mux (mux doesn't compile
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2022-02-23 19:02:56 +01:00 |
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M. Mastella
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6f53a76dbc
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Added arbiter_handshake
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2022-02-23 19:01:54 +01:00 |
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alexmadison
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be33d19762
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renamed reset sigs in A_2C2N cells
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2022-02-23 18:39:28 +01:00 |
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alexmadison
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1dcca99453
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renamed RB cells2
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2022-02-23 18:34:13 +01:00 |
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alexmadison
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9fb7aae0a4
|
renamed RB cells
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2022-02-23 18:33:36 +01:00 |
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Greatorex
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d98ddf37c5
|
Errors on demux fixed
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2022-02-23 16:02:11 +01:00 |
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Greatorex
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10446c43c8
|
Finished demux again
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2022-02-23 15:51:22 +01:00 |
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Greatorex
|
d545221e88
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Merge remote-tracking branch 'origin/dev' into dev
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2022-02-23 15:49:43 +01:00 |
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Greatorex
|
5f74b285a4
|
Finished demux
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2022-02-23 15:49:36 +01:00 |
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M. Mastella
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97b0be5af0
|
trying arbiter
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2022-02-23 15:30:01 +01:00 |
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M. Mastella
|
f2a388fb09
|
Auto stash before merge of "dev" and "origin/dev"
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2022-02-23 12:51:02 +01:00 |
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M. Mastella
|
4bf13b4859
|
Merge remote-tracking branch 'origin/dev' into dev
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2022-02-23 11:36:27 +01:00 |
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M. Mastella
|
84cc93d2e1
|
Added merge empty func
|
2022-02-23 11:36:15 +01:00 |
|
Greatorex
|
04baa491eb
|
Fixed buffer again in FORK
|
2022-02-23 11:35:16 +01:00 |
|
Greatorex
|
6dbc87c455
|
Merge remote-tracking branch 'origin/dev' into dev
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2022-02-23 11:34:02 +01:00 |
|
Greatorex
|
39e863aa92
|
Fixed Buffer and Started MUX
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2022-02-23 11:32:16 +01:00 |
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M. Mastella
|
864460a68a
|
Fork template done (basic simulation works)
|
2022-02-23 11:26:11 +01:00 |
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M. Mastella
|
53d11963fb
|
Async buffer test fully working
|
2022-02-22 18:04:21 +01:00 |
|
Greatorex
|
7e86815e28
|
attempting to complete the buffer
|
2022-02-22 13:52:54 +01:00 |
|
Greatorex
|
0772df30a5
|
we have liftoff - lisp code still needs fixing
ctree/ortree/sigbuf all tests working
|
2022-02-22 11:25:55 +01:00 |
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Greatorex
|
90a429181e
|
ctree test works, wrong folder name - is simmed in primitive_instantiate
|
2022-02-22 11:10:51 +01:00 |
|
Greatorex
|
6dd5df58a1
|
pushing in the meanwhile
|
2022-02-21 18:27:41 +01:00 |
|
Greatorex
|
0a5a271409
|
Trying to get ortree test working
|
2022-02-21 17:59:41 +01:00 |
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alexmadison
|
296411da8c
|
what
|
2022-02-21 17:53:23 +01:00 |
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alexmadison
|
ded1742b72
|
added some 3/4 cells and changed mux cells
|
2022-02-21 17:50:23 +01:00 |
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Greatorex
|
b076513813
|
Added Ortree maybe
|
2022-02-21 16:59:47 +01:00 |
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M. Mastella
|
df97903436
|
test celement tree is working
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2022-02-21 16:44:08 +01:00 |
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alexmadison
|
5928dc9f42
|
init rewriting tree gates
|
2022-02-21 15:54:10 +01:00 |
|
alexmadison
|
30ffd8b16f
|
removed clock buffers
|
2022-02-21 15:53:40 +01:00 |
|
Greatorex
|
5fc6eaab9e
|
Added std test
|
2022-02-21 13:07:14 +01:00 |
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M. Mastella
|
ca0e5df048
|
prepared things for having unit test ready
|
2022-02-21 13:01:45 +01:00 |
|
M. Mastella
|
6dc79383da
|
Merge remote-tracking branch 'origin/dev' into dev
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2022-02-21 10:44:40 +01:00 |
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M. Mastella
|
38e21ac99e
|
testing_facility for async works (we removed a namespace layer though)
|
2022-02-21 10:44:36 +01:00 |
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Greatorex
|
aa92b8bea4
|
Auto stash before merge of "dev" and "origin/dev"
|
2022-02-21 10:32:18 +01:00 |
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M. Mastella
|
f9361e7d66
|
cell_lib_async.act is now error-free
|
2022-02-21 10:28:19 +01:00 |
 Ole Richter
|
48b691d7d4
|
added license, moved cell libs into repo
added buffer (not tested),
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2022-02-21 00:33:58 +01:00 |