Commit Graph

420 Commits

Author SHA1 Message Date
alexmadison 6eb6766bef texel small prs 2022-04-10 15:17:38 +02:00
alexmadison feb28f27bf added set bd channel without setting r 2022-04-10 13:59:27 +02:00
alexmadison 5aab3d2d3b added ands on synapse x mon decoder, on DEV_DEBUG 2022-04-09 14:17:22 +02:00
alexmadison 93aeda77d3 remvoed buffering from decoder dr 2022-04-09 14:10:06 +02:00
alexmadison c81e77a2fa texel30 with manual neurons passing tests 2022-04-08 18:36:58 +02:00
alexmadison cc2487be1c added monitor decoders 2022-04-08 17:55:12 +02:00
alexmadison 1d87a86ba6 texel 30 unit tests working 2022-04-08 14:54:00 +02:00
alexmadison e27d55bff4 fixed stupid typo in d_dr_en 2022-04-08 14:02:55 +02:00
alexmadison fa2b6f6850 added dualrail decoder with enable 2022-04-08 14:01:41 +02:00
alexmadison 7ebd734eee renamed chip nomap to texel_small 2022-04-08 12:14:50 +02:00
alexmadison ec091708a8 changed cells to lowercase 2022-04-08 12:13:43 +02:00
alexmadison 66fdedfb28 gutted KEEPs, readded to coders 2022-04-08 11:53:49 +02:00
alexmadison 74c5b8703f added second delaycfg to bd2qdi 2022-04-05 19:17:54 +02:00
alexmadison 41d76de718 chip unit tests passing baybeeeeee 2022-04-05 18:21:36 +02:00
alexmadison 3697d21698 flipped condition bit on demux 2022-04-05 17:16:10 +02:00
alexmadison 94b4ad2570 fixed hazard caused by buffer delay in bd2qdi 2022-04-05 10:54:25 +02:00
alexmadison fce3eac4e6 bd fifo register unit test working... 2022-04-05 10:02:37 +02:00
alexmadison 531ccf30c2 first tests passed 2022-04-04 20:23:56 +02:00
alexmadison ab52498755 reset working 2022-04-04 19:32:30 +02:00
alexmadison c31248ef34 fixed bug in append and demux 2022-04-04 19:14:35 +02:00
alexmadison daa5e9ca22 adjusted demux msb 2022-04-04 17:51:49 +02:00
alexmadison 5fbd435ca2 XMerge branch 'madison_chip_dev' into dev 2022-04-04 17:49:45 +02:00
alexmadison c462be605d chip wip 2022-04-04 17:48:20 +02:00
Greatorex 0ade5522a2 merge of prims 2022-04-04 17:46:51 +02:00
alexmadison a229dd00cf before the git gets fucked 2022-04-04 17:35:34 +02:00
Greatorex 8f67c42bdb Merge branch 'main' into dev 2022-04-04 17:30:02 +02:00
Greatorex 185a4b2d77 Merge remote-tracking branch 'origin/main' into main 2022-04-04 17:27:34 +02:00
Greatorex a424b496e5 added more demuxs 2022-04-04 17:27:19 +02:00
alexmadison ea3f91d6de chips init 2022-04-04 17:14:08 +02:00
alexmadison 560ae9c5f0 added data slice primitive 2022-04-04 17:13:49 +02:00
Greatorex 31b3853558 added more demuxs 2022-04-04 17:10:05 +02:00
alexmadison 55ed8bb839 added buffered dr decoder 2022-04-04 15:37:31 +02:00
alexmadison 5e4a8ee15c dropper static with unit tests 2022-04-04 15:13:39 +02:00
alexmadison afe332e8ba fifo reg fifo unit test working 2022-04-04 09:49:51 +02:00
alexmadison fa5f83f061 register rw passed initial tests 2022-04-02 18:31:45 +02:00
alexmadison be3cc7a2d7 register rw compiling: 2022-04-02 18:09:09 +02:00
alexmadison b59a57c324 changed write bit selectors from ands to Cels, to avoid selector hazards 2022-04-02 17:37:56 +02:00
alexmadison eda9e2a98b register write array unit tests working 2022-04-02 17:16:20 +02:00
alexmadison e995a78efb dunno what i changed buti it was probably good 2022-04-01 20:54:27 +02:00
alexmadison 87010c256b buffer register unit tests init 2022-04-01 20:47:04 +02:00
alexmadison 0a957fc130 registerA_w unit test working 2022-04-01 20:46:45 +02:00
alexmadison b162cff991 added a comment to mux2 2022-04-01 20:46:03 +02:00
alexmadison 732526f0e3 added cells needed for register 2022-04-01 20:45:37 +02:00
alexmadison a7fc0d2cba write register array compiling 2022-04-01 20:45:04 +02:00
alexmadison 596a6f9c9f register A cell init, compiling not tested 2022-04-01 18:10:49 +02:00
alexmadison ab248d608e init and unit tests for register buffer 2022-04-01 16:58:12 +02:00
alexmadison df1aae7690 added S cells for register 2022-04-01 16:57:44 +02:00
alexmadison 82537e07de added pullup down as wrappers on teh A cells 2022-03-31 18:10:08 +02:00
alexmadison e05196bb7e hybrid decoder in fifo train working 2022-03-31 18:06:47 +02:00
alexmadison c840273ae6 decoder 2d hybrid unit tests working 2022-03-31 18:00:08 +02:00