 Greatorex
|
409fee54e8
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-08 18:49:07 +01:00 |
|
Greatorex
|
9a9c2f7da5
|
encoder sim still not working
|
2022-03-08 18:49:04 +01:00 |
 M. Mastella
|
422a90ad71
|
demux: cond.a has been now shorted to in.a
|
2022-03-08 12:12:45 +01:00 |
alexmadison
|
a78eec5777
|
demux_td reviewed and supplies added
|
2022-03-08 10:11:52 +01:00 |
|
M. Mastella
|
0d3502bf00
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-07 16:36:05 +01:00 |
|
M. Mastella
|
e49866323c
|
register_write works
|
2022-03-07 16:36:01 +01:00 |
|
alexmadison
|
c3f0059bfa
|
encoder2d compiling
|
2022-03-07 16:22:00 +01:00 |
|
alexmadison
|
a411231628
|
added some supplies
|
2022-03-07 16:21:45 +01:00 |
Michele
|
ad318259a5
|
continued registers.c
|
2022-03-07 07:15:53 +01:00 |
|
Michele
|
932e967f3d
|
encoder in register works
|
2022-03-05 20:33:38 +01:00 |
|
Michele
|
aa67bd6168
|
register simulates correctly up to the fake clock generation
|
2022-03-05 20:28:50 +01:00 |
|
Michele
|
78a8f72d25
|
register compiles
|
2022-03-05 09:19:19 +01:00 |
|
Michele
|
7fe31f0ed8
|
started testing the register_w (doesn't compile)
|
2022-03-04 21:17:30 +01:00 |
|
Michele
|
c30a46d6d8
|
I think the encoder2D compiles now
|
2022-03-04 21:11:34 +01:00 |
|
Michele
|
b5fa707c4e
|
forgot proc in defproc
|
2022-03-04 19:04:11 +01:00 |
|
Michele
|
72ec59cbcf
|
added flip flop from XFAB
|
2022-03-04 19:02:34 +01:00 |
|
Michele
|
250f5bcc58
|
Added A_2C2P_RB_X1 because the encoder needs it
|
2022-03-04 19:02:12 +01:00 |
|
alexmadison
|
9b3bdc3f6c
|
rejigged A cell in encoder2d
|
2022-03-04 15:09:49 +01:00 |
|
alexmadison
|
a53110dda4
|
renamed encoder to dualrail_encoder
|
2022-03-04 14:53:14 +01:00 |
|
alexmadison
|
4a4c4eeb14
|
merged encoder
|
2022-03-04 14:27:38 +01:00 |
|
alexmadison
|
f55322bc7c
|
encoder init
|
2022-03-04 14:10:15 +01:00 |
|
Michele
|
18cf090b45
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-04 13:11:44 +01:00 |
|
Michele
|
e8fa8e43a6
|
Changed FF in std. Started test (spoiler: is not working)
|
2022-03-04 13:11:34 +01:00 |
|
Greatorex
|
828fccfb38
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-04 12:34:00 +01:00 |
|
Greatorex
|
1abcc9dc55
|
Added stuff for line end pull U/D
|
2022-03-04 12:33:49 +01:00 |
|
Michele
|
9c6a591dc7
|
started registers
|
2022-03-04 11:44:00 +01:00 |
|
Michele
|
b6c70f7f5e
|
fixed vdd and vss in encoder sigbuf
|
2022-03-04 11:43:49 +01:00 |
|
Michele
|
397c832b7b
|
Added Flip Flop to std.act (still need to try it)
|
2022-03-04 11:43:33 +01:00 |
|
Michele
|
15d3fd1b9b
|
Added sigbuf_1output for signals that cannot have array outputs
|
2022-03-03 19:23:13 +01:00 |
|
Michele
|
a4889ae844
|
fixed conflict with Madison commit
|
2022-03-03 17:54:29 +01:00 |
|
Michele
|
d64afd8c50
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-03 17:53:40 +01:00 |
|
Michele
|
ba096bf6b2
|
wired up most of the stuff in encoder (missing dual rail tree)
Obv not simulated yet and not sure all wires are correct. still need to repass through them
|
2022-03-03 17:52:42 +01:00 |
|
alexmadison
|
c8412606b3
|
merged
|
2022-03-03 17:10:16 +01:00 |
|
alexmadison
|
893f71db92
|
AND grid init
|
2022-03-03 17:09:00 +01:00 |
|
alexmadison
|
da5948f493
|
added N=1 cases
|
2022-03-03 17:05:56 +01:00 |
|
Michele
|
0e9f2ae506
|
started encoder on the coders.act
|
2022-03-03 15:10:31 +01:00 |
|
Michele
|
f7cd7006d0
|
removed arbiter_tree from primitives because is already in coders
|
2022-03-03 12:15:17 +01:00 |
|
Michele
|
3e1b63c201
|
continued handshaking tree, not finished
|
2022-03-03 12:11:20 +01:00 |
|
Michele
|
b49b9d98c3
|
started arbiter tree
|
2022-03-03 12:11:20 +01:00 |
|
alexmadison
|
6fc3e4b99c
|
removed arbiter tree
|
2022-03-03 11:56:59 +01:00 |
|
alexmadison
|
af52c688a3
|
arbiter tree with arbiters, not tested
|
2022-03-03 11:56:34 +01:00 |
|
alexmadison
|
d0a2fff096
|
arbiter init with or2s
|
2022-03-03 10:52:29 +01:00 |
|
alexmadison
|
9c27248e12
|
decoder 2d dly init
|
2022-03-02 15:55:26 +01:00 |
|
alexmadison
|
3bba9fefa4
|
made buf with dly sorry
|
2022-03-02 15:48:54 +01:00 |
|
alexmadison
|
31d2f35042
|
i am a moron re dly cells
|
2022-03-02 15:47:36 +01:00 |
|
alexmadison
|
c61a570f80
|
fixed wiring bug in prog delay
|
2022-03-02 15:11:22 +01:00 |
|
alexmadison
|
6bece2f459
|
renamed gates in or tree
|
2022-03-02 13:51:12 +01:00 |
|
alexmadison
|
659cd2479c
|
oops accidentally hit all trees
|
2022-03-02 13:50:04 +01:00 |
|
alexmadison
|
c5e582ff3e
|
renamed vars in atree
|
2022-03-02 13:48:57 +01:00 |
|
alexmadison
|
e52ec9ed61
|
renamed var in vtree for consciences
|
2022-03-02 11:51:45 +01:00 |