alexmadison
|
ff077c5169
|
regenned with cores having new names
|
2022-07-06 18:25:23 +02:00 |
|
alexmadison
|
1cd1b1d054
|
wiping split modules
|
2022-07-06 18:24:32 +02:00 |
|
alexmadison
|
72dab29f5c
|
regennmed tdc no read to have the same number of reg bits as normal tdcg
|
2022-07-06 17:43:21 +02:00 |
|
alexmadison
|
502d35b000
|
added slice before registers, so register sizes can be reduced
|
2022-07-06 17:26:26 +02:00 |
|
alexmadison
|
27a0d34153
|
genned texel dualcore glue noread netlist clean
|
2022-07-06 16:04:34 +02:00 |
|
alexmadison
|
b21b84e78d
|
added some watches
|
2022-07-06 15:46:41 +02:00 |
|
alexmadison
|
194a7ad196
|
created version of tdc_g without register read functionality
|
2022-07-06 15:35:20 +02:00 |
|
alexmadison
|
2ddbeac978
|
generated a tdc_glue with only 8 registers
|
2022-07-06 14:06:19 +02:00 |
|
alexmadison
|
7896e0de24
|
added tests for dynapse sadc hs
|
2022-07-05 10:53:17 +02:00 |
|
alexmadison
|
8753540b33
|
removed inverted inputs from sadc encoder, regenned with proper reset sigs I hope
|
2022-07-01 17:26:55 +02:00 |
|
alexmadison
|
a70c9a1b6d
|
removed extra supply vss lines from tiehi/lows
|
2022-06-29 18:25:44 +02:00 |
|
alexmadison
|
9a7a34c02f
|
please god let this be the last regen of the act. Tiehi/lo's have been given fake PRs
|
2022-06-29 16:24:00 +02:00 |
|
alexmadison
|
f488e5dc81
|
renamed to sadc_encoder
|
2022-06-29 13:36:14 +02:00 |
|
alexmadison
|
836e19a72d
|
added sadc encoder with inputs low active for dynapse sadcs
|
2022-06-29 13:18:42 +02:00 |
|
alexmadison
|
ba7ae68651
|
lmao forgot to remove top.vdd/vss
|
2022-06-28 18:20:57 +02:00 |
|
alexmadison
|
cd978118b5
|
dindo nuffin
|
2022-06-28 18:04:40 +02:00 |
|
alexmadison
|
1a7c6121a0
|
don't think i regenned netlist.v but just to be safe lol
|
2022-06-28 14:46:43 +02:00 |
|
alexmadison
|
df3bb4022c
|
regenned netlist with sigbufs fixed lol
|
2022-06-27 15:57:02 +02:00 |
|
alexmadison
|
79c3d9ed98
|
tdc glue small for testing
|
2022-06-23 17:54:10 +02:00 |
|
alexmadison
|
6b0eff672c
|
removed split modules folder from git
|
2022-06-23 17:51:50 +02:00 |
|
alexmadison
|
4e01e252b8
|
final final generation of tdc_glue i swear
|
2022-06-23 17:51:16 +02:00 |
|
alexmadison
|
c972419199
|
regenned with delays in encoder
|
2022-06-21 14:00:04 +02:00 |
|
alexmadison
|
17d9d3da41
|
regenned without pulldown delays
|
2022-06-20 16:10:35 +02:00 |
|
alexmadison
|
6a7da77a92
|
removed line pulldown delays oops
|
2022-06-20 15:43:22 +02:00 |
|
alexmadison
|
ce4e6dc23c
|
regenned modules with synapses and neurons removed from top level
|
2022-06-17 12:29:45 +02:00 |
|
alexmadison
|
21d6982763
|
removed synapses and neurons from top level outputs:
|
2022-06-17 12:10:25 +02:00 |
|
alexmadison
|
c790e73e69
|
regenned without name change stuff
|
2022-06-17 11:56:01 +02:00 |
|
alexmadison
|
bfffdb7e97
|
deleted heretical files
|
2022-06-16 18:45:35 +02:00 |
|
alexmadison
|
2cd1a4b91a
|
genned
|
2022-06-16 18:06:06 +02:00 |
|
alexmadison
|
3d0e36fbfb
|
genned verilog netlist
|
2022-06-16 17:48:13 +02:00 |
|
alexmadison
|
0cdc01c279
|
regenned texel dualcore glue with new registers and neuron req keep fix
|
2022-06-16 17:40:33 +02:00 |
|
alexmadison
|
2ea83f3472
|
test merge of sram rw output working
|
2022-05-10 15:34:04 +02:00 |
|
alexmadison
|
016f634ac6
|
test of spike from sram workin
|
2022-05-10 15:22:19 +02:00 |
|
alexmadison
|
9ee41dc390
|
spikes out to sram working
|
2022-05-10 14:53:26 +02:00 |
|
alexmadison
|
4c208bc18a
|
packets to sram rw working
|
2022-05-10 14:07:51 +02:00 |
|
alexmadison
|
03851e19b7
|
mapper test init
|
2022-05-09 18:04:49 +02:00 |
|
alexmadison
|
0d7b82a0dd
|
altered amzo targettting tests to avoid instabilities
|
2022-05-09 16:48:58 +02:00 |
|
alexmadison
|
b1e24fa93c
|
added more monitoring tests
|
2022-05-08 19:05:52 +02:00 |
|
alexmadison
|
6ed0c4bfed
|
beefed up prsim to include AMZIOs
|
2022-05-08 17:03:02 +02:00 |
|
alexmadison
|
04a7a108d5
|
added reset signals in and out
|
2022-05-06 14:17:15 +02:00 |
|
alexmadison
|
71a2192427
|
texel dualcore with glue passed tests
|
2022-05-05 14:57:38 +02:00 |
|
alexmadison
|
10f4821eaa
|
regenned texel dualcore innovus fairly finaly??
|
2022-05-02 19:45:34 +02:00 |
|
alexmadison
|
de06893549
|
added reset sigs to neuron syn cores
|
2022-05-02 18:49:57 +02:00 |
|
alexmadison
|
f70b453ba7
|
Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
|
2022-05-02 15:27:38 +02:00 |
|
alexmadison
|
cd445d1736
|
added inverters on every 4th synapse targetting line
|
2022-05-02 15:26:03 +02:00 |
 Greatorex
|
64828422a0
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-05-02 15:12:42 +02:00 |
|
Greatorex
|
8d7933bf9c
|
wrapped tex_dual_inov
|
2022-05-02 15:12:21 +02:00 |
|
alexmadison
|
a114505a0b
|
fixed size of syn x channel
|
2022-04-25 13:15:53 +02:00 |
|
alexmadison
|
28823c4bca
|
regened texel dualcore prs
|
2022-04-25 10:32:47 +02:00 |
|
alexmadison
|
e6f1a31f68
|
encoder1d with bd simmed
|
2022-04-21 16:09:13 +02:00 |