 Greatorex
|
a424b496e5
|
added more demuxs
|
2022-04-04 17:27:19 +02:00 |
alexmadison
|
ea3f91d6de
|
chips init
|
2022-04-04 17:14:08 +02:00 |
|
alexmadison
|
560ae9c5f0
|
added data slice primitive
|
2022-04-04 17:13:49 +02:00 |
|
Greatorex
|
31b3853558
|
added more demuxs
|
2022-04-04 17:10:05 +02:00 |
|
alexmadison
|
55ed8bb839
|
added buffered dr decoder
|
2022-04-04 15:37:31 +02:00 |
|
alexmadison
|
5e4a8ee15c
|
dropper static with unit tests
|
2022-04-04 15:13:39 +02:00 |
|
alexmadison
|
fa5f83f061
|
register rw passed initial tests
|
2022-04-02 18:31:45 +02:00 |
|
alexmadison
|
be3cc7a2d7
|
register rw compiling:
|
2022-04-02 18:09:09 +02:00 |
|
alexmadison
|
b59a57c324
|
changed write bit selectors from ands to Cels, to avoid selector hazards
|
2022-04-02 17:37:56 +02:00 |
|
alexmadison
|
eda9e2a98b
|
register write array unit tests working
|
2022-04-02 17:16:20 +02:00 |
|
alexmadison
|
b162cff991
|
added a comment to mux2
|
2022-04-01 20:46:03 +02:00 |
|
alexmadison
|
732526f0e3
|
added cells needed for register
|
2022-04-01 20:45:37 +02:00 |
|
alexmadison
|
a7fc0d2cba
|
write register array compiling
|
2022-04-01 20:45:04 +02:00 |
|
alexmadison
|
596a6f9c9f
|
register A cell init, compiling not tested
|
2022-04-01 18:10:49 +02:00 |
|
alexmadison
|
ab248d608e
|
init and unit tests for register buffer
|
2022-04-01 16:58:12 +02:00 |
|
alexmadison
|
df1aae7690
|
added S cells for register
|
2022-04-01 16:57:44 +02:00 |
|
alexmadison
|
82537e07de
|
added pullup down as wrappers on teh A cells
|
2022-03-31 18:10:08 +02:00 |
|
alexmadison
|
c840273ae6
|
decoder 2d hybrid unit tests working
|
2022-03-31 18:00:08 +02:00 |
|
alexmadison
|
2c491a6e37
|
replaced Pullup/downs with A cell naming scheme
|
2022-03-31 16:44:09 +02:00 |
|
alexmadison
|
6751e2807c
|
comments
|
2022-03-31 16:23:01 +02:00 |
|
alexmadison
|
89b8dacd29
|
changed line pull downs to be isochronic as fuk
|
2022-03-31 16:19:20 +02:00 |
|
alexmadison
|
6ecee7f0c7
|
added comments
|
2022-03-31 15:24:51 +02:00 |
|
alexmadison
|
f1ae79cd5a
|
added buffering of dualrail decoder output lines to pull downs
|
2022-03-31 15:22:50 +02:00 |
|
alexmadison
|
6dfc941993
|
added Cel to buf out ack, so that ack can't be removed before the bufs output data is fully invalidated
|
2022-03-31 15:10:47 +02:00 |
|
alexmadison
|
1d5d4738a2
|
cleaned up coders a bit
|
2022-03-31 13:20:18 +02:00 |
|
alexmadison
|
2e4cdd5029
|
vastly improved lazy synapse handshakes
|
2022-03-31 12:44:00 +02:00 |
|
alexmadison
|
cd5d41d7f8
|
synapse handshake unit tests working
|
2022-03-31 11:23:51 +02:00 |
|
alexmadison
|
e779ee55b9
|
added delays to out req-ack buffers, seems to work
|
2022-03-30 19:53:27 +02:00 |
|
alexmadison
|
a53bd58e29
|
added Ole dly4 as per hugh
|
2022-03-30 16:50:05 +02:00 |
|
alexmadison
|
21c78e4461
|
fixed bug in delay fifo
|
2022-03-30 15:47:01 +02:00 |
|
alexmadison
|
4cbe8cb3d1
|
XMerge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
|
2022-03-30 15:16:19 +02:00 |
|
alexmadison
|
f9cdb2e914
|
added pulldown2
|
2022-03-30 15:16:15 +02:00 |
|
Greatorex
|
e09b4a0f7e
|
Merge branch 'dev' into HEAD
|
2022-03-30 15:09:59 +02:00 |
|
Greatorex
|
7db428b827
|
register added again
|
2022-03-30 15:04:35 +02:00 |
|
Greatorex
|
ba17fc0d1b
|
Auto stash before rebase of "origin/dev"
|
2022-03-30 15:03:55 +02:00 |
|
alexmadison
|
87f552b1d0
|
decoder hs wip
|
2022-03-30 14:06:14 +02:00 |
|
alexmadison
|
cff6eba344
|
decoder_2d_hs init
|
2022-03-30 13:18:07 +02:00 |
|
alexmadison
|
d10d78347c
|
refactored decoder into decoder dualrail
|
2022-03-30 11:01:21 +02:00 |
|
alexmadison
|
1707f1043a
|
renamed encoder inputs from x to inx
|
2022-03-30 10:14:29 +02:00 |
|
alexmadison
|
870da14ccd
|
let delay fifos have N= 0, simplified nrn grids thusly
|
2022-03-29 19:07:04 +02:00 |
|
alexmadison
|
5e4e905960
|
fixed minor bug in encoder, renamed nrn_hs
|
2022-03-29 15:42:54 +02:00 |
|
alexmadison
|
921145c450
|
added buffering on out
|
2022-03-29 14:57:20 +02:00 |
|
alexmadison
|
28ea85b9ed
|
reverted nrn handshake to 2c1n
|
2022-03-29 11:24:42 +02:00 |
|
alexmadison
|
8528ee12cd
|
added cells needed for neuron grid
|
2022-03-28 19:51:50 +02:00 |
|
alexmadison
|
d395778a4a
|
neuron 2d handshake fixes
|
2022-03-28 19:51:03 +02:00 |
|
alexmadison
|
fb127d55f5
|
neuron handshake compiling, now testing
|
2022-03-28 16:23:12 +02:00 |
|
alexmadison
|
8cb6eddd37
|
removed line pull up downs, moved to coders
|
2022-03-28 16:22:51 +02:00 |
|
alexmadison
|
8b44a11fd6
|
added append, fixed bug in fifo
|
2022-03-25 18:57:18 +01:00 |
|
alexmadison
|
3587672e69
|
qdi2bd ready for rev
|
2022-03-25 17:15:03 +01:00 |
|
alexmadison
|
9d6e74268f
|
bd2qdi ole backseat reved
|
2022-03-25 15:43:46 +01:00 |
|
alexmadison
|
a42254a57b
|
minor bug fix encoder2d
|
2022-03-22 16:30:58 +01:00 |
|
Greatorex
|
29d43b0a20
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-18 10:06:55 +01:00 |
|
Greatorex
|
b9219f266f
|
Encoder Simmed
|
2022-03-18 10:06:43 +01:00 |
Michele
|
04d12338b7
|
continued register_rw
|
2022-03-15 08:16:59 +01:00 |
 M. Mastella
|
edb0443c01
|
Added new version of Register_rw (still not properly working)
|
2022-03-14 17:15:27 +01:00 |
|
Michele
|
cc2234a1b1
|
moved the ack of the register
|
2022-03-09 20:18:20 +01:00 |
|
Michele
|
4dcd975554
|
register_rw continued
|
2022-03-09 20:02:41 +01:00 |
|
Michele
|
6f1a970cfd
|
register_rw (formerly register_rw_v2) compiles
|
2022-03-09 16:44:44 +01:00 |
|
M. Mastella
|
d2f643dc26
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-09 13:05:14 +01:00 |
|
M. Mastella
|
c8ac3cf37d
|
started register_v2 with reading and writing abilities
|
2022-03-09 13:05:08 +01:00 |
|
Greatorex
|
409fee54e8
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-08 18:49:07 +01:00 |
|
Greatorex
|
9a9c2f7da5
|
encoder sim still not working
|
2022-03-08 18:49:04 +01:00 |
|
M. Mastella
|
422a90ad71
|
demux: cond.a has been now shorted to in.a
|
2022-03-08 12:12:45 +01:00 |
|
alexmadison
|
a78eec5777
|
demux_td reviewed and supplies added
|
2022-03-08 10:11:52 +01:00 |
|
M. Mastella
|
0d3502bf00
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-07 16:36:05 +01:00 |
|
M. Mastella
|
e49866323c
|
register_write works
|
2022-03-07 16:36:01 +01:00 |
|
alexmadison
|
c3f0059bfa
|
encoder2d compiling
|
2022-03-07 16:22:00 +01:00 |
|
alexmadison
|
a411231628
|
added some supplies
|
2022-03-07 16:21:45 +01:00 |
|
Michele
|
ad318259a5
|
continued registers.c
|
2022-03-07 07:15:53 +01:00 |
|
Michele
|
932e967f3d
|
encoder in register works
|
2022-03-05 20:33:38 +01:00 |
|
Michele
|
aa67bd6168
|
register simulates correctly up to the fake clock generation
|
2022-03-05 20:28:50 +01:00 |
|
Michele
|
78a8f72d25
|
register compiles
|
2022-03-05 09:19:19 +01:00 |
|
Michele
|
7fe31f0ed8
|
started testing the register_w (doesn't compile)
|
2022-03-04 21:17:30 +01:00 |
|
Michele
|
c30a46d6d8
|
I think the encoder2D compiles now
|
2022-03-04 21:11:34 +01:00 |
|
Michele
|
b5fa707c4e
|
forgot proc in defproc
|
2022-03-04 19:04:11 +01:00 |
|
Michele
|
72ec59cbcf
|
added flip flop from XFAB
|
2022-03-04 19:02:34 +01:00 |
|
Michele
|
250f5bcc58
|
Added A_2C2P_RB_X1 because the encoder needs it
|
2022-03-04 19:02:12 +01:00 |
|
alexmadison
|
9b3bdc3f6c
|
rejigged A cell in encoder2d
|
2022-03-04 15:09:49 +01:00 |
|
alexmadison
|
a53110dda4
|
renamed encoder to dualrail_encoder
|
2022-03-04 14:53:14 +01:00 |
|
alexmadison
|
4a4c4eeb14
|
merged encoder
|
2022-03-04 14:27:38 +01:00 |
|
alexmadison
|
f55322bc7c
|
encoder init
|
2022-03-04 14:10:15 +01:00 |
|
Michele
|
18cf090b45
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-04 13:11:44 +01:00 |
|
Michele
|
e8fa8e43a6
|
Changed FF in std. Started test (spoiler: is not working)
|
2022-03-04 13:11:34 +01:00 |
|
Greatorex
|
828fccfb38
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-04 12:34:00 +01:00 |
|
Greatorex
|
1abcc9dc55
|
Added stuff for line end pull U/D
|
2022-03-04 12:33:49 +01:00 |
|
Michele
|
9c6a591dc7
|
started registers
|
2022-03-04 11:44:00 +01:00 |
|
Michele
|
b6c70f7f5e
|
fixed vdd and vss in encoder sigbuf
|
2022-03-04 11:43:49 +01:00 |
|
Michele
|
397c832b7b
|
Added Flip Flop to std.act (still need to try it)
|
2022-03-04 11:43:33 +01:00 |
|
Michele
|
15d3fd1b9b
|
Added sigbuf_1output for signals that cannot have array outputs
|
2022-03-03 19:23:13 +01:00 |
|
Michele
|
a4889ae844
|
fixed conflict with Madison commit
|
2022-03-03 17:54:29 +01:00 |
|
Michele
|
d64afd8c50
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-03 17:53:40 +01:00 |
|
Michele
|
ba096bf6b2
|
wired up most of the stuff in encoder (missing dual rail tree)
Obv not simulated yet and not sure all wires are correct. still need to repass through them
|
2022-03-03 17:52:42 +01:00 |
|
alexmadison
|
c8412606b3
|
merged
|
2022-03-03 17:10:16 +01:00 |
|
alexmadison
|
893f71db92
|
AND grid init
|
2022-03-03 17:09:00 +01:00 |
|
alexmadison
|
da5948f493
|
added N=1 cases
|
2022-03-03 17:05:56 +01:00 |
|
Michele
|
0e9f2ae506
|
started encoder on the coders.act
|
2022-03-03 15:10:31 +01:00 |
|
Michele
|
f7cd7006d0
|
removed arbiter_tree from primitives because is already in coders
|
2022-03-03 12:15:17 +01:00 |
|
Michele
|
3e1b63c201
|
continued handshaking tree, not finished
|
2022-03-03 12:11:20 +01:00 |
|
Michele
|
b49b9d98c3
|
started arbiter tree
|
2022-03-03 12:11:20 +01:00 |
|
alexmadison
|
6fc3e4b99c
|
removed arbiter tree
|
2022-03-03 11:56:59 +01:00 |
|
alexmadison
|
af52c688a3
|
arbiter tree with arbiters, not tested
|
2022-03-03 11:56:34 +01:00 |
|
alexmadison
|
d0a2fff096
|
arbiter init with or2s
|
2022-03-03 10:52:29 +01:00 |
|
alexmadison
|
9c27248e12
|
decoder 2d dly init
|
2022-03-02 15:55:26 +01:00 |
|
alexmadison
|
3bba9fefa4
|
made buf with dly sorry
|
2022-03-02 15:48:54 +01:00 |
|
alexmadison
|
31d2f35042
|
i am a moron re dly cells
|
2022-03-02 15:47:36 +01:00 |
|
alexmadison
|
c61a570f80
|
fixed wiring bug in prog delay
|
2022-03-02 15:11:22 +01:00 |
|
alexmadison
|
6bece2f459
|
renamed gates in or tree
|
2022-03-02 13:51:12 +01:00 |
|
alexmadison
|
659cd2479c
|
oops accidentally hit all trees
|
2022-03-02 13:50:04 +01:00 |
|
alexmadison
|
c5e582ff3e
|
renamed vars in atree
|
2022-03-02 13:48:57 +01:00 |
|
alexmadison
|
e52ec9ed61
|
renamed var in vtree for consciences
|
2022-03-02 11:51:45 +01:00 |
|
alexmadison
|
c580d21efe
|
fixed supply in fifo_t
|
2022-03-02 11:24:28 +01:00 |
|
alexmadison
|
1b7e39bc00
|
coders.act file init
|
2022-03-02 09:48:41 +01:00 |
|
alexmadison
|
8060051da0
|
Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
|
2022-03-02 09:48:11 +01:00 |
|
alexmadison
|
b456ea40fd
|
changed delayprog to outin vs ya naming scheme
|
2022-03-02 09:48:05 +01:00 |
|
Michele
|
9f5bbc487d
|
some more supplies added, need still to run all the codes
|
2022-03-01 19:02:10 +01:00 |
|
Michele
|
c99ed439a6
|
added supply also to sigbuf in fifo
|
2022-03-01 18:57:06 +01:00 |
|
Michele
|
d507deba84
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-01 18:51:10 +01:00 |
|
Michele
|
3d273b164d
|
added power supply to sigbuf in fifo_t
|
2022-03-01 18:51:06 +01:00 |
|
Greatorex
|
b15d8c11e9
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-01 17:56:39 +01:00 |
|
Greatorex
|
ba5e695be5
|
finished and simmed demuxtd
|
2022-03-01 17:56:30 +01:00 |
|
Michele
|
357df7f66e
|
merge tested with concurrent inputs work
|
2022-03-01 17:36:49 +01:00 |
|
Michele
|
018b308f61
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-01 17:14:15 +01:00 |
|
Michele
|
97784db492
|
merge with simple test is working
|
2022-03-01 17:14:10 +01:00 |
|
alexmadison
|
79a96ed511
|
added DLY4 cell
|
2022-03-01 15:28:22 +01:00 |
|
alexmadison
|
233c9a7d10
|
cleaned up minor
|
2022-03-01 15:27:27 +01:00 |
|
alexmadison
|
00869fc16e
|
programmable delay tested
|
2022-03-01 15:26:43 +01:00 |
|
Michele
|
0a8496d4f7
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-01 13:26:32 +01:00 |
|
Michele
|
340a20e49e
|
Added merge, syntax clean but violating dual rail
|
2022-03-01 13:26:29 +01:00 |
|
alexmadison
|
fc4ccea3c0
|
added and tree
|
2022-03-01 12:22:36 +01:00 |
|
alexmadison
|
c947b28b03
|
added yours truely to the authors
|
2022-03-01 10:18:32 +01:00 |
|
alexmadison
|
aeed4e5527
|
changed c->v tree in buf_s
|
2022-03-01 10:15:23 +01:00 |
|
alexmadison
|
a8b1710f65
|
merged buf_s into primitives
|
2022-03-01 10:09:08 +01:00 |
|
Michele
|
8b40e70058
|
differentiated between ctree and vtree, all primitives updated
|
2022-03-01 09:44:51 +01:00 |
|
Michele
|
92b0b36325
|
pushed merge in primitives.act
|
2022-02-28 18:58:32 +01:00 |
|
alexmadison
|
3fc4b1fb1a
|
buf_s_tempalte init
|
2022-02-28 18:27:03 +01:00 |
|
Michele
|
c96a154833
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-02-28 11:11:51 +01:00 |
|
Michele
|
2afec288a8
|
fifo_test_adv works
|
2022-02-28 11:11:30 +01:00 |
|
Greatorex
|
705adcfc87
|
started demuxtd
|
2022-02-28 09:46:26 +01:00 |
|
Michele
|
b94715b6d9
|
buffer_t and fifo_t_15 work
|
2022-02-28 09:39:36 +01:00 |
|
M. Mastella
|
c06912d446
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-02-25 19:16:44 +01:00 |
|
M. Mastella
|
72bccc295b
|
started token buffer and token fifo. conmtinued arbiter tb
|
2022-02-25 19:16:40 +01:00 |
|
Greatorex
|
e9f0f4ac0f
|
Added Demux
|
2022-02-25 15:16:38 +01:00 |
|
Greatorex
|
dbb7107da0
|
Demux Simmed, fixed treegates
|
2022-02-25 15:13:21 +01:00 |
|
Michele
|
8057bf54d3
|
Continued test arbiter_handshake, no results
|
2022-02-24 19:02:37 +01:00 |
|
Michele
|
0bdaa87cd2
|
changed mk_excllo from _y to y.
Weird behaviour of in2.r (it raises without reason)
|
2022-02-24 18:37:10 +01:00 |
|
Michele
|
4819635e35
|
continued arbitrer_handshake test (still doesn't work)
|
2022-02-24 16:47:24 +01:00 |
|
M. Mastella
|
739aadbc4d
|
Merged with Hugh mux (mux doesn't compile
|
2022-02-23 19:02:56 +01:00 |
|
M. Mastella
|
6f53a76dbc
|
Added arbiter_handshake
|
2022-02-23 19:01:54 +01:00 |
|
alexmadison
|
be33d19762
|
renamed reset sigs in A_2C2N cells
|
2022-02-23 18:39:28 +01:00 |
|
alexmadison
|
1dcca99453
|
renamed RB cells2
|
2022-02-23 18:34:13 +01:00 |