bics/actlib_dataflow_neuro
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Author SHA1 Message Date
alexmadison ab52498755 reset working 2022-04-04 19:32:30 +02:00
alexmadison c31248ef34 fixed bug in append and demux 2022-04-04 19:14:35 +02:00
alexmadison daa5e9ca22 adjusted demux msb 2022-04-04 17:51:49 +02:00
alexmadison 5fbd435ca2 XMerge branch 'madison_chip_dev' into dev 2022-04-04 17:49:45 +02:00
alexmadison c462be605d chip wip 2022-04-04 17:48:20 +02:00
alexmadison a229dd00cf before the git gets fucked 2022-04-04 17:35:34 +02:00
alexmadison ea3f91d6de chips init 2022-04-04 17:14:08 +02:00
alexmadison 560ae9c5f0 added data slice primitive 2022-04-04 17:13:49 +02:00
alexmadison 55ed8bb839 added buffered dr decoder 2022-04-04 15:37:31 +02:00
alexmadison 5e4a8ee15c dropper static with unit tests 2022-04-04 15:13:39 +02:00
alexmadison afe332e8ba fifo reg fifo unit test working 2022-04-04 09:49:51 +02:00
alexmadison fa5f83f061 register rw passed initial tests 2022-04-02 18:31:45 +02:00
alexmadison be3cc7a2d7 register rw compiling: 2022-04-02 18:09:09 +02:00
alexmadison b59a57c324 changed write bit selectors from ands to Cels, to avoid selector hazards 2022-04-02 17:37:56 +02:00
alexmadison eda9e2a98b register write array unit tests working 2022-04-02 17:16:20 +02:00
alexmadison e995a78efb dunno what i changed buti it was probably good 2022-04-01 20:54:27 +02:00
alexmadison 87010c256b buffer register unit tests init 2022-04-01 20:47:04 +02:00
alexmadison 0a957fc130 registerA_w unit test working 2022-04-01 20:46:45 +02:00
alexmadison b162cff991 added a comment to mux2 2022-04-01 20:46:03 +02:00
alexmadison 732526f0e3 added cells needed for register 2022-04-01 20:45:37 +02:00
alexmadison a7fc0d2cba write register array compiling 2022-04-01 20:45:04 +02:00
alexmadison 596a6f9c9f register A cell init, compiling not tested 2022-04-01 18:10:49 +02:00
alexmadison ab248d608e init and unit tests for register buffer 2022-04-01 16:58:12 +02:00
alexmadison df1aae7690 added S cells for register 2022-04-01 16:57:44 +02:00
alexmadison 82537e07de added pullup down as wrappers on teh A cells 2022-03-31 18:10:08 +02:00
alexmadison e05196bb7e hybrid decoder in fifo train working 2022-03-31 18:06:47 +02:00
alexmadison c840273ae6 decoder 2d hybrid unit tests working 2022-03-31 18:00:08 +02:00
alexmadison 2c491a6e37 replaced Pullup/downs with A cell naming scheme 2022-03-31 16:44:09 +02:00
alexmadison 6751e2807c comments 2022-03-31 16:23:01 +02:00
alexmadison 7b7cd4653e nrn_hs fifo etc unit test working 2022-03-31 16:20:23 +02:00
alexmadison 89b8dacd29 changed line pull downs to be isochronic as fuk 2022-03-31 16:19:20 +02:00
alexmadison 6ecee7f0c7 added comments 2022-03-31 15:24:51 +02:00
alexmadison f1ae79cd5a added buffering of dualrail decoder output lines to pull downs 2022-03-31 15:22:50 +02:00
alexmadison 6dfc941993 added Cel to buf out ack, so that ack can't be removed before the bufs output data is fully invalidated 2022-03-31 15:10:47 +02:00
alexmadison 1d5d4738a2 cleaned up coders a bit 2022-03-31 13:20:18 +02:00
alexmadison 2e4cdd5029 vastly improved lazy synapse handshakes 2022-03-31 12:44:00 +02:00
alexmadison cd5d41d7f8 synapse handshake unit tests working 2022-03-31 11:23:51 +02:00
alexmadison e779ee55b9 added delays to out req-ack buffers, seems to work 2022-03-30 19:53:27 +02:00
alexmadison a53bd58e29 added Ole dly4 as per hugh 2022-03-30 16:50:05 +02:00
alexmadison 21c78e4461 fixed bug in delay fifo 2022-03-30 15:47:01 +02:00
alexmadison 4cbe8cb3d1 XMerge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-03-30 15:16:19 +02:00
alexmadison f9cdb2e914 added pulldown2 2022-03-30 15:16:15 +02:00
alexmadison 87f552b1d0 decoder hs wip 2022-03-30 14:06:14 +02:00
alexmadison cff6eba344 decoder_2d_hs init 2022-03-30 13:18:07 +02:00
alexmadison d10d78347c refactored decoder into decoder dualrail 2022-03-30 11:01:21 +02:00
alexmadison 1707f1043a renamed encoder inputs from x to inx 2022-03-30 10:14:29 +02:00
alexmadison 870da14ccd let delay fifos have N= 0, simplified nrn grids thusly 2022-03-29 19:07:04 +02:00
alexmadison 8b60b23214 omg its working 2022-03-29 18:35:58 +02:00
alexmadison 5e4e905960 fixed minor bug in encoder, renamed nrn_hs 2022-03-29 15:42:54 +02:00
alexmadison 921145c450 added buffering on out 2022-03-29 14:57:20 +02:00
alexmadison 1a68a951e3 unit test for hs 2022-03-29 11:25:14 +02:00
alexmadison 28ea85b9ed reverted nrn handshake to 2c1n 2022-03-29 11:24:42 +02:00
alexmadison 8528ee12cd added cells needed for neuron grid 2022-03-28 19:51:50 +02:00
alexmadison d395778a4a neuron 2d handshake fixes 2022-03-28 19:51:03 +02:00
alexmadison fb127d55f5 neuron handshake compiling, now testing 2022-03-28 16:23:12 +02:00
alexmadison 8cb6eddd37 removed line pull up downs, moved to coders 2022-03-28 16:22:51 +02:00
alexmadison 746ee34107 append unit test with fifos 2022-03-25 18:57:35 +01:00
alexmadison 8b44a11fd6 added append, fixed bug in fifo 2022-03-25 18:57:18 +01:00
alexmadison 3587672e69 qdi2bd ready for rev 2022-03-25 17:15:03 +01:00
alexmadison 9d6e74268f bd2qdi ole backseat reved 2022-03-25 15:43:46 +01:00
alexmadison a42254a57b minor bug fix encoder2d 2022-03-22 16:30:58 +01:00
alexmadison 9ad12dc951 encoder2d revd mdsn 2022-03-22 16:29:30 +01:00
alexmadison f91fa9b158 all times fix 2022-03-08 10:48:43 +01:00
alexmadison 2a4d8c8dee added sig names on rhs, ty maxime 2022-03-08 10:24:42 +01:00
alexmadison a78eec5777 demux_td reviewed and supplies added 2022-03-08 10:11:52 +01:00
alexmadison c3f0059bfa encoder2d compiling 2022-03-07 16:22:00 +01:00
alexmadison a411231628 added some supplies 2022-03-07 16:21:45 +01:00
alexmadison 9b3bdc3f6c rejigged A cell in encoder2d 2022-03-04 15:09:49 +01:00
alexmadison a53110dda4 renamed encoder to dualrail_encoder 2022-03-04 14:53:14 +01:00
alexmadison 2882bc0f24 encoder unit test 2022-03-04 14:32:02 +01:00
alexmadison 4a4c4eeb14 merged encoder 2022-03-04 14:27:38 +01:00
alexmadison f55322bc7c encoder init 2022-03-04 14:10:15 +01:00
alexmadison 382714d11e decoder dly with and grid unit test 2022-03-03 17:10:55 +01:00
alexmadison c8412606b3 merged 2022-03-03 17:10:16 +01:00
alexmadison 893f71db92 AND grid init 2022-03-03 17:09:00 +01:00
alexmadison da5948f493 added N=1 cases 2022-03-03 17:05:56 +01:00
alexmadison 6fc3e4b99c removed arbiter tree 2022-03-03 11:56:59 +01:00
alexmadison af52c688a3 arbiter tree with arbiters, not tested 2022-03-03 11:56:34 +01:00
alexmadison d0a2fff096 arbiter init with or2s 2022-03-03 10:52:29 +01:00
alexmadison 7f40b48b49 arbtree init, using or2s for now 2022-03-03 10:47:37 +01:00
alexmadison 9c27248e12 decoder 2d dly init 2022-03-02 15:55:26 +01:00
alexmadison 3bba9fefa4 made buf with dly sorry 2022-03-02 15:48:54 +01:00
alexmadison 31d2f35042 i am a moron re dly cells 2022-03-02 15:47:36 +01:00
alexmadison c61a570f80 fixed wiring bug in prog delay 2022-03-02 15:11:22 +01:00
alexmadison 6bece2f459 renamed gates in or tree 2022-03-02 13:51:12 +01:00
alexmadison 659cd2479c oops accidentally hit all trees 2022-03-02 13:50:04 +01:00
alexmadison c5e582ff3e renamed vars in atree 2022-03-02 13:48:57 +01:00
alexmadison e52ec9ed61 renamed var in vtree for consciences 2022-03-02 11:51:45 +01:00
alexmadison c580d21efe fixed supply in fifo_t 2022-03-02 11:24:28 +01:00
alexmadison 1b7e39bc00 coders.act file init 2022-03-02 09:48:41 +01:00
alexmadison 8060051da0 Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-03-02 09:48:11 +01:00
alexmadison b456ea40fd changed delayprog to outin vs ya naming scheme 2022-03-02 09:48:05 +01:00
alexmadison 79a96ed511 added DLY4 cell 2022-03-01 15:28:22 +01:00
alexmadison 233c9a7d10 cleaned up minor 2022-03-01 15:27:27 +01:00
alexmadison 00869fc16e programmable delay tested 2022-03-01 15:26:43 +01:00
alexmadison 8268379572 bug to prev bug 2022-03-01 14:00:47 +01:00
alexmadison 18f84bc652 Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-03-01 13:55:47 +01:00
alexmadison 05f46ccf33 added try except for assert printing 2022-03-01 13:55:45 +01:00
alexmadison fc4ccea3c0 added and tree 2022-03-01 12:22:36 +01:00
alexmadison c947b28b03 added yours truely to the authors 2022-03-01 10:18:32 +01:00