alexmadison
|
0cdc01c279
|
regenned texel dualcore glue with new registers and neuron req keep fix
|
2022-06-16 17:40:33 +02:00 |
|
alexmadison
|
2ea83f3472
|
test merge of sram rw output working
|
2022-05-10 15:34:04 +02:00 |
|
alexmadison
|
016f634ac6
|
test of spike from sram workin
|
2022-05-10 15:22:19 +02:00 |
|
alexmadison
|
9ee41dc390
|
spikes out to sram working
|
2022-05-10 14:53:26 +02:00 |
|
alexmadison
|
4c208bc18a
|
packets to sram rw working
|
2022-05-10 14:07:51 +02:00 |
|
alexmadison
|
03851e19b7
|
mapper test init
|
2022-05-09 18:04:49 +02:00 |
|
alexmadison
|
0d7b82a0dd
|
altered amzo targettting tests to avoid instabilities
|
2022-05-09 16:48:58 +02:00 |
|
alexmadison
|
b1e24fa93c
|
added more monitoring tests
|
2022-05-08 19:05:52 +02:00 |
|
alexmadison
|
6ed0c4bfed
|
beefed up prsim to include AMZIOs
|
2022-05-08 17:03:02 +02:00 |
|
alexmadison
|
04a7a108d5
|
added reset signals in and out
|
2022-05-06 14:17:15 +02:00 |
|
alexmadison
|
71a2192427
|
texel dualcore with glue passed tests
|
2022-05-05 14:57:38 +02:00 |
|
alexmadison
|
10f4821eaa
|
regenned texel dualcore innovus fairly finaly??
|
2022-05-02 19:45:34 +02:00 |
|
alexmadison
|
de06893549
|
added reset sigs to neuron syn cores
|
2022-05-02 18:49:57 +02:00 |
|
alexmadison
|
f70b453ba7
|
Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
|
2022-05-02 15:27:38 +02:00 |
|
alexmadison
|
cd445d1736
|
added inverters on every 4th synapse targetting line
|
2022-05-02 15:26:03 +02:00 |
 Greatorex
|
64828422a0
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-05-02 15:12:42 +02:00 |
|
Greatorex
|
8d7933bf9c
|
wrapped tex_dual_inov
|
2022-05-02 15:12:21 +02:00 |
|
alexmadison
|
a114505a0b
|
fixed size of syn x channel
|
2022-04-25 13:15:53 +02:00 |
|
alexmadison
|
28823c4bca
|
regened texel dualcore prs
|
2022-04-25 10:32:47 +02:00 |
|
alexmadison
|
e6f1a31f68
|
encoder1d with bd simmed
|
2022-04-21 16:09:13 +02:00 |
|
alexmadison
|
e3237e6115
|
set line pull down delays to zero, rero, regenned prs
|
2022-04-21 15:10:12 +02:00 |
|
alexmadison
|
3f7cbf2b87
|
Merge branch 'innovus_ready' into dev
|
2022-04-21 14:49:30 +02:00 |
|
alexmadison
|
ec03f8abe4
|
added reg reset sig
|
2022-04-21 14:33:41 +02:00 |
|
alexmadison
|
75a42fff1b
|
texel prs for innovus generated
|
2022-04-21 14:31:35 +02:00 |
|
alexmadison
|
3443d46b9b
|
completely cut out the neuron and synapse hs from core
|
2022-04-21 14:07:15 +02:00 |
|
alexmadison
|
41f240726c
|
internal access added
|
2022-04-21 10:41:37 +02:00 |
|
Greatorex
|
cd1947a2ce
|
Auto stash before merge of "dev" and "origin/dev"
|
2022-04-15 12:48:50 +02:00 |
|
alexmadison
|
cd5900d4dc
|
tapeout freeze
|
2022-04-14 17:51:34 +02:00 |
|
alexmadison
|
bf4af13e04
|
added decoder dualrail refresh
|
2022-04-13 17:35:41 +02:00 |
|
alexmadison
|
4cca8c14fe
|
texel dualcore testing wip
|
2022-04-13 15:22:45 +02:00 |
|
alexmadison
|
ec6d91127f
|
texel small testt working
|
2022-04-12 17:48:59 +02:00 |
|
alexmadison
|
276efdede5
|
ole added no stop on fail
|
2022-04-12 10:31:50 +02:00 |
 Ole Richter
|
87499f834a
|
added flag for start seed
|
2022-04-11 20:16:32 +02:00 |
|
alexmadison
|
adc37f8de2
|
encoder1d passed unit tests
|
2022-04-11 19:49:22 +02:00 |
|
alexmadison
|
631df5e837
|
idk ole did something
|
2022-04-11 17:00:28 +02:00 |
|
alexmadison
|
d3614580dd
|
wqMerge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
|
2022-04-10 19:43:18 +02:00 |
|
alexmadison
|
8481d67f26
|
added sigs
|
2022-04-10 19:42:55 +02:00 |
|
Ole Richter
|
82a955b035
|
changed run sripts
|
2022-04-10 15:44:45 +02:00 |
|
alexmadison
|
19564a5a91
|
added catch for low n syn mon
|
2022-04-10 15:19:11 +02:00 |
|
alexmadison
|
6eb6766bef
|
texel small prs
|
2022-04-10 15:17:38 +02:00 |
|
alexmadison
|
feb28f27bf
|
added set bd channel without setting r
|
2022-04-10 13:59:27 +02:00 |
|
alexmadison
|
c81e77a2fa
|
texel30 with manual neurons passing tests
|
2022-04-08 18:36:58 +02:00 |
|
alexmadison
|
cc2487be1c
|
added monitor decoders
|
2022-04-08 17:55:12 +02:00 |
|
alexmadison
|
1d87a86ba6
|
texel 30 unit tests working
|
2022-04-08 14:54:00 +02:00 |
|
alexmadison
|
7ebd734eee
|
renamed chip nomap to texel_small
|
2022-04-08 12:14:50 +02:00 |
|
alexmadison
|
74c5b8703f
|
added second delaycfg to bd2qdi
|
2022-04-05 19:17:54 +02:00 |
|
alexmadison
|
41d76de718
|
chip unit tests passing baybeeeeee
|
2022-04-05 18:21:36 +02:00 |
|
alexmadison
|
fce3eac4e6
|
bd fifo register unit test working...
|
2022-04-05 10:02:37 +02:00 |
|
alexmadison
|
531ccf30c2
|
first tests passed
|
2022-04-04 20:23:56 +02:00 |
|
alexmadison
|
ab52498755
|
reset working
|
2022-04-04 19:32:30 +02:00 |
|
alexmadison
|
5fbd435ca2
|
XMerge branch 'madison_chip_dev' into dev
|
2022-04-04 17:49:45 +02:00 |
|
alexmadison
|
a229dd00cf
|
before the git gets fucked
|
2022-04-04 17:35:34 +02:00 |
|
Greatorex
|
a424b496e5
|
added more demuxs
|
2022-04-04 17:27:19 +02:00 |
|
alexmadison
|
5e4a8ee15c
|
dropper static with unit tests
|
2022-04-04 15:13:39 +02:00 |
|
alexmadison
|
afe332e8ba
|
fifo reg fifo unit test working
|
2022-04-04 09:49:51 +02:00 |
|
alexmadison
|
fa5f83f061
|
register rw passed initial tests
|
2022-04-02 18:31:45 +02:00 |
|
alexmadison
|
eda9e2a98b
|
register write array unit tests working
|
2022-04-02 17:16:20 +02:00 |
|
alexmadison
|
e995a78efb
|
dunno what i changed buti it was probably good
|
2022-04-01 20:54:27 +02:00 |
|
alexmadison
|
87010c256b
|
buffer register unit tests init
|
2022-04-01 20:47:04 +02:00 |
|
alexmadison
|
0a957fc130
|
registerA_w unit test working
|
2022-04-01 20:46:45 +02:00 |
|
alexmadison
|
ab248d608e
|
init and unit tests for register buffer
|
2022-04-01 16:58:12 +02:00 |
|
alexmadison
|
e05196bb7e
|
hybrid decoder in fifo train working
|
2022-03-31 18:06:47 +02:00 |
|
alexmadison
|
c840273ae6
|
decoder 2d hybrid unit tests working
|
2022-03-31 18:00:08 +02:00 |
|
alexmadison
|
7b7cd4653e
|
nrn_hs fifo etc unit test working
|
2022-03-31 16:20:23 +02:00 |
|
alexmadison
|
cd5d41d7f8
|
synapse handshake unit tests working
|
2022-03-31 11:23:51 +02:00 |
 M. Mastella
|
f468913472
|
flipflop updated
|
2022-03-30 16:03:01 +02:00 |
|
Greatorex
|
e09b4a0f7e
|
Merge branch 'dev' into HEAD
|
2022-03-30 15:09:59 +02:00 |
|
Greatorex
|
ba17fc0d1b
|
Auto stash before rebase of "origin/dev"
|
2022-03-30 15:03:55 +02:00 |
|
Greatorex
|
fbcd679b4c
|
pushing register
|
2022-03-30 15:01:50 +02:00 |
|
alexmadison
|
1707f1043a
|
renamed encoder inputs from x to inx
|
2022-03-30 10:14:29 +02:00 |
|
alexmadison
|
8b60b23214
|
omg its working
|
2022-03-29 18:35:58 +02:00 |
|
alexmadison
|
1a68a951e3
|
unit test for hs
|
2022-03-29 11:25:14 +02:00 |
|
alexmadison
|
746ee34107
|
append unit test with fifos
|
2022-03-25 18:57:35 +01:00 |
|
alexmadison
|
3587672e69
|
qdi2bd ready for rev
|
2022-03-25 17:15:03 +01:00 |
|
alexmadison
|
9d6e74268f
|
bd2qdi ole backseat reved
|
2022-03-25 15:43:46 +01:00 |
|
alexmadison
|
9ad12dc951
|
encoder2d revd mdsn
|
2022-03-22 16:29:30 +01:00 |
|
Greatorex
|
af2cedf54d
|
encoder8x8sim
|
2022-03-18 11:39:30 +01:00 |
|
Greatorex
|
d9cf4669ae
|
renamed encoder sim
|
2022-03-18 10:08:10 +01:00 |
|
Greatorex
|
29d43b0a20
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-18 10:06:55 +01:00 |
|
Greatorex
|
b9219f266f
|
Encoder Simmed
|
2022-03-18 10:06:43 +01:00 |
Michele
|
04d12338b7
|
continued register_rw
|
2022-03-15 08:16:59 +01:00 |
|
Michele
|
b8a74e1bb7
|
Auto stash before merge of "dev" and "origin/dev"
|
2022-03-14 20:43:07 +01:00 |
|
M. Mastella
|
edb0443c01
|
Added new version of Register_rw (still not properly working)
|
2022-03-14 17:15:27 +01:00 |
|
Michele
|
4dcd975554
|
register_rw continued
|
2022-03-09 20:02:41 +01:00 |
|
Michele
|
6f1a970cfd
|
register_rw (formerly register_rw_v2) compiles
|
2022-03-09 16:44:44 +01:00 |
|
M. Mastella
|
d2f643dc26
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-09 13:05:14 +01:00 |
|
M. Mastella
|
c8ac3cf37d
|
started register_v2 with reading and writing abilities
|
2022-03-09 13:05:08 +01:00 |
|
Greatorex
|
409fee54e8
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-08 18:49:07 +01:00 |
|
Greatorex
|
9a9c2f7da5
|
encoder sim still not working
|
2022-03-08 18:49:04 +01:00 |
|
M. Mastella
|
7439381c3c
|
Merge remote-tracking branch 'origin/dev' into dev
|
2022-03-08 11:36:29 +01:00 |
|
M. Mastella
|
7f5054e89b
|
arbiter_test redone without fifos
|
2022-03-08 11:36:25 +01:00 |
|
alexmadison
|
f91fa9b158
|
all times fix
|
2022-03-08 10:48:43 +01:00 |
|
alexmadison
|
2a4d8c8dee
|
added sig names on rhs, ty maxime
|
2022-03-08 10:24:42 +01:00 |
|
alexmadison
|
a78eec5777
|
demux_td reviewed and supplies added
|
2022-03-08 10:11:52 +01:00 |
|
M. Mastella
|
e49866323c
|
register_write works
|
2022-03-07 16:36:01 +01:00 |
|
Michele
|
ad318259a5
|
continued registers.c
|
2022-03-07 07:15:53 +01:00 |
|
Michele
|
932e967f3d
|
encoder in register works
|
2022-03-05 20:33:38 +01:00 |
|
Michele
|
cf66c0e665
|
added a vtree_5 test
|
2022-03-05 20:29:02 +01:00 |
|
Michele
|
aa67bd6168
|
register simulates correctly up to the fake clock generation
|
2022-03-05 20:28:50 +01:00 |
|
Michele
|
7fe31f0ed8
|
started testing the register_w (doesn't compile)
|
2022-03-04 21:17:30 +01:00 |