bics/actlib_dataflow_neuro
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415 Commits 3 Branches 1 Tag
b21b84e78d8894e4f174f337e03505556c5e2f88
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295 Commits
Author SHA1 Message Date
alexmadison d10d78347c refactored decoder into decoder dualrail 2022-03-30 11:01:21 +02:00
alexmadison 1707f1043a renamed encoder inputs from x to inx 2022-03-30 10:14:29 +02:00
alexmadison 870da14ccd let delay fifos have N= 0, simplified nrn grids thusly 2022-03-29 19:07:04 +02:00
alexmadison 5e4e905960 fixed minor bug in encoder, renamed nrn_hs 2022-03-29 15:42:54 +02:00
alexmadison 921145c450 added buffering on out 2022-03-29 14:57:20 +02:00
alexmadison 28ea85b9ed reverted nrn handshake to 2c1n 2022-03-29 11:24:42 +02:00
alexmadison 8528ee12cd added cells needed for neuron grid 2022-03-28 19:51:50 +02:00
alexmadison d395778a4a neuron 2d handshake fixes 2022-03-28 19:51:03 +02:00
alexmadison fb127d55f5 neuron handshake compiling, now testing 2022-03-28 16:23:12 +02:00
alexmadison 8cb6eddd37 removed line pull up downs, moved to coders 2022-03-28 16:22:51 +02:00
alexmadison 8b44a11fd6 added append, fixed bug in fifo 2022-03-25 18:57:18 +01:00
alexmadison 3587672e69 qdi2bd ready for rev 2022-03-25 17:15:03 +01:00
alexmadison 9d6e74268f bd2qdi ole backseat reved 2022-03-25 15:43:46 +01:00
alexmadison a42254a57b minor bug fix encoder2d 2022-03-22 16:30:58 +01:00
Greatorex 29d43b0a20 Merge remote-tracking branch 'origin/dev' into dev 2022-03-18 10:06:55 +01:00
Greatorex b9219f266f Encoder Simmed 2022-03-18 10:06:43 +01:00
Michele 04d12338b7 continued register_rw 2022-03-15 08:16:59 +01:00
M. Mastella edb0443c01 Added new version of Register_rw (still not properly working) 2022-03-14 17:15:27 +01:00
Michele cc2234a1b1 moved the ack of the register 2022-03-09 20:18:20 +01:00
Michele 4dcd975554 register_rw continued 2022-03-09 20:02:41 +01:00
Michele 6f1a970cfd register_rw (formerly register_rw_v2) compiles 2022-03-09 16:44:44 +01:00
M. Mastella d2f643dc26 Merge remote-tracking branch 'origin/dev' into dev 2022-03-09 13:05:14 +01:00
M. Mastella c8ac3cf37d started register_v2 with reading and writing abilities 2022-03-09 13:05:08 +01:00
Greatorex 409fee54e8 Merge remote-tracking branch 'origin/dev' into dev 2022-03-08 18:49:07 +01:00
Greatorex 9a9c2f7da5 encoder sim still not working 2022-03-08 18:49:04 +01:00
M. Mastella 422a90ad71 demux: cond.a has been now shorted to in.a 2022-03-08 12:12:45 +01:00
alexmadison a78eec5777 demux_td reviewed and supplies added 2022-03-08 10:11:52 +01:00
M. Mastella 0d3502bf00 Merge remote-tracking branch 'origin/dev' into dev 2022-03-07 16:36:05 +01:00
M. Mastella e49866323c register_write works 2022-03-07 16:36:01 +01:00
alexmadison c3f0059bfa encoder2d compiling 2022-03-07 16:22:00 +01:00
alexmadison a411231628 added some supplies 2022-03-07 16:21:45 +01:00
Michele ad318259a5 continued registers.c 2022-03-07 07:15:53 +01:00
Michele 932e967f3d encoder in register works 2022-03-05 20:33:38 +01:00
Michele aa67bd6168 register simulates correctly up to the fake clock generation 2022-03-05 20:28:50 +01:00
Michele 78a8f72d25 register compiles 2022-03-05 09:19:19 +01:00
Michele 7fe31f0ed8 started testing the register_w (doesn't compile) 2022-03-04 21:17:30 +01:00
Michele c30a46d6d8 I think the encoder2D compiles now 2022-03-04 21:11:34 +01:00
Michele b5fa707c4e forgot proc in defproc 2022-03-04 19:04:11 +01:00
Michele 72ec59cbcf added flip flop from XFAB 2022-03-04 19:02:34 +01:00
Michele 250f5bcc58 Added A_2C2P_RB_X1 because the encoder needs it 2022-03-04 19:02:12 +01:00
alexmadison 9b3bdc3f6c rejigged A cell in encoder2d 2022-03-04 15:09:49 +01:00
alexmadison a53110dda4 renamed encoder to dualrail_encoder 2022-03-04 14:53:14 +01:00
alexmadison 4a4c4eeb14 merged encoder 2022-03-04 14:27:38 +01:00
alexmadison f55322bc7c encoder init 2022-03-04 14:10:15 +01:00
Michele 18cf090b45 Merge remote-tracking branch 'origin/dev' into dev 2022-03-04 13:11:44 +01:00
Michele e8fa8e43a6 Changed FF in std. Started test (spoiler: is not working) 2022-03-04 13:11:34 +01:00
Greatorex 828fccfb38 Merge remote-tracking branch 'origin/dev' into dev 2022-03-04 12:34:00 +01:00
Greatorex 1abcc9dc55 Added stuff for line end pull U/D 2022-03-04 12:33:49 +01:00
Michele 9c6a591dc7 started registers 2022-03-04 11:44:00 +01:00
Michele b6c70f7f5e fixed vdd and vss in encoder sigbuf 2022-03-04 11:43:49 +01:00