Commit Graph

159 Commits

Author SHA1 Message Date
alexmadison 6dfc941993 added Cel to buf out ack, so that ack can't be removed before the bufs output data is fully invalidated 2022-03-31 15:10:47 +02:00
alexmadison 1d5d4738a2 cleaned up coders a bit 2022-03-31 13:20:18 +02:00
alexmadison 2e4cdd5029 vastly improved lazy synapse handshakes 2022-03-31 12:44:00 +02:00
alexmadison cd5d41d7f8 synapse handshake unit tests working 2022-03-31 11:23:51 +02:00
alexmadison e779ee55b9 added delays to out req-ack buffers, seems to work 2022-03-30 19:53:27 +02:00
alexmadison a53bd58e29 added Ole dly4 as per hugh 2022-03-30 16:50:05 +02:00
alexmadison 21c78e4461 fixed bug in delay fifo 2022-03-30 15:47:01 +02:00
alexmadison 4cbe8cb3d1 XMerge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-03-30 15:16:19 +02:00
alexmadison f9cdb2e914 added pulldown2 2022-03-30 15:16:15 +02:00
Greatorex e09b4a0f7e Merge branch 'dev' into HEAD 2022-03-30 15:09:59 +02:00
Greatorex 7db428b827 register added again 2022-03-30 15:04:35 +02:00
Greatorex ba17fc0d1b Auto stash before rebase of "origin/dev" 2022-03-30 15:03:55 +02:00
alexmadison 87f552b1d0 decoder hs wip 2022-03-30 14:06:14 +02:00
alexmadison cff6eba344 decoder_2d_hs init 2022-03-30 13:18:07 +02:00
alexmadison d10d78347c refactored decoder into decoder dualrail 2022-03-30 11:01:21 +02:00
alexmadison 1707f1043a renamed encoder inputs from x to inx 2022-03-30 10:14:29 +02:00
alexmadison 870da14ccd let delay fifos have N= 0, simplified nrn grids thusly 2022-03-29 19:07:04 +02:00
alexmadison 5e4e905960 fixed minor bug in encoder, renamed nrn_hs 2022-03-29 15:42:54 +02:00
alexmadison 921145c450 added buffering on out 2022-03-29 14:57:20 +02:00
alexmadison 28ea85b9ed reverted nrn handshake to 2c1n 2022-03-29 11:24:42 +02:00
alexmadison 8528ee12cd added cells needed for neuron grid 2022-03-28 19:51:50 +02:00
alexmadison d395778a4a neuron 2d handshake fixes 2022-03-28 19:51:03 +02:00
alexmadison fb127d55f5 neuron handshake compiling, now testing 2022-03-28 16:23:12 +02:00
alexmadison 8cb6eddd37 removed line pull up downs, moved to coders 2022-03-28 16:22:51 +02:00
alexmadison 8b44a11fd6 added append, fixed bug in fifo 2022-03-25 18:57:18 +01:00
alexmadison 3587672e69 qdi2bd ready for rev 2022-03-25 17:15:03 +01:00
alexmadison 9d6e74268f bd2qdi ole backseat reved 2022-03-25 15:43:46 +01:00
alexmadison a42254a57b minor bug fix encoder2d 2022-03-22 16:30:58 +01:00
Greatorex 29d43b0a20 Merge remote-tracking branch 'origin/dev' into dev 2022-03-18 10:06:55 +01:00
Greatorex b9219f266f Encoder Simmed 2022-03-18 10:06:43 +01:00
Michele 04d12338b7 continued register_rw 2022-03-15 08:16:59 +01:00
M. Mastella edb0443c01 Added new version of Register_rw (still not properly working) 2022-03-14 17:15:27 +01:00
Michele cc2234a1b1 moved the ack of the register 2022-03-09 20:18:20 +01:00
Michele 4dcd975554 register_rw continued 2022-03-09 20:02:41 +01:00
Michele 6f1a970cfd register_rw (formerly register_rw_v2) compiles 2022-03-09 16:44:44 +01:00
M. Mastella d2f643dc26 Merge remote-tracking branch 'origin/dev' into dev 2022-03-09 13:05:14 +01:00
M. Mastella c8ac3cf37d started register_v2 with reading and writing abilities 2022-03-09 13:05:08 +01:00
Greatorex 409fee54e8 Merge remote-tracking branch 'origin/dev' into dev 2022-03-08 18:49:07 +01:00
Greatorex 9a9c2f7da5 encoder sim still not working 2022-03-08 18:49:04 +01:00
M. Mastella 422a90ad71 demux: cond.a has been now shorted to in.a 2022-03-08 12:12:45 +01:00
alexmadison a78eec5777 demux_td reviewed and supplies added 2022-03-08 10:11:52 +01:00
M. Mastella 0d3502bf00 Merge remote-tracking branch 'origin/dev' into dev 2022-03-07 16:36:05 +01:00
M. Mastella e49866323c register_write works 2022-03-07 16:36:01 +01:00
alexmadison c3f0059bfa encoder2d compiling 2022-03-07 16:22:00 +01:00
alexmadison a411231628 added some supplies 2022-03-07 16:21:45 +01:00
Michele ad318259a5 continued registers.c 2022-03-07 07:15:53 +01:00
Michele 932e967f3d encoder in register works 2022-03-05 20:33:38 +01:00
Michele aa67bd6168 register simulates correctly up to the fake clock generation 2022-03-05 20:28:50 +01:00
Michele 78a8f72d25 register compiles 2022-03-05 09:19:19 +01:00
Michele 7fe31f0ed8 started testing the register_w (doesn't compile) 2022-03-04 21:17:30 +01:00