regenned with cores having new names

dataflow_neuro/cell_lib_async.act

@@ -26,14 +26,14 @@
 
 namespace tmpl {
     namespace dataflow_neuro{
-        export defcell KEEP_X1 (bool y; bool vdd, vss) {
+        export defcell KEEP (bool y; bool vdd, vss) {
             bool _y;
-            prs{
-                y => _y-
-                [weak=1] _y -> y-
-                [weak=1] ~_y -> y+
+             prs{
+                 // y => _y-
+            //     [weak=1] _y -> y-
+            //     [weak=1] ~_y -> y+
 
-                }
+                 }
         }
 
         export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
@@ -130,6 +130,94 @@ namespace tmpl {
             y {-1}}
         }
 
+        export defcell A_1C1N_X1 (bool! y; bool? c1, n1; bool vdd, vss)
+        {
+        prs{
+            ~c1 -> y+
+            c1&n1-> y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-1}}
+        }
+
+        // export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 | ~pr_B-> _y+
+        //     c1&n1&sr_B -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+        // export defcell A_1C1N_SB_X4 (bool! y; bool? c1, n1, pr, sr; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 & ~sr-> _y+
+        //     c1&n1 | pr -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+        export defcell A_1C2N_R_X1 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
+        {
+        prs{
+            ~c1 | ~pr_B-> y+
+            c1&n1&n2&sr_B -> y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}}
+        }
+
+        export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 | ~pr_B-> _y+
+            c1&n1&n2&sr_B -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+        export defcell A_1C2N_SB_X4 (bool! y; bool? c1, n1, n2, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~sr-> _y+
+            c1&n1&n2 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+        export defcell A_2C1N_SB_X4 (bool! y; bool? c1, c2, n1, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~c2 & ~sr-> _y+
+            c1&c2&n1 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+
         export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
         {
         prs{
@@ -177,12 +265,12 @@ namespace tmpl {
             y {-1}}
         }
 
-        export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss)
+        export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, na1, na2, nb1, nb2, pr_B, sr_B; bool vdd, vss)
         {
         bool _y;
         prs{
             (~c1 & ~c2) | ~pr_B -> _y+
-            c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
+            c1 & c2 & ((na1 & na2) | (nb1 & nb2)) & sr_B -> _y-
             _y => y-
         }
         sizing {    
@@ -354,6 +442,19 @@ namespace tmpl {
                 p_n_mode <- 1;
             y {-1}; _y{-1}}
         }
+
+        export defcell A_2C1N_R_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
+        {
+        prs{
+            (~c1 & ~c2) | ~pr_B -> y+
+            c1 & c2 & n1 & sr_B -> y-
+        }
+        sizing {    
+                leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-1}}
+        }
+
         export defcell A_2C1N_RB_X4(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
         {
             bool _y;
@@ -522,11 +623,11 @@ namespace tmpl {
             y {-1}; _y{-1} }
         }
 
-        export defcell A_4P1N1N_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
+        export defcell A_4P1N1N_X1 (bool! y; bool? na1, nb1, p1, p2, p3, p4; bool? vdd, vss)
         {
         prs{
             ~p1 & ~p2 & ~p3 & ~p4 -> y+
-            n1 | n2 -> y-
+            na1 | nb1 -> y-
             }
         sizing {leak_adjust <- 1; 
                 p_n_mode <- 1;
@@ -565,45 +666,53 @@ namespace tmpl {
           }
         }
         export
-        defproc A_1N_U_X4(bool? a; bool! y; bool? vdd, vss)
+        defproc A_1N_U_X4(bool? n1; bool! y; bool? vdd, vss)
         {
         prs{
-        [keeper=0] a -> y-
+        [keeper=0] n1 -> y-
         }
         }
 
         export
-        defproc A_2N_U_X4(bool? a, b; bool! y; bool? vdd, vss)
+        defproc A_2N_U_X4(bool? n1, n2; bool! y; bool? vdd, vss)
         {
         prs{
-        [keeper=0] a & b -> y-
+        [keeper=0] n1 & n2 -> y-
         }
         }
         
         export
-        defproc A_1P_U_X4(bool? a; bool! y; bool? vdd, vss)
+        defproc A_1P_U_X4(bool? p1; bool! y; bool? vdd, vss)
         {
         prs{
-        [keeper=0] ~a -> y+
+        [keeper=0] ~p1 -> y+
         }
         }
 
         export
-        defproc A_2P_U_X4(bool? a, b; bool! y; bool? vdd, vss)
+        defproc A_2P_U_X4(bool? p1, p2; bool! y; bool? vdd, vss)
         {
         prs{
-        [keeper=0] ~a & ~b -> y+
+        [keeper=0] ~p1 & ~p2 -> y+
+        }
+        }
+
+        export
+        defproc A_3P_U_X4(bool? p1, p2, p3; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] ~p1 & ~p2 & ~p3-> y+
         }
         }
 
         export
         defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
-            A_1N_U_X4 cell(.a = a, .y = y, .vdd = vdd, .vss = vss);
+            A_1N_U_X4 cell(.n1 = a, .y = y, .vdd = vdd, .vss = vss);
         }
 
         export
         defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) {
-            A_1P_U_X4 cell(.a = a, .y = y, .vdd = vdd, .vss = vss);
+            A_1P_U_X4 cell(.p1 = a, .y = y, .vdd = vdd, .vss = vss);
         }
 
         defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){

dataflow_neuro/cell_lib_std.act

@@ -27,14 +27,29 @@
 namespace tmpl {
   namespace dataflow_neuro {
 
+
+    // We have to add a pretend buffer in here
+    // to ensure that act2v doesn't simplify things
+    // and just connect y to vss/vdd lol
     export defproc TIELO_X1(bool! y; bool vdd, vss)
     {
-      y = vss;
+      bool _y, a;
+      a = vss;
+      prs {
+        a => _y-
+        _y => y-
+      }
+
     }
 
     export defproc TIEHI_X1(bool! y; bool vdd, vss)
     {
-      y = vdd;
+      bool _y, a;
+      a = vdd;
+      prs {
+        a => _y-
+        _y => y-
+      }      
     }
 
     /*-- inverters --*/
@@ -94,7 +109,19 @@ namespace tmpl {
     {
       sizing { _y {-4,2}; y {-8,4} }
     }
-        export defcell BUF_X12<: buf()
+    export defcell BUF_X12<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X16<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X24<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X32<: buf()
     {
       sizing { _y {-6,2}; y {-12,4} }
     }
@@ -283,6 +310,8 @@ namespace tmpl {
     export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
     {
       // y = !( S ? b : a )
+      // Actually looks more like
+      // if s = 0 -> use A
       // Adjusted to fit the XFAB Muxes
       bool _s;
       bool _y;
@@ -364,8 +393,8 @@ namespace tmpl {
       prs {
         en => _en-
 
-      ~a & ~_en -> y+
-        a & en -> y-
+      ~a & ~_en -> y-
+        a & en -> y+
       }
       sizing { _en{-1}; y{-1} }
     }
@@ -376,11 +405,24 @@ namespace tmpl {
       prs {
         en => _en-
 
-      ~a & ~_en -> y+
-        a & en -> y-
+      ~a & ~_en -> y-
+        a & en -> y+
       }
       sizing { _en{-2}; y{-2,2} }
     }
+
+    export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
+    {
+      bool _en;
+      prs {
+        en => _en-
+
+      ~a & ~_en -> y-
+        a & en -> y+
+      }
+      sizing { _en{-4}; y{-4,4} }
+    }
+
     export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
     {
       bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;

dataflow_neuro/chips.act

@@ -0,0 +1,793 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_core (avMx1of2<N_IN> in, out;
+    Mx1of2<REG_NCW> reg_data[REG_M];
+
+    // Dummy synapses and neurons in the handshake blocks
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
+    reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+    // Onwards
+    fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Register
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
+    register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
+        .supply = supply, .reset_B = reset_reg_B);
+    fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Spike Decoder
+    pint NC_SYN;
+    NC_SYN = NC_SYN_X + NC_SYN_Y;
+    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
+    fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
+    decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
+        .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
+        .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
+        .supply = supply, .reset_B = _reset_BX);
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    )
+
+    // Synapse handshake circuits, to be removed for innovus
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    //     .synapses = synapses,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
+    //     .to_pu = syn_pu,
+    //     .out_ackB_decoder = dec_ackB,
+    //     .supply = supply);
+
+    // Neurons + encoder
+    pint NC_NRN;
+    NC_NRN = NC_NRN_X + NC_NRN_Y;
+    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
+    fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Neuron handshake circuits, to be removed for innovus
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    //     .outx = enc_inx, .outy = enc_iny,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
+    //     .supply = supply, .reset_B = _reset_BX);
+
+
+
+    // Merge
+    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
+    append<N_IN-2, 2, 2> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
+    merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+
+    // Output
+    fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // Neuron/synapse monitor targeters
+    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
+    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
+    pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
+    pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
+
+    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
+    nrn_mon_dec_x.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_X:
+        nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
+    )
+    sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
+    nrn_mon_dec_y.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_Y:
+        nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
+    )
+    sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
+        .supply = supply);
+    syn_mon_dec_x.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_X:
+        syn_mon_dec_x.in.d[i] = register.data[3].d[i];
+    )
+    sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
+    syn_mon_dec_y.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_Y:
+        syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
+    )
+    sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
+
+    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
+    // Stops the possibility of dev_mon being high while some other sig is high.
+    // Otherwise boom.
+    // Also the 4th monitor line to each synapse is active LOW, needs inverter.
+    bool DEV_DEBUG;
+    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
+    sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+        .supply = supply);
+    DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    INV_X1 syn_targ_set_high_inv[NSMX4];
+    [NSMX4 >= 1 ->
+        AND2_X1 ands_devmon[NSMX4];
+        (i:NSMX4:
+            ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
+            ands_devmon[i].b = DEV_DEBUG;
+            ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
+            ands_devmon[i].vdd = supply.vdd;
+            ands_devmon[i].vss = supply.vss;
+
+            syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
+            syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
+            syn_targ_set_high_inv[i].vdd = supply.vdd;
+            syn_targ_set_high_inv[i].vss = supply.vss;
+
+        )
+        // Wire up the remaining lines.
+        (i:N_SYN_MON_X:
+            [(~(i%4 = 1)) & (~(i%4=3))->
+                syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
+            ]
+        )
+    ]
+
+    // Create TBUFs for each synapse column,
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
+    KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
+    sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
+    (j:N_MON_AMZO_PER_SYN:
+        (i:N_SYN_X:
+            index = i*N_MON_AMZO_PER_SYN + j;
+            syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
+            syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
+            syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
+        )
+
+        syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
+        syn_AMZO_keeps[j].vdd = supply.vdd;
+        syn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+
+    // Create TBUFs for each neuron column, and add keeps.
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
+    KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
+    sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply); 
+    (j:N_MON_AMZO_PER_NRN:
+        (i:N_NRN_X:
+            index = i*N_MON_AMZO_PER_NRN + j;
+            nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
+            nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
+            nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
+        )
+
+        nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
+        nrn_AMZO_keeps[j].vdd = supply.vdd;
+        nrn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+    // Create buffered signals from register to nrns.
+    sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
+    (i:N_FLAGS_PER_NRN:
+        sb_nrn_EFO.in[i] = register.data[5].d[i].t;
+    )
+
+    // Create  buffered signals from register to synapses.
+    // Includes safety on the first 3 flags with dev mon.
+    sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
+    (i:3..N_FLAGS_PER_SYN-1:
+        sb_syn_EFO.in[i] = register.data[4].d[i].t;
+    )  
+    AND2_X1 syn_flags_dev_safety[3];
+    (i:0..2:
+        syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
+        syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
+
+        syn_flags_dev_safety[i].vdd = supply.vdd;
+        syn_flags_dev_safety[i].vss = supply.vss;
+    )
+
+    // Create non-buffered reset signals for the neuron/syn handshakes
+    // Since sigs are buffered before each neuron.
+    sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
+    sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
+    sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
+    INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
+    sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
+
+}
+
+
+
+
+export template<pint N_IN,	// Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_singlecore (bd<N_IN> in, out;
+	Mx1of2<REG_NCW> reg_data[REG_M];
+	// a1of1 synapses[N_SYN_X * N_SYN_Y];
+	// a1of1 neurons[N_NRN_X * N_NRN_Y];
+    
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+	bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+	bool? loopback_en;
+	power supply;
+	bool? reset_B){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+	bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+	fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+	fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+	// Loopback
+	fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+	dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+		.supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+	// Onwards to core
+	fifo<N_IN,N_BUFFERS> fifo_fork2core(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+
+    texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core(.in = fifo_fork2core.out,
+            .reg_data = reg_data,
+            // .synapses = synapses,
+            // .neurons = neurons,
+            .nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
+            .syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
+            .syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
+            .syn_mon_AMZO = syn_mon_AMZO, .nrn_mon_AMZO = nrn_mon_AMZO,
+            .syn_flags_EFO = syn_flags_EFO, .nrn_flags_EFO = nrn_flags_EFO,
+
+            .reset_B = _reset_BX,
+            .supply = supply
+            );
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_core2mrg(.in = core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    
+
+    // merge core output and loopback
+    merge<N_IN> merge_drop8core(.in1 = fifo_core2mrg.out, .in2 = fifo_drop2mrg.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = merge_drop8core.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+
+
+}
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+   
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+    // Merge cores and loopback
+    merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore_mapper (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+
+    // MAPPER STUFF
+
+    bool? mapper_en;
+    avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
+    avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
+    avMx1of2<29> in_sram_r; // Readout packets from SRAM
+    avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
+
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+
+    // dmx to SRAM
+    bool is_to_sram, is_to_cores;
+    fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
+    demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX);
+    sram_dmx.cond.d.d[0].t = is_to_sram;
+    sram_dmx.cond.d.d[0].f = is_to_cores;
+    AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t,
+        .y = is_to_sram,
+        .vdd = supply.vdd, .vss = supply.vss);
+    OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f,
+        .y = is_to_cores,
+        .vdd = supply.vdd, .vss = supply.vss);
+    slice_data<32, 0, 30> pre_sram_slice(.supply = supply);
+    pre_sram_slice.in.a = sram_dmx.out2.a;
+    pre_sram_slice.in.v = sram_dmx.out2.v;
+    (i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
+    pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
+    pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
+    pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
+    fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // spikes from sram
+    // requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]
+    fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply);
+    append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply);
+    merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    merge_dmx8spk.in2.a = sram_spk_in_append.out.a;
+    merge_dmx8spk.in2.v = sram_spk_in_append.out.v;
+    (i:13: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i];)
+    merge_dmx8spk.in2.d.d[31] = sram_spk_in_append.out.d.d[13];
+    (i:13..30: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i+1];)
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = merge_dmx8spk.out, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+
+    // fork after core merge then go to mapper if its a spike
+    fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
+    fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply);
+    // Need to have it then drop the spike if its from a register.
+    demux_td<32, true> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data
+    drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30];
+    drop_if_reg.token.r  = drop_if_reg.token.a;
+
+    slice_data<32,0,8> slice_to_sram(.supply = supply);
+    // And move the msb (core bit) to just after the neuron address...
+    slice_to_sram.in.a = drop_if_reg.out.a;
+    slice_to_sram.in.v = drop_if_reg.out.v;
+    (i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];)
+    slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31];
+    (i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];)
+
+    fifo<8,N_BUFFERS> fifo_out_sram_spk(.in = slice_to_sram.out, .out = out_sram_spk,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // merge from cores and sram read in
+    fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply);
+    fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply);
+    append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply);
+    merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Merge cores and loopback
+    fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply);
+    merge<N_IN> merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+}
+}
+

dataflow_neuro/chips_noread.act

@@ -0,0 +1,467 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_core (avMx1of2<N_IN> in, out;
+    Mx1of2<REG_NCW> reg_data[REG_M];
+
+    // Dummy synapses and neurons in the handshake blocks
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
+    reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+    // Onwards
+    fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Register
+    slice_data<N_IN-1, 0,REG_NCW+REG_NCA> slice_pre_reg(.in = _demux.out2, .supply = supply);
+    fifo<REG_NCW+REG_NCA,N_BUFFERS> fifo_dmx2reg(.in = slice_pre_reg.out, .reset_B = _reset_BX, .supply = supply);
+    register_w_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
+        .supply = supply, .reset_B = reset_reg_B);
+
+
+    // Spike Decoder
+    pint NC_SYN;
+    NC_SYN = NC_SYN_X + NC_SYN_Y;
+    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
+    fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
+    decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
+        .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
+        .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
+        .supply = supply, .reset_B = _reset_BX);
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    )
+
+    // Synapse handshake circuits, to be removed for innovus
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    //     .synapses = synapses,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
+    //     .to_pu = syn_pu,
+    //     .out_ackB_decoder = dec_ackB,
+    //     .supply = supply);
+
+    // Neurons + encoder
+    pint NC_NRN;
+    NC_NRN = NC_NRN_X + NC_NRN_Y;
+    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
+    fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Neuron handshake circuits, to be removed for innovus
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    //     .outx = enc_inx, .outy = enc_iny,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
+    //     .supply = supply, .reset_B = _reset_BX);
+
+
+
+    // Merge
+    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
+
+    // Output
+    fifo<N_IN, N_BUFFERS> fifo_out(.in = append_enc.out, .out = out,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // Neuron/synapse monitor targeters
+    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
+    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
+    pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
+    pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
+
+    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
+    nrn_mon_dec_x.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_X:
+        nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
+    )
+    sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
+    nrn_mon_dec_y.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_Y:
+        nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
+    )
+    sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
+        .supply = supply);
+    syn_mon_dec_x.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_X:
+        syn_mon_dec_x.in.d[i] = register.data[3].d[i];
+    )
+    sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
+    syn_mon_dec_y.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_Y:
+        syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
+    )
+    sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
+
+    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
+    // Stops the possibility of dev_mon being high while some other sig is high.
+    // Otherwise boom.
+    // Also the 4th monitor line to each synapse is active LOW, needs inverter.
+    bool DEV_DEBUG;
+    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
+    sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+        .supply = supply);
+    DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    INV_X1 syn_targ_set_high_inv[NSMX4];
+    [NSMX4 >= 1 ->
+        AND2_X1 ands_devmon[NSMX4];
+        (i:NSMX4:
+            ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
+            ands_devmon[i].b = DEV_DEBUG;
+            ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
+            ands_devmon[i].vdd = supply.vdd;
+            ands_devmon[i].vss = supply.vss;
+
+            syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
+            syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
+            syn_targ_set_high_inv[i].vdd = supply.vdd;
+            syn_targ_set_high_inv[i].vss = supply.vss;
+
+        )
+        // Wire up the remaining lines.
+        (i:N_SYN_MON_X:
+            [(~(i%4 = 1)) & (~(i%4=3))->
+                syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
+            ]
+        )
+    ]
+
+    // Create TBUFs for each synapse column,
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
+    KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
+    sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
+    (j:N_MON_AMZO_PER_SYN:
+        (i:N_SYN_X:
+            index = i*N_MON_AMZO_PER_SYN + j;
+            syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
+            syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
+            syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
+        )
+
+        syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
+        syn_AMZO_keeps[j].vdd = supply.vdd;
+        syn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+
+    // Create TBUFs for each neuron column, and add keeps.
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
+    KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
+    sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply); 
+    (j:N_MON_AMZO_PER_NRN:
+        (i:N_NRN_X:
+            index = i*N_MON_AMZO_PER_NRN + j;
+            nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
+            nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
+            nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
+        )
+
+        nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
+        nrn_AMZO_keeps[j].vdd = supply.vdd;
+        nrn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+    // Create buffered signals from register to nrns.
+    sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
+    (i:N_FLAGS_PER_NRN:
+        sb_nrn_EFO.in[i] = register.data[5].d[i].t;
+    )
+
+    // Create  buffered signals from register to synapses.
+    // Includes safety on the first 3 flags with dev mon.
+    sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
+    (i:3..N_FLAGS_PER_SYN-1:
+        sb_syn_EFO.in[i] = register.data[4].d[i].t;
+    )  
+    AND2_X1 syn_flags_dev_safety[3];
+    (i:0..2:
+        syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
+        syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
+
+        syn_flags_dev_safety[i].vdd = supply.vdd;
+        syn_flags_dev_safety[i].vss = supply.vss;
+    )
+
+    // Create non-buffered reset signals for the neuron/syn handshakes
+    // Since sigs are buffered before each neuron.
+    sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
+    sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
+    sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
+    INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
+    sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
+
+}
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+   
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+    // Merge cores and loopback
+    merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+}
+}
+

dataflow_neuro/coders.act

@@ -29,6 +29,7 @@ import "../../dataflow_neuro/cell_lib_async.act";
 import "../../dataflow_neuro/cell_lib_std.act";
 import "../../dataflow_neuro/treegates.act";
 import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/interfaces.act";
 // import tmpl::dataflow_neuro;
 // import tmpl::dataflow_neuro;
 import std::channel;
@@ -48,11 +49,11 @@ open std::data;
 namespace tmpl {
 	namespace dataflow_neuro {
 
-		/**
-		 * Dualrail decoder.
-		 * Nc is the number of dualrail input channels.
-		 * Then builds N output AND gates, connecting to the right input wires.
-		 */
+/**
+ * Dualrail decoder.
+ * Nc is the number of dualrail input channels.
+ * Then builds N output AND gates, connecting to the right input wires.
+ */
 export template<pint Nc, N>
 defproc decoder_dualrail (Mx1of2<Nc> in; bool? out[N]; power supply) {
 	// signal buffers
@@ -87,6 +88,127 @@ defproc decoder_dualrail (Mx1of2<Nc> in; bool? out[N]; power supply) {
 }
 
 
+/**
+ * Dualrail decoder, but the signals to the decoders are refreshed every 48 gates.
+ * final_refresh is signal at the end of the refresh line.
+ * Is needed for doing validity checking etc, since it is the laggiest signal.
+ */
+export template<pint Nc, N>
+defproc decoder_dualrail_refresh (Mx1of2<Nc> in; bool? out[N]; Mx1of2<Nc> final_refresh; power supply) {
+	// signal buffers
+	pint index;
+	pint NUM_OUTS_PER_BUF = 96;
+	pint NUM_REFRESH = N/(NUM_OUTS_PER_BUF); // x2 bc only half the output bits look for it.
+	// NUM_REFRESH = 0;
+	BUF_X12 in_tX[Nc*(NUM_REFRESH+1)];
+	BUF_X12 in_fX[Nc*(NUM_REFRESH+1)];
+
+	(i:Nc:
+		// Connect start
+		in_tX[i].a =  in.d[i].t;
+		in_fX[i].a =  in.d[i].f;
+
+		// Connect mid bois
+		(j:NUM_REFRESH:
+			index = i + (1+j)*Nc;
+			in_tX[index].a = in_tX[index-Nc].y;
+			in_fX[index].a = in_fX[index-Nc].y;
+		)
+
+		// Connect end
+		in_tX[i+NUM_REFRESH*Nc].y = final_refresh.d[i].t;
+		in_fX[i+NUM_REFRESH*Nc].y = final_refresh.d[i].f;
+	)
+	
+	(i:Nc*(NUM_REFRESH+1):
+		in_tX[i].vdd = supply.vdd;
+		in_tX[i].vss = supply.vss;
+		in_fX[i].vdd = supply.vdd;
+		in_fX[i].vss = supply.vss;
+	)
+
+	// AND trees
+	pint bitval;
+	andtree<Nc> atree[N];
+	(k:0..N-1:atree[k].supply = supply;)
+	(i:0..N-1:
+		(j:0..Nc-1:
+			bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
+			[bitval = 1 ->
+				atree[i].in[j] = in_tX[j+((i/NUM_OUTS_PER_BUF)*Nc)].y;
+				// atree[i].in[j] = addr_buf.out.d.d[j].t;
+				[]bitval = 0 ->
+				atree[i].in[j] = in_fX[j+((i/NUM_OUTS_PER_BUF)*Nc)].y;
+				// atree[i].in[j] = addr_buf.out.d.d[j].f;
+				[]bitval >= 2 -> {false : "fuck"};
+				]
+			atree[i].out = out[i];
+			)
+		)
+}
+
+/**
+ * Dualrail decoder with buffered outputs.
+ * Be careful of out[] indexing.
+ */
+export template<pint Nc, N, OUT_STRENGTH>
+defproc decoder_dualrail_x(Mx1of2<Nc> in; bool? out[N]; power supply) {
+	decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
+	sigbuf<OUT_STRENGTH> sb[N];
+	(i:N:
+		sb[i].in = decoder.out[i];
+		sb[i].supply = supply;
+		sb[i].out[0] = out[i];
+		// (j:OUT_STRENGTH:
+		// 	sb[i].out[j] = out[j + i*OUT_STRENGTH];
+		// )
+	)
+}
+
+/**
+ * Dualrail decoder with on/off switch.
+ * Outputs are NOT buffered.
+ */
+export template<pint Nc, N>
+defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
+
+	decoder_dualrail_refresh<Nc, N> decoder(.out = out, .supply = supply);
+
+	sigbuf<Nc*2> sb_en(.in = en, .supply = supply);
+	// AND2_X1 en_ands[N];
+	// (i:N:
+	// 	en_ands[i].a = decoder.out[i];
+	// 	en_ands[i].b = sb_en.out[i];
+
+	// 	en_ands[i].vdd = supply.vdd;
+	// 	en_ands[i].vss = supply.vss;
+
+	// 	en_ands[i].y = out[i];
+
+	// )
+
+	AND2_X1 en_ands_t[Nc];
+	AND2_X1 en_ands_f[Nc];
+	(i:Nc:
+		en_ands_t[i].a = in.d[i].t;
+		en_ands_f[i].a = in.d[i].f;
+
+		en_ands_t[i].b = sb_en.out[i];
+		en_ands_f[i].b = sb_en.out[i+Nc];
+		
+		en_ands_t[i].y = decoder.in.d[i].t;
+		en_ands_f[i].y = decoder.in.d[i].f;
+
+		en_ands_t[i].vdd = supply.vdd;
+		en_ands_t[i].vss = supply.vss;
+		en_ands_f[i].vdd = supply.vdd;
+		en_ands_f[i].vss = supply.vss;
+	)
+
+}
+
+
+
 /**
  * 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
  *	Nx is the x size of the decoder array
@@ -131,8 +253,10 @@ defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
 export template<pint Nx, Ny>
 defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
 	// Buffer inputs
-	sigbuf<Ny> xbuf[Nx];
-	sigbuf<Nx> ybuf[Ny];
+	// sigbuf<Ny> xbuf[Nx];
+	// sigbuf<Nx> ybuf[Ny];
+	sigbuf<47> xbuf[Nx]; // BUFFERING DISABLED FOR NOW
+	sigbuf<47> ybuf[Ny]; // CUS GET BUFFERED IN THE CORE
 	(i:Nx:
 		xbuf[i].in = inx[i];
 		xbuf[i].supply = supply;
@@ -146,8 +270,8 @@ defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
 	(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
 	(x:0..Nx-1:
 		(y:0..Ny-1:
-			ands[x + y*Nx].a = xbuf[x].out[y];
-			ands[x + y*Nx].b = ybuf[y].out[x];
+			ands[x + y*Nx].a = xbuf[x].out[0];
+			ands[x + y*Nx].b = ybuf[y].out[0];
 			ands[x + y*Nx].y = out[x + y*Nx];
 			)
 		)
@@ -167,6 +291,9 @@ defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
 export template<pint NxC, NyC, Nx, Ny>
 defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; power supply) {
 
+	bool _reset_BX[Nx];
+	sigbuf<Nx> reset_sb(.in = reset_B, .out = _reset_BX, .supply = supply);
+
 	// Buffer to recieve concat(x,y) address packet
 	buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
 
@@ -207,8 +334,8 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 	(i:Nx:
 		(j:Ny:
 			index = i + Nx*j;
-			ack_pulldowns[index].a = out[index].a;
-			ack_pulldowns[index].b = d_dr_xX[i].out[j];
+			ack_pulldowns[index].n1 = out[index].a;
+			ack_pulldowns[index].n2 = d_dr_xX[i].out[j];
 			ack_pulldowns[index].y = _out_acksB[i];
 			ack_pulldowns[index].vss = supply.vss;
 			ack_pulldowns[index].vdd = supply.vdd;
@@ -223,12 +350,12 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 	A_1P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
 	A_1P_U_X4 pu_reset[Nx];
 	(i:Nx:
-		pu[i].a = d_dr_xX[i].out[Ny];
+		pu[i].p1 = d_dr_xX[i].out[Ny];
 		pu[i].y = _out_acksB[i];
 		pu[i].vdd = supply.vdd;
 		pu[i].vss = supply.vss;
 
-		pu_reset[i].a = reset_B;
+		pu_reset[i].p1 = _reset_BX[i];
 		pu_reset[i].y = _out_acksB[i];
 		pu_reset[i].vdd = supply.vdd;
 		pu_reset[i].vss = supply.vss;
@@ -256,6 +383,44 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 
 }
 
+
+/**
+ * Synapse handshaking stuff which exists in the core, and so will not be spawned in
+ * when innovusing all the periphery.
+ */
+export template<pint Nx, Ny>
+defproc decoder_2d_synapse_hs (bool? in_req_x[Nx], in_req_y[Ny]; a1of1 synapses[Nx*Ny];
+	bool out_ackB_decoder[Nx];
+	a1of1 to_pu[Nx];
+	power supply) {
+
+
+	// and grid for reqs into synapses
+	and_grid<Nx, Ny> _and_grid(.inx = in_req_x, .iny = in_req_y, .supply = supply);
+	(i:Nx*Ny: synapses[i].r = _and_grid.out[i];)
+	
+
+	// Pull DOWNs on the ackB lines by synapses (easier to invert).
+	A_2N_U_X4 ack_pulldowns[Nx*Ny];
+	pint index;
+	(i:Nx:
+		(j:Ny:
+			index = i + Nx*j;
+			ack_pulldowns[index].n1 = synapses[index].a;
+			ack_pulldowns[index].n2 = in_req_x[i]; // GET REFRHRESED IN CORE
+			ack_pulldowns[index].y = out_ackB_decoder[i];
+			ack_pulldowns[index].vss = supply.vss;
+			ack_pulldowns[index].vdd = supply.vdd;
+		)
+	)
+
+	// Connect the ackB lines together
+	(i:Nx: out_ackB_decoder[i] = to_pu[i].a;)
+
+	// Pipe req x lines down to the ackB pullups
+	(i:Nx: to_pu[i].r = in_req_x[i];)
+}
+
 /**
  * 2D decoder which uses either synapse handshaking, or just a delay.
  * Controlled by the "hs_en" (handshake_enable) config bit.
@@ -265,10 +430,19 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
  * goes through the prog_delay block.
  * Thus, for the handshaking version to be used "correctly", 
  * dly_cfg should be set to all zeros.
+ * ack_disable blocks the ack being returned to the buffer.
+ * Is needed in case there are instabilities while we fiddle with delays.
  */
 export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
-defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
-	reset_B; power supply) {
+defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[Ny]; bool? dly_cfg[N_dly_cfg], hs_en, ack_disable;
+	bool in_ackB_decoder[Nx]; // AckB lines back to the decoder for handshaking
+	a1of1 to_pu[Nx];
+	// bool out_ackB_pullups[Nx]; // AckB lines from the line end pull ups
+	// bool in_req_x_pullups[Nx]; // req x lines going to the line pull ups
+	bool? reset_B; power supply) {
+
+	bool _reset_BX[Nx];
+	sigbuf<Nx> reset_sb(.in = reset_B, .out = _reset_BX, .supply = supply);
 
 	bool hs_enB;
 	INV_X4 hs_inv(.a = hs_en, .y = hs_enB, .vdd = supply.vdd, .vss = supply.vss);
@@ -277,50 +451,27 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
 
 	// Decoder X/Y And trees
-	decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
+	decoder_dualrail_refresh<NxC,Nx> d_dr_x(.supply = supply);
 	(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
-	decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
+	decoder_dualrail_refresh<NyC,Ny> d_dr_y(.supply = supply);
 	(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
 
 	// sig buf for reqx lines, since they go to synapse pull down gates.
-	sigbuf<Ny+1> d_dr_xX[Nx];
-	(i:Nx:
-		d_dr_xX[i].in = d_dr_x.out[i];
-		d_dr_xX[i].supply = supply;
-	)
+	// Signals to the and-grid are buffered therein.
+	sigbuf_boolarray<Nx,15> d_dr_xX(.in = d_dr_x.out, .supply = supply);
+	d_dr_xX.out = out_req_x;
+	sigbuf_boolarray<Ny,47> d_dr_yX(.in = d_dr_y.out, .supply = supply);
+	d_dr_yX.out = out_req_y;
+
 
 	// Validity 
-	vtree<NxC> vtree_x (.supply = supply);
-	vtree<NyC> vtree_y (.supply = supply);
-	(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
-	(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
-	(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
-	(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
+	vtree<NxC> vtree_x (.in = d_dr_x.final_refresh, .supply = supply);
+	vtree<NyC> vtree_y (.in = d_dr_y.final_refresh, .supply = supply);
 	A_2C_B_X1 valid_Cel(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
 		.vdd = supply.vdd, .vss = supply.vss);
 
 
-	// and grid for reqs into synapses
-	and_grid<Nx, Ny> _and_grid(.inx = d_dr_x.out, .iny = d_dr_y.out, .supply = supply);
-	(i:Nx*Ny: out[i].r = _and_grid.out[i];)
-
-	// Acknowledge pull down time
-
-	// Pull DOWNs on the ackB lines by synapses (easier to invert).
-	bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
-	A_2N_U_X4 ack_pulldowns[Nx*Ny];
-	pint index;
-	(i:Nx:
-		(j:Ny:
-			index = i + Nx*j;
-			ack_pulldowns[index].a = out[index].a;
-			ack_pulldowns[index].b = d_dr_xX[i].out[j];
-			ack_pulldowns[index].y = _out_acksB[i];
-			ack_pulldowns[index].vss = supply.vss;
-			ack_pulldowns[index].vdd = supply.vdd;
-		)
-	)
-
+	
 	// Line end pull UPs (triggered once reqs removed)
 	// Use two pullups rather than and-pullup 
 	// bc smaller
@@ -329,25 +480,34 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	A_2P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
 	A_1P_U_X4 pu_reset[Nx];
 	(i:Nx:
-		pu[i].a = d_dr_xX[i].out[Ny];
-		pu[i].b = hs_enB;
-		pu[i].y = _out_acksB[i];
+		pu[i].p1 = to_pu[i].r;
+		pu[i].p2 = hs_enB;
+		pu[i].y = to_pu[i].a;
 		pu[i].vdd = supply.vdd;
 		pu[i].vss = supply.vss;
 
-		pu_reset[i].a = reset_B;
-		pu_reset[i].y = _out_acksB[i];
+		pu_reset[i].p1 = _reset_BX[i];
+		pu_reset[i].y = to_pu[i].a;
 		pu_reset[i].vdd = supply.vdd;
 		pu_reset[i].vss = supply.vss;
 	)
 
+	// Add keeps (currently don't do anything in ACT)
+	KEEP keeps[Nx];
+	(i:Nx:
+		keeps[i].vdd = supply.vdd;
+		keeps[i].vss = supply.vss;
+		keeps[i].y = to_pu[i].a;
+	)
+
+
 	// ORtree from all output acks, back to the buffer ack.
 	// This is instead of the ack that came from the delayed validity trees,
 	// in decoder_2d_dly.
 	ortree<Nx>  _ortree(.supply = supply);
 	INV_X1 out_ack_invs[Nx];
 	(i:Nx:
-		out_ack_invs[i].a = _out_acksB[i];
+		out_ack_invs[i].a = in_ackB_decoder[i];
 		out_ack_invs[i].vdd = supply.vdd;
 		out_ack_invs[i].vss = supply.vss;
 
@@ -366,7 +526,13 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 		.vdd = supply.vdd, .vss = supply.vss);
 
 	// Programmable delay
-	delayprog<N_dly_cfg> dly(.in = ack_mux.y, .out = addr_buf.out.a, .s = dly_cfg, .supply = supply);
+	delayprog<N_dly_cfg> dly(.in = ack_mux.y, .s = dly_cfg, .supply = supply);
+
+	// Final switch from register to maybe block the ack
+	INV_X1 ack_disableB(.a = ack_disable, .vdd = supply.vdd, .vss = supply.vss);
+	AND2_X1 ack_block(.a = dly.out, .b = ack_disableB.y, .y = addr_buf.out.a,
+	 .vdd = supply.vdd, .vss = supply.vss);
+
 
 }
 
@@ -487,10 +653,15 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 			(i:Nc:ors_t[i].supply = supply; ors_t[i].out = out.d[i].t;)
 			(i:Nc:ors_f[i].supply = supply; ors_f[i].out = out.d[i].f;)
 
+			bool _inX[N];
+			sigbuf_boolarray<N, Nc> sb_in(.in = in, .out = _inX, .supply = supply);
+
 			pint num_connected_t; // Number of guys already connected to the current OR tree
 			pint num_connected_f;
 
-			TIELO_X1 tielo(.vdd = supply.vdd, .vss = supply.vss); // I'm sorry
+			TIELO_X1 tielo[Nc]; // I'm sorry
+			(i:Nc:tielo[i].vdd = supply.vdd; tielo[i].vss = supply.vss;)
+
 			pint bitval;
 			(i:0..Nc-1: // For each output line
 				num_connected_t = 0;
@@ -498,16 +669,16 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 				(j:0.. _N-1:
 					bitval = (j & ( 1 << i )) >> i; // Get binary digit of integer j, column i
 					[bitval = 1 & j <= N-1->
-						ors_t[i].in[num_connected_t] = in[j];
+						ors_t[i].in[num_connected_t] = _inX[j];
 						num_connected_t = num_connected_t + 1;
 					[] bitval = 0  & j <= N-1->
-						ors_f[i].in[num_connected_f] = in[j];
+						ors_f[i].in[num_connected_f] = _inX[j];
 						num_connected_f = num_connected_f + 1;
 					[] bitval = 1 & j > N-1->
-						ors_t[i].in[num_connected_t] = tielo.y;
+						ors_t[i].in[num_connected_t] = tielo[i].y;
 						num_connected_t = num_connected_t + 1;
 					[] bitval = 0  & j > N-1->
-						ors_f[i].in[num_connected_f] = tielo.y;
+						ors_f[i].in[num_connected_f] = tielo[i].y;
 						num_connected_f = num_connected_f + 1;
 					]
 
@@ -521,24 +692,25 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 
 
 
-		/**
-	   * Buffer function code.
-	   * Is the function block ripped from the buffer_s.
-	   * Used in the encoder2d.
-	   */
+	/**
+   * Buffer function code.
+   * Is the function block ripped from the buffer_s.
+   * Used in the encoder2d.
+   */
     export template<pint N>
     defproc buffer_s_func (Mx1of2<N> in; avMx1of2<N> out; bool? in_v, en, reset_B; power supply) {
 		    //function
-		    bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N], _in_vX, _in_vXX_t[N],_in_vXX_f[N];
+		    bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N], _in_vX;
+		    // bool  _in_vXX_t[N],_in_vXX_f[N];
 
 
 		    A_2C2N_RB_X4 f_buf_func[N];
 		    A_2C2N_RB_X4 t_buf_func[N];
 
 		    // reset buffers
-		    bool _reset_BX,_reset_BXX[N];
+		    bool _reset_BX,_reset_BXX[N*2];
 		    BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-        sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
+        sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
 		    
 		    // Enable signal buffers
 		    sigbuf<N> en_buf_t(.in=en, .out=_en_X_t, .supply=supply);
@@ -551,8 +723,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 
 		    // in val signal buffers
 		    BUF_X4 in_v_prebuf(.a = in_v, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
-				sigbuf<N> in_v_buf_t(.in=_in_vX, .out=_in_vXX_t, .supply=supply);
-		    sigbuf<N> in_v_buf_f(.in=_in_vX, .out=_in_vXX_f, .supply=supply);
+			// sigbuf<N> in_v_buf_t(.in=_in_vX, .out=_in_vXX_t, .supply=supply);
+		    // sigbuf<N> in_v_buf_f(.in=_in_vX, .out=_in_vXX_f, .supply=supply);
+		    sigbuf<N*2> in_v_buf(.in=_in_vX,.supply=supply);
+
 
 		    (i:N: 
 		        f_buf_func[i].y=out.d.d[i].f;
@@ -563,28 +737,29 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 		        t_buf_func[i].c2=_out_a_BX_t[i];
 		        f_buf_func[i].n1=in.d[i].f;
 		        t_buf_func[i].n1=in.d[i].t;
-		        f_buf_func[i].n2=_in_vXX_f[i];
-		        t_buf_func[i].n2=_in_vXX_t[i];
+		        f_buf_func[i].n2=in_v_buf.out[i];
+		        t_buf_func[i].n2=in_v_buf.out[i+N];
 		        f_buf_func[i].vdd=supply.vdd;
 		        t_buf_func[i].vdd=supply.vdd;
 		        f_buf_func[i].vss=supply.vss;
 		        t_buf_func[i].vss=supply.vss;
 		        t_buf_func[i].pr_B = _reset_BXX[i];
 		        t_buf_func[i].sr_B = _reset_BXX[i];
-		        f_buf_func[i].pr_B = _reset_BXX[i];
-		        f_buf_func[i].sr_B = _reset_BXX[i];
+		        f_buf_func[i].pr_B = _reset_BXX[i+N];
+		        f_buf_func[i].sr_B = _reset_BXX[i+N];
 		    )
         
     }
 
 
 		export template<pint NxC, NyC, Nx, Ny, ACK_STRENGTH>
-		defproc encoder2D(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B)		{
+		defproc encoder2d(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B)	{
 			// Reset buffers
 			pint H = 2*(NxC + NyC); //Reset strength? to be investigated
+			
 			bool _reset_BX,_reset_BXX[H];
-      BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-      sigbuf<2*(NxC + NyC)> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
+		    BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+		    sigbuf<2*(NxC + NyC)> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
 
 			// Arbiters 
 			a1of1 _arb_out_x, _arb_out_y;
@@ -640,8 +815,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 			// X_req ORtree
 			bool _x_req_array[Nx], _x_v_B;
 			(i:Nx:_x_req_array[i] = inx[i].r;)
-			ortree<Nx> x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply); //todo BUFF
-			INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
+			ortree<Nx> x_req_ortree(.in = _x_req_array, .supply = supply); //todo BUFF
+			INV_X1 not_x_req_ortree(.a = x_req_ortree.out, .y = _x_v_B);
+			INV_X1 not_x_req_ortree2(.a = _x_v_B,.y = _x_v);
+
 
 			//X_REQ validation
 			// bool _x_req_array[Nx],_x_v_B, _en;
@@ -649,9 +826,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 			// ortree x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply);
 			// INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
 
+			bool _x_a_B2; // sorry
 			
 			bool _en;
-			A_1C3P2P2N_R_X1 x_ack(); // NEEDS BUFFERING TO X4
+			A_1C3P2P2N_R_X1 x_ack();
 			//branch1
 			x_ack.p4 = _in_x_v;
 			x_ack.p5 = _x_v_B;
@@ -664,14 +842,15 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 			x_ack.n1 = out.v;
 			x_ack.n2 = _in_x_v;
 			//
-			x_ack.y = _x_a_B;
+			x_ack.y = _x_a_B2;
 			//
 			x_ack.vdd = supply.vdd;
 			x_ack.vss = supply.vss;
 			x_ack.pr_B = _reset_BX;
 			x_ack.sr_B = _reset_BX;
 
-			INV_X1 not_x_ack(.a = _x_a_B, .y = _x_a, .vdd = supply.vdd, .vss = supply.vss);
+			INV_X1 not_x_ack(.a = _x_a_B2, .y = _x_a, .vdd = supply.vdd, .vss = supply.vss);
+			INV_X1 not_x_ack2(.a = _x_a, .y = _x_a_B, .vdd = supply.vdd, .vss = supply.vss);
 
 
 			A_1C2P_X1 enabling(.p1 = out.a, .p2 = out.v, .c1 = _x_a, .y = _en, .vdd = supply.vdd, .vss = supply.vss);
@@ -704,6 +883,228 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 		}
 
 
+    export
+    defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
+    {
+      INV_X1 inv(.a = reset_B, .vdd=supply.vdd,.vss =supply.vss);
+
+      TIEHI_X1 tiehi(.vdd = supply.vdd, .vss = supply.vss);
+
+      A_2N_U_X4 pull_down(.n1=in, .n2 = tiehi.y, .y=out);
+      A_2N_U_X4 pull_downR(.n1=inv.y, .n2 = tiehi.y, .y=out);
+    }
+
+
+
+		export template<pint NxC, NyC, Nx, Ny, N_dly>
+		defproc encoder2d_simple(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out;
+			a1of1 to_pd_x[Nx], to_pd_y[Ny]; // Ports for the line end pull downs to tap into
+			power supply; bool reset_B)		{
+
+			bool _a_x, _a_y;
+			bool _r_x, _r_y;
+			bool _r_x_B, _r_y_B;
+
+			buffer<NxC + NyC> buf(.out = out, .supply = supply, .reset_B = reset_B);
+
+			// Arbiters
+			arbtree<Nx> Xarb(.supply = supply);
+			arbtree<Ny> Yarb(.supply = supply);
+			Xarb.out.a = _a_x;
+			Xarb.out.r = _r_x;
+			Yarb.out.a = _a_y;
+			Yarb.out.r = _r_y;
+
+			// Encoders
+			dualrail_encoder<NxC, Nx> Xenc(.supply = supply);
+			dualrail_encoder<NyC, Ny> Yenc(.supply = supply);
+
+			delay_chain<N_dly> dly_x[Nx];
+			delay_chain<N_dly> dly_y[Ny];
+
+			BUF_X12 sb_inx_a[Nx];
+			BUF_X12 sb_iny_a[Ny];
+
+			// Wire up inputs to encoders and arb
+			(i:Nx:
+				Xarb.in[i].r = inx[i].r;
+				
+				dly_x[i].in = Xarb.in[i].a;
+				dly_x[i].out = sb_inx_a[i].a;
+				sb_inx_a[i].y = inx[i].a;
+				// Xarb.in[i].a = inx[i].a;
+				Xenc.in[i] = inx[i].a;
+
+				dly_x[i].supply = supply;
+				sb_inx_a[i].vdd = supply.vdd;
+				sb_inx_a[i].vss = supply.vss;
+			)
+
+			// Wire up inputs to encoders and arb
+			(i:Ny:
+				Yarb.in[i].r = iny[i].r;
+
+				dly_y[i].in = Yarb.in[i].a;
+				dly_y[i].out = sb_iny_a[i].a;
+				sb_iny_a[i].y = iny[i].a;
+				// Yarb.in[i].a = iny[i].a;
+				Yenc.in[i] = iny[i].a;
+
+				dly_y[i].supply = supply;
+				sb_iny_a[i].vdd = supply.vdd;
+				sb_iny_a[i].vss = supply.vss;
+			)
+
+			INV_X2 inv_buf(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
+
+			A_2C_RB_X1 a_x_Cel(.c1 = inv_buf.y, .c2 = _r_x, .y = _a_x,
+				.sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
+			A_2C_RB_X1 a_y_Cel(.c1 = inv_buf.y, .c2 = _r_y, .y = _a_y,
+				.sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
+
+			// Wire up encoder to buffer
+			(i:NxC:
+				Xenc.out.d[i] = buf.in.d.d[i];
+			)
+			(i:NyC:
+				Yenc.out.d[i] = buf.in.d.d[i+NxC];
+			)
+
+
+			// Line pull down stuff
+			// Create delay fifos to emulate the fact that the line pull downs
+			// are at the end of the line, and thus slow.
+			// Note that if N_dly = 0, delay fifo is just a pipe.
+			// delay_chain<N_dly> dly_x[Nx];
+			// delay_chain<N_dly> dly_y[Ny];	
+			
+			// Create x line req pull downs
+			nrn_line_end_pull_down pd_x[Nx];
+			sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
+			(i:0..Nx-1:
+				// dly_x[i].supply = supply;
+				// dly_x[i].in = to_pd_x[i].a;
+				// pd_x[i].in = dly_x[i].out;
+				pd_x[i].in = to_pd_x[i].a;
+				
+				pd_x[i].out = to_pd_x[i].r;
+				pd_x[i].reset_B = rsb_pd_x.out[i];
+				pd_x[i].supply = supply;
+			)
+
+			// Create y line req pull downs
+			nrn_line_end_pull_down pd_y[Ny];
+			sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
+			(j:0..Ny-1:
+				// dly_y[j].supply = supply;
+				// dly_y[j].in = to_pd_y[j].a;
+				// pd_y[j].in = dly_y[j].out;
+				pd_y[j].in = to_pd_y[j].a;
+			
+				pd_y[j].out = to_pd_y[j].r;
+				pd_y[j].reset_B = rsb_pd_y.out[j];
+				pd_y[j].supply = supply;
+			)
+
+			// Add keeps
+			// Note that these are attached to the channel coming from the pull downs,
+			// not inx/y.r!!!
+			// This is because inx/y.r may be buffered.
+			KEEP keep_x[Nx];
+			(i:Nx:
+				keep_x[i].vdd = supply.vdd;
+				keep_x[i].vss = supply.vss;
+				// keep_x[i].y = inx[i].r;
+				keep_x[i].y = to_pd_x[i].r;
+
+			)
+
+			KEEP keep_y[Ny];
+			(j:Ny:
+				keep_y[j].vdd = supply.vdd;
+				keep_y[j].vss = supply.vss;
+				// keep_y[j].y = iny[j].r;
+				keep_y[j].y = to_pd_y[j].r;
+
+			)
+
+		}
+
+		export template<pint Nc, N>
+		defproc encoder1d_simple(a1of1 in[N]; avMx1of2<Nc> out;
+			power supply; bool reset_B)		{
+
+			bool _a_x, _r_x;
+			bool _r_x_B;
+
+			buffer<Nc> buf(.out = out, .supply = supply, .reset_B = reset_B);
+
+			// Arbiters
+			arbtree<N> Xarb(.supply = supply);
+			Xarb.out.a = _a_x;
+			Xarb.out.r = _r_x;
+
+			// Encoders
+			dualrail_encoder<Nc, N> Xenc(.supply = supply);
+
+			// Wire up inputs to encoders and arb
+			(i:N:
+				Xarb.in[i].r = in[i].r;
+				Xarb.in[i].a = in[i].a;
+				Xenc.in[i] = in[i].a;
+			)
+
+			INV_X2 inv_buf(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
+
+			A_2C_RB_X1 a_x_Cel(.c1 = inv_buf.y, .c2 = _r_x, .y = _a_x,
+				.sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
+
+			// Wire up encoder to buffer
+			(i:Nc:
+				Xenc.out.d[i] = buf.in.d.d[i];
+			)
+
+		}
+
+
+		/**
+	   * Encoder 1d followed by some fifos then a qd2bdi conversion.
+	   */
+		export template<pint Nc, N, N_BUFFERS, N_BD_DLY_CFG>
+		defproc encoder1d_bd(a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG], reset_B; power supply) {
+			bool _reset_BX;
+			BUF_X4 rsb(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+			encoder1d_simple<Nc, N> _enc(.in = in, .reset_B = _reset_BX, .supply = supply);
+			fifo<Nc, N_BUFFERS> _fifo(.in = _enc.out, .reset_B = _reset_BX, .supply = supply);
+			qdi2bd<Nc, N_BD_DLY_CFG> _qdi2bd(.in = _fifo.out, .out = out, .dly_cfg = dly_cfg,
+				.reset_B = _reset_BX, .supply = supply);
+		}
+
+		/**
+	   * Same as encoder1d_bd above but with inverters on in.a/r bc sadc neuron handshake
+	   * signals are backwards lol.
+	   */
+		export template<pint Nc, N, N_BUFFERS, N_BD_DLY_CFG>
+		defproc encoder1d_bd_sadc(a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG], reset_B; power supply) {
+			
+
+			encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.out = out, .dly_cfg = dly_cfg,
+				.reset_B = reset_B, .supply = supply);
+
+			INV_X1 req_invs[N];
+			INV_X1 ack_invs[N];
+			(i:N:
+				req_invs[i](.a = in[i].r, .y = c.in[i].r, .vdd = supply.vdd, .vss = supply.vss);
+				ack_invs[i](.a = c.in[i].a, .y = in[i].a, .vdd = supply.vdd, .vss = supply.vss);
+
+			)
+			
+
+		}
+
+
+
+
 
 		/**
 	   * Neuron handshaking.
@@ -711,19 +1112,12 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	   * Then performs a 2d handshake out outy then outx.
 	   */
 		export
-		defproc nrn_hs_2D(a1of1 in; a1of1 outx; a1of1 outy; power supply; bool reset_B)	{
+		defproc nrn_hs_2d(a1of1 in; a1of1 outx; a1of1 outy; power supply; bool reset_B)	{
 			bool _reset_BX;
 			BUF_X2 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
 
 			bool _en, _req;
-			
-			// A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
-			// 	.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
 
-			// Switched it back
-			// Because had the problem that if the req was not removed in time,
-			// it would be recounted as a double spike,
-			// since in.req is still high after the out has been dealt with.
 			A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = _req, .y = in.a,
 				.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
 
@@ -735,35 +1129,36 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 			INV_X2 inv_x(.a = outx.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
 			INV_X2 inv_y(.a = outy.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
 
+
+			// WARNUNG WARNUNG WARNUNG //
+			// This neuron hs design has a fat timing assumption.
+			// Say that the neuron has sent out both reqs, and is now receiving the acks.
+			// _x_a_B and _y_a_B are then low, and _req starts to be pulled down to reset the hs.
+			// However, if the line pull downs at the end of the neuron row/column are fast enough,
+			// then seeing the high acks, they will pull the ack lines down. If the arbiter tree
+			// is sufficiently fast enough, then it will remove the ack lines.
+			// If this cell were rather tardy, then _req's pd would be cancelled midway,
+			// it missed its window of opportunity to switch, and would probably make the system hang.
+			// Or starts oscillating with the line pull down and goes brrrrapppppppp.
+			// This issue may be somewhat unavoidable, as from a black box perspective,
+			// we are giving the neuron acks, but then not listening to it at all to check
+			// that it has had time to act upon these acks.
 			A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req,
 				.pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
 
 			// y_req pull up
-			NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
-			A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
+			bool _reqB;
+			INV_X1 req_inv(.a = _req, .y = _reqB, .vdd= supply.vdd, .vss = supply.vss);
+			A_2P_U_X4 pu_y(.p1 = outy.a, .p2 = _reqB, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
  
 			// x_req pull up
-			NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
-			A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
+			A_3P_U_X4 pu_x(.p1 = outx.a,  .p2 = _y_a_B, .p3 = _reqB, .y = outx.r,
+				.vdd = supply.vdd, .vss = supply.vss);
+
+
 		}
 
 
-
-		export
-    defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
-    {
-      bool _out, __out, nand_out;
-      BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
-      BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
-      INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
-
-      NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss);
-
-      A_1N_U_X4 pull_down(.a=nand_out, .y=out);
-    }
-
-
-
 		/**
 	   * A 2d grid of neuron handshakers.
 	   * Should then slot into the encoder.
@@ -772,8 +1167,9 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	   * for the purpose of running ACT sims.
 	   * It should probably be set to 0 though.
 	   */
-		export template<pint Nx, Ny, N_dly>
-		defproc nrn_hs_2D_array(a1of1 in[Nx*Ny]; a1of1 outx[Nx], outy[Ny];
+		export template<pint Nx, Ny>
+		defproc nrn_hs_2d_array(a1of1 in[Nx*Ny]; a1of1 outx[Nx], outy[Ny];
+			a1of1 to_pd_x[Nx], to_pd_y[Ny];
 			power supply; bool reset_B) {
 
 			// Make hella signal buffers
@@ -800,18 +1196,16 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 				out_req_buf_y[i].a = _outy[i].r;
 				out_req_buf_y[i].y = outy[i].r;
 			)
+
 			// Add buffers on output ack lines
-			// Note that this should be generalised.
-			// And probably won't even be done by ACT/innovus anwyay
-			// TODO: do it properly with sigbufs?
-			BUF_X4 out_ack_buf_x[Nx];
+			BUF_X12 out_ack_buf_x[Nx];
 			(i:Nx:
 				out_ack_buf_x[i].vss = supply.vss;
 				out_ack_buf_x[i].vdd = supply.vdd;
 				out_ack_buf_x[i].a = outx[i].a;
 				out_ack_buf_x[i].y = _outx[i].a;
 			)
-			BUF_X4 out_ack_buf_y[Ny];
+			BUF_X12 out_ack_buf_y[Ny];
 			(i:Ny:
 				out_ack_buf_y[i].vss = supply.vss;
 				out_ack_buf_y[i].vdd = supply.vdd;
@@ -823,7 +1217,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 
 			// Create handshake grid 
 			pint index;
-			nrn_hs_2D neurons[Nx*Ny];
+			nrn_hs_2d neurons[Nx*Ny];
 			(i:0..Nx-1:
 				(j:0..Ny-1:
 					index = i + j*Nx;
@@ -835,55 +1229,14 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 				)
 			)
 
-			// Create delay fifos to emulate the fact that the line pull downs
-			// are at the end of the line, and thus slow.
-			// Note that if N_dly = 0, delay fifo is just a pipe.
-			delay_chain<N_dly> dly_x[Nx];
-			delay_chain<N_dly> dly_y[Ny];	
-			
-			// Create x line req pull downs
-			nrn_line_end_pull_down pd_x[Nx];
-			sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
-			(i:0..Nx-1:
-				dly_x[i].supply = supply;
-				dly_x[i].in = _outx[i].a;
-				pd_x[i].in = dly_x[i].out;
-				
-				pd_x[i].out = _outx[i].r;
-				pd_x[i].reset_B = rsb_pd_x.out[i];
-				pd_x[i].supply = supply;
-			)
+			// Pipe the ack/req lines through to the pulldowns
+			to_pd_x = _outx;
+			to_pd_y = _outy;
 
-			// Create y line req pull downs
-			nrn_line_end_pull_down pd_y[Ny];
-			sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
-			(j:0..Ny-1:
-				dly_y[j].supply = supply;
-				dly_y[j].in = _outy[j].a;
-				pd_y[j].in = dly_y[j].out;
-			
-				pd_y[j].out = _outy[j].r;
-				pd_y[j].reset_B = rsb_pd_y.out[j];
-				pd_y[j].supply = supply;
-			)
 
-			// Add keeps
-			KEEP_X1 keep_x[Nx];
-			(i:Nx:
-				keep_x[i].vdd = supply.vdd;
-				keep_x[i].vss = supply.vss;
-				keep_x[i].y = _outx[i].r;
-			)
-
-			KEEP_X1 keep_y[Ny];
-			(j:Ny:
-				keep_y[j].vdd = supply.vdd;
-				keep_y[j].vss = supply.vss;
-				keep_y[j].y = _outy[j].r;
-			)
 		}
 
 
 	}
 
-}
+}

dataflow_neuro/dummy.act

@@ -0,0 +1,94 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+/**
+ * Creates a synapse-neuron dummy block, 
+ * where any synapse being triggered makes the neuron "spike".
+ */
+export template<pint N_SYN>
+defproc dummy_neuron_block (a1of1 synapses[N_SYN], neuron; power supply){
+    // OR over reqs from syn in to neuron out
+    ortree<N_SYN> _ortree(.out = neuron.r, .supply = supply);
+    (i:N_SYN: _ortree.in[i] = synapses[i].r;)
+
+    // ANDs piping the ack back to the proper synapse
+
+    BUF_X12 nrn_ack_buf(.a = neuron.a, .vdd = supply.vdd, .vss = supply.vss);
+
+    AND2_X1 ands[N_SYN];
+    (i:N_SYN:
+        ands[i].a = nrn_ack_buf.y;
+        ands[i].b = synapses[i].r;
+        ands[i].y = synapses[i].a;
+
+        ands[i].vss = supply.vss;
+        ands[i].vdd = supply.vdd;
+    )
+}
+
+/**
+ * Create an array of neuron dummy blocks.
+ * Note that this is custom made for the indexing on the texel chip.
+ * And so should be reused *with care*.
+ */
+export template<pint N_SYN_PER_NRN, N_NRN, N_NRN_X>
+defproc dummy_neuron_core (a1of1 synapses[N_SYN_PER_NRN * N_NRN], neurons[N_NRN]; power supply){
+    dummy_neuron_block<N_SYN_PER_NRN> blocks[N_NRN];
+    pint Xn, Yn, Xs, Ys;
+    (i:N_NRN:
+        Yn = i/N_NRN_X;
+        Xn = i-Yn*N_NRN_X;
+        neurons[i] = blocks[i].neuron;
+        blocks[i].supply = supply;
+        (j:N_SYN_PER_NRN: // moron, need to think about neuron indexxing too
+            Xs = Xn;
+            Ys = Yn*N_SYN_PER_NRN + j;
+            blocks[i].synapses[j] = synapses[Ys*N_NRN_X + Xs];
+        )
+    )
+}
+
+
+
+
+}
+}

dataflow_neuro/dynapse.act

@@ -0,0 +1,66 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export
+defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
+	bool _en;
+	bool _out_a_B;
+
+	INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
+
+	A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_1C1P_X1 A_en(.c1 = in.a, .p1 =  out.r, .y = _en,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+}
+
+}
+}
+

dataflow_neuro/interfaces.act

@@ -48,24 +48,34 @@ namespace tmpl {
 		 * quasi delay insensitive channel (dual rail).
 		 * Basically a buffer with a bitwise conversion in front of it.
 		 */
-		export template<pint N, N_dly_cfg>
-		defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
+		export template<pint N, N_dly_cfg, N_dly_cfg2>
+		defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
+			power supply; bool? reset_B) {
+			
 			// Delay on req_in
 			bool _req;
 			delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
 
 			// sig buff the reset signal
-			bool _reset_BX, _reset_BXX[N];
+			bool _reset_BX, _reset_BXX[N*2];
 			BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
+            sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
 
             // sig buff the req
-			bool _reqX, _reqXX[N];
+			bool _reqX, _reqXX[N*2];
 			BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
+        	sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
+
+			// For reasons of pure spice, the control circuitry 
+			// requires a req signal that FALLS SLOWER than the req going to the function block.
+			// Thus need another delay prog.
+			bool _req_slowfall;
+			delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
+			OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
+				.vss = supply.vss, .vdd = supply.vdd);
 
             // bd2qdi conversion
-            // Each line goes to a t pin, its not to a f.
+            // Each line goes to a t pin, its not to an f.
             bool _inB[N];
             INV_X1 input_invs[N];
             (i:N:
@@ -89,42 +99,39 @@ namespace tmpl {
 
             //control
             bool _en;
-            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_reqX,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
 
             //function
-            bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
+            bool _out_a_B;
             A_2C2N_RB_X4 f_buf_func[N];
             A_2C2N_RB_X4 t_buf_func[N];
-            sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
-            sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
             INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
                 f_buf_func[i].y=out.d.d[i].f;
                 t_buf_func[i].y=out.d.d[i].t;
-                f_buf_func[i].c1=_en_X_f[i];
-                t_buf_func[i].c1=_en_X_t[i];
-                f_buf_func[i].c2=_out_a_BX_f[i];
-                t_buf_func[i].c2=_out_a_BX_t[i];
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=out_a_B_buf.out[i];
+                t_buf_func[i].c2=out_a_B_buf.out[i+N];
                 f_buf_func[i].n1=_inB[i];
                 t_buf_func[i].n1=in.d[i];
                 f_buf_func[i].n2=_reqXX[i];
-                t_buf_func[i].n2=_reqXX[i];
+                t_buf_func[i].n2=_reqXX[i+N];
                 f_buf_func[i].vdd=supply.vdd;
                 t_buf_func[i].vdd=supply.vdd;
                 f_buf_func[i].vss=supply.vss;
                 t_buf_func[i].vss=supply.vss;
                 t_buf_func[i].pr_B = _reset_BXX[i];
                 t_buf_func[i].sr_B = _reset_BXX[i];
-                f_buf_func[i].pr_B = _reset_BXX[i];
-                f_buf_func[i].sr_B = _reset_BXX[i];
+                f_buf_func[i].pr_B = _reset_BXX[i+N];
+                f_buf_func[i].sr_B = _reset_BXX[i+N];
             )
 
-
 		}
 
 

dataflow_neuro/primitives.act

@@ -33,6 +33,9 @@ import "../../dataflow_neuro/treegates.act";
 import std::channel;
 open std::channel;
 
+// import std::func;
+
+
 namespace tmpl {
     namespace dataflow_neuro {
 
@@ -75,8 +78,8 @@ namespace tmpl {
               [(&i:M: d.d[i].t | d.d[i].f)];
               self := 0;
               (;i:M: [ d.d[i].t -> self := self | (1 << i)
-        	     [] else -> skip
-        	     ]
+               [] else -> skip
+               ]
               )
             }
         
@@ -108,37 +111,35 @@ namespace tmpl {
         export template<pint N>
         defproc buffer (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
             //control
-            bool _en, _reset_BX,_reset_BXX[N];
+            bool _en, _reset_BX,_reset_BXX[N*2];
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
 
 
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-	          sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
-	    
+            sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
+      
             //validity
             bool _in_v;
             vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
             BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
             
             //function
-            bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
+            bool _out_a_BX[N*2],_out_a_B;
             A_2C1N_RB_X4 f_buf_func[N];
             A_2C1N_RB_X4 t_buf_func[N];
-            sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
-            sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
             INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B,.out=_out_a_BX, .supply = supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
                 f_buf_func[i].y=out.d.d[i].f;
                 t_buf_func[i].y=out.d.d[i].t;
-                f_buf_func[i].c1=_en_X_f[i];
-                t_buf_func[i].c1=_en_X_t[i];
-                f_buf_func[i].c2=_out_a_BX_f[i];
-                t_buf_func[i].c2=_out_a_BX_t[i];
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=_out_a_BX[i];
+                t_buf_func[i].c2=_out_a_BX[i+N];
                 f_buf_func[i].n1=in.d.d[i].f;
                 t_buf_func[i].n1=in.d.d[i].t;
                 f_buf_func[i].vdd=supply.vdd;
@@ -147,8 +148,8 @@ namespace tmpl {
                 t_buf_func[i].vss=supply.vss;
                 t_buf_func[i].pr_B = _reset_BXX[i];
                 t_buf_func[i].sr_B = _reset_BXX[i];
-                f_buf_func[i].pr_B = _reset_BXX[i];
-                f_buf_func[i].sr_B = _reset_BXX[i];
+                f_buf_func[i].pr_B = _reset_BXX[i+N];
+                f_buf_func[i].sr_B = _reset_BXX[i+N];
             )
         }
         // A template creating a FIFO of M buffers with N bits each
@@ -193,33 +194,31 @@ namespace tmpl {
             sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
         
             //validity
-            bool _in_v, _in_vX[N];
+            bool _in_v;
             vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
             BUF_X4 in_v_buf4(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N> in_v_bufN(.in = in.v, .out = _in_vX, .supply = supply);
+            sigbuf<N*2> in_v_bufN(.in = in.v, .supply = supply);
 
             //function
-            bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
+            bool _out_a_B;
             A_2C2N_RB_X4 f_buf_func[N];
             A_2C2N_RB_X4 t_buf_func[N];
-            sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
-            sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
             INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
                 f_buf_func[i].y=out.d.d[i].f;
                 t_buf_func[i].y=out.d.d[i].t;
-                f_buf_func[i].c1=_en_X_f[i];
-                t_buf_func[i].c1=_en_X_t[i];
-                f_buf_func[i].c2=_out_a_BX_f[i];
-                t_buf_func[i].c2=_out_a_BX_t[i];
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=out_a_B_buf.out[i];
+                t_buf_func[i].c2=out_a_B_buf.out[i+N];
                 f_buf_func[i].n1=in.d.d[i].f;
                 t_buf_func[i].n1=in.d.d[i].t;
-                f_buf_func[i].n2=_in_vX[i];
-                t_buf_func[i].n2=_in_vX[i];
+                f_buf_func[i].n2=in_v_bufN.out[i];
+                t_buf_func[i].n2=in_v_bufN.out[i+N];
                 f_buf_func[i].vdd=supply.vdd;
                 t_buf_func[i].vdd=supply.vdd;
                 f_buf_func[i].vss=supply.vss;
@@ -238,7 +237,8 @@ namespace tmpl {
             
             OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-            cond.a = in.a;
+            cond.a = in.a; // THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
+            cond.v = _in_c_v_;
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
@@ -257,21 +257,19 @@ namespace tmpl {
             
             //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C2N_RB_X4 out1_f_buf_func[N];
             A_2C2N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
-            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
+            sigbuf<N*4> out_en_buf(.in=_en, .supply=supply);
+            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vdd = supply.vdd, .vss = supply.vss);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out_en_buf.out[i];
+                out1_t_buf_func[i].c1=out_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -282,38 +280,36 @@ namespace tmpl {
                 out1_t_buf_func[i].sr_B = _reset_BXX[i];
                 out1_f_buf_func[i].pr_B = _reset_BXX[i];
                 out1_f_buf_func[i].sr_B = _reset_BXX[i];
-                out1_f_buf_func[i].n2=_c_t_buf[i];
-                out1_t_buf_func[i].n2=_c_t_buf[i];
+                out1_f_buf_func[i].n2=_c_f_buf[i];
+                out1_t_buf_func[i].n2=_c_f_buf[i];
             )
 
             //func buffer out2
-            bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
+            bool _out2_a_B;
             A_2C2N_RB_X4 out2_f_buf_func[N];
             A_2C2N_RB_X4 out2_t_buf_func[N];
-            sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
-            sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
-            INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
-            sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
-            sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
+            // sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
+            INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B, .vdd = supply.vdd, .vss = supply.vss);
+            sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
             (i:N: 
                 out2_f_buf_func[i].y=out2.d.d[i].f;
                 out2_t_buf_func[i].y=out2.d.d[i].t;
-                out2_f_buf_func[i].c1=_en2_X_f[i];
-                out2_t_buf_func[i].c1=_en2_X_t[i];
-                out2_f_buf_func[i].c2=_out2_a_BX_f[i];
-                out2_t_buf_func[i].c2=_out2_a_BX_t[i];
+                out2_f_buf_func[i].c1=out_en_buf.out[i+2*N];
+                out2_t_buf_func[i].c1=out_en_buf.out[i+3*N];
+                out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
+                out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
                 out2_f_buf_func[i].n1=in.d.d[i].f;
                 out2_t_buf_func[i].n1=in.d.d[i].t;
                 out2_f_buf_func[i].vdd=supply.vdd;
                 out2_t_buf_func[i].vdd=supply.vdd;
                 out2_f_buf_func[i].vss=supply.vss;
                 out2_t_buf_func[i].vss=supply.vss;
-                out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].n2=_c_f_buf[i];
-                out2_t_buf_func[i].n2=_c_f_buf[i];
+                out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
+                out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].n2=_c_t_buf[i];
+                out2_t_buf_func[i].n2=_c_t_buf[i];
             )
         }
 
@@ -338,21 +334,19 @@ namespace tmpl {
 
           //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C1N_RB_X4 out1_f_buf_func[N];
             A_2C1N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
+            sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
             INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out1_en_buf.out[i];
+                out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -365,39 +359,42 @@ namespace tmpl {
                 out1_f_buf_func[i].sr_B = _reset_BXX[i];
             )
             //func buffer out2
-            bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
+            bool _out2_a_B;
             A_2C1N_RB_X4 out2_f_buf_func[N];
             A_2C1N_RB_X4 out2_t_buf_func[N];
-            sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
-            sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
+            sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
             INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
-            sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
-            sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
+            sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
             (i:N: 
                 out2_f_buf_func[i].y=out2.d.d[i].f;
                 out2_t_buf_func[i].y=out2.d.d[i].t;
-                out2_f_buf_func[i].c1=_en2_X_f[i];
-                out2_t_buf_func[i].c1=_en2_X_t[i];
-                out2_f_buf_func[i].c2=_out2_a_BX_f[i];
-                out2_t_buf_func[i].c2=_out2_a_BX_t[i];
+                out2_f_buf_func[i].c1=out2_en_buf.out[i];
+                out2_t_buf_func[i].c1=out2_en_buf.out[i+N];
+                out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
+                out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
                 out2_f_buf_func[i].n1=in.d.d[i].f;
                 out2_t_buf_func[i].n1=in.d.d[i].t;
                 out2_f_buf_func[i].vdd=supply.vdd;
                 out2_t_buf_func[i].vdd=supply.vdd;
                 out2_f_buf_func[i].vss=supply.vss;
                 out2_t_buf_func[i].vss=supply.vss;
-                out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
+                out2_t_buf_func[i].pr_B = _reset_BXX[i];
+                out2_t_buf_func[i].sr_B = _reset_BXX[i];
+                out2_f_buf_func[i].pr_B = _reset_BXX[i];
+                out2_f_buf_func[i].sr_B = _reset_BXX[i];
             )
         }
         
         // Demux 
         export template<pint N; pbool CONDITION_SIGN>
-        defproc demux_td (avMx1of2<N> in; avMx1of2<N> out1; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
+        // WARNING WARNING WARNING
+        // With a False CONDITION_SIGN, this is wrong.
+        // the c.t/f just need to be swapped, not inverted!!!
+        defproc demux_td (avMx1of2<N> in; avMx1of2<N> out; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
             //control
             bool _en, _reset_BX,_reset_BXX[N], _out_v, _in_c_v_, _reset_BXt;
+            avMx1of2<N> out1 = out;
+
             
             OR2_X1 out_or(.a=out1.v, .b=token.r, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
@@ -407,6 +404,10 @@ namespace tmpl {
             sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
             //validity
             bool _in_v, _c_tk_buf, _c_d_buf[N], _c_v, cond_inv_t, cond_inv_f;
+
+
+            cond.a = in.a;
+            cond.v = _c_v;
             
             OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
             
@@ -430,21 +431,19 @@ namespace tmpl {
             
             //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C2N_RB_X4 out1_f_buf_func[N];
             A_2C2N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
+            sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
             INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out1_en_buf.out[i];
+                out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -477,6 +476,64 @@ namespace tmpl {
           token_buf.pr_B = _reset_BXt;
           token_buf.sr_B = _reset_BXt;
         }
+
+        /** 
+         * Drops a packet if condition is met, otherwise passes it on.
+         * This is a very lazy implementation, where the cond MUST NOT CHANGE DURING OPERATION.
+         * Means that this should be used in a very small set of circumstances.
+         * 
+         * params:
+         * N: size of packet
+         * CONDITION_DROP: value of cond when packets are dropped.
+         */
+        export template<pint N; pbool CONDITION_DROP>
+        defproc dropper_static (avMx1of2<N> in; avMx1of2<N> out; bool? cond; power supply) {
+            bool _drop, _dropB;
+            INV_X1 inv(.a = cond, .vss = supply.vss, .vdd = supply.vdd);
+
+            [~CONDITION_DROP ->
+                _dropB = cond;
+                _drop = inv.y;
+            [] CONDITION_DROP ->
+                _drop = cond;
+                _dropB = inv.y;
+            ]
+
+            bool _in_vX;
+            vtree<N> vt(.in = in.d, .supply = supply);
+            BUF_X4 in_v_buf(.a = vt.out, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
+            AND2_X1 and2(.a = _drop, .b = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
+            OR2_X1 or2(.a = out.a, .b = and2.y, .vss = supply.vss, .vdd = supply.vdd);
+            A_2C_B_X1 ack_Cel(.c1 = or2.y, .c2 = _in_vX, .y = in.a);
+            // _in_vX = in.v;
+
+            // Sigbufs
+            sigbuf<N*2> sb_dropB(.in = _dropB, .supply = supply);
+            sigbuf<N*2+1> sb_in_v(.in = _in_vX, .supply = supply);
+            sb_in_v.out[2*N] = in.v;
+
+            AND3_X1 and_t[N];
+            AND3_X1 and_f[N];
+            (i:N:
+                and_t[i].a = in.d.d[i].t;
+                and_f[i].a = in.d.d[i].f;
+
+                and_t[i].y = out.d.d[i].t;
+                and_f[i].y = out.d.d[i].f;
+                
+                and_t[i].b = sb_dropB.out[i];
+                and_f[i].b = sb_dropB.out[i+N];
+
+                and_t[i].c = sb_in_v.out[i];
+                and_f[i].c = sb_in_v.out[i+N];
+
+                and_t[i].vss = supply.vss;
+                and_t[i].vdd = supply.vdd;
+            )
+
+
+
+        }
         
         
         export 
@@ -491,23 +548,23 @@ namespace tmpl {
           
         }
         //The buffer_t_valid doesn't work
-        export 
-        defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
-        {
-            //control
-            bool _en, _reset_BX;
-            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-            A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
+        // export 
+        // defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
+        // {
+        //     //control
+        //     bool _en, _reset_BX;
+        //     A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+        //     A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
             
-            //function
-            bool _out_a_B;
-            INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
-            A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
+        //     //function
+        //     bool _out_a_B;
+        //     INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
+        //     A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
 
             
-            //reset buffers
-            BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-        }
+        //     //reset buffers
+        //     BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+        // }
 
         
 
@@ -524,7 +581,7 @@ namespace tmpl {
           bool _in1_arb,_in2_arb,_in1_arb_X[2*N],_in2_arb_X[2*N];
           A_4C_RB_X4 in1ack_ctl(.c1=_in1_arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
           A_4C_RB_X4 in2ack_ctl(.c1=_in2_arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-          A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .n1 = in1.a,.n2 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
+          A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .na1 = in1.a,.nb1 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
           sigbuf<2*N> en_buffer(.in = _en,.out = _en_X,.supply=supply);
           INV_X1 in1ack_ctl_inv(.a=in1.a,.y=_in1_a_B,.vdd=supply.vdd,.vss=supply.vss);
           INV_X1 in2ack_ctl_inv(.a=in2.a,.y=_in2_a_B,.vdd=supply.vdd,.vss=supply.vss);
@@ -555,10 +612,10 @@ namespace tmpl {
           (i:N: 
             merge_func_t[i].c1 = _en_X[i];
             merge_func_t[i].c2 = _out_a_BX[i];
-            merge_func_t[i].n1 = _in1_arb_X[i];
-            merge_func_t[i].n2 = in1.d.d[i].t;
-            merge_func_t[i].n3 = _in2_arb_X[i];
-            merge_func_t[i].n4 = in2.d.d[i].t;
+            merge_func_t[i].na1 = _in1_arb_X[i];
+            merge_func_t[i].na2 = in1.d.d[i].t;
+            merge_func_t[i].nb1 = _in2_arb_X[i];
+            merge_func_t[i].nb2 = in2.d.d[i].t;
             merge_func_t[i].y = out.d.d[i].t;
             merge_func_t[i].vdd=supply.vdd;
             merge_func_t[i].vss=supply.vss;
@@ -567,10 +624,10 @@ namespace tmpl {
 
             merge_func_f[i].c1 = _en_X[i+N];
             merge_func_f[i].c2 = _out_a_BX[i+N];
-            merge_func_f[i].n1 = _in1_arb_X[i+N];
-            merge_func_f[i].n2 = in1.d.d[i].f;
-            merge_func_f[i].n3 = _in2_arb_X[i+N];
-            merge_func_f[i].n4 = in2.d.d[i].f;
+            merge_func_f[i].na1 = _in1_arb_X[i+N];
+            merge_func_f[i].na2 = in1.d.d[i].f;
+            merge_func_f[i].nb1 = _in2_arb_X[i+N];
+            merge_func_f[i].nb2 = in2.d.d[i].f;
             merge_func_f[i].y = out.d.d[i].f;
             merge_func_f[i].vdd=supply.vdd;
             merge_func_f[i].vss=supply.vss;
@@ -690,26 +747,26 @@ namespace tmpl {
         // Is useful for testing purposes.
         // But should probably remove before running innovus etc.
         export template<pint N>
-        defproc delay_fifo (bool out; bool in; power supply) {
+        defproc delay_chain (bool out; bool in; power supply) {
             { N >= 0 : "What?" };
             [N >= 1 ->
-            DLY4_X1 dly[N];
+              DLY4_X1 dly[N];
 
-            dly[0].vdd = supply.vdd;
-            dly[0].vss = supply.vss;
-            dly[0].a = in;
+              dly[0].vdd = supply.vdd;
+              dly[0].vss = supply.vss;
+              dly[0].a = in;
 
-            (i:1..N-1:
-                dly[i].vdd = supply.vdd;
-                dly[i].vss = supply.vss;
-                dly[i].a = dly[i-1].y;
-            )
+              (i:1..N-1:
+                  dly[i].vdd = supply.vdd;
+                  dly[i].vss = supply.vss;
+                  dly[i].a = dly[i-1].y;
+              )
 
-            dly[N-1].vdd = supply.vdd;
-            dly[N-1].vss = supply.vss;
-            dly[N-1].y = out;
+              dly[N-1].vdd = supply.vdd;
+              dly[N-1].vss = supply.vss;
+              dly[N-1].y = out;
             [] N = 0 ->
-            in = out;
+              in = out;
             ]
             
         }
@@ -732,7 +789,7 @@ namespace tmpl {
         {
             { N >= 0 : "What?" };
             { NVAL >= 0 : "What?" };
-            { NVAL < 1<<VAL : "VAL too big!" };
+            { VAL < 1<<NVAL : "VAL too big!" };
 
             // valid tree
             vtree<N> in_val(.supply = supply);
@@ -767,8 +824,93 @@ namespace tmpl {
             )
 
         }
+/**
+* Drops bits. Slices lines. Crop in. Enhance.
+* Useful if say, have an 8 bit packet coming in, but 
+* receiver only needs 3 of them.
+* KEEPS all bits between the two bounds.
+* e.g. drop_lines(8, 0, 3) would keep lines [0,1,2]
+**/
+export template<pint N, N0, N1>
+defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out; power supply) {
+    // {N0 >= 0 : "N0 can be minimum 0!"};
+    // {N1 <= N : "N1 can be maximum N"};
+
+    pint _N1, _N0;
+
+    _N1 = std::min(N1,N);
+    _N0 = std::max(N0,0);
+
+    [_N0 = 0 & _N1 = N ->
+      in = out;
+    [] _N0 != 0 | _N1 != N ->
+
+      vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
+      (i:_N1-_N0:
+          in.d.d[i + _N0] = out.d.d[i];
+      )
+
+      // in.a = out.a;
+
+      A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
+
+    ]
 
 
 
+}
+
+
+  export template<pint N; pint CONDITION_BIT>
+        defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
+        {
+            demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
+
+            in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
+            in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
+
+            A_2C_B_X1 val_Cel(.c1 = demux.in.v, .c2 = demux.cond.v, .y = in.v,
+                .vdd = supply.vdd, .vss = supply.vss);
+
+            // Not actually needed bc the current version of demux
+            // Something like below should be added once the handshakes are properly decoupled.
+            // wires the data and cond ack lines together anyway.
+            // A_2C_B_X1 ack_Cel(.c1 = demux.in.a, .c2 = demux.cond.a, .y = in.a,
+            //     .vdd = supply.vdd, .vss = supply.vss);
+
+            // in.v = demux.in.v;
+            in.a = demux.in.a;
+
+            (i:0..CONDITION_BIT-1:
+                in.d.d[i].f = demux.in.d.d[i].f;
+                in.d.d[i].t = demux.in.d.d[i].t;)
+
+            (i:CONDITION_BIT+1..N:
+                in.d.d[i].f = demux.in.d.d[i-1].f;
+                in.d.d[i].t = demux.in.d.d[i-1].t;)
+
+        }
+
+      export template<pint N>
+        defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
+        {
+            demux_bit<N,N> demux(.in = in, .out1 = out1, .out2 = out2, .reset_B = reset_B, .out1=out1, .out2=out2);
+        }
+
+/**
+* Create M sigbufs to buffer an M bool array to N strength.
+* Done lazily.
+**/
+export template<pint M, N>
+defproc sigbuf_boolarray(bool? in[M]; bool! out[M]; power supply) {
+    sigbuf<N> sb[M];
+    (i:M:
+        sb[i].in = in[i];
+        sb[i].out[0] = out[i];
+        sb[i].supply = supply;
+    )
+
+}
+
 
 }}

dataflow_neuro/registers.act

@@ -39,219 +39,311 @@ open std::channel;
 
 namespace tmpl {
     namespace dataflow_neuro {
-// Circuit for storing registers using AER
-// The block has the parameters:
-// lognw -> log2(number of words), parameters you can store
-// wl -> word length, length of each word 
-// N_dly_cfg -> the number of config bits in the ACK delay line
-// The block has the pins:
-// in -> input data,
-//        - the first bit is write/read_B
-//        - the next lognw bits describe the location, 
-//        - the last wl the word to write
-// data -> the data saved in the flip flop, sized wl x nw
-export template<pint lognw,wl,N_dly_cfg>
-defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
-    bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
-    pint nw = 1<<lognw;
-    //Validation of the input 
-    vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
-    sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
-    // Generation of the fake clock pulse (inverted because the ff clocks are low_active)
-    delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
-    INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
-    sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
-    // Sending back to the ackowledge
-    delayprog<N_dly_cfg> ack_dly(.in = _clock_temp_inv, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
-    sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
-    //Reset Buffers
-    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
-    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
-    // Creating the different flip flop arrays
-    bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
-    andtree<lognw> atree[nw];
-    AND2_X1 and_encoder[nw];
-    sigbuf<wl> clock_buffer[nw];
-    DFFQ_R_X1 ff[nw*wl];
-    pint bitval;
-    (k:nw:atree[k].supply = supply;)
-    (word_idx:nw:
-        // Decoding the bit pattern to understand which word we are looking at
-        (pin_idx:lognw:
-            bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
-            [bitval = 1 -> 
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
-            [] bitval = 0 ->
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
-            []bitval >= 2 -> {false : "fuck"};
-            ]
-        )
-        // Activating the fake clock for the right word
-        atree[word_idx].out = _out_encoder[word_idx];    
-        and_encoder[word_idx].a = _out_encoder[word_idx];
-        and_encoder[word_idx].b = _clock;
-        and_encoder[word_idx].y = _clock_word_temp[word_idx];
-        and_encoder[word_idx].vdd = supply.vdd;
-        and_encoder[word_idx].vss = supply.vss;
-        clock_buffer[word_idx].in = _clock_word_temp[word_idx];
-        clock_buffer[word_idx].supply = supply;
-        // Describing all the FF and their connection
-        (bit_idx:wl:
-            ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
-            ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
-            ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
-            ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
-            ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
-            ff[bit_idx+word_idx*(wl)].vss = supply.vss;
-        )
-    )
-    }
 
-// Circuit for storing  and reading registers using AER
-// The block has the parameters:
-// lognw -> log2(number of words), parameters you can store
-// wl -> word length, length of each word 
-// N_dly_cfg -> the number of config bits in the ACK delay line
-// The block has the pins:
-// in -> input data,
-//        - the MSB is write/read_B
-//        - the next MSB bits (size lognw) are the location, 
-//        - the LSB (size wl) are the word to write
-// out -> in case a reading phase is required, the output is used to show the stored data
-//        - the MSB bits (size lognw) tell the read register
-//        - the LSB bits (size wl) tell the word read
-// data -> the data saved in the flip flop, sized wl x nw
-export template<pint lognw,wl,N_dly_cfg>
-defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
-    pint nw = 1<<lognw;
-    bool _in_v_temp,_in_a_temp,_clock_temp,_clock[nw],_clock_temp_inv, _in_a_write, _in_a_read;
-    //Validation of the input 
-    vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
-    sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
-    // Acknowledgment
-    OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
-    sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
-    // WRITE
-        // Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
-        bool _in_v_temp_write;
-        AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f,.y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
-        delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
-        INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
-        sigbuf<nw> clk_X(.in = _clock_temp_inv, .out = _clock,.supply = supply);
-        sigbuf<wl> clock_buffer[nw];
-        bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
-        // Sending back to the acknowledge
-        bool _in_a_write_temp;
-        delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
-        AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
-    // READ
-        //Outputing the word to read
-        AND2_X1 word_to_read[nw];
-        sigbuf<wl*2> word_to_read_X[nw];
-        ortree<nw> bitselector_t[wl];
-        ortree<nw> bitselector_f[wl];
-        AND2_X1 word_selector_t[nw*wl];
-        AND2_X1 word_selector_f[nw*wl];
-        buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
-        AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
-        // Outputting the address if the read is true
-        (i:lognw:
-            address_propagator_t[i].a = in.d.d[lognw+wl].t;
-            address_propagator_t[i].b = in.d.d[i+wl].t;
-            address_propagator_t[i].y = output_buf.in.d.d[i+wl].t;
-            address_propagator_t[i].vdd = supply.vdd;
-            address_propagator_t[i].vss = supply.vss;
-            
-            address_propagator_f[i].a = in.d.d[lognw+wl].t;
-            address_propagator_f[i].b = in.d.d[i+wl].f;
-            address_propagator_f[i].y = output_buf.in.d.d[i+wl].f;
-            address_propagator_f[i].vdd = supply.vdd;
-            address_propagator_f[i].vss = supply.vss;
-        )
-        AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
-    //Reset Buffers
-    bool _reset_BX, _reset_BXX[nw],_reset_mem_BX,_reset_mem_BXX[nw*wl];
-    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<nw*wl> reset_mem_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
-    sigbuf<nw> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
 
-    //Creating the encoder
-    andtree<lognw> atree[nw];
-    OR2_X1 or_encoder[nw];
-    INV_X1 inv_encoder[nw];
-    // Creating the different flip flop arrays
-    bool _out_encoder[nw];
-    DFFQ_R_X1 ff[nw*wl];
-    AND2_X1 val_chck[nw*wl];
-    bool _val_chck_out[nw*wl];
-    bool _in_v_temp_buf[nw*wl];
-    sigbuf<nw*wl> v_buf(.in = _in_v_temp,.out = _in_v_temp_buf,.supply = supply);
+/**
+ * A single register made out of A cells.
+ * MSB is whether to read or write.
+ * Currently only handles writing.
+ * NOTE: this does not handle in.v properly, and instead has in.v = in.a
+ */
+export template<pint N>
+defproc register_acells_improved(avMx1of2<N+1> in; Mx1of2<N> out;
+    bool? reset_B; power supply) {
+
+bool _resetX[N], _reset_BX[N];
+bool _en, _enBX;
+bool _flush, _flushBX;
+bool _out_v, _out_vB;
+bool _w = in.d.d[N].t;
+
+INV_X2 out_val_inv(.a = _out_v, .y = _out_vB,
+    .vdd = supply.vdd, .vss= supply.vss);
+
+// Reset sigs
+INV_X1 reset_inv(.a = reset_B, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N> reset_sb(.in = reset_inv.y, .out = _resetX, .supply = supply);
+sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
+
+A_2C1N_RB_X1 A_flush(.c1 = _en, .c2 = _out_v, .n1 = _w, .y = _flush,
+    .vdd = supply.vdd, .vss = supply.vss, .pr_B = _reset_BX[0], .sr_B = _reset_BX[0]);
+
+A_2C_X1 A_en(.c1  = _w, .c2 = _out_vB, .y = _en,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+INV_X1 flush_inv(.a = _flush, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_flushB(.in = flush_inv.y, .supply = supply);
+sb_flushB.out[0] = _flushBX;
+
+INV_X1 en_inv(.a = _en, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_enB(.in = en_inv.y, .supply = supply);
+sb_enB.out[0] = _enBX;
+
+vtree<N> vc(.in = out, .out = _out_v, .supply = supply);
+
+// WARNING WARNING
+in.v = in.a;
+
+A_1C1P_X1 A_ack(.c1 = _en, .p1 = _out_vB, .y = in.a,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+//function
+A_2C1N_SB_X4 f_buf_func[N];
+A_2C1N_RB_X4 t_buf_func[N];
+(i:N: 
+    f_buf_func[i].y=out.d[i].f;
+    t_buf_func[i].y=out.d[i].t;
+
+    f_buf_func[i].c1=_flushBX;
+    t_buf_func[i].c1=_flushBX;
+
+    f_buf_func[i].c2=_enBX;
+    t_buf_func[i].c2=_enBX;
     
-    // For loop for assigning the different components
-    pint bitval;
-    (k:nw:atree[k].supply = supply;)
-    (word_idx:nw:
-        // Decoding the bit pattern to understand which word we are looking at
-        (pin_idx:lognw:
-            bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
-            [bitval = 1 -> 
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
-            [] bitval = 0 ->
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
-            []bitval >= 2 -> {false : "fuck"};
-            ]
-        )
-        // WRITE: Activating the fake clock for the right word
-        atree[word_idx].out = _out_encoder[word_idx];    
-        inv_encoder[word_idx].a = _out_encoder[word_idx];
-        inv_encoder[word_idx].y = or_encoder[word_idx].a;
-        inv_encoder[word_idx].vdd = supply.vdd;
-        inv_encoder[word_idx].vss = supply.vss;
-        or_encoder[word_idx].b = _clock[word_idx];
-        or_encoder[word_idx].y = _clock_word_temp[word_idx];
-        or_encoder[word_idx].vdd = supply.vdd;
-        or_encoder[word_idx].vss = supply.vss;
-        clock_buffer[word_idx].in = _clock_word_temp[word_idx];
-        clock_buffer[word_idx].supply = supply;
-        // READ: Selecting the right word to read if read is high
-        word_to_read[word_idx].a = in.d.d[lognw+wl].t;
-        word_to_read[word_idx].b = _out_encoder[word_idx];
-        word_to_read[word_idx].y = word_to_read_X[word_idx].in;
-        word_to_read[word_idx].vdd = supply.vdd;
-        word_to_read[word_idx].vss = supply.vss;
-        word_to_read_X[word_idx].supply = supply;
+    f_buf_func[i].n1=in.d.d[i].f;
+    t_buf_func[i].n1=in.d.d[i].t;
 
-        
-        (bit_idx:wl:
-            // Describing all the FF and their connection
-            val_chck[bit_idx].a = _in_v_temp_buf[word_idx+bit_idx];
-            val_chck[bit_idx].b = in.d.d[bit_idx].t;
-            val_chck[bit_idx].y = _val_chck_out[bit_idx];
-            val_chck[bit_idx].vdd = supply.vdd;
-            val_chck[bit_idx].vss = supply.vss;
-            ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
-            ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
-            ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
-            ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
-            ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
-            ff[bit_idx+word_idx*(wl)].vss = supply.vss;
-            // READ: creating the selectors for propagating the right word
-            word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+(word_idx*(wl))].a;
-            word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+(word_idx*(wl))].a;
-            word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q;
-            word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
-            word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q_B;
-            word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
-            bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
-            bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
-            bitselector_t[bit_idx].supply = supply;
-            bitselector_f[bit_idx].supply = supply;
-        )
+    f_buf_func[i].vdd=supply.vdd;
+    t_buf_func[i].vdd=supply.vdd;
+    f_buf_func[i].vss=supply.vss;
+    t_buf_func[i].vss=supply.vss;
+    
+    f_buf_func[i].pr = _resetX[i];
+    f_buf_func[i].sr = _resetX[i];
+    t_buf_func[i].pr_B = _reset_BX[i];
+    t_buf_func[i].sr_B = _reset_BX[i];
+)
+
+}
+
+
+
+
+/** 
+ * Array of registers made out of A-cells
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * [-addr-][-word-][r/w]
+ */
+export template<pint NcA, NcW, M>
+defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
+    bool? reset_B; power supply) {
+
+
+// Input valid tree
+vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+bool _write_ack;
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+// Bit to join the acks either from read or write
+bool _read_ack;
+_read_ack = out.a;
+OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
+    .vdd = supply.vdd, .vss = supply.vss);
+A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
+
+// Write bit selector
+bool _w = in.d.d[NcA+NcW].t;
+bool _wX[M];
+sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
+A_2C_B_X1 write_selectors[M];
+(i:M:
+    write_selectors[i].c1 = _wX[i];
+    write_selectors[i].c2 = decoder.out[i];
+    write_selectors[i].vdd = supply.vdd;
+    write_selectors[i].vss = supply.vss;
+)
+
+
+// Registers
+register_acells_improved<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
     )
-    }
+
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcW].t = write_selectors[i].y;
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
+
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
+
+    // Connect outputs
+    data[i] = registers[i].out;
+
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+// Read bit selector
+bool _r = in.d.d[NcA+NcW].f;
+bool _rX[M+NcA];
+sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
+A_2C_B_X1 read_selectors[M];
+sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
+(i:M:
+    read_selectors[i].c1 = _rX[i];
+    read_selectors[i].c2 = decoder.out[i];
+    read_selectors[i].vdd = supply.vdd;
+    read_selectors[i].vss = supply.vss;
+
+    read_selectorsX.in[i] = read_selectors[i].y;
+)
+
+// OrTrees for each output word bit on read
+ortree<M> out_ortrees_t[NcW];
+ortree<M> out_ortrees_f[NcW];
+(i:NcW:
+    out_ortrees_t[i].out = out.d.d[i+NcA].t;
+    out_ortrees_f[i].out = out.d.d[i+NcA].f;
+
+    out_ortrees_t[i].supply = supply;
+    out_ortrees_f[i].supply = supply;
+)
+
+// ANDs over each reg's data
+// and whether it is selected for read.
+AND2_X1 and_reads_t[NcW * M];
+AND2_X1 and_reads_f[NcW * M];
+pint index;
+(i:NcW:
+    (j:M:
+        index = i + j*NcW;
+
+        and_reads_t[index].a = data[j].d[i].t;
+        and_reads_t[index].b = read_selectorsX.out[j];
+        and_reads_f[index].a = data[j].d[i].f;
+        and_reads_f[index].b = read_selectorsX.out[j];
+
+        and_reads_t[index].y = out_ortrees_t[i].in[j];
+        and_reads_f[index].y = out_ortrees_f[i].in[j];
+
+        and_reads_t[index].vss = supply.vss;
+        and_reads_t[index].vdd = supply.vdd;
+        and_reads_f[index].vss = supply.vss;
+        and_reads_f[index].vdd = supply.vdd;
+    )
+
+)
+
+// C elements passing address to out on read.
+A_2C_B_X1 addr_read_t[NcA];
+A_2C_B_X1 addr_read_f[NcA];
+(i:NcA:
+    addr_read_t[i].c1 = in.d.d[i].t;
+    addr_read_f[i].c1 = in.d.d[i].f;
+
+    addr_read_t[i].c2 = _rX[M+i];
+    addr_read_f[i].c2 = _rX[M+i];
+
+    addr_read_t[i].y = out.d.d[i].t;
+    addr_read_f[i].y = out.d.d[i].f;
+
+    addr_read_t[i].vdd = supply.vdd;
+    addr_read_t[i].vss = supply.vss;
+    addr_read_f[i].vdd = supply.vdd;
+    addr_read_f[i].vss = supply.vss;
+
+
+)
+
+
+
+}
+
+
+
+
+
+
+/** 
+ * Array of registers made out of A-cells.
+ * !!!Registers ONLY have write functionality!!!
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * LSB [-addr-][-word-] MSB
+ */
+export template<pint NcA, NcW, M>
+defproc register_w_array(avMx1of2<NcA + NcW> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
+    bool? reset_B; power supply) {
+
+
+// Input valid tree
+vtree<NcA + NcW> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+bool _write_ack;
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+A_2C_B_X1 ack_safety(.c1 = _write_ack, .c2 = in.v, .y = in.a);
+
+
+// Registers
+register_acells_improved<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
+    )
+
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcW].t = decoder.out[i];
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
+
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
+
+    // Connect outputs
+    data[i] = registers[i].out;
+
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+
+}
+
+
 
 
 }}

dataflow_neuro/treegates.act

@@ -418,7 +418,7 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
 {
 
   { N >= 0 : "sigbuf: parameter error" };
-  { N <= 43 : "sigbuf: parameter error, N too big" };
+//  { N <= 43 : "sigbuf: parameter error, N too big" };
 
 	  /* -- just use in sized driver here -- */
     [ N <= 4 ->
@@ -433,8 +433,18 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
     BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
    [] N >= 19 & N <= 29 -> 
     BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
-   [] N >= 30 & N <= 42 -> 
+   [] N >= 30 & N<= 48-> 
     BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 49 & N <= 64 -> 
+    BUF_X16 buf16 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 65 & N <= 96 -> 
+    BUF_X24 buf24 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 97 -> 
+    BUF_X32 buf32 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+  //  [] N >= 129 & N <=192 -> 
+  //   BUF_X48 buf48 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+  // [] N >= 193 & N <= 256-> 
+  //   BUF_X64 buf64 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
    ]
    (i:1..N-1:out[i]=out[0];)
 }
@@ -445,7 +455,7 @@ defproc sigbuf_1output (bool? in; bool! out; power supply)
 {
 
   { N >= 0 : "sigbuf: parameter error" };
-  { N <= 43 : "sigbuf: parameter error, N too big" };
+  { N <= 43 : "sigbuf: parameter error, N too big" }; 
 
     /* -- just use in sized driver here -- */
     [ N <= 4 ->

test/prsim_plot.py

@@ -99,10 +99,18 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 		if len(r) >= 1:
 			include_all_times = True
 
+
+	# Check if user gave "nowarn" flag
+	plot_warn = True
+	for arg in argv:
+		r = re.findall(r'(-nowarn?)', arg)
+		if len(r) >= 1:
+			plot_warn = False
+
 	# Get list of all times (before filtering)
 	unique_times = np.unique([int(e[0]) for e in entries])
 
-	assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
+	# assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
 	if include_given: print(f"Including signals that match regex {include_re}")
 	if exclude_given: print(f"Excluding signals that match regex {exclude_re}")
 
@@ -225,8 +233,8 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 		ax.text(time_to_index(time), num_sigs, time, ha = "center", va = "top", size = 10, rotation = 90)
 
 	# Find and plot wrong Assert statements
-	asserts = re.findall(r"\t *(\d+) .*\nWRONG ASSERT:\t(.+)", f)
-	if len(asserts): print("Failed asserts found!")
+	asserts = re.findall(r"\t *(\d+) .*\n(WRONG ASSERT|WARNING):\t?(.+)", f)
+	if len(asserts): print("Warnings found!")
 	for a in asserts:
 		print(a)
 		time = int(a[0])
@@ -234,11 +242,12 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 			try:
 				time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
 			except:
-				print(f"Couldn't find an appropriate time for assert {a}")
+				print(f"Couldn't find an appropriate time for warning {a}")
 				continue
 		index = time_to_index(time)
-		ax.axvline(index+0.5, c = "red", lw = 2)
-		ax.text(index+0.5, -1, a[1], rotation = 90, ha = "center", va = "bottom", c = "red")
+		if plot_warn:
+			ax.axvline(index+0.5, c = "red", lw = 2)
+			ax.text(index+0.5, -1, a[2], rotation = 90, ha = "center", va = "bottom", c = "red")
 
 	# Find echoed statements of the form "[digits] text"
 	echoes = re.findall(r"\t *(\d+) [^\t]*\n(\[\d*\].+)", f)

test/repeat_unit.sh

@@ -1,85 +1,94 @@
-# repeatedly run prsim on one unit_test's PRs
+#!/bin/sh
 
+fail=0
+faildirs=""
+proc=""
 bold=$(tput bold)
 normal=$(tput sgr0)
 und=$(tput smul)
-i=${unit}
-proc="$i<>"
 
-echo ""
-echo "${bold}******************************************"
-echo "* ${i} repetitions , show warnings=${warning}*"
-echo "******************************************${normal}"
+faildirs=""
+failed=0
+iteration=0
+numberofruns=100
+
+#
+#  run_test name [option]
+#
+run_test () {
+    echo "Testing ${bold}$1 ${normal} for $2 random delay runs"
+    # clear run directory
+    if [ -d $1/run ]; then
+	    rm -rf $1/run
+    fi
+    mkdir $1/run
+    cp init.prs $1/run/test.prs
+    if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
+            echo "random_seed $2" > $1/run/prsim.in
+	    cat init_qdi.prsim $1/test.prsim >> $1/run/prsim.in
+	    cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
+	    if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
+	        echo "${bold}*** simulation failed seed: $2 ***${normal}"
+	        faildirs="${faildirs} ${1}-sim($2)"
+	        failed=1
+	        echo	
+	    fi
+    else
+	    echo "${bold}*** circuit construction failed ***${normal}"
+	    faildirs="${faildirs} ${1}-ckt"
+	    failed=1
+        echo
+    fi
+}
+
+if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
+    echo "${bold}Error:${bold} aflat & prsim necessary for tests."
+    exit 1
+fi
+
+if [ ! -d "unit_tests" ];
+then
+    echo "${bold}Error:${bold} no unit_tests directory."
+    exit 1
+fi    
 
 cd "unit_tests"
-echo "${bold}... checking aflat${normal}"
 
-# check aflat
-if ($ACT_HOME/bin/aflat "$i/test_final.act" > "$i/test.prs");
-then
-    echo "${bold}... aflat complete, checking in prsim${normal}"
-    
-  # run prsim on prs
-    (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test.prsim") > "$i/prsim.out");
-    if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found")
-    then
-        echo "FAILED in first prsim"
-    else
-        
-        # show warnings setting
-        if [ "${warning}" = "1" ];
-        then
-          echo "${bold}Exit on prsim warnings turned ON${normal}"
-        else
-          echo "${bold}Exit on prsim warnings turned OFF${normal}"
-        fi
-        echo ""
-        
-        # begin prsim test loop
-        has_failed=0
-        iter=0
-        echo "${bold}using random_seed${normal}"
-        echo "\nusing random_seed" >> "$i/prsim.out"
-        while [ has_failed=0 ]
-        do
-            # write prsim test file with random seed appended to top of file
-            (echo "random_seed $iter \nrandom" > "$i/test_rand.prsim");
-            (cat "$i/test.prsim" >> "$i/test_rand.prsim");
-            (echo "\nTEST $iter\n" >> "$i/prsim.out");
-            
-            # validate prsim output
-            if (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test_rand.prsim") >> "$i/prsim.out");
-            then
-                if [ "${warning}" = "1" ];
-                then
-                  if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found" -e "WARNING:");
-                  then
-                      echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
-                      has_failed=1
-                      exit 0
-                  else
-                      echo "==> passed test #${iter}"
-                      iter=$(($iter + 1))
-                  fi
-                else
-                  if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found");
-                  then
-                      echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
-                      has_failed=1
-                      exit 0
-                  else
-                      echo "==> passed test #${iter}"
-                      iter=$(($iter + 1))
-                  fi
-                fi
-            else
-                has_failed=1
-                exit 0
-            fi
-        done
-        (cd ".."; pwd);
-        exit 1
-    fi
-else
-    echo "FAILED in aflat conversion"
+# run all test except single one is specified
+if [ ! -z $3 ]; then 
+  iteration=$3
 fi
+if [ ! -z $2 ]; then 
+  numberofruns=$2
+fi
+  
+if [ -z $1 ]; then
+    for i in *
+    do
+        if [ -d $i -a -f $i/test.act ]; then
+        	while [ $iteration -lt $numberofruns ]
+        	do
+	        	run_test $iteration
+                iteration=$iteration+1
+	        done 
+        fi
+    done
+else
+       while [ $iteration -lt $numberofruns ]
+       do
+	       run_test $1 $iteration
+           iteration=$((iteration+1))
+       done 
+    
+fi
+
+if [ $failed -eq 1 ]; then
+    echo ""
+    echo "${bold}*********************************"
+    echo "* FAILED DIRECTORIES:${normal}$faildirs ${bold}*"
+    echo "*********************************${normal}"
+fi
+
+exit $failed
+
+

test/run.sh

@@ -22,7 +22,8 @@ run_test () {
     mkdir $1/run
     cp init.prs $1/run/test.prs
     if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
-	    cat init_qdi.prsim $1/test.prsim | prsim -r $1/run/test.prs > $1/run/prsim.out
+	    cat init_qdi.prsim $1/test.prsim > $1/run/prsim.in
+	    cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
 	    if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
 	        echo "${bold}*** simulation failed ***${normal}"
 	        faildirs="${faildirs} ${1}-sim"

test/unit_tests/arbtree_5/run/prsim.out

@@ -1,85 +1,2 @@
-t.in[0] t.out t.in[2] t.in[3] t.at.tmp[6] t.at.tmp[5] t.at.tmp[8] t.in[4] t.at.arbs[1]._y t.in[1] t.at.arbs[2]._y t.at.arbs[3]._y t.at.arbs[0]._y 
+t.at.arbs[2]._y1_arb t.in[2].r t.at.arbs[0].ack_cell1._y t.at.arbs[0]._y1_arb t.at.tmp[6].a t.at.arbs[1]._y1_arb t.at.arbs[3]._y1_arb t.in[1].a t.out.r t.in[4].r t.at.tmp[8].a t.at.tmp[5].r t.in[1].r t.in[3].r t.in[0].r t.at.tmp[6].r t.at.arbs[0].ack_cell2._y t.in[3].a t.at.tmp[8].r t.at.tmp[5].a t.at.arbs[2]._y2_arb t.in[0].a t.at.arbs[2].arbiter._y1 t.at.arbs[3]._y2_arb t.in[2].a t.out.a t.at.arbs[1].arbiter._y2 t.at.arbs[0].arbiter._y1 t.in[4].a t.at.arbs[2].arbiter._y2 t.at.arbs[0]._y2_arb t.at.arbs[3].ack_cell2._y t.at.arbs[2].ack_cell2._y t.at.arbs[1]._y2_arb t.at.arbs[1].or_cell._y t.at.arbs[1].arbiter._y1 t.at.arbs[3].arbiter._y1 t.at.arbs[3].ack_cell1._y t.at.arbs[0].or_cell._y t.at.arbs[1].ack_cell2._y t.at.arbs[2].ack_cell1._y t.at.arbs[3].arbiter._y2 t.at.arbs[0].arbiter._y2 t.at.arbs[2].or_cell._y t.at.arbs[1].ack_cell1._y t.at.arbs[3].or_cell._y 
 0
-1
-	         0 t.in[0] : 0
-	         0 t.in[4] : 0
-	         0 t.in[3] : 0
-	         0 t.in[2] : 0
-	         0 t.in[1] : 0
-	         1 t.at.arbs[1]._y : 1  [by t.in[2]:=0]
-	      7092 t.at.arbs[0]._y : 1  [by t.in[1]:=0]
-	      7094 t.at.tmp[5] : 0  [by t.at.arbs[0]._y:=1]
-	     10468 t.at.tmp[6] : 0  [by t.at.arbs[1]._y:=1]
-	     15221 t.at.arbs[2]._y : 1  [by t.at.tmp[6]:=0]
-	     16358 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	     16472 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	     81838 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting all low
-[] setting bit 0 high
-	     81838 t.in[0] : 1
-	     83564 t.at.arbs[0]._y : 0  [by t.in[0]:=1]
-	     83603 t.at.tmp[5] : 1  [by t.at.arbs[0]._y:=0]
-	     83618 t.at.arbs[2]._y : 0  [by t.at.tmp[5]:=1]
-	     84109 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	     84122 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	     84162 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	     84162 t.in[0] : 0
-	     84577 t.at.arbs[0]._y : 1  [by t.in[0]:=0]
-	     84597 t.at.tmp[5] : 0  [by t.at.arbs[0]._y:=1]
-	     90658 t.at.arbs[2]._y : 1  [by t.at.tmp[5]:=0]
-	     90705 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	     90721 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    134819 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 1 high
-	    134819 t.in[1] : 1
-	    148543 t.at.arbs[0]._y : 0  [by t.in[1]:=1]
-	    148547 t.at.tmp[5] : 1  [by t.at.arbs[0]._y:=0]
-	    157676 t.at.arbs[2]._y : 0  [by t.at.tmp[5]:=1]
-	    157691 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	    200939 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	    237870 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	    237870 t.in[1] : 0
-	    237925 t.at.arbs[0]._y : 1  [by t.in[1]:=0]
-	    289578 t.at.tmp[5] : 0  [by t.at.arbs[0]._y:=1]
-	    319358 t.at.arbs[2]._y : 1  [by t.at.tmp[5]:=0]
-	    333207 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	    358019 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    372362 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 2 high
-	    372362 t.in[2] : 1
-	    372784 t.at.arbs[1]._y : 0  [by t.in[2]:=1]
-	    421498 t.at.tmp[6] : 1  [by t.at.arbs[1]._y:=0]
-	    421499 t.at.arbs[2]._y : 0  [by t.at.tmp[6]:=1]
-	    421500 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	    441705 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	    441987 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	    441987 t.in[2] : 0
-	    442755 t.at.arbs[1]._y : 1  [by t.in[2]:=0]
-	    442758 t.at.tmp[6] : 0  [by t.at.arbs[1]._y:=1]
-	    465199 t.at.arbs[2]._y : 1  [by t.at.tmp[6]:=0]
-	    465750 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	    466821 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    467775 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 3 high
-	    467775 t.in[3] : 1
-	    468856 t.at.arbs[1]._y : 0  [by t.in[3]:=1]
-	    523326 t.at.tmp[6] : 1  [by t.at.arbs[1]._y:=0]
-	    524308 t.at.arbs[2]._y : 0  [by t.at.tmp[6]:=1]
-	    524326 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	    528339 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	    532342 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	    532342 t.in[3] : 0
-	    577243 t.at.arbs[1]._y : 1  [by t.in[3]:=0]
-	    598827 t.at.tmp[6] : 0  [by t.at.arbs[1]._y:=1]
-	    603587 t.at.arbs[2]._y : 1  [by t.at.tmp[6]:=0]
-	    604089 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	    604292 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    606146 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 4 high
-	    606146 t.in[4] : 1
-	    606285 t.at.arbs[3]._y : 0  [by t.in[4]:=1]
-	    642631 t.out : 1  [by t.at.arbs[3]._y:=0]

test/unit_tests/arbtree_5/run/test.prs

@@ -1,55 +1,321 @@
 = "GND" "GND"
 = "Vdd" "Vdd"
 = "Reset" "Reset"
-"t.at.arbs[0].a"|"t.at.arbs[0].b"->"t.at.arbs[0]._y"-
-~("t.at.arbs[0].a"|"t.at.arbs[0].b")->"t.at.arbs[0]._y"+
-"t.at.arbs[0]._y"->"t.at.arbs[0].y"-
-~("t.at.arbs[0]._y")->"t.at.arbs[0].y"+
-"t.at.arbs[1].a"|"t.at.arbs[1].b"->"t.at.arbs[1]._y"-
-~("t.at.arbs[1].a"|"t.at.arbs[1].b")->"t.at.arbs[1]._y"+
-"t.at.arbs[1]._y"->"t.at.arbs[1].y"-
-~("t.at.arbs[1]._y")->"t.at.arbs[1].y"+
-"t.at.arbs[2].a"|"t.at.arbs[2].b"->"t.at.arbs[2]._y"-
-~("t.at.arbs[2].a"|"t.at.arbs[2].b")->"t.at.arbs[2]._y"+
-"t.at.arbs[2]._y"->"t.at.arbs[2].y"-
-~("t.at.arbs[2]._y")->"t.at.arbs[2].y"+
-"t.at.arbs[3].a"|"t.at.arbs[3].b"->"t.at.arbs[3]._y"-
-~("t.at.arbs[3].a"|"t.at.arbs[3].b")->"t.at.arbs[3]._y"+
-"t.at.arbs[3]._y"->"t.at.arbs[3].y"-
-~("t.at.arbs[3]._y")->"t.at.arbs[3].y"+
-= "t.at.tmp[5]" "t.at.arbs[2].a"
-= "t.at.tmp[5]" "t.at.arbs[0].y"
-= "t.at.tmp[6]" "t.at.arbs[2].b"
-= "t.at.tmp[6]" "t.at.arbs[1].y"
-= "t.at.tmp[8]" "t.at.arbs[3].a"
-= "t.at.tmp[8]" "t.at.arbs[2].y"
-= "t.at.supply.vdd" "t.at.arbs[3].vdd"
-= "t.at.supply.vdd" "t.at.arbs[2].vdd"
-= "t.at.supply.vdd" "t.at.arbs[1].vdd"
-= "t.at.supply.vdd" "t.at.arbs[0].vdd"
-= "t.at.supply.vss" "t.at.arbs[3].vss"
-= "t.at.supply.vss" "t.at.arbs[2].vss"
-= "t.at.supply.vss" "t.at.arbs[1].vss"
-= "t.at.supply.vss" "t.at.arbs[0].vss"
-= "t.at.in[0]" "t.at.arbs[0].a"
-= "t.at.in[0]" "t.at.tmp[0]"
-= "t.at.in[1]" "t.at.arbs[0].b"
-= "t.at.in[1]" "t.at.tmp[1]"
-= "t.at.in[2]" "t.at.arbs[1].a"
-= "t.at.in[2]" "t.at.tmp[2]"
-= "t.at.in[3]" "t.at.arbs[1].b"
-= "t.at.in[3]" "t.at.tmp[3]"
-= "t.at.in[4]" "t.at.arbs[3].b"
-= "t.at.in[4]" "t.at.tmp[9]"
-= "t.at.in[4]" "t.at.tmp[7]"
-= "t.at.in[4]" "t.at.tmp[4]"
-= "t.at.out" "t.at.arbs[3].y"
-= "t.at.out" "t.at.tmp[10]"
+= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
+= "t.at.arbs[0].in1.a" "t.at.arbs[0].arbiter.d"
+= "t.at.arbs[0].in1.a" "t.at.arbs[0].ack_cell1.y"
+= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].arbiter.a"
+= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
+~"t.at.arbs[0].ack_cell1.c1"&~"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"+
+"t.at.arbs[0].ack_cell1.c1"&"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"-
+"t.at.arbs[0].ack_cell1._y"->"t.at.arbs[0].ack_cell1.y"-
+~("t.at.arbs[0].ack_cell1._y")->"t.at.arbs[0].ack_cell1.y"+
+= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
+= "t.at.arbs[0].in2.a" "t.at.arbs[0].arbiter.c"
+= "t.at.arbs[0].in2.a" "t.at.arbs[0].ack_cell2.y"
+= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].arbiter.b"
+= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].arbiter.vdd"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].or_cell.vdd"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell2.vdd"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell1.vdd"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].arbiter.vss"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].or_cell.vss"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell2.vss"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell1.vss"
+"t.at.arbs[0].arbiter.a"&"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"-
+~"t.at.arbs[0].arbiter.a"|~"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"+
+"t.at.arbs[0].arbiter.b"&"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"-
+~"t.at.arbs[0].arbiter.b"|~"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"+
+"t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c"->"t.at.arbs[0].arbiter.y1"-
+~("t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c")->"t.at.arbs[0].arbiter.y1"+
+"t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d"->"t.at.arbs[0].arbiter.y2"-
+~("t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d")->"t.at.arbs[0].arbiter.y2"+
+mk_excllo("t.at.arbs[0].arbiter._y1","t.at.arbs[0].arbiter._y2")
+= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].arbiter.y1"
+= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].or_cell.a"
+= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].ack_cell1.c2"
+~"t.at.arbs[0].ack_cell2.c1"&~"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"+
+"t.at.arbs[0].ack_cell2.c1"&"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"-
+"t.at.arbs[0].ack_cell2._y"->"t.at.arbs[0].ack_cell2.y"-
+~("t.at.arbs[0].ack_cell2._y")->"t.at.arbs[0].ack_cell2.y"+
+"t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b"->"t.at.arbs[0].or_cell._y"-
+~("t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b")->"t.at.arbs[0].or_cell._y"+
+"t.at.arbs[0].or_cell._y"->"t.at.arbs[0].or_cell.y"-
+~("t.at.arbs[0].or_cell._y")->"t.at.arbs[0].or_cell.y"+
+= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
+= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell2.c1"
+= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell1.c1"
+= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].or_cell.y"
+= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
+= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].arbiter.y2"
+= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].or_cell.b"
+= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].ack_cell2.c2"
+= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
+= "t.at.arbs[1].in1.a" "t.at.arbs[1].arbiter.d"
+= "t.at.arbs[1].in1.a" "t.at.arbs[1].ack_cell1.y"
+= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].arbiter.a"
+= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
+~"t.at.arbs[1].ack_cell1.c1"&~"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"+
+"t.at.arbs[1].ack_cell1.c1"&"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"-
+"t.at.arbs[1].ack_cell1._y"->"t.at.arbs[1].ack_cell1.y"-
+~("t.at.arbs[1].ack_cell1._y")->"t.at.arbs[1].ack_cell1.y"+
+= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
+= "t.at.arbs[1].in2.a" "t.at.arbs[1].arbiter.c"
+= "t.at.arbs[1].in2.a" "t.at.arbs[1].ack_cell2.y"
+= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].arbiter.b"
+= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].arbiter.vdd"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].or_cell.vdd"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell2.vdd"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell1.vdd"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].arbiter.vss"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].or_cell.vss"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell2.vss"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell1.vss"
+"t.at.arbs[1].arbiter.a"&"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"-
+~"t.at.arbs[1].arbiter.a"|~"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"+
+"t.at.arbs[1].arbiter.b"&"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"-
+~"t.at.arbs[1].arbiter.b"|~"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"+
+"t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c"->"t.at.arbs[1].arbiter.y1"-
+~("t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c")->"t.at.arbs[1].arbiter.y1"+
+"t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d"->"t.at.arbs[1].arbiter.y2"-
+~("t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d")->"t.at.arbs[1].arbiter.y2"+
+mk_excllo("t.at.arbs[1].arbiter._y1","t.at.arbs[1].arbiter._y2")
+= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].arbiter.y1"
+= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].or_cell.a"
+= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].ack_cell1.c2"
+~"t.at.arbs[1].ack_cell2.c1"&~"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"+
+"t.at.arbs[1].ack_cell2.c1"&"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"-
+"t.at.arbs[1].ack_cell2._y"->"t.at.arbs[1].ack_cell2.y"-
+~("t.at.arbs[1].ack_cell2._y")->"t.at.arbs[1].ack_cell2.y"+
+"t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b"->"t.at.arbs[1].or_cell._y"-
+~("t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b")->"t.at.arbs[1].or_cell._y"+
+"t.at.arbs[1].or_cell._y"->"t.at.arbs[1].or_cell.y"-
+~("t.at.arbs[1].or_cell._y")->"t.at.arbs[1].or_cell.y"+
+= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
+= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell2.c1"
+= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell1.c1"
+= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].or_cell.y"
+= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
+= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].arbiter.y2"
+= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].or_cell.b"
+= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].ack_cell2.c2"
+= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
+= "t.at.arbs[2].in1.a" "t.at.arbs[2].arbiter.d"
+= "t.at.arbs[2].in1.a" "t.at.arbs[2].ack_cell1.y"
+= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].arbiter.a"
+= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
+~"t.at.arbs[2].ack_cell1.c1"&~"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"+
+"t.at.arbs[2].ack_cell1.c1"&"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"-
+"t.at.arbs[2].ack_cell1._y"->"t.at.arbs[2].ack_cell1.y"-
+~("t.at.arbs[2].ack_cell1._y")->"t.at.arbs[2].ack_cell1.y"+
+= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
+= "t.at.arbs[2].in2.a" "t.at.arbs[2].arbiter.c"
+= "t.at.arbs[2].in2.a" "t.at.arbs[2].ack_cell2.y"
+= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].arbiter.b"
+= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].arbiter.vdd"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].or_cell.vdd"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell2.vdd"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell1.vdd"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].arbiter.vss"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].or_cell.vss"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell2.vss"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell1.vss"
+"t.at.arbs[2].arbiter.a"&"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"-
+~"t.at.arbs[2].arbiter.a"|~"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"+
+"t.at.arbs[2].arbiter.b"&"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"-
+~"t.at.arbs[2].arbiter.b"|~"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"+
+"t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c"->"t.at.arbs[2].arbiter.y1"-
+~("t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c")->"t.at.arbs[2].arbiter.y1"+
+"t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d"->"t.at.arbs[2].arbiter.y2"-
+~("t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d")->"t.at.arbs[2].arbiter.y2"+
+mk_excllo("t.at.arbs[2].arbiter._y1","t.at.arbs[2].arbiter._y2")
+= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].arbiter.y1"
+= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].or_cell.a"
+= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].ack_cell1.c2"
+~"t.at.arbs[2].ack_cell2.c1"&~"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"+
+"t.at.arbs[2].ack_cell2.c1"&"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"-
+"t.at.arbs[2].ack_cell2._y"->"t.at.arbs[2].ack_cell2.y"-
+~("t.at.arbs[2].ack_cell2._y")->"t.at.arbs[2].ack_cell2.y"+
+"t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b"->"t.at.arbs[2].or_cell._y"-
+~("t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b")->"t.at.arbs[2].or_cell._y"+
+"t.at.arbs[2].or_cell._y"->"t.at.arbs[2].or_cell.y"-
+~("t.at.arbs[2].or_cell._y")->"t.at.arbs[2].or_cell.y"+
+= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
+= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell2.c1"
+= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell1.c1"
+= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].or_cell.y"
+= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
+= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].arbiter.y2"
+= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].or_cell.b"
+= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].ack_cell2.c2"
+= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
+= "t.at.arbs[3].in1.a" "t.at.arbs[3].arbiter.d"
+= "t.at.arbs[3].in1.a" "t.at.arbs[3].ack_cell1.y"
+= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].arbiter.a"
+= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
+~"t.at.arbs[3].ack_cell1.c1"&~"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"+
+"t.at.arbs[3].ack_cell1.c1"&"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"-
+"t.at.arbs[3].ack_cell1._y"->"t.at.arbs[3].ack_cell1.y"-
+~("t.at.arbs[3].ack_cell1._y")->"t.at.arbs[3].ack_cell1.y"+
+= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
+= "t.at.arbs[3].in2.a" "t.at.arbs[3].arbiter.c"
+= "t.at.arbs[3].in2.a" "t.at.arbs[3].ack_cell2.y"
+= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].arbiter.b"
+= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].arbiter.vdd"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].or_cell.vdd"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell2.vdd"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell1.vdd"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].arbiter.vss"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].or_cell.vss"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell2.vss"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell1.vss"
+"t.at.arbs[3].arbiter.a"&"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"-
+~"t.at.arbs[3].arbiter.a"|~"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"+
+"t.at.arbs[3].arbiter.b"&"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"-
+~"t.at.arbs[3].arbiter.b"|~"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"+
+"t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c"->"t.at.arbs[3].arbiter.y1"-
+~("t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c")->"t.at.arbs[3].arbiter.y1"+
+"t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d"->"t.at.arbs[3].arbiter.y2"-
+~("t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d")->"t.at.arbs[3].arbiter.y2"+
+mk_excllo("t.at.arbs[3].arbiter._y1","t.at.arbs[3].arbiter._y2")
+= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].arbiter.y1"
+= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].or_cell.a"
+= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].ack_cell1.c2"
+~"t.at.arbs[3].ack_cell2.c1"&~"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"+
+"t.at.arbs[3].ack_cell2.c1"&"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"-
+"t.at.arbs[3].ack_cell2._y"->"t.at.arbs[3].ack_cell2.y"-
+~("t.at.arbs[3].ack_cell2._y")->"t.at.arbs[3].ack_cell2.y"+
+"t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b"->"t.at.arbs[3].or_cell._y"-
+~("t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b")->"t.at.arbs[3].or_cell._y"+
+"t.at.arbs[3].or_cell._y"->"t.at.arbs[3].or_cell.y"-
+~("t.at.arbs[3].or_cell._y")->"t.at.arbs[3].or_cell.y"+
+= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
+= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell2.c1"
+= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell1.c1"
+= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].or_cell.y"
+= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
+= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].arbiter.y2"
+= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].or_cell.b"
+= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].ack_cell2.c2"
+= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
+= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
+= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
+= "t.at.tmp[5].r" "t.at.arbs[2].in1.r"
+= "t.at.tmp[5].a" "t.at.arbs[2].in1.a"
+= "t.at.tmp[5].d.d[0]" "t.at.arbs[2].in1.d.d[0]"
+= "t.at.tmp[5].r" "t.at.arbs[0].out.r"
+= "t.at.tmp[5].a" "t.at.arbs[0].out.a"
+= "t.at.tmp[5].d.d[0]" "t.at.arbs[0].out.d.d[0]"
+= "t.at.tmp[6].r" "t.at.arbs[2].in2.r"
+= "t.at.tmp[6].a" "t.at.arbs[2].in2.a"
+= "t.at.tmp[6].d.d[0]" "t.at.arbs[2].in2.d.d[0]"
+= "t.at.tmp[6].r" "t.at.arbs[1].out.r"
+= "t.at.tmp[6].a" "t.at.arbs[1].out.a"
+= "t.at.tmp[6].d.d[0]" "t.at.arbs[1].out.d.d[0]"
+= "t.at.tmp[8].r" "t.at.arbs[3].in1.r"
+= "t.at.tmp[8].a" "t.at.arbs[3].in1.a"
+= "t.at.tmp[8].d.d[0]" "t.at.arbs[3].in1.d.d[0]"
+= "t.at.tmp[8].r" "t.at.arbs[2].out.r"
+= "t.at.tmp[8].a" "t.at.arbs[2].out.a"
+= "t.at.tmp[8].d.d[0]" "t.at.arbs[2].out.d.d[0]"
+= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
+= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
+= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
+= "t.at.supply.vss" "t.at.arbs[3].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[3].supply.vdd"
+= "t.at.supply.vss" "t.at.arbs[2].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[2].supply.vdd"
+= "t.at.supply.vss" "t.at.arbs[1].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[1].supply.vdd"
+= "t.at.supply.vss" "t.at.arbs[0].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[0].supply.vdd"
+= "t.at.in[0].d.d[0]" "t.at.in[0].r"
+= "t.at.in[1].d.d[0]" "t.at.in[1].r"
+= "t.at.in[2].d.d[0]" "t.at.in[2].r"
+= "t.at.in[3].d.d[0]" "t.at.in[3].r"
+= "t.at.in[4].d.d[0]" "t.at.in[4].r"
+= "t.at.in[0].r" "t.at.arbs[0].in1.r"
+= "t.at.in[0].a" "t.at.arbs[0].in1.a"
+= "t.at.in[0].d.d[0]" "t.at.arbs[0].in1.d.d[0]"
+= "t.at.in[0].r" "t.at.tmp[0].r"
+= "t.at.in[0].a" "t.at.tmp[0].a"
+= "t.at.in[0].d.d[0]" "t.at.tmp[0].d.d[0]"
+= "t.at.in[1].r" "t.at.arbs[0].in2.r"
+= "t.at.in[1].a" "t.at.arbs[0].in2.a"
+= "t.at.in[1].d.d[0]" "t.at.arbs[0].in2.d.d[0]"
+= "t.at.in[1].r" "t.at.tmp[1].r"
+= "t.at.in[1].a" "t.at.tmp[1].a"
+= "t.at.in[1].d.d[0]" "t.at.tmp[1].d.d[0]"
+= "t.at.in[2].r" "t.at.arbs[1].in1.r"
+= "t.at.in[2].a" "t.at.arbs[1].in1.a"
+= "t.at.in[2].d.d[0]" "t.at.arbs[1].in1.d.d[0]"
+= "t.at.in[2].r" "t.at.tmp[2].r"
+= "t.at.in[2].a" "t.at.tmp[2].a"
+= "t.at.in[2].d.d[0]" "t.at.tmp[2].d.d[0]"
+= "t.at.in[3].r" "t.at.arbs[1].in2.r"
+= "t.at.in[3].a" "t.at.arbs[1].in2.a"
+= "t.at.in[3].d.d[0]" "t.at.arbs[1].in2.d.d[0]"
+= "t.at.in[3].r" "t.at.tmp[3].r"
+= "t.at.in[3].a" "t.at.tmp[3].a"
+= "t.at.in[3].d.d[0]" "t.at.tmp[3].d.d[0]"
+= "t.at.in[4].r" "t.at.arbs[3].in2.r"
+= "t.at.in[4].a" "t.at.arbs[3].in2.a"
+= "t.at.in[4].d.d[0]" "t.at.arbs[3].in2.d.d[0]"
+= "t.at.in[4].r" "t.at.tmp[9].r"
+= "t.at.in[4].a" "t.at.tmp[9].a"
+= "t.at.in[4].d.d[0]" "t.at.tmp[9].d.d[0]"
+= "t.at.in[4].r" "t.at.tmp[7].r"
+= "t.at.in[4].a" "t.at.tmp[7].a"
+= "t.at.in[4].d.d[0]" "t.at.tmp[7].d.d[0]"
+= "t.at.in[4].r" "t.at.tmp[4].r"
+= "t.at.in[4].a" "t.at.tmp[4].a"
+= "t.at.in[4].d.d[0]" "t.at.tmp[4].d.d[0]"
+= "t.at.in[4].d.d[0]" "t.at.in[4].r"
+= "t.at.in[3].d.d[0]" "t.at.in[3].r"
+= "t.at.in[2].d.d[0]" "t.at.in[2].r"
+= "t.at.in[1].d.d[0]" "t.at.in[1].r"
+= "t.at.in[0].d.d[0]" "t.at.in[0].r"
+= "t.at.out.d.d[0]" "t.at.out.r"
+= "t.at.out.r" "t.at.arbs[3].out.r"
+= "t.at.out.a" "t.at.arbs[3].out.a"
+= "t.at.out.d.d[0]" "t.at.arbs[3].out.d.d[0]"
+= "t.at.out.r" "t.at.tmp[10].r"
+= "t.at.out.a" "t.at.tmp[10].a"
+= "t.at.out.d.d[0]" "t.at.tmp[10].d.d[0]"
+= "t.at.out.d.d[0]" "t.at.out.r"
 = "Vdd" "t.at.supply.vdd"
 = "GND" "t.at.supply.vss"
-= "t.out" "t.at.out"
-= "t.in[0]" "t.at.in[0]"
-= "t.in[1]" "t.at.in[1]"
-= "t.in[2]" "t.at.in[2]"
-= "t.in[3]" "t.at.in[3]"
-= "t.in[4]" "t.at.in[4]"
+= "t.out.d.d[0]" "t.out.r"
+= "t.out.r" "t.at.out.r"
+= "t.out.a" "t.at.out.a"
+= "t.out.d.d[0]" "t.at.out.d.d[0]"
+= "t.out.d.d[0]" "t.out.r"
+= "t.in[0].d.d[0]" "t.in[0].r"
+= "t.in[1].d.d[0]" "t.in[1].r"
+= "t.in[2].d.d[0]" "t.in[2].r"
+= "t.in[3].d.d[0]" "t.in[3].r"
+= "t.in[4].d.d[0]" "t.in[4].r"
+= "t.in[0].r" "t.at.in[0].r"
+= "t.in[1].r" "t.at.in[1].r"
+= "t.in[2].r" "t.at.in[2].r"
+= "t.in[3].r" "t.at.in[3].r"
+= "t.in[4].r" "t.at.in[4].r"
+= "t.in[0].a" "t.at.in[0].a"
+= "t.in[1].a" "t.at.in[1].a"
+= "t.in[2].a" "t.at.in[2].a"
+= "t.in[3].a" "t.at.in[3].a"
+= "t.in[4].a" "t.at.in[4].a"
+= "t.in[0].d.d[0]" "t.at.in[0].d.d[0]"
+= "t.in[1].d.d[0]" "t.at.in[1].d.d[0]"
+= "t.in[2].d.d[0]" "t.at.in[2].d.d[0]"
+= "t.in[3].d.d[0]" "t.at.in[3].d.d[0]"
+= "t.in[4].d.d[0]" "t.at.in[4].d.d[0]"
+= "t.in[4].d.d[0]" "t.in[4].r"
+= "t.in[3].d.d[0]" "t.in[3].r"
+= "t.in[2].d.d[0]" "t.in[2].r"
+= "t.in[1].d.d[0]" "t.in[1].r"
+= "t.in[0].d.d[0]" "t.in[0].r"

test/unit_tests/arbtree_5/test.act

@@ -25,17 +25,29 @@
  *
  **************************************************************************
  */
-
-import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/coders.act";
 import globals;
-
 open tmpl::dataflow_neuro;
-
-defproc arbtree_5 (bool? in[5]; bool! out){
-    arbtree<5> at(.in=in, .out=out);
-    at.supply.vss = GND;
-    at.supply.vdd = Vdd;
-
+defproc arbtree (a1of1 in[5]; a1of1 out)
+{
+    a1of1 _in[5];
+    power _supply
+    _supply.vdd = Vdd;
+    _supply.vss = GND;
+    fifo_t<2> fifo_to_tree[5];
+    (i:5:
+        fifo_to_tree[i].in = in[i];
+        fifo_to_tree[i].out = _in[i];
+        fifo_to_tree.supply = _supply;
+        fifo_to_tree.reset_B = _reset_B;
+    )
+    arbtree<5> at(.in=_in, .out = out);
+    //Low active Reset
+    bool _reset_B;
+    prs {
+        Reset => _reset_B-
+    }
+    at.supply = _supply;
+    
 }
-
-arbtree_5 t;
+arbtree t;

test/unit_tests/arbtree_5/test.prsim

@@ -1,88 +1,127 @@
 watchall
 
-system "echo '0'"
+system "echo '[] setting channels neutral'"
 
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-
-system "echo '1'"
+set t.in[0].r 0
+set t.in[1].r 0
+set t.in[2].r 0
+set t.in[3].r 0
+set t.in[4].r 0
+set t.out.a 0
 
 cycle
 mode run
+assert t.out.r 0
 
-# assert t.out 0
+assert t.in[0].a 0
+assert t.in[1].a 0
+assert t.in[2].a 0
+assert t.in[3].a 0
+assert t.in[4].a 0
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
+
+system "echo '[] setting some reqs high'"
+set t.in[0].r 1
+set t.in[1].r 1
+set t.in[2].r 1
 cycle
+assert t.out.r 1
 
-system "echo '[] setting bit 0 high'"
-set t.in[0] 1
+system "echo '[] receiving ack'"
+set t.out.a 1
 cycle
+assert t.in.a 1
 
-
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
+system "echo '[] removing first req (guess)'"
+set t.in[0].r 0
 cycle
+assert t.out.r
 
 
-system "echo '[] setting bit 1 high'"
-set t.in[0] 0
-set t.in[1] 1
-cycle
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-cycle
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+
+# system "echo '1'"
+
+# cycle
+# mode run
+
+# # assert t.out 0
 
 
-system "echo '[] setting bit 2 high'"
-set t.in[1] 0
-set t.in[2] 1
-cycle
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
+
+# system "echo '[] setting bit 0 high'"
+# set t.in[0] 1
+# cycle
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-cycle
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
 
 
-system "echo '[] setting bit 3 high'"
-set t.in[2] 0
-set t.in[3] 1
-cycle
+# system "echo '[] setting bit 1 high'"
+# set t.in[0] 0
+# set t.in[1] 1
+# cycle
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-cycle
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
 
-system "echo '[] setting bit 4 high'"
-set t.in[3] 0
-set t.in[4] 1
-cycle
+
+# system "echo '[] setting bit 2 high'"
+# set t.in[1] 0
+# set t.in[2] 1
+# cycle
+
+
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
+
+
+# system "echo '[] setting bit 3 high'"
+# set t.in[2] 0
+# set t.in[3] 1
+# cycle
+
+
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
+
+# system "echo '[] setting bit 4 high'"
+# set t.in[3] 0
+# set t.in[4] 1
+# cycle

test/unit_tests/bd-fifo-register-fifo-bd/test.act

@@ -0,0 +1,64 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/interfaces.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    bd2qdi<9,4> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
+
+    fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);
+
+    // Make a register array with 3 bit address (-> 8 registers), 
+    // each register holding 5 bits.
+    registerA_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
+        .reset_B = _reset_B, .supply = supply);
+
+    fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);
+
+    qdi2bd<8,4> _qdi2bd(.in = fifo_post.out, .out = out, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_reg_fifo_3x5x8 b;

test/unit_tests/bd-fifo-register-fifo-bd/test.prsim

@@ -0,0 +1,202 @@
+watchall
+
+set-bd-channel-neutral "b.in" 9
+# set b.in.r 0
+set b.out.a 0
+
+set b.dly_cfg[0] 1
+set b.dly_cfg[1] 1
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
+
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert-bd-channel-neutral "b.out" 8
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-bd-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+# assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+# assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+# system "echo '[] Sending packet write 0s to reg0'"
+# set-qdi-channel-valid "b.in" 9 256
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+# assert-var-int "b.data[0]" 5 0
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+# assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 01100=12 to reg0'"
+set-bd-channel-valid "b.in" 9 352
+cycle
+assert b.in.a 1
+# assert b.in.v 1
+assert-var-int "b.data[0]" 5 12
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+# assert b.in.v 0
+assert-var-int "b.data[0]" 5 12
+
+
+# system "echo '[] Sending packet write 0s to reg1'"
+# set-qdi-channel-valid "b.in" 9 257
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+# assert-var-int "b.data[1]" 5 0
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg2'"
+# set-qdi-channel-valid "b.in" 9 258
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+# assert-var-int "b.data[2]" 5 0
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+# assert-var-int "b.data[2]" 5 0
+
+# system "echo '[] Sending packet write 0s to reg3'"
+# set-qdi-channel-valid "b.in" 9 259
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg4'"
+# set-qdi-channel-valid "b.in" 9 260
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg5'"
+# set-qdi-channel-valid "b.in" 9 261
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg6'"
+# set-qdi-channel-valid "b.in" 9 262
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg7'"
+# set-qdi-channel-valid "b.in" 9 263
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# assert-var-int "b.data[2]" 5 0
+# assert-var-int "b.data[3]" 5 0
+# assert-var-int "b.data[4]" 5 0
+# assert-var-int "b.data[5]" 5 0
+# assert-var-int "b.data[6]" 5 0
+# assert-var-int "b.data[7]" 5 0
+
+
+system "echo '[] Reading register 0'"
+set-bd-channel-valid "b.in" 9 0
+cycle
+assert-bd-channel-valid "b.out" 8 96
+assert b.out.r 1
+# assert b.in.v 1
+assert b.in.a 1
+
+set b.out.a 1
+cycle
+assert-bd-channel-neutral "b.out" 8
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+set b.out.a 0
+cycle
+
+
+# system "echo '[] Reading register 1'"
+# set-qdi-channel-valid "b.in" 9 1
+# cycle
+# assert-qdi-channel-valid "b.out" 8 1
+# assert b.in.v 1
+# assert b.in.a 1
+
+# set b.out.a 1
+# set b.out.v 1
+# cycle
+# assert b.in.a 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert-qdi-channel-neutral "b.out" 8
+# set b.out.a 0
+# set b.out.v 0
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0

test/unit_tests/buf_s_5/run/prsim.out

@@ -1,4 +1,4 @@
-b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.vc.tmp[0] b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.tmp[2] b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.OR2_tf[2]._y b.b.en_buf_f.buf2._y b.b.vc.tmp[5] b.b.en_buf_t.buf2._y b.b._en b.b.vc.tmp[4] b.b.vc.C3Els[0]._y b.b.vc.OR2_tf[4]._y b.out.a b.b._in_v b.b.vc.tmp[6] b.b.vc.tmp[3] b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.vc.C2Els[0]._y b.b.out_a_B_buf_f.buf2._y b.b.vc.OR2_tf[3]._y 
+b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[0].y b.b.vc.OR2_tf[1]._y b.b.vc.OR2_tf[1].y b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.vc.OR2_tf[4].y b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.myctree.tmp[5] b.b.vc.OR2_tf[3].y b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.myctree.C3Els[0]._y b.b.vc.OR2_tf[2]._y b.b.vc.myctree.tmp[6] b.b.en_buf_f.buf2._y b.b._in_v b.b.vc.myctree.C2Els[0]._y b.b.en_buf_t.buf2._y b.b._en b.b.vc.OR2_tf[4]._y b.out.a b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.out_a_B_buf_f.buf2._y b.b.vc.myctree.C2Els[1]._y b.b.vc.OR2_tf[3]._y 
 	     84120 b.b.f_buf_func[0].n1 : 0
 	     84120 b.b.f_buf_func[4].y : 1
 	     84120 b.b.t_buf_func[4].y : 1
@@ -25,7 +25,7 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	     84121 b.b.f_buf_func[2].y : 0
 	     84121 b.b._en : 1  [by b.out.v:=0]
 	     84123 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
-	     84141 b.b.vc.tmp[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	     84141 b.b.vc.OR2_tf[1].y : 0  [by b.b.vc.OR2_tf[1]._y:=1]
 	     84402 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
 	     84542 b.b.t_buf_func[0].y : 0
 	     84671 b.b.t_buf_func[2].y : 0
@@ -34,16 +34,16 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	     85103 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
 	     85191 b.b.vc.OR2_tf[3]._y : 1  [by b.b.t_buf_func[3].n1:=0]
 	     85201 b.b.t_buf_func[1].y : 0
-	     88415 b.b.vc.tmp[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	     88415 b.b.vc.OR2_tf[2].y : 0  [by b.b.vc.OR2_tf[2]._y:=1]
 	     88891 b.b.out_a_B_buf_t.buf2._y : 0  [by b.b._out_a_B:=1]
 	     89393 b.b._out_a_BX_f[0] : 1  [by b.b.out_a_B_buf_t.buf2._y:=0]
-	     89951 b.b.vc.tmp[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	     89951 b.b.vc.OR2_tf[3].y : 0  [by b.b.vc.OR2_tf[3]._y:=1]
 	     97969 b.b.f_buf_func[3].y : 0
 	     98463 b.b.f_buf_func[0].y : 0
 	    104325 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
-	    104528 b.b.vc.tmp[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
-	    106382 b.b.vc.C2Els[0]._y : 1  [by b.b.vc.tmp[0]:=0]
-	    106521 b.b.vc.tmp[5] : 0  [by b.b.vc.C2Els[0]._y:=1]
+	    104528 b.b.vc.OR2_tf[0].y : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    106382 b.b.vc.myctree.C2Els[0]._y : 1  [by b.b.vc.OR2_tf[0].y:=0]
+	    106521 b.b.vc.myctree.tmp[5] : 0  [by b.b.vc.myctree.C2Els[0]._y:=1]
 	    106561 b.b.vc.OR2_tf[4]._y : 1  [by b.b.f_buf_func[4].n1:=0]
 	    106687 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
 	    108932 b.b.t_buf_func[3].y : 0
@@ -55,11 +55,11 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	    135773 b.b.f_buf_func[4].y : 0
 	    138591 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
 	    138795 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
-	    142907 b.b.vc.tmp[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
-	    142922 b.b.vc.C3Els[0]._y : 1  [by b.b.vc.tmp[4]:=0]
-	    142923 b.b.vc.tmp[6] : 0  [by b.b.vc.C3Els[0]._y:=1]
-	    142960 b.b.vc.C2Els[1]._y : 1  [by b.b.vc.tmp[6]:=0]
-	    143699 b.b._in_v : 0  [by b.b.vc.C2Els[1]._y:=1]
+	    142907 b.b.vc.OR2_tf[4].y : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    142922 b.b.vc.myctree.C3Els[0]._y : 1  [by b.b.vc.OR2_tf[4].y:=0]
+	    142923 b.b.vc.myctree.tmp[6] : 0  [by b.b.vc.myctree.C3Els[0]._y:=1]
+	    142960 b.b.vc.myctree.C2Els[1]._y : 1  [by b.b.vc.myctree.tmp[6]:=0]
+	    143699 b.b._in_v : 0  [by b.b.vc.myctree.C2Els[1]._y:=1]
 	    143811 b.b.in_v_buf4._y : 1  [by b.b._in_v:=0]
 	    184631 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
 	    184671 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
@@ -88,23 +88,23 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	    200679 b.b.f_buf_func[2].n1 : 1
 	    200679 b.b.t_buf_func[1].n1 : 1
 	    200812 b.b.vc.OR2_tf[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
-	    201171 b.b.vc.tmp[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    201171 b.b.vc.OR2_tf[2].y : 1  [by b.b.vc.OR2_tf[2]._y:=0]
 	    201526 b.b.vc.OR2_tf[0]._y : 0  [by b.b.t_buf_func[0].n1:=1]
-	    215642 b.b.vc.tmp[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    215642 b.b.vc.OR2_tf[0].y : 1  [by b.b.vc.OR2_tf[0]._y:=0]
 	    216341 b.b.vc.OR2_tf[1]._y : 0  [by b.b.t_buf_func[1].n1:=1]
-	    216562 b.b.vc.tmp[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
-	    216569 b.b.vc.C2Els[0]._y : 0  [by b.b.vc.tmp[1]:=1]
-	    216599 b.b.vc.tmp[5] : 1  [by b.b.vc.C2Els[0]._y:=0]
+	    216562 b.b.vc.OR2_tf[1].y : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    216569 b.b.vc.myctree.C2Els[0]._y : 0  [by b.b.vc.OR2_tf[1].y:=1]
+	    216599 b.b.vc.myctree.tmp[5] : 1  [by b.b.vc.myctree.C2Els[0]._y:=0]
 	    230807 b.b.vc.OR2_tf[3]._y : 0  [by b.b.f_buf_func[3].n1:=1]
-	    237520 b.b.vc.tmp[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    237520 b.b.vc.OR2_tf[3].y : 1  [by b.b.vc.OR2_tf[3]._y:=0]
 [] Setting final input
 	    237520 b.b.t_buf_func[4].n1 : 1
 	    294981 b.b.vc.OR2_tf[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
-	    295072 b.b.vc.tmp[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
-	    297261 b.b.vc.C3Els[0]._y : 0  [by b.b.vc.tmp[4]:=1]
-	    297268 b.b.vc.tmp[6] : 1  [by b.b.vc.C3Els[0]._y:=0]
-	    300055 b.b.vc.C2Els[1]._y : 0  [by b.b.vc.tmp[6]:=1]
-	    300161 b.b._in_v : 1  [by b.b.vc.C2Els[1]._y:=0]
+	    295072 b.b.vc.OR2_tf[4].y : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    297261 b.b.vc.myctree.C3Els[0]._y : 0  [by b.b.vc.OR2_tf[4].y:=1]
+	    297268 b.b.vc.myctree.tmp[6] : 1  [by b.b.vc.myctree.C3Els[0]._y:=0]
+	    300055 b.b.vc.myctree.C2Els[1]._y : 0  [by b.b.vc.myctree.tmp[6]:=1]
+	    300161 b.b._in_v : 1  [by b.b.vc.myctree.C2Els[1]._y:=0]
 	    300239 b.b.in_v_buf4._y : 0  [by b.b._in_v:=1]
 	    300514 b.in.v : 1  [by b.b.in_v_buf4._y:=0]
 	    319510 b.b.in_v_bufN.buf2._y : 0  [by b.in.v:=1]
@@ -136,20 +136,20 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	    337917 b.b.f_buf_func[3].n1 : 0
 	    337918 b.b.vc.OR2_tf[4]._y : 1  [by b.b.t_buf_func[4].n1:=0]
 	    337928 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
-	    337985 b.b.vc.tmp[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    337985 b.b.vc.OR2_tf[4].y : 0  [by b.b.vc.OR2_tf[4]._y:=1]
 	    338287 b.b.vc.OR2_tf[3]._y : 1  [by b.b.f_buf_func[3].n1:=0]
-	    338303 b.b.vc.tmp[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    338303 b.b.vc.OR2_tf[3].y : 0  [by b.b.vc.OR2_tf[3]._y:=1]
 	    338465 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
-	    340569 b.b.vc.tmp[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
-	    343027 b.b.vc.tmp[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
-	    343555 b.b.vc.C3Els[0]._y : 1  [by b.b.vc.tmp[2]:=0]
-	    345990 b.b.vc.tmp[6] : 0  [by b.b.vc.C3Els[0]._y:=1]
+	    340569 b.b.vc.OR2_tf[1].y : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    343027 b.b.vc.OR2_tf[2].y : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    343555 b.b.vc.myctree.C3Els[0]._y : 1  [by b.b.vc.OR2_tf[2].y:=0]
+	    345990 b.b.vc.myctree.tmp[6] : 0  [by b.b.vc.myctree.C3Els[0]._y:=1]
 	    381834 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
-	    408714 b.b.vc.tmp[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
-	    432639 b.b.vc.C2Els[0]._y : 1  [by b.b.vc.tmp[0]:=0]
-	    445680 b.b.vc.tmp[5] : 0  [by b.b.vc.C2Els[0]._y:=1]
-	    445682 b.b.vc.C2Els[1]._y : 1  [by b.b.vc.tmp[5]:=0]
-	    506640 b.b._in_v : 0  [by b.b.vc.C2Els[1]._y:=1]
+	    408714 b.b.vc.OR2_tf[0].y : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    432639 b.b.vc.myctree.C2Els[0]._y : 1  [by b.b.vc.OR2_tf[0].y:=0]
+	    445680 b.b.vc.myctree.tmp[5] : 0  [by b.b.vc.myctree.C2Els[0]._y:=1]
+	    445682 b.b.vc.myctree.C2Els[1]._y : 1  [by b.b.vc.myctree.tmp[5]:=0]
+	    506640 b.b._in_v : 0  [by b.b.vc.myctree.C2Els[1]._y:=1]
 	    506643 b.b.in_v_buf4._y : 1  [by b.b._in_v:=0]
 	    506672 b.in.v : 0  [by b.b.in_v_buf4._y:=1]
 	    506989 b.b.in_v_bufN.buf2._y : 1  [by b.in.v:=0]

test/unit_tests/buf_s_5/run/test.prs

@@ -101,18 +101,40 @@
 = "b.b.supply.vss" "b.b.reset_buf.vss"
 = "b.b.supply.vss" "b.b.en_ctl.vss"
 = "b.b.supply.vss" "b.b.inack_ctl.vss"
-~"b.b.vc.C2Els[0].c1"&~"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"+
-"b.b.vc.C2Els[0].c1"&"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"-
-"b.b.vc.C2Els[0]._y"->"b.b.vc.C2Els[0].y"-
-~("b.b.vc.C2Els[0]._y")->"b.b.vc.C2Els[0].y"+
-~"b.b.vc.C2Els[1].c1"&~"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"+
-"b.b.vc.C2Els[1].c1"&"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"-
-"b.b.vc.C2Els[1]._y"->"b.b.vc.C2Els[1].y"-
-~("b.b.vc.C2Els[1]._y")->"b.b.vc.C2Els[1].y"+
-~"b.b.vc.C3Els[0].c1"&~"b.b.vc.C3Els[0].c2"&~"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"+
-"b.b.vc.C3Els[0].c1"&"b.b.vc.C3Els[0].c2"&"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"-
-"b.b.vc.C3Els[0]._y"->"b.b.vc.C3Els[0].y"-
-~("b.b.vc.C3Els[0]._y")->"b.b.vc.C3Els[0].y"+
+~"b.b.vc.myctree.C2Els[0].c1"&~"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"+
+"b.b.vc.myctree.C2Els[0].c1"&"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"-
+"b.b.vc.myctree.C2Els[0]._y"->"b.b.vc.myctree.C2Els[0].y"-
+~("b.b.vc.myctree.C2Els[0]._y")->"b.b.vc.myctree.C2Els[0].y"+
+~"b.b.vc.myctree.C2Els[1].c1"&~"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"+
+"b.b.vc.myctree.C2Els[1].c1"&"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"-
+"b.b.vc.myctree.C2Els[1]._y"->"b.b.vc.myctree.C2Els[1].y"-
+~("b.b.vc.myctree.C2Els[1]._y")->"b.b.vc.myctree.C2Els[1].y"+
+~"b.b.vc.myctree.C3Els[0].c1"&~"b.b.vc.myctree.C3Els[0].c2"&~"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"+
+"b.b.vc.myctree.C3Els[0].c1"&"b.b.vc.myctree.C3Els[0].c2"&"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"-
+"b.b.vc.myctree.C3Els[0]._y"->"b.b.vc.myctree.C3Els[0].y"-
+~("b.b.vc.myctree.C3Els[0]._y")->"b.b.vc.myctree.C3Els[0].y"+
+= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[1].c1"
+= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[0].y"
+= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C2Els[1].c2"
+= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C3Els[0].y"
+= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C3Els[0].vdd"
+= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[1].vdd"
+= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[0].vdd"
+= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C3Els[0].vss"
+= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[1].vss"
+= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[0].vss"
+= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.C2Els[0].c1"
+= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.tmp[0]"
+= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.C2Els[0].c2"
+= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.tmp[1]"
+= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.C3Els[0].c1"
+= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.tmp[2]"
+= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.C3Els[0].c2"
+= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.tmp[3]"
+= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.C3Els[0].c3"
+= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.tmp[4]"
+= "b.b.vc.myctree.out" "b.b.vc.myctree.C2Els[1].y"
+= "b.b.vc.myctree.out" "b.b.vc.myctree.tmp[7]"
 "b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
 ~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
 "b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
@@ -133,36 +155,24 @@
 ~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
 "b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
 ~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
-= "b.b.vc.tmp[0]" "b.b.vc.C2Els[0].c1"
-= "b.b.vc.tmp[0]" "b.b.vc.OR2_tf[0].y"
-= "b.b.vc.tmp[1]" "b.b.vc.C2Els[0].c2"
-= "b.b.vc.tmp[1]" "b.b.vc.OR2_tf[1].y"
-= "b.b.vc.tmp[2]" "b.b.vc.C3Els[0].c1"
-= "b.b.vc.tmp[2]" "b.b.vc.OR2_tf[2].y"
-= "b.b.vc.tmp[3]" "b.b.vc.C3Els[0].c2"
-= "b.b.vc.tmp[3]" "b.b.vc.OR2_tf[3].y"
-= "b.b.vc.tmp[4]" "b.b.vc.C3Els[0].c3"
-= "b.b.vc.tmp[4]" "b.b.vc.OR2_tf[4].y"
-= "b.b.vc.tmp[5]" "b.b.vc.C2Els[1].c1"
-= "b.b.vc.tmp[5]" "b.b.vc.C2Els[0].y"
-= "b.b.vc.tmp[6]" "b.b.vc.C2Els[1].c2"
-= "b.b.vc.tmp[6]" "b.b.vc.C3Els[0].y"
-= "b.b.vc.supply.vdd" "b.b.vc.C3Els[0].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.C2Els[1].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.C2Els[0].vdd"
+= "b.b.vc.OR2_tf[4].y" "b.b.vc.myctree.in[4]"
+= "b.b.vc.OR2_tf[3].y" "b.b.vc.myctree.in[3]"
+= "b.b.vc.OR2_tf[2].y" "b.b.vc.myctree.in[2]"
+= "b.b.vc.OR2_tf[1].y" "b.b.vc.myctree.in[1]"
+= "b.b.vc.OR2_tf[0].y" "b.b.vc.myctree.in[0]"
+= "b.b.vc.supply.vss" "b.b.vc.myctree.supply.vss"
+= "b.b.vc.supply.vdd" "b.b.vc.myctree.supply.vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
-= "b.b.vc.supply.vss" "b.b.vc.C3Els[0].vss"
-= "b.b.vc.supply.vss" "b.b.vc.C2Els[1].vss"
-= "b.b.vc.supply.vss" "b.b.vc.C2Els[0].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
+= "b.b.vc.out" "b.b.vc.myctree.out"
 = "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
 = "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
 = "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
@@ -203,8 +213,6 @@
 = "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
 = "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
 = "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
-= "b.b.vc.out" "b.b.vc.C2Els[1].y"
-= "b.b.vc.out" "b.b.vc.tmp[7]"
 "b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
 ~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
 "b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-

test/unit_tests/buff.v

@@ -0,0 +1,685 @@
+//
+// Verilog module for: BUF_X6<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   wire a;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: sigbuf<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
+   input in;
+   output \out[0] ;
+
+// -- signals ---
+   reg \out[0] ;
+   wire in;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6  (.y(\out[0] ), .a(in));
+endmodule
+
+//
+// Verilog module for: A_3C_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   wire pr_B;
+   wire c3;
+   wire c1;
+   wire sr_B;
+   wire c2;
+   reg _y;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: INV_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
+   output y;
+   input c1;
+   input c2;
+
+// -- signals ---
+   wire c2;
+   wire c1;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_3C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+
+// -- signals ---
+   wire c1;
+   reg y;
+   reg _y;
+   wire c3;
+   wire c2;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: ctree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
+   input \in[0] ;
+   input \in[1] ;
+   input \in[2] ;
+   input \in[3] ;
+   input \in[4] ;
+   input \in[5] ;
+   input \in[6] ;
+   input \in[7] ;
+   input \in[8] ;
+   input \in[9] ;
+   input \in[10] ;
+   input \in[11] ;
+   input \in[12] ;
+   input \in[13] ;
+   input \in[14] ;
+   output out;
+
+// -- signals ---
+   wire \in[9] ;
+   wire \in[11] ;
+   reg \tmp[18] ;
+   reg \tmp[16] ;
+   reg \tmp[24] ;
+   wire \in[0] ;
+   reg \tmp[22] ;
+   reg out;
+   wire \in[7] ;
+   reg \tmp[23] ;
+   wire \in[4] ;
+   wire \in[3] ;
+   wire \in[12] ;
+   reg \tmp[20] ;
+   wire \in[2] ;
+   reg \tmp[19] ;
+   wire \in[14] ;
+   wire \in[6] ;
+   wire \in[10] ;
+   wire \in[5] ;
+   wire \in[8] ;
+   wire \in[13] ;
+   wire \in[1] ;
+   reg \tmp[21] ;
+   reg \tmp[17] ;
+   reg \tmp[15] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0]  (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1]  (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2]  (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3]  (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4]  (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5]  (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6]  (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7]  (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0]  (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1]  (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2]  (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
+endmodule
+
+//
+// Verilog module for: OR2_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
+   output y;
+   input a;
+   input b;
+
+// -- signals ---
+   wire a;
+   wire b;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: vtree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
+   input \in.d[0].d[0] ;
+   input \in.d[0].d[1] ;
+   input \in.d[1].d[0] ;
+   input \in.d[1].d[1] ;
+   input \in.d[2].d[0] ;
+   input \in.d[2].d[1] ;
+   input \in.d[3].d[0] ;
+   input \in.d[3].d[1] ;
+   input \in.d[4].d[0] ;
+   input \in.d[4].d[1] ;
+   input \in.d[5].d[0] ;
+   input \in.d[5].d[1] ;
+   input \in.d[6].d[0] ;
+   input \in.d[6].d[1] ;
+   input \in.d[7].d[0] ;
+   input \in.d[7].d[1] ;
+   input \in.d[8].d[0] ;
+   input \in.d[8].d[1] ;
+   input \in.d[9].d[0] ;
+   input \in.d[9].d[1] ;
+   input \in.d[10].d[0] ;
+   input \in.d[10].d[1] ;
+   input \in.d[11].d[0] ;
+   input \in.d[11].d[1] ;
+   input \in.d[12].d[0] ;
+   input \in.d[12].d[1] ;
+   input \in.d[13].d[0] ;
+   input \in.d[13].d[1] ;
+   input \in.d[14].d[0] ;
+   input \in.d[14].d[1] ;
+   output out;
+
+// -- signals ---
+   wire \in.d[2].d[1] ;
+   wire \in.d[14].d[1] ;
+   reg \ct.in[8] ;
+   wire \in.d[10].d[1] ;
+   wire \in.d[7].d[1] ;
+   reg \ct.in[14] ;
+   wire \in.d[3].d[0] ;
+   reg \ct.in[0] ;
+   wire \in.d[8].d[1] ;
+   wire \in.d[6].d[1] ;
+   reg out;
+   wire \in.d[14].d[0] ;
+   wire \in.d[6].d[0] ;
+   wire \in.d[10].d[0] ;
+   wire \in.d[5].d[1] ;
+   wire \in.d[7].d[0] ;
+   wire \in.d[3].d[1] ;
+   wire \in.d[2].d[0] ;
+   reg \ct.in[6] ;
+   reg \ct.in[4] ;
+   wire \in.d[5].d[0] ;
+   wire \in.d[1].d[1] ;
+   wire \in.d[0].d[1] ;
+   reg \ct.in[5] ;
+   reg \ct.in[1] ;
+   wire \in.d[9].d[0] ;
+   wire \in.d[0].d[0] ;
+   wire \in.d[4].d[1] ;
+   reg \ct.in[12] ;
+   wire \in.d[12].d[1] ;
+   wire \in.d[8].d[0] ;
+   reg \ct.in[2] ;
+   wire \in.d[13].d[0] ;
+   wire \in.d[4].d[0] ;
+   wire \in.d[12].d[0] ;
+   wire \in.d[11].d[0] ;
+   wire \in.d[13].d[1] ;
+   reg \ct.in[9] ;
+   reg \ct.in[3] ;
+   reg \ct.in[11] ;
+   wire \in.d[1].d[0] ;
+   reg \ct.in[7] ;
+   wire \in.d[11].d[1] ;
+   wire \in.d[9].d[1] ;
+   reg \ct.in[10] ;
+   reg \ct.in[13] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct  (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0]  (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1]  (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2]  (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3]  (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4]  (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5]  (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6]  (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7]  (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8]  (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9]  (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10]  (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11]  (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12]  (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13]  (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14]  (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
+endmodule
+
+//
+// Verilog module for: A_1C1P_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
+   output y;
+   input c1;
+   input p1;
+
+// -- signals ---
+   wire c1;
+   wire p1;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C1N_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input n1;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   reg y;
+   wire n1;
+   wire sr_B;
+   wire pr_B;
+   wire c2;
+   wire c1;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: buffer<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+   input reset_B;
+
+// -- signals ---
+   wire \in.d.d[9].d[0] ;
+   reg _out_a_B;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   wire \in.d.d[14].d[0] ;
+   wire \in.d.d[10].d[1] ;
+   reg \out.d.d[14].d[1] ;
+   wire \in.d.d[8].d[1] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[3].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[5].d[0] ;
+   wire \out.v ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[1].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[4].d[1] ;
+   reg _reset_BX;
+   reg \in.v ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   reg \out.d.d[5].d[0] ;
+   reg \out.d.d[10].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   reg \out.d.d[7].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[5].d[1] ;
+   reg _en;
+   reg \_out_a_BX_f[0] ;
+   reg \out.d.d[9].d[0] ;
+   wire \in.d.d[13].d[1] ;
+   reg \out.d.d[11].d[0] ;
+   wire \in.d.d[12].d[0] ;
+   wire \in.d.d[11].d[0] ;
+   wire \in.d.d[1].d[1] ;
+   wire \in.d.d[1].d[0] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[4].d[1] ;
+   reg _in_v;
+   reg \out.d.d[13].d[0] ;
+   reg \out.d.d[2].d[0] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[2].d[1] ;
+   reg \in.a ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[3].d[1] ;
+   reg \_out_a_BX_t[0] ;
+   wire \in.d.d[2].d[0] ;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[0].d[0] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \_en_X_t[0] ;
+   wire \in.d.d[10].d[0] ;
+   wire \out.a ;
+   reg \out.d.d[12].d[1] ;
+   wire reset_B;
+   wire \in.d.d[7].d[1] ;
+   wire \in.d.d[6].d[1] ;
+   wire \in.d.d[12].d[1] ;
+   wire \in.d.d[0].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   reg \_reset_BXX[0] ;
+   reg \out.d.d[4].d[0] ;
+   reg \out.d.d[13].d[1] ;
+   reg \_en_X_f[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t  (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl  (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray  (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf  (.y(\in.v ), .a(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv  (.y(_out_a_B), .a(\out.a ));
+_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc  (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f  (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl  (.y(_en), .c1(\in.a ), .p1(\out.v ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf  (.y(_reset_BX), .a(reset_B));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f  (.in(_en), .\out[0] (\_en_X_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t  (.in(_en), .\out[0] (\_en_X_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0]  (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1]  (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2]  (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3]  (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4]  (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5]  (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6]  (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7]  (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8]  (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9]  (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10]  (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11]  (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12]  (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13]  (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14]  (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0]  (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1]  (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2]  (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3]  (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4]  (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5]  (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6]  (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7]  (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8]  (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9]  (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10]  (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11]  (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12]  (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13]  (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14]  (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+endmodule
+
+//
+// Verilog module for: buffer_15<>
+//
+module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+
+// -- signals ---
+   reg \out.d.d[2].d[0] ;
+   reg \out.d.d[14].d[1] ;
+   reg \out.d.d[4].d[0] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[8].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   wire \in.d.d[1].d[0] ;
+   reg _reset_B;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[5].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   wire \in.d.d[2].d[1] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[5].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[10].d[0] ;
+   wire \in.d.d[3].d[1] ;
+   wire \in.d.d[11].d[0] ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[9].d[0] ;
+   wire \in.d.d[2].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[4].d[1] ;
+   wire \in.d.d[1].d[1] ;
+   reg \out.d.d[13].d[1] ;
+   reg \out.d.d[1].d[1] ;
+   reg \out.d.d[10].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   wire \in.d.d[5].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[0].d[1] ;
+   wire \out.v ;
+   wire \in.d.d[12].d[0] ;
+   reg \out.d.d[3].d[1] ;
+   reg \out.d.d[7].d[1] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[11].d[0] ;
+   reg \out.d.d[4].d[1] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[7].d[1] ;
+   wire \out.a ;
+   reg \in.a ;
+   wire \in.d.d[13].d[1] ;
+   wire \in.d.d[10].d[1] ;
+   reg \out.d.d[12].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[6].d[1] ;
+   reg \in.v ;
+   wire \in.d.d[14].d[0] ;
+   reg \out.d.d[13].d[0] ;
+   wire \in.d.d[12].d[1] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[9].d[0] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[0].d[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test  (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
+endmodule
+

test/unit_tests/buffer_register_7/run/prsim.out

@@ -0,0 +1,417 @@
+b.b.f_buf_func[3].n1 b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.f_buf_func[5].n1 b.b.vc.ct.in[6] b.in.v b.b._flushB b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b.f_buf_func[6].n1 b.b.vc.OR2_tf[6]._y b.b.vc.ct.in[1] b.out_v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b.vc.ct.C3Els[1]._y b.b.t_buf_func[2].n1 b.b.t_buf_func[6].n1 b.b.vc.OR2_tf[0]._y b.b.vc.ct.in[3] b.b.t_buf_func[0].n1 b.flush b.b._in_v b.b.vc.ct.in[4] b.b.f_buf_func[4].n1 b.b.vc.ct.in[5] b.b.vc.OR2_tf[2]._y b.b.vc.ct.tmp[8] b.b.vc.ct.tmp[9] b.b.vc.ct.C2Els[0]._y b.b.t_buf_func[5].n1 b.b.vc.OR2_tf[4]._y b.b.vc.ct.in[2] b.b.vc.ct.tmp[7] b.b.vc.OR2_tf[5]._y b.b.vc.ct.in[0] b.b.vc.OR2_tf[3]._y b.b.in_v_buf._y b.b.vc.ct.C3Els[0]._y b.b.vc.ct.C2Els[1]._y 
+	     74426 b.out_v : 0
+	     74426 b.b.t_buf_func[6].n1 : 0
+	     74426 b.b.f_buf_func[6].n1 : 0
+	     74426 b.b.t_buf_func[5].n1 : 0
+	     74426 b.b.f_buf_func[0].n1 : 0
+	     74426 b.b.f_buf_func[5].n1 : 0
+	     74426 b.b.t_buf_func[4].n1 : 0
+	     74426 b.b.f_buf_func[2].n1 : 0
+	     74426 b.b.f_buf_func[4].n1 : 0
+	     74426 b.b.t_buf_func[3].n1 : 0
+	     74426 b.b.t_buf_func[1].n1 : 0
+	     74426 b.b.f_buf_func[3].n1 : 0
+	     74426 b.b.t_buf_func[2].n1 : 0
+	     74426 b.flush : 0
+	     74426 b.b.f_buf_func[1].n1 : 0
+	     74426 b.b.t_buf_func[0].n1 : 0
+	     74444 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
+	     74977 b.b.vc.OR2_tf[5]._y : 1  [by b.b.f_buf_func[5].n1:=0]
+	     75380 b.b.vc.OR2_tf[3]._y : 1  [by b.b.f_buf_func[3].n1:=0]
+	     75408 b.b.vc.OR2_tf[1]._y : 1  [by b.b.f_buf_func[1].n1:=0]
+	     75497 b.b.vc.OR2_tf[4]._y : 1  [by b.b.f_buf_func[4].n1:=0]
+	     75507 b.b.vc.OR2_tf[2]._y : 1  [by b.b.t_buf_func[2].n1:=0]
+	     76009 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	     78457 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	     78980 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	     80257 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	     96867 b.b.vc.OR2_tf[6]._y : 1  [by b.b.f_buf_func[6].n1:=0]
+	     96992 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	     97070 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	     97209 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[6]:=0]
+	     98846 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[1]:=0]
+	     98915 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    120281 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    120292 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[3]:=0]
+	    128896 b.b._flushB : 1  [by b.flush:=0]
+	    133555 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    172078 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    172282 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[8]:=0]
+	    172297 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    172298 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    172335 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+[] Set reset 0
+
+	    172335 Reset : 0
+	    173074 b._reset_B : 1  [by Reset:=0]
+	    173186 b.b.reset_buf._y : 0  [by b._reset_B:=1]
+	    173226 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
+	    173483 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
+	    173570 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]
+	    220586 b.b._reset : 0  [by b._reset_B:=1]
+[] Flushing data
+	    220586 b.flush : 1
+	    220880 b.b._flushB : 0  [by b.flush:=1]
+	    220881 b.b.t_buf_func[0]._y : 1  [by b.b._flushB:=0]
+	    221045 b.out.d[0].t : 0  [by b.b.t_buf_func[0]._y:=1]
+	    221058 b.b.t_buf_func[5]._y : 1  [by b.b._flushB:=0]
+	    221470 b.b.t_buf_func[4]._y : 1  [by b.b._flushB:=0]
+	    221492 b.out.d[4].t : 0  [by b.b.t_buf_func[4]._y:=1]
+	    221683 b.b.t_buf_func[6]._y : 1  [by b.b._flushB:=0]
+	    222089 b.b.t_buf_func[3]._y : 1  [by b.b._flushB:=0]
+	    222530 b.out.d[6].t : 0  [by b.b.t_buf_func[6]._y:=1]
+	    222686 b.b.t_buf_func[1]._y : 1  [by b.b._flushB:=0]
+	    222819 b.out.d[1].t : 0  [by b.b.t_buf_func[1]._y:=1]
+	    222887 b.b.t_buf_func[2]._y : 1  [by b.b._flushB:=0]
+	    223253 b.out.d[5].t : 0  [by b.b.t_buf_func[5]._y:=1]
+	    238549 b.out.d[2].t : 0  [by b.b.t_buf_func[2]._y:=1]
+	    252217 b.out.d[3].t : 0  [by b.b.t_buf_func[3]._y:=1]
+	    252217 b.flush : 0
+	    252576 b.b._flushB : 1  [by b.flush:=0]
+[] Sending in a 0
+	    252576 b.b.f_buf_func[0].n1 : 1
+	    252576 b.b.f_buf_func[6].n1 : 1
+	    252576 b.b.f_buf_func[2].n1 : 1
+	    252576 b.b.f_buf_func[5].n1 : 1
+	    252576 b.b.f_buf_func[1].n1 : 1
+	    252576 b.b.f_buf_func[4].n1 : 1
+	    252576 b.b.f_buf_func[3].n1 : 1
+	    252583 b.b.vc.OR2_tf[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    252583 b.b.vc.OR2_tf[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    252595 b.b.vc.ct.in[6] : 1  [by b.b.vc.OR2_tf[6]._y:=0]
+	    252606 b.b.f_buf_func[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    252654 b.b.f_buf_func[4]._y : 0  [by b.b.f_buf_func[4].n1:=1]
+	    252666 b.out.d[4].f : 1  [by b.b.f_buf_func[4]._y:=0]
+	    252667 b.b.vc.OR2_tf[5]._y : 0  [by b.b.f_buf_func[5].n1:=1]
+	    252682 b.b.vc.OR2_tf[4]._y : 0  [by b.b.f_buf_func[4].n1:=1]
+	    252797 b.b.f_buf_func[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    252851 b.b.vc.OR2_tf[3]._y : 0  [by b.b.f_buf_func[3].n1:=1]
+	    253010 b.out.d[6].f : 1  [by b.b.f_buf_func[6]._y:=0]
+	    253038 b.b.vc.ct.in[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    254765 b.b.f_buf_func[5]._y : 0  [by b.b.f_buf_func[5].n1:=1]
+	    254767 b.out.d[5].f : 1  [by b.b.f_buf_func[5]._y:=0]
+	    255363 b.b.f_buf_func[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    255696 b.out.d[0].f : 1  [by b.b.f_buf_func[0]._y:=0]
+	    256958 b.b.vc.ct.in[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    257146 b.b.vc.ct.in[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    258583 b.b.vc.ct.in[5] : 1  [by b.b.vc.OR2_tf[5]._y:=0]
+	    259289 b.b.vc.OR2_tf[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    259832 b.b.vc.ct.C3Els[0]._y : 0  [by b.b.vc.ct.in[5]:=1]
+	    259898 b.out.d[1].f : 1  [by b.b.f_buf_func[1]._y:=0]
+	    259998 b.b.vc.ct.tmp[9] : 1  [by b.b.vc.ct.C3Els[0]._y:=0]
+	    262788 b.b.vc.ct.in[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    262863 b.b.vc.ct.C2Els[1]._y : 0  [by b.b.vc.ct.in[2]:=1]
+	    263208 b.b.vc.ct.tmp[8] : 1  [by b.b.vc.ct.C2Els[1]._y:=0]
+	    266692 b.b.vc.OR2_tf[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    266830 b.b.vc.ct.in[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    271572 b.b.f_buf_func[3]._y : 0  [by b.b.f_buf_func[3].n1:=1]
+	    271574 b.out.d[3].f : 1  [by b.b.f_buf_func[3]._y:=0]
+	    272093 b.b.vc.ct.C2Els[0]._y : 0  [by b.b.vc.ct.in[0]:=1]
+	    310037 b.b.f_buf_func[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    310038 b.out.d[2].f : 1  [by b.b.f_buf_func[2]._y:=0]
+	    316010 b.b.vc.ct.tmp[7] : 1  [by b.b.vc.ct.C2Els[0]._y:=0]
+	    316558 b.b.vc.ct.C3Els[1]._y : 0  [by b.b.vc.ct.tmp[7]:=1]
+	    316569 b.b._in_v : 1  [by b.b.vc.ct.C3Els[1]._y:=0]
+	    316939 b.b.in_v_buf._y : 0  [by b.b._in_v:=1]
+	    317006 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+[] Sending in output valid
+	    317006 b.out_v : 1
+	    319647 b.b._en : 0  [by b.out_v:=1]
+	    319663 b.in.a : 1  [by b.b._en:=0]
+	    320175 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	    322610 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+	    324209 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	    351089 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+[] Removing input
+	    351089 b.b.f_buf_func[0].n1 : 0
+	    351089 b.b.f_buf_func[6].n1 : 0
+	    351089 b.b.f_buf_func[2].n1 : 0
+	    351089 b.b.f_buf_func[5].n1 : 0
+	    351089 b.b.f_buf_func[1].n1 : 0
+	    351089 b.b.f_buf_func[4].n1 : 0
+	    351089 b.b.f_buf_func[3].n1 : 0
+	    351091 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
+	    351092 b.b.vc.OR2_tf[1]._y : 1  [by b.b.f_buf_func[1].n1:=0]
+	    351118 b.b.vc.OR2_tf[4]._y : 1  [by b.b.f_buf_func[4].n1:=0]
+	    351162 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    351245 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    351406 b.b.vc.OR2_tf[3]._y : 1  [by b.b.f_buf_func[3].n1:=0]
+	    352692 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    354167 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    364130 b.b.vc.OR2_tf[6]._y : 1  [by b.b.f_buf_func[6].n1:=0]
+	    364131 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	    367850 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[3]:=0]
+	    368067 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    375014 b.b.vc.OR2_tf[0]._y : 1  [by b.b.f_buf_func[0].n1:=0]
+	    375036 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    375037 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[0]:=0]
+	    376618 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    412047 b.b.vc.OR2_tf[5]._y : 1  [by b.b.f_buf_func[5].n1:=0]
+	    421392 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	    421551 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[5]:=0]
+	    441227 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    442514 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[9]:=0]
+	    444746 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    444891 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    447723 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    454077 b.b._en : 1  [by b.in.v:=0]
+	    454078 b.in.a : 0  [by b.b._en:=1]
+	    454239 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	    461608 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+	    493361 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	    493375 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+[] Flushing data
+	    493375 b.flush : 1
+	    493382 b.b._flushB : 0  [by b.flush:=1]
+	    493383 b.b.f_buf_func[2]._y : 1  [by b.b._flushB:=0]
+	    493383 b.b.f_buf_func[3]._y : 1  [by b.b._flushB:=0]
+	    493383 b.b.f_buf_func[4]._y : 1  [by b.b._flushB:=0]
+	    493384 b.out.d[2].f : 0  [by b.b.f_buf_func[2]._y:=1]
+	    493542 b.b.f_buf_func[0]._y : 1  [by b.b._flushB:=0]
+	    493543 b.out.d[0].f : 0  [by b.b.f_buf_func[0]._y:=1]
+	    493569 b.b.f_buf_func[6]._y : 1  [by b.b._flushB:=0]
+	    494422 b.out.d[6].f : 0  [by b.b.f_buf_func[6]._y:=1]
+	    495625 b.b.f_buf_func[5]._y : 1  [by b.b._flushB:=0]
+	    495630 b.out.d[5].f : 0  [by b.b.f_buf_func[5]._y:=1]
+	    497565 b.out.d[3].f : 0  [by b.b.f_buf_func[3]._y:=1]
+	    514939 b.b.f_buf_func[1]._y : 1  [by b.b._flushB:=0]
+	    515830 b.out.d[1].f : 0  [by b.b.f_buf_func[1]._y:=1]
+	    528165 b.out.d[4].f : 0  [by b.b.f_buf_func[4]._y:=1]
+	    528165 b.out_v : 0
+	    528165 b.flush : 0
+	    528166 b.b._flushB : 1  [by b.flush:=0]
+[] Sending in a 127
+	    528166 b.b.t_buf_func[0].n1 : 1
+	    528166 b.b.t_buf_func[6].n1 : 1
+	    528166 b.b.t_buf_func[2].n1 : 1
+	    528166 b.b.t_buf_func[5].n1 : 1
+	    528166 b.b.t_buf_func[1].n1 : 1
+	    528166 b.b.t_buf_func[4].n1 : 1
+	    528166 b.b.t_buf_func[3].n1 : 1
+	    528167 b.b.vc.OR2_tf[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    528169 b.b.t_buf_func[6]._y : 0  [by b.b.t_buf_func[6].n1:=1]
+	    528174 b.b.vc.OR2_tf[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    528178 b.b.vc.ct.in[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    528183 b.b.vc.OR2_tf[0]._y : 0  [by b.b.t_buf_func[0].n1:=1]
+	    528200 b.b.t_buf_func[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    528208 b.b.t_buf_func[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    528261 b.b.vc.OR2_tf[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    528501 b.b.t_buf_func[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    528549 b.out.d[4].t : 1  [by b.b.t_buf_func[4]._y:=0]
+	    529087 b.out.d[6].t : 1  [by b.b.t_buf_func[6]._y:=0]
+	    529107 b.b.vc.OR2_tf[2]._y : 0  [by b.b.t_buf_func[2].n1:=1]
+	    529110 b.b.vc.ct.in[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    529288 b.b.vc.ct.C2Els[1]._y : 0  [by b.b.vc.ct.in[2]:=1]
+	    530598 b.out.d[3].t : 1  [by b.b.t_buf_func[3]._y:=0]
+	    530739 b.b.t_buf_func[0]._y : 0  [by b.b.t_buf_func[0].n1:=1]
+	    530983 b.b.vc.OR2_tf[1]._y : 0  [by b.b.t_buf_func[1].n1:=1]
+	    531423 b.out.d[5].t : 1  [by b.b.t_buf_func[5]._y:=0]
+	    536527 b.b.vc.OR2_tf[6]._y : 0  [by b.b.t_buf_func[6].n1:=1]
+	    536934 b.b.vc.ct.in[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    541899 b.b.t_buf_func[1]._y : 0  [by b.b.t_buf_func[1].n1:=1]
+	    542054 b.b.vc.ct.in[5] : 1  [by b.b.vc.OR2_tf[5]._y:=0]
+	    542638 b.out.d[0].t : 1  [by b.b.t_buf_func[0]._y:=0]
+	    542726 b.out.d[1].t : 1  [by b.b.t_buf_func[1]._y:=0]
+	    550265 b.b.vc.ct.tmp[8] : 1  [by b.b.vc.ct.C2Els[1]._y:=0]
+	    574561 b.b.vc.ct.in[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    574734 b.b.vc.ct.C2Els[0]._y : 0  [by b.b.vc.ct.in[0]:=1]
+	    574918 b.b.vc.ct.tmp[7] : 1  [by b.b.vc.ct.C2Els[0]._y:=0]
+	    575380 b.b.vc.ct.in[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    576012 b.b.vc.ct.in[6] : 1  [by b.b.vc.OR2_tf[6]._y:=0]
+	    576013 b.b.vc.ct.C3Els[0]._y : 0  [by b.b.vc.ct.in[6]:=1]
+	    576086 b.b.vc.ct.tmp[9] : 1  [by b.b.vc.ct.C3Els[0]._y:=0]
+	    576090 b.b.vc.ct.C3Els[1]._y : 0  [by b.b.vc.ct.tmp[9]:=1]
+	    587128 b.b.t_buf_func[2]._y : 0  [by b.b.t_buf_func[2].n1:=1]
+	    587224 b.out.d[2].t : 1  [by b.b.t_buf_func[2]._y:=0]
+	    613378 b.b._in_v : 1  [by b.b.vc.ct.C3Els[1]._y:=0]
+	    613514 b.b.in_v_buf._y : 0  [by b.b._in_v:=1]
+	    613515 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+[] Sending in output valid
+	    613515 b.out_v : 1
+	    632561 b.b._en : 0  [by b.out_v:=1]
+	    632573 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	    632802 b.in.a : 1  [by b.b._en:=0]
+	    636473 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+	    636520 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	    637549 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+[] Removing input
+	    637549 b.b.t_buf_func[0].n1 : 0
+	    637549 b.b.t_buf_func[6].n1 : 0
+	    637549 b.b.t_buf_func[2].n1 : 0
+	    637549 b.b.t_buf_func[5].n1 : 0
+	    637549 b.b.t_buf_func[1].n1 : 0
+	    637549 b.b.t_buf_func[4].n1 : 0
+	    637549 b.b.t_buf_func[3].n1 : 0
+	    637550 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
+	    637550 b.b.vc.OR2_tf[3]._y : 1  [by b.b.t_buf_func[3].n1:=0]
+	    637550 b.b.vc.OR2_tf[5]._y : 1  [by b.b.t_buf_func[5].n1:=0]
+	    637563 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	    637586 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
+	    637605 b.b.vc.OR2_tf[6]._y : 1  [by b.b.t_buf_func[6].n1:=0]
+	    637962 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	    639242 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    641114 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    654570 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    654595 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[1]:=0]
+	    654616 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    660924 b.b.vc.OR2_tf[4]._y : 1  [by b.b.t_buf_func[4].n1:=0]
+	    660925 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    670573 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[4]:=0]
+	    670574 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    682555 b.b.vc.OR2_tf[2]._y : 1  [by b.b.t_buf_func[2].n1:=0]
+	    682556 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    682717 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[2]:=0]
+	    683754 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    683759 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[8]:=0]
+	    684340 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    684748 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    684759 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    685806 b.b._en : 1  [by b.in.v:=0]
+	    685810 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	    685820 b.in.a : 0  [by b.b._en:=1]
+	    685824 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	    685914 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+	    717268 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+[] Flushing data
+	    717268 b.flush : 1
+	    718472 b.b._flushB : 0  [by b.flush:=1]
+	    718483 b.b.t_buf_func[6]._y : 1  [by b.b._flushB:=0]
+	    718486 b.out.d[6].t : 0  [by b.b.t_buf_func[6]._y:=1]
+	    718542 b.b.t_buf_func[4]._y : 1  [by b.b._flushB:=0]
+	    718596 b.out.d[4].t : 0  [by b.b.t_buf_func[4]._y:=1]
+	    718700 b.b.t_buf_func[1]._y : 1  [by b.b._flushB:=0]
+	    719315 b.b.t_buf_func[2]._y : 1  [by b.b._flushB:=0]
+	    719848 b.out.d[1].t : 0  [by b.b.t_buf_func[1]._y:=1]
+	    719931 b.b.t_buf_func[3]._y : 1  [by b.b._flushB:=0]
+	    720476 b.out.d[2].t : 0  [by b.b.t_buf_func[2]._y:=1]
+	    726927 b.b.t_buf_func[0]._y : 1  [by b.b._flushB:=0]
+	    727008 b.out.d[0].t : 0  [by b.b.t_buf_func[0]._y:=1]
+	    728583 b.out.d[3].t : 0  [by b.b.t_buf_func[3]._y:=1]
+	    768894 b.b.t_buf_func[5]._y : 1  [by b.b._flushB:=0]
+	    779971 b.out.d[5].t : 0  [by b.b.t_buf_func[5]._y:=1]
+	    779971 b.out_v : 0
+	    779971 b.flush : 0
+	    797954 b.b._flushB : 1  [by b.flush:=0]
+[] Sending in a 56
+	    797954 b.b.f_buf_func[0].n1 : 1
+	    797954 b.b.f_buf_func[6].n1 : 1
+	    797954 b.b.f_buf_func[2].n1 : 1
+	    797954 b.b.t_buf_func[5].n1 : 1
+	    797954 b.b.f_buf_func[1].n1 : 1
+	    797954 b.b.t_buf_func[4].n1 : 1
+	    797954 b.b.t_buf_func[3].n1 : 1
+	    797961 b.b.t_buf_func[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    797963 b.out.d[4].t : 1  [by b.b.t_buf_func[4]._y:=0]
+	    797999 b.b.f_buf_func[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    798006 b.b.vc.OR2_tf[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    798046 b.b.vc.OR2_tf[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    798047 b.b.vc.ct.in[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    798139 b.b.vc.ct.in[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    798353 b.out.d[2].f : 1  [by b.b.f_buf_func[2]._y:=0]
+	    798479 b.b.vc.OR2_tf[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    798483 b.b.vc.ct.in[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    798567 b.b.f_buf_func[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    798854 b.b.f_buf_func[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    798855 b.out.d[1].f : 1  [by b.b.f_buf_func[1]._y:=0]
+	    798951 b.b.vc.OR2_tf[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    799029 b.b.vc.ct.C2Els[0]._y : 0  [by b.b.vc.ct.in[1]:=1]
+	    799108 b.b.vc.ct.tmp[7] : 1  [by b.b.vc.ct.C2Els[0]._y:=0]
+	    799603 b.b.t_buf_func[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    799698 b.b.vc.OR2_tf[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    799786 b.b.vc.ct.in[6] : 1  [by b.b.vc.OR2_tf[6]._y:=0]
+	    802036 b.out.d[5].t : 1  [by b.b.t_buf_func[5]._y:=0]
+	    804421 b.b.t_buf_func[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    806265 b.b.f_buf_func[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    811329 b.b.vc.ct.in[5] : 1  [by b.b.vc.OR2_tf[5]._y:=0]
+	    811388 b.b.vc.ct.C3Els[0]._y : 0  [by b.b.vc.ct.in[5]:=1]
+	    811418 b.b.vc.ct.tmp[9] : 1  [by b.b.vc.ct.C3Els[0]._y:=0]
+	    811976 b.b.vc.OR2_tf[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    812203 b.out.d[3].t : 1  [by b.b.t_buf_func[3]._y:=0]
+	    813443 b.b.vc.ct.in[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    813566 b.b.vc.OR2_tf[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    834592 b.out.d[0].f : 1  [by b.b.f_buf_func[0]._y:=0]
+	    844130 b.out.d[6].f : 1  [by b.b.f_buf_func[6]._y:=0]
+	    873070 b.b.vc.ct.in[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    892454 b.b.vc.ct.C2Els[1]._y : 0  [by b.b.vc.ct.in[3]:=1]
+	    893139 b.b.vc.ct.tmp[8] : 1  [by b.b.vc.ct.C2Els[1]._y:=0]
+	    909854 b.b.vc.ct.C3Els[1]._y : 0  [by b.b.vc.ct.tmp[8]:=1]
+	    909981 b.b._in_v : 1  [by b.b.vc.ct.C3Els[1]._y:=0]
+	    910150 b.b.in_v_buf._y : 0  [by b.b._in_v:=1]
+	    910193 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+[] Sending in output valid
+	    910193 b.out_v : 1
+	    910205 b.b._en : 0  [by b.out_v:=1]
+	    910208 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	    910246 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+	    910438 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	    910439 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+	    911484 b.in.a : 1  [by b.b._en:=0]
+[] Removing input
+	    911484 b.b.f_buf_func[0].n1 : 0
+	    911484 b.b.f_buf_func[6].n1 : 0
+	    911484 b.b.f_buf_func[2].n1 : 0
+	    911484 b.b.t_buf_func[5].n1 : 0
+	    911484 b.b.f_buf_func[1].n1 : 0
+	    911484 b.b.t_buf_func[4].n1 : 0
+	    911484 b.b.t_buf_func[3].n1 : 0
+	    911485 b.b.vc.OR2_tf[1]._y : 1  [by b.b.f_buf_func[1].n1:=0]
+	    911486 b.b.vc.OR2_tf[3]._y : 1  [by b.b.t_buf_func[3].n1:=0]
+	    911486 b.b.vc.OR2_tf[5]._y : 1  [by b.b.t_buf_func[5].n1:=0]
+	    911503 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    911576 b.b.vc.OR2_tf[6]._y : 1  [by b.b.f_buf_func[6].n1:=0]
+	    911584 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	    911605 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    912985 b.b.vc.OR2_tf[4]._y : 1  [by b.b.t_buf_func[4].n1:=0]
+	    913039 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    914211 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
+	    917206 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	    917211 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[5]:=0]
+	    918278 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    924236 b.b.vc.OR2_tf[0]._y : 1  [by b.b.f_buf_func[0].n1:=0]
+	    924237 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    924375 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[0]:=0]
+	    924376 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    964749 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    964813 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[2]:=0]
+	    964936 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    964938 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[8]:=0]
+	    964975 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    965118 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    965169 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    965611 b.b._en : 1  [by b.in.v:=0]
+	    965612 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	    965620 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	    965622 b.in.a : 0  [by b.b._en:=1]
+	    965637 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+	    975873 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+[] Resetting
+	    975873 Reset : 1
+	    979394 b._reset_B : 0  [by Reset:=1]
+	    979539 b.b.reset_buf._y : 1  [by b._reset_B:=0]
+	    979769 b.b._reset_BX : 0  [by b.b.reset_buf._y:=1]
+	    980460 b.b.reset_bufarray.buf2._y : 1  [by b.b._reset_BX:=0]
+	    980474 b.b._reset_BXX[0] : 0  [by b.b.reset_bufarray.buf2._y:=1]
+	    980485 b.b.f_buf_func[6]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    980486 b.out.d[6].f : 0  [by b.b.f_buf_func[6]._y:=1]
+	    982017 b.b.f_buf_func[0]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    982018 b.out.d[0].f : 0  [by b.b.f_buf_func[0]._y:=1]
+	    982085 b.b.f_buf_func[1]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    988586 b.out.d[1].f : 0  [by b.b.f_buf_func[1]._y:=1]
+	    995562 b.b._reset : 1  [by b._reset_B:=0]
+	    995563 b.b.t_buf_func[6]._y : 0  [by b.b._reset:=1]
+	    995580 b.out.d[6].t : 1  [by b.b.t_buf_func[6]._y:=0]
+	    995694 b.b.t_buf_func[2]._y : 0  [by b.b._reset:=1]
+	    995846 b.out.d[2].t : 1  [by b.b.t_buf_func[2]._y:=0]
+	    996201 b.b.t_buf_func[0]._y : 0  [by b.b._reset:=1]
+	    997355 b.b.t_buf_func[1]._y : 0  [by b.b._reset:=1]
+	    997358 b.out.d[1].t : 1  [by b.b.t_buf_func[1]._y:=0]
+	    997986 b.b.f_buf_func[2]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    998410 b.out.d[2].f : 0  [by b.b.f_buf_func[2]._y:=1]
+	    999184 b.out.d[0].t : 1  [by b.b.t_buf_func[0]._y:=0]
+	    999184 Reset : 0
+	    999190 b._reset_B : 1  [by Reset:=0]
+	   1001651 b.b._reset : 0  [by b._reset_B:=1]
+	   1001778 b.b.reset_buf._y : 0  [by b._reset_B:=1]
+	   1002608 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
+	   1025540 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
+	   1025542 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]

test/unit_tests/buffer_register_7/run/test.prs

@@ -0,0 +1,746 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"Reset"->"b._reset_B"-
+~("Reset")->"b._reset_B"+
+= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
+= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
+= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
+= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
+= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
+= "b.b._en_X_f[5]" "b.b.en_buf_f.out[5]"
+= "b.b._en_X_f[6]" "b.b.en_buf_f.out[6]"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[6].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[5].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[4].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[3].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[2].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[1].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[0].n2"
+= "b.b._en_X_f[0]" "b.b._en_X_f[6]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[5]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
+"b.b.in_v_buf.a"->"b.b.in_v_buf._y"-
+~("b.b.in_v_buf.a")->"b.b.in_v_buf._y"+
+"b.b.in_v_buf._y"->"b.b.in_v_buf.y"-
+~("b.b.in_v_buf._y")->"b.b.in_v_buf.y"+
+"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
+~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
+"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
+~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
+= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
+= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[6]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[5]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
+= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
+= "b.b.flush" "b.b.flush_inv.a"
+~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl.y"+
+"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.n1"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl.y"-
+~"b.b.vc.ct.C2Els[0].c1"&~"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"+
+"b.b.vc.ct.C2Els[0].c1"&"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"-
+"b.b.vc.ct.C2Els[0]._y"->"b.b.vc.ct.C2Els[0].y"-
+~("b.b.vc.ct.C2Els[0]._y")->"b.b.vc.ct.C2Els[0].y"+
+~"b.b.vc.ct.C2Els[1].c1"&~"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"+
+"b.b.vc.ct.C2Els[1].c1"&"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"-
+"b.b.vc.ct.C2Els[1]._y"->"b.b.vc.ct.C2Els[1].y"-
+~("b.b.vc.ct.C2Els[1]._y")->"b.b.vc.ct.C2Els[1].y"+
+~"b.b.vc.ct.C3Els[0].c1"&~"b.b.vc.ct.C3Els[0].c2"&~"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"+
+"b.b.vc.ct.C3Els[0].c1"&"b.b.vc.ct.C3Els[0].c2"&"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"-
+"b.b.vc.ct.C3Els[0]._y"->"b.b.vc.ct.C3Els[0].y"-
+~("b.b.vc.ct.C3Els[0]._y")->"b.b.vc.ct.C3Els[0].y"+
+~"b.b.vc.ct.C3Els[1].c1"&~"b.b.vc.ct.C3Els[1].c2"&~"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"+
+"b.b.vc.ct.C3Els[1].c1"&"b.b.vc.ct.C3Els[1].c2"&"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"-
+"b.b.vc.ct.C3Els[1]._y"->"b.b.vc.ct.C3Els[1].y"-
+~("b.b.vc.ct.C3Els[1]._y")->"b.b.vc.ct.C3Els[1].y"+
+= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C3Els[1].c1"
+= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C2Els[0].y"
+= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C3Els[1].c2"
+= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C2Els[1].y"
+= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[1].c3"
+= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[0].y"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[1].vdd"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[0].vdd"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[1].vdd"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[0].vdd"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[1].vss"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[0].vss"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[1].vss"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[0].vss"
+= "b.b.vc.ct.in[0]" "b.b.vc.ct.C2Els[0].c1"
+= "b.b.vc.ct.in[0]" "b.b.vc.ct.tmp[0]"
+= "b.b.vc.ct.in[1]" "b.b.vc.ct.C2Els[0].c2"
+= "b.b.vc.ct.in[1]" "b.b.vc.ct.tmp[1]"
+= "b.b.vc.ct.in[2]" "b.b.vc.ct.C2Els[1].c1"
+= "b.b.vc.ct.in[2]" "b.b.vc.ct.tmp[2]"
+= "b.b.vc.ct.in[3]" "b.b.vc.ct.C2Els[1].c2"
+= "b.b.vc.ct.in[3]" "b.b.vc.ct.tmp[3]"
+= "b.b.vc.ct.in[4]" "b.b.vc.ct.C3Els[0].c1"
+= "b.b.vc.ct.in[4]" "b.b.vc.ct.tmp[4]"
+= "b.b.vc.ct.in[5]" "b.b.vc.ct.C3Els[0].c2"
+= "b.b.vc.ct.in[5]" "b.b.vc.ct.tmp[5]"
+= "b.b.vc.ct.in[6]" "b.b.vc.ct.C3Els[0].c3"
+= "b.b.vc.ct.in[6]" "b.b.vc.ct.tmp[6]"
+= "b.b.vc.ct.out" "b.b.vc.ct.C3Els[1].y"
+= "b.b.vc.ct.out" "b.b.vc.ct.tmp[10]"
+= "b.b.vc.ct.in[0]" "b.b.vc.OR2_tf[0].y"
+= "b.b.vc.ct.in[1]" "b.b.vc.OR2_tf[1].y"
+= "b.b.vc.ct.in[2]" "b.b.vc.OR2_tf[2].y"
+= "b.b.vc.ct.in[3]" "b.b.vc.OR2_tf[3].y"
+= "b.b.vc.ct.in[4]" "b.b.vc.OR2_tf[4].y"
+= "b.b.vc.ct.in[5]" "b.b.vc.OR2_tf[5].y"
+= "b.b.vc.ct.in[6]" "b.b.vc.OR2_tf[6].y"
+"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
+~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
+"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
+~("b.b.vc.OR2_tf[0]._y")->"b.b.vc.OR2_tf[0].y"+
+"b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b"->"b.b.vc.OR2_tf[1]._y"-
+~("b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b")->"b.b.vc.OR2_tf[1]._y"+
+"b.b.vc.OR2_tf[1]._y"->"b.b.vc.OR2_tf[1].y"-
+~("b.b.vc.OR2_tf[1]._y")->"b.b.vc.OR2_tf[1].y"+
+"b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b"->"b.b.vc.OR2_tf[2]._y"-
+~("b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b")->"b.b.vc.OR2_tf[2]._y"+
+"b.b.vc.OR2_tf[2]._y"->"b.b.vc.OR2_tf[2].y"-
+~("b.b.vc.OR2_tf[2]._y")->"b.b.vc.OR2_tf[2].y"+
+"b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b"->"b.b.vc.OR2_tf[3]._y"-
+~("b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b")->"b.b.vc.OR2_tf[3]._y"+
+"b.b.vc.OR2_tf[3]._y"->"b.b.vc.OR2_tf[3].y"-
+~("b.b.vc.OR2_tf[3]._y")->"b.b.vc.OR2_tf[3].y"+
+"b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b"->"b.b.vc.OR2_tf[4]._y"-
+~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
+"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
+~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
+"b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b"->"b.b.vc.OR2_tf[5]._y"-
+~("b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b")->"b.b.vc.OR2_tf[5]._y"+
+"b.b.vc.OR2_tf[5]._y"->"b.b.vc.OR2_tf[5].y"-
+~("b.b.vc.OR2_tf[5]._y")->"b.b.vc.OR2_tf[5].y"+
+"b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b"->"b.b.vc.OR2_tf[6]._y"-
+~("b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b")->"b.b.vc.OR2_tf[6]._y"+
+"b.b.vc.OR2_tf[6]._y"->"b.b.vc.OR2_tf[6].y"-
+~("b.b.vc.OR2_tf[6]._y")->"b.b.vc.OR2_tf[6].y"+
+= "b.b.vc.supply.vss" "b.b.vc.ct.supply.vss"
+= "b.b.vc.supply.vdd" "b.b.vc.ct.supply.vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[6].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[5].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[6].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[5].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
+= "b.b.vc.out" "b.b.vc.ct.out"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.OR2_tf[6].b"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.OR2_tf[6].a"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.OR2_tf[5].b"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.OR2_tf[5].a"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.OR2_tf[4].b"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.OR2_tf[4].a"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.OR2_tf[3].b"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.OR2_tf[3].a"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.OR2_tf[2].b"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.OR2_tf[2].a"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.OR2_tf[1].b"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.OR2_tf[1].a"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.OR2_tf[0].b"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
+= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
+= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
+= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
+= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
+= "b.b.supply.vss" "b.b.vc.supply.vss"
+= "b.b.supply.vdd" "b.b.vc.supply.vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[6].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[6].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[5].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[5].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
+= "b.b.supply.vdd" "b.b.in_v_buf.vdd"
+= "b.b.supply.vdd" "b.b.reset_buf.vdd"
+= "b.b.supply.vdd" "b.b.inack_inv.vdd"
+= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
+= "b.b.supply.vss" "b.b.t_buf_func[6].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[6].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[5].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[5].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
+= "b.b.supply.vss" "b.b.in_v_buf.vss"
+= "b.b.supply.vss" "b.b.reset_buf.vss"
+= "b.b.supply.vss" "b.b.inack_inv.vss"
+= "b.b.supply.vss" "b.b.inack_ctl.vss"
+= "b.b._en" "b.b.en_buf_f.in"
+= "b.b._en" "b.b.en_buf_t.in"
+= "b.b._en" "b.b.inack_inv.a"
+= "b.b._en" "b.b.inack_ctl.y"
+= "b.b._en" "b.b.inack_ctl.c1"
+= "b.b._en" "b.b._in_aB"
+"b.b.reset_inv.a"->"b.b.reset_inv.y"-
+~("b.b.reset_inv.a")->"b.b.reset_inv.y"+
+= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
+= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
+= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
+= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
+= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
+= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
+= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
+= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
+= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
+= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
+= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
+= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
+= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
+= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
+= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
+= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
+= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
+= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
+= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
+= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
+= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
+= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
+= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
+= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
+= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
+= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
+= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
+= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
+= "b.b.out.d[6].d[0]" "b.b.f_buf_func[6].y"
+= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
+= "b.b.out.d[6].d[1]" "b.b.t_buf_func[6].y"
+= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
+= "b.b.out.d[5].d[0]" "b.b.f_buf_func[5].y"
+= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
+= "b.b.out.d[5].d[1]" "b.b.t_buf_func[5].y"
+= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
+= "b.b.out.d[4].d[0]" "b.b.f_buf_func[4].y"
+= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
+= "b.b.out.d[4].d[1]" "b.b.t_buf_func[4].y"
+= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
+= "b.b.out.d[3].d[0]" "b.b.f_buf_func[3].y"
+= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
+= "b.b.out.d[3].d[1]" "b.b.t_buf_func[3].y"
+= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
+= "b.b.out.d[2].d[0]" "b.b.f_buf_func[2].y"
+= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
+= "b.b.out.d[2].d[1]" "b.b.t_buf_func[2].y"
+= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
+= "b.b.out.d[1].d[0]" "b.b.f_buf_func[1].y"
+= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
+= "b.b.out.d[1].d[1]" "b.b.t_buf_func[1].y"
+= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
+= "b.b.out.d[0].d[0]" "b.b.f_buf_func[0].y"
+= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
+= "b.b.out.d[0].d[1]" "b.b.t_buf_func[0].y"
+= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[0].f" "b.b.vc.in.d[0].f"
+= "b.b.in.d.d[0].t" "b.b.vc.in.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.vc.in.d[0].d[0]"
+= "b.b.in.d.d[0].d[1]" "b.b.vc.in.d[0].d[1]"
+= "b.b.in.d.d[1].f" "b.b.vc.in.d[1].f"
+= "b.b.in.d.d[1].t" "b.b.vc.in.d[1].t"
+= "b.b.in.d.d[1].d[0]" "b.b.vc.in.d[1].d[0]"
+= "b.b.in.d.d[1].d[1]" "b.b.vc.in.d[1].d[1]"
+= "b.b.in.d.d[2].f" "b.b.vc.in.d[2].f"
+= "b.b.in.d.d[2].t" "b.b.vc.in.d[2].t"
+= "b.b.in.d.d[2].d[0]" "b.b.vc.in.d[2].d[0]"
+= "b.b.in.d.d[2].d[1]" "b.b.vc.in.d[2].d[1]"
+= "b.b.in.d.d[3].f" "b.b.vc.in.d[3].f"
+= "b.b.in.d.d[3].t" "b.b.vc.in.d[3].t"
+= "b.b.in.d.d[3].d[0]" "b.b.vc.in.d[3].d[0]"
+= "b.b.in.d.d[3].d[1]" "b.b.vc.in.d[3].d[1]"
+= "b.b.in.d.d[4].f" "b.b.vc.in.d[4].f"
+= "b.b.in.d.d[4].t" "b.b.vc.in.d[4].t"
+= "b.b.in.d.d[4].d[0]" "b.b.vc.in.d[4].d[0]"
+= "b.b.in.d.d[4].d[1]" "b.b.vc.in.d[4].d[1]"
+= "b.b.in.d.d[5].f" "b.b.vc.in.d[5].f"
+= "b.b.in.d.d[5].t" "b.b.vc.in.d[5].t"
+= "b.b.in.d.d[5].d[0]" "b.b.vc.in.d[5].d[0]"
+= "b.b.in.d.d[5].d[1]" "b.b.vc.in.d[5].d[1]"
+= "b.b.in.d.d[6].f" "b.b.vc.in.d[6].f"
+= "b.b.in.d.d[6].t" "b.b.vc.in.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.vc.in.d[6].d[0]"
+= "b.b.in.d.d[6].d[1]" "b.b.vc.in.d[6].d[1]"
+= "b.b.in.a" "b.b.inack_inv.y"
+= "b.b.in.v" "b.b.in_v_buf.y"
+= "b.b.in.v" "b.b.inack_ctl.c2"
+= "b.b.in.d.d[6].d[0]" "b.b.f_buf_func[6].n1"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.t_buf_func[6].n1"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.f_buf_func[5].n1"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.t_buf_func[5].n1"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.f_buf_func[4].n1"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.t_buf_func[4].n1"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.f_buf_func[3].n1"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.t_buf_func[3].n1"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.f_buf_func[2].n1"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.t_buf_func[2].n1"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.f_buf_func[1].n1"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.t_buf_func[1].n1"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.f_buf_func[0].n1"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.t_buf_func[0].n1"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+"b.b.inack_inv.a"->"b.b.inack_inv.y"-
+~("b.b.inack_inv.a")->"b.b.inack_inv.y"+
+= "b.b._in_v" "b.b.in_v_buf.a"
+= "b.b._in_v" "b.b.vc.out"
+"b.b.reset_buf.a"->"b.b.reset_buf._y"-
+~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
+"b.b.reset_buf._y"->"b.b.reset_buf.y"-
+~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
+"b.b.flush_inv.a"->"b.b.flush_inv.y"-
+~("b.b.flush_inv.a")->"b.b.flush_inv.y"+
+= "b.b._reset_BX" "b.b.reset_bufarray.in"
+= "b.b._reset_BX" "b.b.reset_buf.y"
+= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
+= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
+= "b.b.reset_B" "b.b.reset_buf.a"
+= "b.b.reset_B" "b.b.reset_inv.a"
+= "b.b._reset" "b.b.t_buf_func[6].sr"
+= "b.b._reset" "b.b.t_buf_func[6].pr"
+= "b.b._reset" "b.b.t_buf_func[5].sr"
+= "b.b._reset" "b.b.t_buf_func[5].pr"
+= "b.b._reset" "b.b.t_buf_func[4].sr"
+= "b.b._reset" "b.b.t_buf_func[4].pr"
+= "b.b._reset" "b.b.t_buf_func[3].sr"
+= "b.b._reset" "b.b.t_buf_func[3].pr"
+= "b.b._reset" "b.b.t_buf_func[2].sr"
+= "b.b._reset" "b.b.t_buf_func[2].pr"
+= "b.b._reset" "b.b.t_buf_func[1].sr"
+= "b.b._reset" "b.b.t_buf_func[1].pr"
+= "b.b._reset" "b.b.t_buf_func[0].sr"
+= "b.b._reset" "b.b.t_buf_func[0].pr"
+= "b.b._reset" "b.b.reset_inv.y"
+= "b.b._flushB" "b.b.t_buf_func[6].c1"
+= "b.b._flushB" "b.b.f_buf_func[6].c1"
+= "b.b._flushB" "b.b.t_buf_func[5].c1"
+= "b.b._flushB" "b.b.f_buf_func[5].c1"
+= "b.b._flushB" "b.b.t_buf_func[4].c1"
+= "b.b._flushB" "b.b.f_buf_func[4].c1"
+= "b.b._flushB" "b.b.t_buf_func[3].c1"
+= "b.b._flushB" "b.b.f_buf_func[3].c1"
+= "b.b._flushB" "b.b.t_buf_func[2].c1"
+= "b.b._flushB" "b.b.f_buf_func[2].c1"
+= "b.b._flushB" "b.b.t_buf_func[1].c1"
+= "b.b._flushB" "b.b.f_buf_func[1].c1"
+= "b.b._flushB" "b.b.t_buf_func[0].c1"
+= "b.b._flushB" "b.b.f_buf_func[0].c1"
+= "b.b._flushB" "b.b.flush_inv.y"
+"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
+~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
+"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
+~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
+= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
+= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[6]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[5]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
+= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
+"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
+~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
+"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
+~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
+= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
+= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[6]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[5]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
+= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
+= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
+= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
+= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
+= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
+= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
+= "b.b._reset_BXX[5]" "b.b.reset_bufarray.out[5]"
+= "b.b._reset_BXX[6]" "b.b.reset_bufarray.out[6]"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[6]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[5]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
+~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].sr"->"b.b.t_buf_func[0]._y"+
+"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"|"b.b.t_buf_func[0].pr"->"b.b.t_buf_func[0]._y"-
+"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
+~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
+~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].sr"->"b.b.t_buf_func[1]._y"+
+"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"|"b.b.t_buf_func[1].pr"->"b.b.t_buf_func[1]._y"-
+"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
+~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
+~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].sr"->"b.b.t_buf_func[2]._y"+
+"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"|"b.b.t_buf_func[2].pr"->"b.b.t_buf_func[2]._y"-
+"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
+~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
+~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].sr"->"b.b.t_buf_func[3]._y"+
+"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"|"b.b.t_buf_func[3].pr"->"b.b.t_buf_func[3]._y"-
+"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
+~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
+~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].sr"->"b.b.t_buf_func[4]._y"+
+"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"|"b.b.t_buf_func[4].pr"->"b.b.t_buf_func[4]._y"-
+"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
+~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
+~"b.b.t_buf_func[5].c1"&~"b.b.t_buf_func[5].sr"->"b.b.t_buf_func[5]._y"+
+"b.b.t_buf_func[5].c1"&"b.b.t_buf_func[5].n1"&"b.b.t_buf_func[5].n2"|"b.b.t_buf_func[5].pr"->"b.b.t_buf_func[5]._y"-
+"b.b.t_buf_func[5]._y"->"b.b.t_buf_func[5].y"-
+~("b.b.t_buf_func[5]._y")->"b.b.t_buf_func[5].y"+
+~"b.b.t_buf_func[6].c1"&~"b.b.t_buf_func[6].sr"->"b.b.t_buf_func[6]._y"+
+"b.b.t_buf_func[6].c1"&"b.b.t_buf_func[6].n1"&"b.b.t_buf_func[6].n2"|"b.b.t_buf_func[6].pr"->"b.b.t_buf_func[6]._y"-
+"b.b.t_buf_func[6]._y"->"b.b.t_buf_func[6].y"-
+~("b.b.t_buf_func[6]._y")->"b.b.t_buf_func[6].y"+
+~"b.b.f_buf_func[0].c1"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
+"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
+"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
+~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
+~"b.b.f_buf_func[1].c1"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
+"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
+"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
+~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
+~"b.b.f_buf_func[2].c1"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
+"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
+"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
+~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
+~"b.b.f_buf_func[3].c1"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
+"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
+"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
+~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
+~"b.b.f_buf_func[4].c1"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
+"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
+"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
+~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
+~"b.b.f_buf_func[5].c1"|~"b.b.f_buf_func[5].pr_B"->"b.b.f_buf_func[5]._y"+
+"b.b.f_buf_func[5].c1"&"b.b.f_buf_func[5].n1"&"b.b.f_buf_func[5].n2"&"b.b.f_buf_func[5].sr_B"->"b.b.f_buf_func[5]._y"-
+"b.b.f_buf_func[5]._y"->"b.b.f_buf_func[5].y"-
+~("b.b.f_buf_func[5]._y")->"b.b.f_buf_func[5].y"+
+~"b.b.f_buf_func[6].c1"|~"b.b.f_buf_func[6].pr_B"->"b.b.f_buf_func[6]._y"+
+"b.b.f_buf_func[6].c1"&"b.b.f_buf_func[6].n1"&"b.b.f_buf_func[6].n2"&"b.b.f_buf_func[6].sr_B"->"b.b.f_buf_func[6]._y"-
+"b.b.f_buf_func[6]._y"->"b.b.f_buf_func[6].y"-
+~("b.b.f_buf_func[6]._y")->"b.b.f_buf_func[6].y"+
+= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
+= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
+= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
+= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
+= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
+= "b.b._en_X_t[5]" "b.b.en_buf_t.out[5]"
+= "b.b._en_X_t[6]" "b.b.en_buf_t.out[6]"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[6].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[5].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[4].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[3].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[2].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[1].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[0].n2"
+= "b.b._en_X_t[0]" "b.b._en_X_t[6]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[5]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
+= "b.b.out_v" "b.b.inack_ctl.n1"
+= "b._reset_B" "b.b.reset_B"
+= "b.flush" "b.b.flush"
+= "Vdd" "b.supply.vdd"
+= "GND" "b.supply.vss"
+= "b.out_v" "b.b.out_v"
+= "b.out.d[0].d[0]" "b.out.d[0].f"
+= "b.out.d[0].d[1]" "b.out.d[0].t"
+= "b.out.d[1].d[0]" "b.out.d[1].f"
+= "b.out.d[1].d[1]" "b.out.d[1].t"
+= "b.out.d[2].d[0]" "b.out.d[2].f"
+= "b.out.d[2].d[1]" "b.out.d[2].t"
+= "b.out.d[3].d[0]" "b.out.d[3].f"
+= "b.out.d[3].d[1]" "b.out.d[3].t"
+= "b.out.d[4].d[0]" "b.out.d[4].f"
+= "b.out.d[4].d[1]" "b.out.d[4].t"
+= "b.out.d[5].d[0]" "b.out.d[5].f"
+= "b.out.d[5].d[1]" "b.out.d[5].t"
+= "b.out.d[6].d[0]" "b.out.d[6].f"
+= "b.out.d[6].d[1]" "b.out.d[6].t"
+= "b.out.d[6].d[0]" "b.out.d[6].f"
+= "b.out.d[6].d[1]" "b.out.d[6].t"
+= "b.out.d[5].d[0]" "b.out.d[5].f"
+= "b.out.d[5].d[1]" "b.out.d[5].t"
+= "b.out.d[4].d[0]" "b.out.d[4].f"
+= "b.out.d[4].d[1]" "b.out.d[4].t"
+= "b.out.d[3].d[0]" "b.out.d[3].f"
+= "b.out.d[3].d[1]" "b.out.d[3].t"
+= "b.out.d[2].d[0]" "b.out.d[2].f"
+= "b.out.d[2].d[1]" "b.out.d[2].t"
+= "b.out.d[1].d[0]" "b.out.d[1].f"
+= "b.out.d[1].d[1]" "b.out.d[1].t"
+= "b.out.d[0].d[0]" "b.out.d[0].f"
+= "b.out.d[0].d[1]" "b.out.d[0].t"
+= "b.out.d[0].f" "b.b.out.d[0].f"
+= "b.out.d[0].t" "b.b.out.d[0].t"
+= "b.out.d[0].d[0]" "b.b.out.d[0].d[0]"
+= "b.out.d[0].d[1]" "b.b.out.d[0].d[1]"
+= "b.out.d[1].f" "b.b.out.d[1].f"
+= "b.out.d[1].t" "b.b.out.d[1].t"
+= "b.out.d[1].d[0]" "b.b.out.d[1].d[0]"
+= "b.out.d[1].d[1]" "b.b.out.d[1].d[1]"
+= "b.out.d[2].f" "b.b.out.d[2].f"
+= "b.out.d[2].t" "b.b.out.d[2].t"
+= "b.out.d[2].d[0]" "b.b.out.d[2].d[0]"
+= "b.out.d[2].d[1]" "b.b.out.d[2].d[1]"
+= "b.out.d[3].f" "b.b.out.d[3].f"
+= "b.out.d[3].t" "b.b.out.d[3].t"
+= "b.out.d[3].d[0]" "b.b.out.d[3].d[0]"
+= "b.out.d[3].d[1]" "b.b.out.d[3].d[1]"
+= "b.out.d[4].f" "b.b.out.d[4].f"
+= "b.out.d[4].t" "b.b.out.d[4].t"
+= "b.out.d[4].d[0]" "b.b.out.d[4].d[0]"
+= "b.out.d[4].d[1]" "b.b.out.d[4].d[1]"
+= "b.out.d[5].f" "b.b.out.d[5].f"
+= "b.out.d[5].t" "b.b.out.d[5].t"
+= "b.out.d[5].d[0]" "b.b.out.d[5].d[0]"
+= "b.out.d[5].d[1]" "b.b.out.d[5].d[1]"
+= "b.out.d[6].f" "b.b.out.d[6].f"
+= "b.out.d[6].t" "b.b.out.d[6].t"
+= "b.out.d[6].d[0]" "b.b.out.d[6].d[0]"
+= "b.out.d[6].d[1]" "b.b.out.d[6].d[1]"
+= "b.out.d[6].d[0]" "b.out.d[6].f"
+= "b.out.d[6].d[1]" "b.out.d[6].t"
+= "b.out.d[5].d[0]" "b.out.d[5].f"
+= "b.out.d[5].d[1]" "b.out.d[5].t"
+= "b.out.d[4].d[0]" "b.out.d[4].f"
+= "b.out.d[4].d[1]" "b.out.d[4].t"
+= "b.out.d[3].d[0]" "b.out.d[3].f"
+= "b.out.d[3].d[1]" "b.out.d[3].t"
+= "b.out.d[2].d[0]" "b.out.d[2].f"
+= "b.out.d[2].d[1]" "b.out.d[2].t"
+= "b.out.d[1].d[0]" "b.out.d[1].f"
+= "b.out.d[1].d[1]" "b.out.d[1].t"
+= "b.out.d[0].d[0]" "b.out.d[0].f"
+= "b.out.d[0].d[1]" "b.out.d[0].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.v" "b.b.in.v"
+= "b.in.a" "b.b.in.a"
+= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
+= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
+= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
+= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
+= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
+= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
+= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
+= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
+= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
+= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
+= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
+= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
+= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
+= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
+= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
+= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
+= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
+= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
+= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
+= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
+= "b.in.d.d[5].f" "b.b.in.d.d[5].f"
+= "b.in.d.d[5].t" "b.b.in.d.d[5].t"
+= "b.in.d.d[5].d[0]" "b.b.in.d.d[5].d[0]"
+= "b.in.d.d[5].d[1]" "b.b.in.d.d[5].d[1]"
+= "b.in.d.d[6].f" "b.b.in.d.d[6].f"
+= "b.in.d.d[6].t" "b.b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.b.in.d.d[6].d[0]"
+= "b.in.d.d[6].d[1]" "b.b.in.d.d[6].d[1]"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

test/unit_tests/buffer_register_7/test.act

@@ -0,0 +1,52 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc buffer_register_7 (avMx1of2<7> in; Mx1of2<7> out; bool? out_v, flush){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    buffer_register<7> b(.in = in, .out = out, .out_v = out_v, .flush = flush, .reset_B = _reset_B);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+buffer_register_7 b;

test/unit_tests/buffer_register_7/test.prsim

@@ -0,0 +1,163 @@
+watchall
+
+set b.out_v 0
+set b.flush 0
+set-qdi-channel-neutral "b.in" 7
+
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+
+system "echo '[] Flushing data'"
+set b.flush 1
+cycle
+assert b.out.d[0].t 0
+assert b.out.d[1].t 0
+assert b.out.d[2].t 0
+assert b.out.d[3].t 0
+assert b.out.d[4].t 0
+assert b.out.d[5].t 0
+assert b.out.d[6].t 0
+assert b.out.d[0].f 0
+assert b.out.d[1].f 0
+assert b.out.d[2].f 0
+assert b.out.d[3].f 0
+assert b.out.d[4].f 0
+assert b.out.d[5].f 0
+assert b.out.d[6].f 0
+set b.out_v 0
+set b.flush 0
+cycle
+
+system "echo '[] Sending in a 0'"
+set-qdi-channel-valid "b.in" 7 0
+cycle
+# assert-qdi-channel-valid 'b.out' 7 127
+assert b.in.a 0
+assert b.in.v 1
+assert-var-int "b.out" 7 0
+
+system "echo '[] Sending in output valid'"
+set b.out_v 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 0
+
+
+system "echo '[] Flushing data'"
+set b.flush 1
+cycle
+assert b.out.d[0].t 0
+assert b.out.d[1].t 0
+assert b.out.d[2].t 0
+assert b.out.d[3].t 0
+assert b.out.d[4].t 0
+assert b.out.d[5].t 0
+assert b.out.d[6].t 0
+assert b.out.d[0].f 0
+assert b.out.d[1].f 0
+assert b.out.d[2].f 0
+assert b.out.d[3].f 0
+assert b.out.d[4].f 0
+assert b.out.d[5].f 0
+assert b.out.d[6].f 0
+set b.out_v 0
+cycle
+set b.flush 0
+cycle
+
+
+system "echo '[] Sending in a 127'"
+set-qdi-channel-valid "b.in" 7 127
+cycle
+# assert-qdi-channel-valid 'b.out' 7 127
+assert b.in.a 0
+assert b.in.v 1
+assert-var-int "b.out" 7 127
+
+system "echo '[] Sending in output valid'"
+set b.out_v 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 127
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 127
+
+
+
+
+system "echo '[] Flushing data'"
+set b.flush 1
+cycle
+assert b.out.d[0].t 0
+assert b.out.d[1].t 0
+assert b.out.d[2].t 0
+assert b.out.d[3].t 0
+assert b.out.d[4].t 0
+assert b.out.d[5].t 0
+assert b.out.d[6].t 0
+assert b.out.d[0].f 0
+assert b.out.d[1].f 0
+assert b.out.d[2].f 0
+assert b.out.d[3].f 0
+assert b.out.d[4].f 0
+assert b.out.d[5].f 0
+assert b.out.d[6].f 0
+set b.out_v 0
+cycle
+set b.flush 0
+cycle
+
+
+
+
+system "echo '[] Sending in a 56'"
+set-qdi-channel-valid "b.in" 7 56
+cycle
+assert b.in.a 0
+assert b.in.v 1
+assert-var-int "b.out" 7 56
+
+system "echo '[] Sending in output valid'"
+set b.out_v 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 56
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 56
+
+system "echo '[] Resetting'"
+set Reset 1
+cycle
+assert-var-int "b.out" 7 127
+set Reset 0
+cycle
+assert-var-int "b.out" 7 127

test/unit_tests/decoder_2d_dly_8_16/test.prsim

@@ -7,8 +7,8 @@ set Reset 0
 # Set delay config lines
 set b.dly_cfg[0] 1
 set b.dly_cfg[1] 1
-set b.dly_cfg[2] 0
-set b.dly_cfg[3] 0
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
 
 cycle
 

test/unit_tests/decoder_2d_dly_and_2_4/run/prsim.out

@@ -1,351 +0,0 @@
-t.de.dly.dly[2].y t.de.dly.dly[4].y t.de.addr_buf._in_v t.de.dly._a[2] t.in.d.d[1].f t.de.dly.mu2[3].b t.de.dly.dly[3].y t.de.dly.dly[7].y t.de.dly.dly[3].___y t.in.d.d[0].t t.dly_cfg[1] t.de.dly.dly[13].__y t.de.dly.dly[1]._y t.de.dly.dly[13]._y t.de.addr_buf._out_a_BX_t[0] t.de.dly.dly[7].a t.de.dly.mu2[3]._y t.de.dly.dly[3].a t.in.d.d[0].f t.de.dly.dly[5]._y t.de.dly.dly[7].__y t.de.addr_buf._out_a_B t.de.dly.dly[3].__y t.dly_cfg[2] t.de.dly.dly[2].__y t.de.dly.dly[8].___y t.de.addr_buf._out_a_BX_f[0] t.de.addr_buf.vc.ct.in[0] t.de.dly.dly[13].___y t.de.dly.dly[1].a t.in.d.d[1].t t.in.v t.de.dly.dly[5].__y t.in.d.d[2].t t.de.addr_buf.in_v_buf._y t.de.dly.dly[9].y t.dly_cfg[0] t.in.d.d[2].f t.de.dly.out t.de.dly.mu2[2]._y t.dly_cfg[3] t.de.dly.dly[10]._y t.de.dly.dly[9].__y t.de.dly.and2[3]._y t.de.dly._a[3] t.de.addr_buf.vc.OR2_tf[1]._y t.de.addr_buf.vc.ct.in[2] t.de.dly.dly[5].y t.de.dly.dly[11].___y t.de.dly.dly[4].__y t.de.dly.and2[1]._y t.de.dly.dly[6].___y t.de.dly.dly[10].y t.de.dly.dly[11]._y t.de.dly.dly[10].__y t.de.dly.dly[12].__y t.de.dly.dly[1].__y t.de.addr_buf.vc.ct.in[1] t.de.addr_buf.out_a_B_buf_f.buf1._y t.de.dly._a[1] t.de.dly.dly[14].__y t.de.dly.dly[6].y t.de.dly.dly[11].y t.de.dly.dly[7]._y t.de.addr_buf.vc.ct.C3Els[0]._y t.de.dly.mu2[1]._y t.de.dly.dly[9]._y t.de.dly.dly[5].___y t.de.dly.dly[14]._y t.de.dly.and2[2]._y t.de.dly.dly[8].y t.de.dly.dly[9].___y t.de.dly.mu2[0]._s t.de.dly.mu2[1]._s t.de.dly.dly[2]._y t.de.dly.dly[8].__y t.de.dly.dly[12].___y t.de.dly.dly[13].y t.de.dly.dly[10].___y t.de.dly.dly[1].y t.de.dly.dly[1].___y t.de.dly.dly[2].___y t.de.addr_buf.out_a_B_buf_t.buf1._y t.de.dly.dly[4]._y t.de.dly.dly[8]._y t.de.dly.dly[4].___y t.de.dly.dly[12].y t.de.dly.dly[6].__y t.de.dly.dly[7].___y t.de.addr_buf.vc.OR2_tf[2]._y t.de.dly.dly[3]._y t.de.dly.dly[14].___y t.de.dly.mu2[3]._s t.de.dly.dly[11].__y t.de.dly.dly[6]._y t.de.addr_buf.vc.OR2_tf[0]._y t.de.dly.mu2[2]._s t.de.dly.mu2[0]._y t.de.dly.dly[12]._y 
-	    244317 t.in.d.d[0].f : 0
-	    244317 t.dly_cfg[3] : 1
-	    244317 t.dly_cfg[2] : 1
-	    244317 t.in.d.d[1].f : 0
-	    244317 Reset : 0
-	    244317 t.dly_cfg[1] : 1
-	    244317 t.in.d.d[2].t : 0
-	    244317 t.in.d.d[0].t : 0
-	    244317 t.dly_cfg[0] : 1
-	    244317 t.in.d.d[2].f : 0
-	    244317 t.in.d.d[1].t : 0
-	    244318 t._reset_B : 1  [by Reset:=0]
-	    244404 t.de.dly.mu2[3]._s : 0  [by t.dly_cfg[3]:=1]
-	    244495 t.de.addr_buf.vc.OR2_tf[1]._y : 1  [by t.in.d.d[1].t:=0]
-	    244611 t.de.dly.mu2[2]._s : 0  [by t.dly_cfg[2]:=1]
-	    244659 t.de.addr_buf.vc.ct.in[1] : 0  [by t.de.addr_buf.vc.OR2_tf[1]._y:=1]
-	    244907 t.de.addr_buf.vc.OR2_tf[2]._y : 1  [by t.in.d.d[2].f:=0]
-	    245121 t.de.addr_buf.reset_buf._y : 0  [by t._reset_B:=1]
-	    245143 t.de.addr_buf._reset_BX : 1  [by t.de.addr_buf.reset_buf._y:=0]
-	    245526 t.de.dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
-	    245990 t.de.addr_buf.reset_bufarray.buf1._y : 0  [by t.de.addr_buf._reset_BX:=1]
-	    246123 t.de.dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
-	    246123 t.de.addr_buf._reset_BXX[0] : 1  [by t.de.addr_buf.reset_bufarray.buf1._y:=0]
-	    246324 t.de.addr_buf.vc.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
-	    247102 t.de.addr_buf.vc.ct.in[2] : 0  [by t.de.addr_buf.vc.OR2_tf[2]._y:=1]
-	    261986 t.de.addr_buf.vc.ct.in[0] : 0  [by t.de.addr_buf.vc.OR2_tf[0]._y:=1]
-	    262345 t.de.addr_buf.vc.ct.C3Els[0]._y : 1  [by t.de.addr_buf.vc.ct.in[0]:=0]
-	    275654 t.de.dly.mu2[0]._y : 1  [by t.de.dly.mu2[0]._s:=0]
-	    275875 t.de.dly._a[1] : 0  [by t.de.dly.mu2[0]._y:=1]
-	    275882 t.de.dly.and2[1]._y : 1  [by t.de.dly._a[1]:=0]
-	    275912 t.de.dly.dly[1].a : 0  [by t.de.dly.and2[1]._y:=1]
-	    276461 t.de.addr_buf._in_v : 0  [by t.de.addr_buf.vc.ct.C3Els[0]._y:=1]
-	    282625 t.de.dly.dly[1]._y : 1  [by t.de.dly.dly[1].a:=0]
-	    282716 t.de.dly.dly[1].__y : 0  [by t.de.dly.dly[1]._y:=1]
-	    284905 t.de.dly.dly[1].___y : 1  [by t.de.dly.dly[1].__y:=0]
-	    284912 t.de.dly.dly[1].y : 0  [by t.de.dly.dly[1].___y:=1]
-	    287699 t.de.dly.dly[2]._y : 1  [by t.de.dly.dly[1].y:=0]
-	    287805 t.de.dly.dly[2].__y : 0  [by t.de.dly.dly[2]._y:=1]
-	    287883 t.de.dly.dly[2].___y : 1  [by t.de.dly.dly[2].__y:=0]
-	    288158 t.de.dly.dly[2].y : 0  [by t.de.dly.dly[2].___y:=1]
-	    307154 t.de.dly.mu2[1]._y : 1  [by t.de.dly.dly[2].y:=0]
-	    307609 t.de.dly._a[2] : 0  [by t.de.dly.mu2[1]._y:=1]
-	    307621 t.de.dly.and2[2]._y : 1  [by t.de.dly._a[2]:=0]
-	    308025 t.de.dly.dly[3].a : 0  [by t.de.dly.and2[2]._y:=1]
-	    308037 t.de.dly.dly[3]._y : 1  [by t.de.dly.dly[3].a:=0]
-	    313953 t.de.dly.dly[3].__y : 0  [by t.de.dly.dly[3]._y:=1]
-	    318229 t.de.dly.dly[3].___y : 1  [by t.de.dly.dly[3].__y:=0]
-	    321128 t.de.dly.dly[3].y : 0  [by t.de.dly.dly[3].___y:=1]
-	    325423 t.de.dly.dly[4]._y : 1  [by t.de.dly.dly[3].y:=0]
-	    325425 t.de.dly.dly[4].__y : 0  [by t.de.dly.dly[4]._y:=1]
-	    329960 t.de.dly.dly[4].___y : 1  [by t.de.dly.dly[4].__y:=0]
-	    331209 t.de.dly.dly[4].y : 0  [by t.de.dly.dly[4].___y:=1]
-	    333922 t.de.addr_buf.in_v_buf._y : 1  [by t.de.addr_buf._in_v:=0]
-	    334088 t.in.v : 0  [by t.de.addr_buf.in_v_buf._y:=1]
-	    334708 t.de.dly.dly[5]._y : 1  [by t.de.dly.dly[4].y:=0]
-	    334783 t.de.dly.dly[5].__y : 0  [by t.de.dly.dly[5]._y:=1]
-	    335128 t.de.dly.dly[5].___y : 1  [by t.de.dly.dly[5].__y:=0]
-	    335266 t.de.dly.dly[5].y : 0  [by t.de.dly.dly[5].___y:=1]
-	    340529 t.de.dly.dly[6]._y : 1  [by t.de.dly.dly[5].y:=0]
-	    340531 t.de.dly.dly[6].__y : 0  [by t.de.dly.dly[6]._y:=1]
-	    384448 t.de.dly.dly[6].___y : 1  [by t.de.dly.dly[6].__y:=0]
-	    384449 t.de.dly.dly[6].y : 0  [by t.de.dly.dly[6].___y:=1]
-	    384997 t.de.dly.mu2[2]._y : 1  [by t.de.dly.dly[6].y:=0]
-	    385008 t.de.dly._a[3] : 0  [by t.de.dly.mu2[2]._y:=1]
-	    385378 t.de.dly.and2[3]._y : 1  [by t.de.dly._a[3]:=0]
-	    385445 t.de.dly.dly[7].a : 0  [by t.de.dly.and2[3]._y:=1]
-	    388086 t.de.dly.dly[7]._y : 1  [by t.de.dly.dly[7].a:=0]
-	    388102 t.de.dly.dly[7].__y : 0  [by t.de.dly.dly[7]._y:=1]
-	    392664 t.de.dly.dly[7].___y : 1  [by t.de.dly.dly[7].__y:=0]
-	    393192 t.de.dly.dly[7].y : 0  [by t.de.dly.dly[7].___y:=1]
-	    395627 t.de.dly.dly[8]._y : 1  [by t.de.dly.dly[7].y:=0]
-	    422507 t.de.dly.dly[8].__y : 0  [by t.de.dly.dly[8]._y:=1]
-	    446432 t.de.dly.dly[8].___y : 1  [by t.de.dly.dly[8].__y:=0]
-	    459473 t.de.dly.dly[8].y : 0  [by t.de.dly.dly[8].___y:=1]
-	    459475 t.de.dly.dly[9]._y : 1  [by t.de.dly.dly[8].y:=0]
-	    520433 t.de.dly.dly[9].__y : 0  [by t.de.dly.dly[9]._y:=1]
-	    520436 t.de.dly.dly[9].___y : 1  [by t.de.dly.dly[9].__y:=0]
-	    520465 t.de.dly.dly[9].y : 0  [by t.de.dly.dly[9].___y:=1]
-	    520782 t.de.dly.dly[10]._y : 1  [by t.de.dly.dly[9].y:=0]
-	    522383 t.de.dly.dly[10].__y : 0  [by t.de.dly.dly[10]._y:=1]
-	    522536 t.de.dly.dly[10].___y : 1  [by t.de.dly.dly[10].__y:=0]
-	    522580 t.de.dly.dly[10].y : 0  [by t.de.dly.dly[10].___y:=1]
-	    525341 t.de.dly.dly[11]._y : 1  [by t.de.dly.dly[10].y:=0]
-	    539024 t.de.dly.dly[11].__y : 0  [by t.de.dly.dly[11]._y:=1]
-	    539025 t.de.dly.dly[11].___y : 1  [by t.de.dly.dly[11].__y:=0]
-	    539242 t.de.dly.dly[11].y : 0  [by t.de.dly.dly[11].___y:=1]
-	    539264 t.de.dly.dly[12]._y : 1  [by t.de.dly.dly[11].y:=0]
-	    539265 t.de.dly.dly[12].__y : 0  [by t.de.dly.dly[12]._y:=1]
-	    540846 t.de.dly.dly[12].___y : 1  [by t.de.dly.dly[12].__y:=0]
-	    550191 t.de.dly.dly[12].y : 0  [by t.de.dly.dly[12].___y:=1]
-	    550350 t.de.dly.dly[13]._y : 1  [by t.de.dly.dly[12].y:=0]
-	    570026 t.de.dly.dly[13].__y : 0  [by t.de.dly.dly[13]._y:=1]
-	    571313 t.de.dly.dly[13].___y : 1  [by t.de.dly.dly[13].__y:=0]
-	    573545 t.de.dly.dly[13].y : 0  [by t.de.dly.dly[13].___y:=1]
-	    573690 t.de.dly.dly[14]._y : 1  [by t.de.dly.dly[13].y:=0]
-	    576522 t.de.dly.dly[14].__y : 0  [by t.de.dly.dly[14]._y:=1]
-	    582876 t.de.dly.dly[14].___y : 1  [by t.de.dly.dly[14].__y:=0]
-	    582877 t.de.dly.mu2[3].b : 0  [by t.de.dly.dly[14].___y:=1]
-	    622161 t.de.dly.mu2[3]._y : 1  [by t.de.dly.mu2[3].b:=0]
-	    622323 t.de.dly.out : 0  [by t.de.dly.mu2[3]._y:=1]
-	    629692 t.de.addr_buf._out_a_B : 1  [by t.de.dly.out:=0]
-	    629699 t.de.addr_buf.out_a_B_buf_f.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	    629706 t.de.addr_buf.out_a_B_buf_t.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	    629859 t.de.addr_buf._out_a_BX_t[0] : 1  [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=0]
-	    651263 t.de.addr_buf._out_a_BX_f[0] : 1  [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=0]
-[] set Reset 1
-	    651263 Reset : 1
-	    651264 t._reset_B : 0  [by Reset:=1]
-	    651265 t.de.addr_buf.reset_buf._y : 1  [by t._reset_B:=0]
-	    651266 t.de.addr_buf._reset_BX : 0  [by t.de.addr_buf.reset_buf._y:=1]
-	    653509 t.de.addr_buf.reset_bufarray.buf1._y : 1  [by t.de.addr_buf._reset_BX:=0]
-	    653696 t.de.addr_buf._reset_BXX[0] : 0  [by t.de.addr_buf.reset_bufarray.buf1._y:=1]
-[] set Reset 0
-	    653696 Reset : 0
-	    653697 t._reset_B : 1  [by Reset:=0]
-	    657879 t.de.addr_buf.reset_buf._y : 0  [by t._reset_B:=1]
-	    692661 t.de.addr_buf._reset_BX : 1  [by t.de.addr_buf.reset_buf._y:=0]
-	    692662 t.de.addr_buf.reset_bufarray.buf1._y : 0  [by t.de.addr_buf._reset_BX:=1]
-	    693515 t.de.addr_buf._reset_BXX[0] : 1  [by t.de.addr_buf.reset_bufarray.buf1._y:=0]
-[] Sending packet in
-	    693515 t.in.d.d[0].t : 1
-	    693515 t.in.d.d[2].t : 1
-	    693515 t.in.d.d[1].t : 1
-	    693516 t.de.addr_buf.vc.OR2_tf[2]._y : 0  [by t.in.d.d[2].t:=1]
-	    693519 t.de.addr_buf.vc.ct.in[2] : 1  [by t.de.addr_buf.vc.OR2_tf[2]._y:=0]
-	    693520 t.de.addr_buf.vc.OR2_tf[0]._y : 0  [by t.in.d.d[0].t:=1]
-	    693532 t.de.addr_buf.t_buf_func[2]._y : 0  [by t.in.d.d[2].t:=1]
-	    694406 t.de.addr_buf.t_buf_func[0]._y : 0  [by t.in.d.d[0].t:=1]
-	    694407 t.de.atree_x[1].in[0] : 1  [by t.de.addr_buf.t_buf_func[0]._y:=0]
-	    694449 t.de.atree_x[1].b._y : 0  [by t.de.atree_x[1].in[0]:=1]
-	    694461 t.de.addr_buf.vc.ct.in[0] : 1  [by t.de.addr_buf.vc.OR2_tf[0]._y:=0]
-	    696088 t.de.addr_buf.vc.OR2_tf[1]._y : 0  [by t.in.d.d[1].t:=1]
-	    696183 t.de.addr_buf.vc.ct.in[1] : 1  [by t.de.addr_buf.vc.OR2_tf[1]._y:=0]
-	    696518 t.de.addr_buf.vc.ct.C3Els[0]._y : 0  [by t.de.addr_buf.vc.ct.in[1]:=1]
-	    696526 t.de.addr_buf._in_v : 1  [by t.de.addr_buf.vc.ct.C3Els[0]._y:=0]
-	    696560 t.de.addr_buf.in_v_buf._y : 0  [by t.de.addr_buf._in_v:=1]
-	    697224 t.de.vtree_x.OR2_tf[0]._y : 0  [by t.de.atree_x[1].in[0]:=1]
-	    698142 t.de.vtree_x.ct.in[0] : 1  [by t.de.vtree_x.OR2_tf[0]._y:=0]
-	    698146 t.de.vtree_x.ct.b._y : 0  [by t.de.vtree_x.ct.in[0]:=1]
-	    701876 t.de.addr_buf.t_buf_func[1]._y : 0  [by t.in.d.d[1].t:=1]
-	    704274 t.de.atree_y[1].in[0] : 1  [by t.de.addr_buf.t_buf_func[1]._y:=0]
-	    707489 t.de.vtree_y.OR2_tf[0]._y : 0  [by t.de.atree_y[1].in[0]:=1]
-	    708182 t.ag.inx[1] : 1  [by t.de.atree_x[1].b._y:=0]
-	    710447 t.in.v : 1  [by t.de.addr_buf.in_v_buf._y:=0]
-	    744524 t.de.C2el.c1 : 1  [by t.de.vtree_x.ct.b._y:=0]
-	    752494 t.de.atree_y[2].in[1] : 1  [by t.de.addr_buf.t_buf_func[2]._y:=0]
-	    752497 t.de.vtree_y.OR2_tf[1]._y : 0  [by t.de.atree_y[2].in[1]:=1]
-	    752542 t.de.atree_y[3].and2s[0]._y : 0  [by t.de.atree_y[2].in[1]:=1]
-	    752675 t.de.vtree_y.ct.in[1] : 1  [by t.de.vtree_y.OR2_tf[1]._y:=0]
-	    754608 t.de.vtree_y.ct.in[0] : 1  [by t.de.vtree_y.OR2_tf[0]._y:=0]
-	    766507 t.de.vtree_y.ct.C2Els[0]._y : 0  [by t.de.vtree_y.ct.in[0]:=1]
-	    772458 t.de.C2el.c2 : 1  [by t.de.vtree_y.ct.C2Els[0]._y:=0]
-	    773519 t.ag.iny[3] : 1  [by t.de.atree_y[3].and2s[0]._y:=0]
-	    774346 t.ag.ands[7]._y : 0  [by t.ag.iny[3]:=1]
-	    774519 t.out[7] : 1  [by t.ag.ands[7]._y:=0]
-	    811943 t.de.C2el._y : 0  [by t.de.C2el.c2:=1]
-	    812127 t.de.C2el.y : 1  [by t.de.C2el._y:=0]
-	    812128 t.de.dly.and2[0]._y : 0  [by t.de.C2el.y:=1]
-	    812132 t.de.dly.dly[0].a : 1  [by t.de.dly.and2[0]._y:=0]
-	    812200 t.de.addr_buf.inack_ctl._y : 0  [by t.de.C2el.y:=1]
-	    812296 t.in.a : 1  [by t.de.addr_buf.inack_ctl._y:=0]
-	    812432 t.de.addr_buf._en : 0  [by t.in.a:=1]
-	    812433 t.de.addr_buf.en_buf_f.buf1._y : 1  [by t.de.addr_buf._en:=0]
-	    812674 t.de.addr_buf._en_X_f[0] : 0  [by t.de.addr_buf.en_buf_f.buf1._y:=1]
-	    831478 t.de.addr_buf.en_buf_t.buf1._y : 1  [by t.de.addr_buf._en:=0]
-	    835437 t.de.addr_buf._en_X_t[0] : 0  [by t.de.addr_buf.en_buf_t.buf1._y:=1]
-	    849420 t.de.dly.dly[0]._y : 0  [by t.de.dly.dly[0].a:=1]
-	    849432 t.de.dly.dly[0].__y : 1  [by t.de.dly.dly[0]._y:=0]
-	    853332 t.de.dly.dly[0].___y : 0  [by t.de.dly.dly[0].__y:=1]
-	    854361 t.de.dly.dly[0].y : 1  [by t.de.dly.dly[0].___y:=0]
-	    854362 t.de.dly.mu2[0]._y : 0  [by t.de.dly.dly[0].y:=1]
-	    854418 t.de.dly._a[1] : 1  [by t.de.dly.mu2[0]._y:=0]
-	    899424 t.de.dly.and2[1]._y : 0  [by t.de.dly._a[1]:=1]
-	    899425 t.de.dly.dly[1].a : 1  [by t.de.dly.and2[1]._y:=0]
-	    899462 t.de.dly.dly[1]._y : 0  [by t.de.dly.dly[1].a:=1]
-	    922837 t.de.dly.dly[1].__y : 1  [by t.de.dly.dly[1]._y:=0]
-	    922838 t.de.dly.dly[1].___y : 0  [by t.de.dly.dly[1].__y:=1]
-	    926402 t.de.dly.dly[1].y : 1  [by t.de.dly.dly[1].___y:=0]
-	    928094 t.de.dly.dly[2]._y : 0  [by t.de.dly.dly[1].y:=1]
-	    928107 t.de.dly.dly[2].__y : 1  [by t.de.dly.dly[2]._y:=0]
-	    945091 t.de.dly.dly[2].___y : 0  [by t.de.dly.dly[2].__y:=1]
-	    945448 t.de.dly.dly[2].y : 1  [by t.de.dly.dly[2].___y:=0]
-	    945473 t.de.dly.mu2[1]._y : 0  [by t.de.dly.dly[2].y:=1]
-	    945494 t.de.dly._a[2] : 1  [by t.de.dly.mu2[1]._y:=0]
-	    945495 t.de.dly.and2[2]._y : 0  [by t.de.dly._a[2]:=1]
-	    955143 t.de.dly.dly[3].a : 1  [by t.de.dly.and2[2]._y:=0]
-	    955144 t.de.dly.dly[3]._y : 0  [by t.de.dly.dly[3].a:=1]
-	    955145 t.de.dly.dly[3].__y : 1  [by t.de.dly.dly[3]._y:=0]
-	    955306 t.de.dly.dly[3].___y : 0  [by t.de.dly.dly[3].__y:=1]
-	    956343 t.de.dly.dly[3].y : 1  [by t.de.dly.dly[3].___y:=0]
-	    956348 t.de.dly.dly[4]._y : 0  [by t.de.dly.dly[3].y:=1]
-	    956929 t.de.dly.dly[4].__y : 1  [by t.de.dly.dly[4]._y:=0]
-	    957337 t.de.dly.dly[4].___y : 0  [by t.de.dly.dly[4].__y:=1]
-	    957348 t.de.dly.dly[4].y : 1  [by t.de.dly.dly[4].___y:=0]
-	    958395 t.de.dly.dly[5]._y : 0  [by t.de.dly.dly[4].y:=1]
-	    958409 t.de.dly.dly[5].__y : 1  [by t.de.dly.dly[5]._y:=0]
-	    958427 t.de.dly.dly[5].___y : 0  [by t.de.dly.dly[5].__y:=1]
-	    958431 t.de.dly.dly[5].y : 1  [by t.de.dly.dly[5].___y:=0]
-	    958535 t.de.dly.dly[6]._y : 0  [by t.de.dly.dly[5].y:=1]
-	    989979 t.de.dly.dly[6].__y : 1  [by t.de.dly.dly[6]._y:=0]
-	    991183 t.de.dly.dly[6].___y : 0  [by t.de.dly.dly[6].__y:=1]
-	    999638 t.de.dly.dly[6].y : 1  [by t.de.dly.dly[6].___y:=0]
-	    999866 t.de.dly.mu2[2]._y : 0  [by t.de.dly.dly[6].y:=1]
-	   1000709 t.de.dly._a[3] : 1  [by t.de.dly.mu2[2]._y:=0]
-	   1002168 t.de.dly.and2[3]._y : 0  [by t.de.dly._a[3]:=1]
-	   1002238 t.de.dly.dly[7].a : 1  [by t.de.dly.and2[3]._y:=0]
-	   1052660 t.de.dly.dly[7]._y : 0  [by t.de.dly.dly[7].a:=1]
-	   1052671 t.de.dly.dly[7].__y : 1  [by t.de.dly.dly[7]._y:=0]
-	   1052674 t.de.dly.dly[7].___y : 0  [by t.de.dly.dly[7].__y:=1]
-	   1052728 t.de.dly.dly[7].y : 1  [by t.de.dly.dly[7].___y:=0]
-	   1053876 t.de.dly.dly[8]._y : 0  [by t.de.dly.dly[7].y:=1]
-	   1055037 t.de.dly.dly[8].__y : 1  [by t.de.dly.dly[8]._y:=0]
-	   1063689 t.de.dly.dly[8].___y : 0  [by t.de.dly.dly[8].__y:=1]
-	   1063770 t.de.dly.dly[8].y : 1  [by t.de.dly.dly[8].___y:=0]
-	   1074847 t.de.dly.dly[9]._y : 0  [by t.de.dly.dly[8].y:=1]
-	   1092830 t.de.dly.dly[9].__y : 1  [by t.de.dly.dly[9]._y:=0]
-	   1092922 t.de.dly.dly[9].___y : 0  [by t.de.dly.dly[9].__y:=1]
-	   1101233 t.de.dly.dly[9].y : 1  [by t.de.dly.dly[9].___y:=0]
-	   1102977 t.de.dly.dly[10]._y : 0  [by t.de.dly.dly[9].y:=1]
-	   1103590 t.de.dly.dly[10].__y : 1  [by t.de.dly.dly[10]._y:=0]
-	   1117612 t.de.dly.dly[10].___y : 0  [by t.de.dly.dly[10].__y:=1]
-	   1117657 t.de.dly.dly[10].y : 1  [by t.de.dly.dly[10].___y:=0]
-	   1118654 t.de.dly.dly[11]._y : 0  [by t.de.dly.dly[10].y:=1]
-	   1120303 t.de.dly.dly[11].__y : 1  [by t.de.dly.dly[11]._y:=0]
-	   1120828 t.de.dly.dly[11].___y : 0  [by t.de.dly.dly[11].__y:=1]
-	   1121728 t.de.dly.dly[11].y : 1  [by t.de.dly.dly[11].___y:=0]
-	   1121780 t.de.dly.dly[12]._y : 0  [by t.de.dly.dly[11].y:=1]
-	   1121787 t.de.dly.dly[12].__y : 1  [by t.de.dly.dly[12]._y:=0]
-	   1137399 t.de.dly.dly[12].___y : 0  [by t.de.dly.dly[12].__y:=1]
-	   1143866 t.de.dly.dly[12].y : 1  [by t.de.dly.dly[12].___y:=0]
-	   1143868 t.de.dly.dly[13]._y : 0  [by t.de.dly.dly[12].y:=1]
-	   1144222 t.de.dly.dly[13].__y : 1  [by t.de.dly.dly[13]._y:=0]
-	   1144355 t.de.dly.dly[13].___y : 0  [by t.de.dly.dly[13].__y:=1]
-	   1144356 t.de.dly.dly[13].y : 1  [by t.de.dly.dly[13].___y:=0]
-	   1144360 t.de.dly.dly[14]._y : 0  [by t.de.dly.dly[13].y:=1]
-	   1144906 t.de.dly.dly[14].__y : 1  [by t.de.dly.dly[14]._y:=0]
-	   1190469 t.de.dly.dly[14].___y : 0  [by t.de.dly.dly[14].__y:=1]
-	   1190470 t.de.dly.mu2[3].b : 1  [by t.de.dly.dly[14].___y:=0]
-	   1202848 t.de.dly.mu2[3]._y : 0  [by t.de.dly.mu2[3].b:=1]
-	   1202927 t.de.dly.out : 1  [by t.de.dly.mu2[3]._y:=0]
-	   1205360 t.de.addr_buf._out_a_B : 0  [by t.de.dly.out:=1]
-	   1205448 t.de.addr_buf.out_a_B_buf_t.buf1._y : 1  [by t.de.addr_buf._out_a_B:=0]
-	   1213142 t.de.addr_buf.out_a_B_buf_f.buf1._y : 1  [by t.de.addr_buf._out_a_B:=0]
-	   1213201 t.de.addr_buf._out_a_BX_t[0] : 0  [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=1]
-	   1213231 t.de.addr_buf.t_buf_func[0]._y : 1  [by t.de.addr_buf._out_a_BX_t[0]:=0]
-	   1214668 t.de.addr_buf.t_buf_func[1]._y : 1  [by t.de.addr_buf._out_a_BX_t[0]:=0]
-	   1215353 t.de.atree_y[1].in[0] : 0  [by t.de.addr_buf.t_buf_func[1]._y:=1]
-	   1215480 t.de.vtree_y.OR2_tf[0]._y : 1  [by t.de.atree_y[1].in[0]:=0]
-	   1215649 t.de.vtree_y.ct.in[0] : 0  [by t.de.vtree_y.OR2_tf[0]._y:=1]
-	   1232068 t.de.atree_y[3].and2s[0]._y : 1  [by t.de.atree_y[1].in[0]:=0]
-	   1232111 t.ag.iny[3] : 0  [by t.de.atree_y[3].and2s[0]._y:=1]
-	   1232123 t.ag.ands[7]._y : 1  [by t.ag.iny[3]:=0]
-	   1232615 t.de.atree_x[1].in[0] : 0  [by t.de.addr_buf.t_buf_func[0]._y:=1]
-	   1232618 t.de.vtree_x.OR2_tf[0]._y : 1  [by t.de.atree_x[1].in[0]:=0]
-	   1232656 t.de.vtree_x.ct.in[0] : 0  [by t.de.vtree_x.OR2_tf[0]._y:=1]
-	   1232657 t.de.vtree_x.ct.b._y : 1  [by t.de.vtree_x.ct.in[0]:=0]
-	   1232848 t.de.atree_x[1].b._y : 1  [by t.de.atree_x[1].in[0]:=0]
-	   1232940 t.ag.inx[1] : 0  [by t.de.atree_x[1].b._y:=1]
-	   1233402 t.out[7] : 0  [by t.ag.ands[7]._y:=1]
-	   1233775 t.de.addr_buf._out_a_BX_f[0] : 0  [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=1]
-	   1245409 t.de.C2el.c1 : 0  [by t.de.vtree_x.ct.b._y:=1]
-	   1272705 t.de.addr_buf.t_buf_func[2]._y : 1  [by t.de.addr_buf._out_a_BX_t[0]:=0]
-	   1275432 t.de.atree_y[2].in[1] : 0  [by t.de.addr_buf.t_buf_func[2]._y:=1]
-	   1275434 t.de.vtree_y.OR2_tf[1]._y : 1  [by t.de.atree_y[2].in[1]:=0]
-	   1275435 t.de.vtree_y.ct.in[1] : 0  [by t.de.vtree_y.OR2_tf[1]._y:=1]
-	   1276936 t.de.vtree_y.ct.C2Els[0]._y : 1  [by t.de.vtree_y.ct.in[1]:=0]
-	   1276938 t.de.C2el.c2 : 0  [by t.de.vtree_y.ct.C2Els[0]._y:=1]
-	   1276956 t.de.C2el._y : 1  [by t.de.C2el.c2:=0]
-	   1277075 t.de.C2el.y : 0  [by t.de.C2el._y:=1]
-	   1282795 t.de.dly.and2[0]._y : 1  [by t.de.C2el.y:=0]
-	   1282803 t.de.dly.dly[0].a : 0  [by t.de.dly.and2[0]._y:=1]
-	   1282857 t.de.dly.dly[0]._y : 1  [by t.de.dly.dly[0].a:=0]
-	   1333395 t.de.dly.dly[0].__y : 0  [by t.de.dly.dly[0]._y:=1]
-	   1333400 t.de.dly.dly[0].___y : 1  [by t.de.dly.dly[0].__y:=0]
-	   1334467 t.de.dly.dly[0].y : 0  [by t.de.dly.dly[0].___y:=1]
-	   1334468 t.de.dly.mu2[0]._y : 1  [by t.de.dly.dly[0].y:=0]
-	   1334606 t.de.dly._a[1] : 0  [by t.de.dly.mu2[0]._y:=1]
-	   1334607 t.de.dly.and2[1]._y : 1  [by t.de.dly._a[1]:=0]
-	   1334671 t.de.dly.dly[1].a : 0  [by t.de.dly.and2[1]._y:=1]
-	   1334794 t.de.dly.dly[1]._y : 1  [by t.de.dly.dly[1].a:=0]
-	   1334796 t.de.dly.dly[1].__y : 0  [by t.de.dly.dly[1]._y:=1]
-	   1334833 t.de.dly.dly[1].___y : 1  [by t.de.dly.dly[1].__y:=0]
-	   1334976 t.de.dly.dly[1].y : 0  [by t.de.dly.dly[1].___y:=1]
-	   1335027 t.de.dly.dly[2]._y : 1  [by t.de.dly.dly[1].y:=0]
-	   1335469 t.de.dly.dly[2].__y : 0  [by t.de.dly.dly[2]._y:=1]
-	   1335480 t.de.dly.dly[2].___y : 1  [by t.de.dly.dly[2].__y:=0]
-	   1335481 t.de.dly.dly[2].y : 0  [by t.de.dly.dly[2].___y:=1]
-	   1335490 t.de.dly.mu2[1]._y : 1  [by t.de.dly.dly[2].y:=0]
-	   1335515 t.de.dly._a[2] : 0  [by t.de.dly.mu2[1]._y:=1]
-	   1345768 t.de.dly.and2[2]._y : 1  [by t.de.dly._a[2]:=0]
-	   1349289 t.de.dly.dly[3].a : 0  [by t.de.dly.and2[2]._y:=1]
-	   1349434 t.de.dly.dly[3]._y : 1  [by t.de.dly.dly[3].a:=0]
-	   1365602 t.de.dly.dly[3].__y : 0  [by t.de.dly.dly[3]._y:=1]
-	   1365832 t.de.dly.dly[3].___y : 1  [by t.de.dly.dly[3].__y:=0]
-	   1366523 t.de.dly.dly[3].y : 0  [by t.de.dly.dly[3].___y:=1]
-	   1366537 t.de.dly.dly[4]._y : 1  [by t.de.dly.dly[3].y:=0]
-	   1368080 t.de.dly.dly[4].__y : 0  [by t.de.dly.dly[4]._y:=1]
-	   1369691 t.de.dly.dly[4].___y : 1  [by t.de.dly.dly[4].__y:=0]
-	   1387203 t.de.dly.dly[4].y : 0  [by t.de.dly.dly[4].___y:=1]
-	   1387214 t.de.dly.dly[5]._y : 1  [by t.de.dly.dly[4].y:=0]
-	   1387215 t.de.dly.dly[5].__y : 0  [by t.de.dly.dly[5]._y:=1]
-	   1387216 t.de.dly.dly[5].___y : 1  [by t.de.dly.dly[5].__y:=0]
-	   1393717 t.de.dly.dly[5].y : 0  [by t.de.dly.dly[5].___y:=1]
-	   1394356 t.de.dly.dly[6]._y : 1  [by t.de.dly.dly[5].y:=0]
-	   1396149 t.de.dly.dly[6].__y : 0  [by t.de.dly.dly[6]._y:=1]
-	   1396281 t.de.dly.dly[6].___y : 1  [by t.de.dly.dly[6].__y:=0]
-	   1396282 t.de.dly.dly[6].y : 0  [by t.de.dly.dly[6].___y:=1]
-	   1396299 t.de.dly.mu2[2]._y : 1  [by t.de.dly.dly[6].y:=0]
-	   1396451 t.de.dly._a[3] : 0  [by t.de.dly.mu2[2]._y:=1]
-	   1399434 t.de.dly.and2[3]._y : 1  [by t.de.dly._a[3]:=0]
-	   1399437 t.de.dly.dly[7].a : 0  [by t.de.dly.and2[3]._y:=1]
-	   1399861 t.de.dly.dly[7]._y : 1  [by t.de.dly.dly[7].a:=0]
-	   1399867 t.de.dly.dly[7].__y : 0  [by t.de.dly.dly[7]._y:=1]
-	   1402455 t.de.dly.dly[7].___y : 1  [by t.de.dly.dly[7].__y:=0]
-	   1404916 t.de.dly.dly[7].y : 0  [by t.de.dly.dly[7].___y:=1]
-	   1405746 t.de.dly.dly[8]._y : 1  [by t.de.dly.dly[7].y:=0]
-	   1428678 t.de.dly.dly[8].__y : 0  [by t.de.dly.dly[8]._y:=1]
-	   1428680 t.de.dly.dly[8].___y : 1  [by t.de.dly.dly[8].__y:=0]
-	   1428874 t.de.dly.dly[8].y : 0  [by t.de.dly.dly[8].___y:=1]
-	   1429477 t.de.dly.dly[9]._y : 1  [by t.de.dly.dly[8].y:=0]
-	   1429615 t.de.dly.dly[9].__y : 0  [by t.de.dly.dly[9]._y:=1]
-	   1429632 t.de.dly.dly[9].___y : 1  [by t.de.dly.dly[9].__y:=0]
-	   1429649 t.de.dly.dly[9].y : 0  [by t.de.dly.dly[9].___y:=1]
-	   1430075 t.de.dly.dly[10]._y : 1  [by t.de.dly.dly[9].y:=0]
-	   1430076 t.de.dly.dly[10].__y : 0  [by t.de.dly.dly[10]._y:=1]
-	   1430077 t.de.dly.dly[10].___y : 1  [by t.de.dly.dly[10].__y:=0]
-	   1431103 t.de.dly.dly[10].y : 0  [by t.de.dly.dly[10].___y:=1]
-	   1431104 t.de.dly.dly[11]._y : 1  [by t.de.dly.dly[10].y:=0]
-	   1431123 t.de.dly.dly[11].__y : 0  [by t.de.dly.dly[11]._y:=1]
-	   1431291 t.de.dly.dly[11].___y : 1  [by t.de.dly.dly[11].__y:=0]
-	   1431830 t.de.dly.dly[11].y : 0  [by t.de.dly.dly[11].___y:=1]
-	   1431991 t.de.dly.dly[12]._y : 1  [by t.de.dly.dly[11].y:=0]
-	   1432164 t.de.dly.dly[12].__y : 0  [by t.de.dly.dly[12]._y:=1]
-	   1434711 t.de.dly.dly[12].___y : 1  [by t.de.dly.dly[12].__y:=0]
-	   1449772 t.de.dly.dly[12].y : 0  [by t.de.dly.dly[12].___y:=1]
-	   1449773 t.de.dly.dly[13]._y : 1  [by t.de.dly.dly[12].y:=0]
-	   1449774 t.de.dly.dly[13].__y : 0  [by t.de.dly.dly[13]._y:=1]
-	   1450164 t.de.dly.dly[13].___y : 1  [by t.de.dly.dly[13].__y:=0]
-	   1450371 t.de.dly.dly[13].y : 0  [by t.de.dly.dly[13].___y:=1]
-	   1451204 t.de.dly.dly[14]._y : 1  [by t.de.dly.dly[13].y:=0]
-	   1451232 t.de.dly.dly[14].__y : 0  [by t.de.dly.dly[14]._y:=1]
-	   1451239 t.de.dly.dly[14].___y : 1  [by t.de.dly.dly[14].__y:=0]
-	   1451653 t.de.dly.mu2[3].b : 0  [by t.de.dly.dly[14].___y:=1]
-	   1451657 t.de.dly.mu2[3]._y : 1  [by t.de.dly.mu2[3].b:=0]
-	   1453436 t.de.dly.out : 0  [by t.de.dly.mu2[3]._y:=1]
-	   1476310 t.de.addr_buf._out_a_B : 1  [by t.de.dly.out:=0]
-	   1476476 t.de.addr_buf.out_a_B_buf_t.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	   1485121 t.de.addr_buf._out_a_BX_f[0] : 1  [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=0]
-	   1516180 t.de.addr_buf.out_a_B_buf_f.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	   1517113 t.de.addr_buf._out_a_BX_t[0] : 1  [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=0]

test/unit_tests/decoder_2d_dly_and_2_4/run/test.prs

@@ -1,948 +1,3 @@
 = "GND" "GND"
 = "Vdd" "Vdd"
 = "Reset" "Reset"
-"Reset"->"t._reset_B"-
-~("Reset")->"t._reset_B"+
-= "t._reset_B" "t.de.reset_B"
-= "t.ag.iny[0]" "t.ag.ands[1].b"
-= "t.ag.iny[0]" "t.ag.ands[0].b"
-= "t.ag.iny[1]" "t.ag.ands[3].b"
-= "t.ag.iny[1]" "t.ag.ands[2].b"
-= "t.ag.iny[2]" "t.ag.ands[5].b"
-= "t.ag.iny[2]" "t.ag.ands[4].b"
-= "t.ag.iny[3]" "t.ag.ands[7].b"
-= "t.ag.iny[3]" "t.ag.ands[6].b"
-= "t.ag.inx[0]" "t.ag.ands[6].a"
-= "t.ag.inx[0]" "t.ag.ands[4].a"
-= "t.ag.inx[0]" "t.ag.ands[2].a"
-= "t.ag.inx[0]" "t.ag.ands[0].a"
-= "t.ag.inx[1]" "t.ag.ands[7].a"
-= "t.ag.inx[1]" "t.ag.ands[5].a"
-= "t.ag.inx[1]" "t.ag.ands[3].a"
-= "t.ag.inx[1]" "t.ag.ands[1].a"
-"t.ag.ands[0].a"&"t.ag.ands[0].b"->"t.ag.ands[0]._y"-
-~("t.ag.ands[0].a"&"t.ag.ands[0].b")->"t.ag.ands[0]._y"+
-"t.ag.ands[0]._y"->"t.ag.ands[0].y"-
-~("t.ag.ands[0]._y")->"t.ag.ands[0].y"+
-"t.ag.ands[1].a"&"t.ag.ands[1].b"->"t.ag.ands[1]._y"-
-~("t.ag.ands[1].a"&"t.ag.ands[1].b")->"t.ag.ands[1]._y"+
-"t.ag.ands[1]._y"->"t.ag.ands[1].y"-
-~("t.ag.ands[1]._y")->"t.ag.ands[1].y"+
-"t.ag.ands[2].a"&"t.ag.ands[2].b"->"t.ag.ands[2]._y"-
-~("t.ag.ands[2].a"&"t.ag.ands[2].b")->"t.ag.ands[2]._y"+
-"t.ag.ands[2]._y"->"t.ag.ands[2].y"-
-~("t.ag.ands[2]._y")->"t.ag.ands[2].y"+
-"t.ag.ands[3].a"&"t.ag.ands[3].b"->"t.ag.ands[3]._y"-
-~("t.ag.ands[3].a"&"t.ag.ands[3].b")->"t.ag.ands[3]._y"+
-"t.ag.ands[3]._y"->"t.ag.ands[3].y"-
-~("t.ag.ands[3]._y")->"t.ag.ands[3].y"+
-"t.ag.ands[4].a"&"t.ag.ands[4].b"->"t.ag.ands[4]._y"-
-~("t.ag.ands[4].a"&"t.ag.ands[4].b")->"t.ag.ands[4]._y"+
-"t.ag.ands[4]._y"->"t.ag.ands[4].y"-
-~("t.ag.ands[4]._y")->"t.ag.ands[4].y"+
-"t.ag.ands[5].a"&"t.ag.ands[5].b"->"t.ag.ands[5]._y"-
-~("t.ag.ands[5].a"&"t.ag.ands[5].b")->"t.ag.ands[5]._y"+
-"t.ag.ands[5]._y"->"t.ag.ands[5].y"-
-~("t.ag.ands[5]._y")->"t.ag.ands[5].y"+
-"t.ag.ands[6].a"&"t.ag.ands[6].b"->"t.ag.ands[6]._y"-
-~("t.ag.ands[6].a"&"t.ag.ands[6].b")->"t.ag.ands[6]._y"+
-"t.ag.ands[6]._y"->"t.ag.ands[6].y"-
-~("t.ag.ands[6]._y")->"t.ag.ands[6].y"+
-"t.ag.ands[7].a"&"t.ag.ands[7].b"->"t.ag.ands[7]._y"-
-~("t.ag.ands[7].a"&"t.ag.ands[7].b")->"t.ag.ands[7]._y"+
-"t.ag.ands[7]._y"->"t.ag.ands[7].y"-
-~("t.ag.ands[7]._y")->"t.ag.ands[7].y"+
-= "t.ag.supply.vdd" "t.ag.ands[7].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[6].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[5].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[4].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[3].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[2].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[1].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[0].vdd"
-= "t.ag.supply.vss" "t.ag.ands[7].vss"
-= "t.ag.supply.vss" "t.ag.ands[6].vss"
-= "t.ag.supply.vss" "t.ag.ands[5].vss"
-= "t.ag.supply.vss" "t.ag.ands[4].vss"
-= "t.ag.supply.vss" "t.ag.ands[3].vss"
-= "t.ag.supply.vss" "t.ag.ands[2].vss"
-= "t.ag.supply.vss" "t.ag.ands[1].vss"
-= "t.ag.supply.vss" "t.ag.ands[0].vss"
-= "t.ag.out[0]" "t.ag.ands[0].y"
-= "t.ag.out[1]" "t.ag.ands[1].y"
-= "t.ag.out[2]" "t.ag.ands[2].y"
-= "t.ag.out[3]" "t.ag.ands[3].y"
-= "t.ag.out[4]" "t.ag.ands[4].y"
-= "t.ag.out[5]" "t.ag.ands[5].y"
-= "t.ag.out[6]" "t.ag.ands[6].y"
-= "t.ag.out[7]" "t.ag.ands[7].y"
-= "t.ag.inx[0]" "t.de.outx[0]"
-= "t.ag.inx[1]" "t.de.outx[1]"
-= "t.ag.iny[0]" "t.de.outy[0]"
-= "t.ag.iny[1]" "t.de.outy[1]"
-= "t.ag.iny[2]" "t.de.outy[2]"
-= "t.ag.iny[3]" "t.de.outy[3]"
-= "Vdd" "t.ag.supply.vdd"
-= "GND" "t.ag.supply.vss"
-"t.de.atree_x[0].b.a"->"t.de.atree_x[0].b._y"-
-~("t.de.atree_x[0].b.a")->"t.de.atree_x[0].b._y"+
-"t.de.atree_x[0].b._y"->"t.de.atree_x[0].b.y"-
-~("t.de.atree_x[0].b._y")->"t.de.atree_x[0].b.y"+
-= "t.de.atree_x[0].supply.vdd" "t.de.atree_x[0].b.vdd"
-= "t.de.atree_x[0].supply.vss" "t.de.atree_x[0].b.vss"
-= "t.de.atree_x[0].out" "t.de.atree_x[0].b.y"
-= "t.de.atree_x[0].in[0]" "t.de.atree_x[0].b.a"
-"t.de.atree_x[1].b.a"->"t.de.atree_x[1].b._y"-
-~("t.de.atree_x[1].b.a")->"t.de.atree_x[1].b._y"+
-"t.de.atree_x[1].b._y"->"t.de.atree_x[1].b.y"-
-~("t.de.atree_x[1].b._y")->"t.de.atree_x[1].b.y"+
-= "t.de.atree_x[1].supply.vdd" "t.de.atree_x[1].b.vdd"
-= "t.de.atree_x[1].supply.vss" "t.de.atree_x[1].b.vss"
-= "t.de.atree_x[1].out" "t.de.atree_x[1].b.y"
-= "t.de.atree_x[1].in[0]" "t.de.atree_x[1].b.a"
-= "t.de.atree_x[1].in[0]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.atree_x[1].in[0]" "t.de.addr_buf.out.d.d[0].d[1]"
-= "t.de.atree_x[1].in[0]" "t.de.vtree_x.in.d[0].t"
-= "t.de.atree_x[1].in[0]" "t.de.vtree_x.in.d[0].d[1]"
-= "t.de.atree_x[0].in[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.atree_x[0].in[0]" "t.de.addr_buf.out.d.d[0].d[0]"
-= "t.de.atree_x[0].in[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.atree_x[0].in[0]" "t.de.vtree_x.in.d[0].d[0]"
-= "t.de.dly_cfg[0]" "t.de.dly.s[0]"
-= "t.de.dly_cfg[1]" "t.de.dly.s[1]"
-= "t.de.dly_cfg[2]" "t.de.dly.s[2]"
-= "t.de.dly_cfg[3]" "t.de.dly.s[3]"
-= "t.de.supply.vss" "t.de.atree_y[3].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[3].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_y[2].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[2].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_y[1].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[1].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_y[0].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[0].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_x[1].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_x[1].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_x[0].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_x[0].supply.vdd"
-= "t.de.supply.vss" "t.de.dly.supply.vss"
-= "t.de.supply.vdd" "t.de.dly.supply.vdd"
-= "t.de.supply.vss" "t.de.vtree_y.supply.vss"
-= "t.de.supply.vdd" "t.de.vtree_y.supply.vdd"
-= "t.de.supply.vss" "t.de.vtree_x.supply.vss"
-= "t.de.supply.vdd" "t.de.vtree_x.supply.vdd"
-= "t.de.supply.vss" "t.de.addr_buf.supply.vss"
-= "t.de.supply.vdd" "t.de.addr_buf.supply.vdd"
-= "t.de.supply.vdd" "t.de.C2el.vdd"
-= "t.de.supply.vss" "t.de.C2el.vss"
-~"t.de.C2el.c1"&~"t.de.C2el.c2"->"t.de.C2el._y"+
-"t.de.C2el.c1"&"t.de.C2el.c2"->"t.de.C2el._y"-
-"t.de.C2el._y"->"t.de.C2el.y"-
-~("t.de.C2el._y")->"t.de.C2el.y"+
-= "t.de.C2el.c1" "t.de.vtree_x.out"
-= "t.de.C2el.c2" "t.de.vtree_y.out"
-"t.de.dly.and2[0].a"&"t.de.dly.and2[0].b"->"t.de.dly.and2[0]._y"-
-~("t.de.dly.and2[0].a"&"t.de.dly.and2[0].b")->"t.de.dly.and2[0]._y"+
-"t.de.dly.and2[0]._y"->"t.de.dly.and2[0].y"-
-~("t.de.dly.and2[0]._y")->"t.de.dly.and2[0].y"+
-"t.de.dly.and2[1].a"&"t.de.dly.and2[1].b"->"t.de.dly.and2[1]._y"-
-~("t.de.dly.and2[1].a"&"t.de.dly.and2[1].b")->"t.de.dly.and2[1]._y"+
-"t.de.dly.and2[1]._y"->"t.de.dly.and2[1].y"-
-~("t.de.dly.and2[1]._y")->"t.de.dly.and2[1].y"+
-"t.de.dly.and2[2].a"&"t.de.dly.and2[2].b"->"t.de.dly.and2[2]._y"-
-~("t.de.dly.and2[2].a"&"t.de.dly.and2[2].b")->"t.de.dly.and2[2]._y"+
-"t.de.dly.and2[2]._y"->"t.de.dly.and2[2].y"-
-~("t.de.dly.and2[2]._y")->"t.de.dly.and2[2].y"+
-"t.de.dly.and2[3].a"&"t.de.dly.and2[3].b"->"t.de.dly.and2[3]._y"-
-~("t.de.dly.and2[3].a"&"t.de.dly.and2[3].b")->"t.de.dly.and2[3]._y"+
-"t.de.dly.and2[3]._y"->"t.de.dly.and2[3].y"-
-~("t.de.dly.and2[3]._y")->"t.de.dly.and2[3].y"+
-= "t.de.dly.s[0]" "t.de.dly.mu2[0].s"
-= "t.de.dly.s[0]" "t.de.dly.and2[0].b"
-= "t.de.dly.s[1]" "t.de.dly.mu2[1].s"
-= "t.de.dly.s[1]" "t.de.dly.and2[1].b"
-= "t.de.dly.s[2]" "t.de.dly.mu2[2].s"
-= "t.de.dly.s[2]" "t.de.dly.and2[2].b"
-= "t.de.dly.s[3]" "t.de.dly.mu2[3].s"
-= "t.de.dly.s[3]" "t.de.dly.and2[3].b"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[14].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[13].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[12].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[11].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[10].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[9].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[8].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[7].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[6].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[5].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[4].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[3].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[2].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[1].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[0].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[3].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[2].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[1].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[0].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[3].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[2].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[1].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[0].vdd"
-= "t.de.dly.supply.vss" "t.de.dly.dly[14].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[13].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[12].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[11].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[10].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[9].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[8].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[7].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[6].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[5].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[4].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[3].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[2].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[1].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[0].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[3].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[2].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[1].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[0].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[3].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[2].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[1].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[0].vss"
-"t.de.dly.mu2[0].s"->"t.de.dly.mu2[0]._s"-
-~("t.de.dly.mu2[0].s")->"t.de.dly.mu2[0]._s"+
-~"t.de.dly.mu2[0].a"&~"t.de.dly.mu2[0].s"|~"t.de.dly.mu2[0].b"&~"t.de.dly.mu2[0]._s"->"t.de.dly.mu2[0]._y"+
-"t.de.dly.mu2[0].a"&"t.de.dly.mu2[0]._s"|"t.de.dly.mu2[0].b"&"t.de.dly.mu2[0].s"->"t.de.dly.mu2[0]._y"-
-"t.de.dly.mu2[0]._y"->"t.de.dly.mu2[0].y"-
-~("t.de.dly.mu2[0]._y")->"t.de.dly.mu2[0].y"+
-"t.de.dly.mu2[1].s"->"t.de.dly.mu2[1]._s"-
-~("t.de.dly.mu2[1].s")->"t.de.dly.mu2[1]._s"+
-~"t.de.dly.mu2[1].a"&~"t.de.dly.mu2[1].s"|~"t.de.dly.mu2[1].b"&~"t.de.dly.mu2[1]._s"->"t.de.dly.mu2[1]._y"+
-"t.de.dly.mu2[1].a"&"t.de.dly.mu2[1]._s"|"t.de.dly.mu2[1].b"&"t.de.dly.mu2[1].s"->"t.de.dly.mu2[1]._y"-
-"t.de.dly.mu2[1]._y"->"t.de.dly.mu2[1].y"-
-~("t.de.dly.mu2[1]._y")->"t.de.dly.mu2[1].y"+
-"t.de.dly.mu2[2].s"->"t.de.dly.mu2[2]._s"-
-~("t.de.dly.mu2[2].s")->"t.de.dly.mu2[2]._s"+
-~"t.de.dly.mu2[2].a"&~"t.de.dly.mu2[2].s"|~"t.de.dly.mu2[2].b"&~"t.de.dly.mu2[2]._s"->"t.de.dly.mu2[2]._y"+
-"t.de.dly.mu2[2].a"&"t.de.dly.mu2[2]._s"|"t.de.dly.mu2[2].b"&"t.de.dly.mu2[2].s"->"t.de.dly.mu2[2]._y"-
-"t.de.dly.mu2[2]._y"->"t.de.dly.mu2[2].y"-
-~("t.de.dly.mu2[2]._y")->"t.de.dly.mu2[2].y"+
-"t.de.dly.mu2[3].s"->"t.de.dly.mu2[3]._s"-
-~("t.de.dly.mu2[3].s")->"t.de.dly.mu2[3]._s"+
-~"t.de.dly.mu2[3].a"&~"t.de.dly.mu2[3].s"|~"t.de.dly.mu2[3].b"&~"t.de.dly.mu2[3]._s"->"t.de.dly.mu2[3]._y"+
-"t.de.dly.mu2[3].a"&"t.de.dly.mu2[3]._s"|"t.de.dly.mu2[3].b"&"t.de.dly.mu2[3].s"->"t.de.dly.mu2[3]._y"-
-"t.de.dly.mu2[3]._y"->"t.de.dly.mu2[3].y"-
-~("t.de.dly.mu2[3]._y")->"t.de.dly.mu2[3].y"+
-"t.de.dly.dly[0].a"->"t.de.dly.dly[0]._y"-
-~("t.de.dly.dly[0].a")->"t.de.dly.dly[0]._y"+
-"t.de.dly.dly[0]._y"->"t.de.dly.dly[0].__y"-
-~("t.de.dly.dly[0]._y")->"t.de.dly.dly[0].__y"+
-"t.de.dly.dly[0].__y"->"t.de.dly.dly[0].___y"-
-~("t.de.dly.dly[0].__y")->"t.de.dly.dly[0].___y"+
-"t.de.dly.dly[0].___y"->"t.de.dly.dly[0].y"-
-~("t.de.dly.dly[0].___y")->"t.de.dly.dly[0].y"+
-"t.de.dly.dly[1].a"->"t.de.dly.dly[1]._y"-
-~("t.de.dly.dly[1].a")->"t.de.dly.dly[1]._y"+
-"t.de.dly.dly[1]._y"->"t.de.dly.dly[1].__y"-
-~("t.de.dly.dly[1]._y")->"t.de.dly.dly[1].__y"+
-"t.de.dly.dly[1].__y"->"t.de.dly.dly[1].___y"-
-~("t.de.dly.dly[1].__y")->"t.de.dly.dly[1].___y"+
-"t.de.dly.dly[1].___y"->"t.de.dly.dly[1].y"-
-~("t.de.dly.dly[1].___y")->"t.de.dly.dly[1].y"+
-"t.de.dly.dly[2].a"->"t.de.dly.dly[2]._y"-
-~("t.de.dly.dly[2].a")->"t.de.dly.dly[2]._y"+
-"t.de.dly.dly[2]._y"->"t.de.dly.dly[2].__y"-
-~("t.de.dly.dly[2]._y")->"t.de.dly.dly[2].__y"+
-"t.de.dly.dly[2].__y"->"t.de.dly.dly[2].___y"-
-~("t.de.dly.dly[2].__y")->"t.de.dly.dly[2].___y"+
-"t.de.dly.dly[2].___y"->"t.de.dly.dly[2].y"-
-~("t.de.dly.dly[2].___y")->"t.de.dly.dly[2].y"+
-"t.de.dly.dly[3].a"->"t.de.dly.dly[3]._y"-
-~("t.de.dly.dly[3].a")->"t.de.dly.dly[3]._y"+
-"t.de.dly.dly[3]._y"->"t.de.dly.dly[3].__y"-
-~("t.de.dly.dly[3]._y")->"t.de.dly.dly[3].__y"+
-"t.de.dly.dly[3].__y"->"t.de.dly.dly[3].___y"-
-~("t.de.dly.dly[3].__y")->"t.de.dly.dly[3].___y"+
-"t.de.dly.dly[3].___y"->"t.de.dly.dly[3].y"-
-~("t.de.dly.dly[3].___y")->"t.de.dly.dly[3].y"+
-"t.de.dly.dly[4].a"->"t.de.dly.dly[4]._y"-
-~("t.de.dly.dly[4].a")->"t.de.dly.dly[4]._y"+
-"t.de.dly.dly[4]._y"->"t.de.dly.dly[4].__y"-
-~("t.de.dly.dly[4]._y")->"t.de.dly.dly[4].__y"+
-"t.de.dly.dly[4].__y"->"t.de.dly.dly[4].___y"-
-~("t.de.dly.dly[4].__y")->"t.de.dly.dly[4].___y"+
-"t.de.dly.dly[4].___y"->"t.de.dly.dly[4].y"-
-~("t.de.dly.dly[4].___y")->"t.de.dly.dly[4].y"+
-"t.de.dly.dly[5].a"->"t.de.dly.dly[5]._y"-
-~("t.de.dly.dly[5].a")->"t.de.dly.dly[5]._y"+
-"t.de.dly.dly[5]._y"->"t.de.dly.dly[5].__y"-
-~("t.de.dly.dly[5]._y")->"t.de.dly.dly[5].__y"+
-"t.de.dly.dly[5].__y"->"t.de.dly.dly[5].___y"-
-~("t.de.dly.dly[5].__y")->"t.de.dly.dly[5].___y"+
-"t.de.dly.dly[5].___y"->"t.de.dly.dly[5].y"-
-~("t.de.dly.dly[5].___y")->"t.de.dly.dly[5].y"+
-"t.de.dly.dly[6].a"->"t.de.dly.dly[6]._y"-
-~("t.de.dly.dly[6].a")->"t.de.dly.dly[6]._y"+
-"t.de.dly.dly[6]._y"->"t.de.dly.dly[6].__y"-
-~("t.de.dly.dly[6]._y")->"t.de.dly.dly[6].__y"+
-"t.de.dly.dly[6].__y"->"t.de.dly.dly[6].___y"-
-~("t.de.dly.dly[6].__y")->"t.de.dly.dly[6].___y"+
-"t.de.dly.dly[6].___y"->"t.de.dly.dly[6].y"-
-~("t.de.dly.dly[6].___y")->"t.de.dly.dly[6].y"+
-"t.de.dly.dly[7].a"->"t.de.dly.dly[7]._y"-
-~("t.de.dly.dly[7].a")->"t.de.dly.dly[7]._y"+
-"t.de.dly.dly[7]._y"->"t.de.dly.dly[7].__y"-
-~("t.de.dly.dly[7]._y")->"t.de.dly.dly[7].__y"+
-"t.de.dly.dly[7].__y"->"t.de.dly.dly[7].___y"-
-~("t.de.dly.dly[7].__y")->"t.de.dly.dly[7].___y"+
-"t.de.dly.dly[7].___y"->"t.de.dly.dly[7].y"-
-~("t.de.dly.dly[7].___y")->"t.de.dly.dly[7].y"+
-"t.de.dly.dly[8].a"->"t.de.dly.dly[8]._y"-
-~("t.de.dly.dly[8].a")->"t.de.dly.dly[8]._y"+
-"t.de.dly.dly[8]._y"->"t.de.dly.dly[8].__y"-
-~("t.de.dly.dly[8]._y")->"t.de.dly.dly[8].__y"+
-"t.de.dly.dly[8].__y"->"t.de.dly.dly[8].___y"-
-~("t.de.dly.dly[8].__y")->"t.de.dly.dly[8].___y"+
-"t.de.dly.dly[8].___y"->"t.de.dly.dly[8].y"-
-~("t.de.dly.dly[8].___y")->"t.de.dly.dly[8].y"+
-"t.de.dly.dly[9].a"->"t.de.dly.dly[9]._y"-
-~("t.de.dly.dly[9].a")->"t.de.dly.dly[9]._y"+
-"t.de.dly.dly[9]._y"->"t.de.dly.dly[9].__y"-
-~("t.de.dly.dly[9]._y")->"t.de.dly.dly[9].__y"+
-"t.de.dly.dly[9].__y"->"t.de.dly.dly[9].___y"-
-~("t.de.dly.dly[9].__y")->"t.de.dly.dly[9].___y"+
-"t.de.dly.dly[9].___y"->"t.de.dly.dly[9].y"-
-~("t.de.dly.dly[9].___y")->"t.de.dly.dly[9].y"+
-"t.de.dly.dly[10].a"->"t.de.dly.dly[10]._y"-
-~("t.de.dly.dly[10].a")->"t.de.dly.dly[10]._y"+
-"t.de.dly.dly[10]._y"->"t.de.dly.dly[10].__y"-
-~("t.de.dly.dly[10]._y")->"t.de.dly.dly[10].__y"+
-"t.de.dly.dly[10].__y"->"t.de.dly.dly[10].___y"-
-~("t.de.dly.dly[10].__y")->"t.de.dly.dly[10].___y"+
-"t.de.dly.dly[10].___y"->"t.de.dly.dly[10].y"-
-~("t.de.dly.dly[10].___y")->"t.de.dly.dly[10].y"+
-"t.de.dly.dly[11].a"->"t.de.dly.dly[11]._y"-
-~("t.de.dly.dly[11].a")->"t.de.dly.dly[11]._y"+
-"t.de.dly.dly[11]._y"->"t.de.dly.dly[11].__y"-
-~("t.de.dly.dly[11]._y")->"t.de.dly.dly[11].__y"+
-"t.de.dly.dly[11].__y"->"t.de.dly.dly[11].___y"-
-~("t.de.dly.dly[11].__y")->"t.de.dly.dly[11].___y"+
-"t.de.dly.dly[11].___y"->"t.de.dly.dly[11].y"-
-~("t.de.dly.dly[11].___y")->"t.de.dly.dly[11].y"+
-"t.de.dly.dly[12].a"->"t.de.dly.dly[12]._y"-
-~("t.de.dly.dly[12].a")->"t.de.dly.dly[12]._y"+
-"t.de.dly.dly[12]._y"->"t.de.dly.dly[12].__y"-
-~("t.de.dly.dly[12]._y")->"t.de.dly.dly[12].__y"+
-"t.de.dly.dly[12].__y"->"t.de.dly.dly[12].___y"-
-~("t.de.dly.dly[12].__y")->"t.de.dly.dly[12].___y"+
-"t.de.dly.dly[12].___y"->"t.de.dly.dly[12].y"-
-~("t.de.dly.dly[12].___y")->"t.de.dly.dly[12].y"+
-"t.de.dly.dly[13].a"->"t.de.dly.dly[13]._y"-
-~("t.de.dly.dly[13].a")->"t.de.dly.dly[13]._y"+
-"t.de.dly.dly[13]._y"->"t.de.dly.dly[13].__y"-
-~("t.de.dly.dly[13]._y")->"t.de.dly.dly[13].__y"+
-"t.de.dly.dly[13].__y"->"t.de.dly.dly[13].___y"-
-~("t.de.dly.dly[13].__y")->"t.de.dly.dly[13].___y"+
-"t.de.dly.dly[13].___y"->"t.de.dly.dly[13].y"-
-~("t.de.dly.dly[13].___y")->"t.de.dly.dly[13].y"+
-"t.de.dly.dly[14].a"->"t.de.dly.dly[14]._y"-
-~("t.de.dly.dly[14].a")->"t.de.dly.dly[14]._y"+
-"t.de.dly.dly[14]._y"->"t.de.dly.dly[14].__y"-
-~("t.de.dly.dly[14]._y")->"t.de.dly.dly[14].__y"+
-"t.de.dly.dly[14].__y"->"t.de.dly.dly[14].___y"-
-~("t.de.dly.dly[14].__y")->"t.de.dly.dly[14].___y"+
-"t.de.dly.dly[14].___y"->"t.de.dly.dly[14].y"-
-~("t.de.dly.dly[14].___y")->"t.de.dly.dly[14].y"+
-= "t.de.dly.dly[14].y" "t.de.dly.mu2[3].b"
-= "t.de.dly.dly[14].a" "t.de.dly.dly[13].y"
-= "t.de.dly.dly[13].a" "t.de.dly.dly[12].y"
-= "t.de.dly.dly[12].a" "t.de.dly.dly[11].y"
-= "t.de.dly.dly[11].a" "t.de.dly.dly[10].y"
-= "t.de.dly.dly[10].a" "t.de.dly.dly[9].y"
-= "t.de.dly.dly[9].a" "t.de.dly.dly[8].y"
-= "t.de.dly.dly[8].a" "t.de.dly.dly[7].y"
-= "t.de.dly.dly[7].a" "t.de.dly.and2[3].y"
-= "t.de.dly.dly[6].y" "t.de.dly.mu2[2].b"
-= "t.de.dly.dly[6].a" "t.de.dly.dly[5].y"
-= "t.de.dly.dly[5].a" "t.de.dly.dly[4].y"
-= "t.de.dly.dly[4].a" "t.de.dly.dly[3].y"
-= "t.de.dly.dly[3].a" "t.de.dly.and2[2].y"
-= "t.de.dly.dly[2].y" "t.de.dly.mu2[1].b"
-= "t.de.dly.dly[2].a" "t.de.dly.dly[1].y"
-= "t.de.dly.dly[1].a" "t.de.dly.and2[1].y"
-= "t.de.dly.dly[0].y" "t.de.dly.mu2[0].b"
-= "t.de.dly.dly[0].a" "t.de.dly.and2[0].y"
-= "t.de.dly._a[1]" "t.de.dly.mu2[1].a"
-= "t.de.dly._a[1]" "t.de.dly.and2[1].a"
-= "t.de.dly._a[1]" "t.de.dly.mu2[0].y"
-= "t.de.dly._a[2]" "t.de.dly.mu2[2].a"
-= "t.de.dly._a[2]" "t.de.dly.and2[2].a"
-= "t.de.dly._a[2]" "t.de.dly.mu2[1].y"
-= "t.de.dly._a[3]" "t.de.dly.mu2[3].a"
-= "t.de.dly._a[3]" "t.de.dly.and2[3].a"
-= "t.de.dly._a[3]" "t.de.dly.mu2[2].y"
-= "t.de.dly.out" "t.de.dly.mu2[3].y"
-= "t.de.dly.out" "t.de.dly._a[4]"
-= "t.de.dly.in" "t.de.dly.mu2[0].a"
-= "t.de.dly.in" "t.de.dly.and2[0].a"
-= "t.de.dly.in" "t.de.dly._a[0]"
-= "t.de.dly.out" "t.de.addr_buf.out.a"
-= "t.de.dly.in" "t.de.addr_buf.out.v"
-= "t.de.dly.in" "t.de.C2el.y"
-= "t.de.atree_y[0].supply.vdd" "t.de.atree_y[0].and2s[0].vdd"
-= "t.de.atree_y[0].supply.vss" "t.de.atree_y[0].and2s[0].vss"
-"t.de.atree_y[0].and2s[0].a"&"t.de.atree_y[0].and2s[0].b"->"t.de.atree_y[0].and2s[0]._y"-
-~("t.de.atree_y[0].and2s[0].a"&"t.de.atree_y[0].and2s[0].b")->"t.de.atree_y[0].and2s[0]._y"+
-"t.de.atree_y[0].and2s[0]._y"->"t.de.atree_y[0].and2s[0].y"-
-~("t.de.atree_y[0].and2s[0]._y")->"t.de.atree_y[0].and2s[0].y"+
-= "t.de.atree_y[0].in[0]" "t.de.atree_y[0].and2s[0].a"
-= "t.de.atree_y[0].in[0]" "t.de.atree_y[0].tmp[0]"
-= "t.de.atree_y[0].in[1]" "t.de.atree_y[0].and2s[0].b"
-= "t.de.atree_y[0].in[1]" "t.de.atree_y[0].tmp[1]"
-= "t.de.atree_y[0].out" "t.de.atree_y[0].and2s[0].y"
-= "t.de.atree_y[0].out" "t.de.atree_y[0].tmp[2]"
-= "t.de.atree_y[1].supply.vdd" "t.de.atree_y[1].and2s[0].vdd"
-= "t.de.atree_y[1].supply.vss" "t.de.atree_y[1].and2s[0].vss"
-"t.de.atree_y[1].and2s[0].a"&"t.de.atree_y[1].and2s[0].b"->"t.de.atree_y[1].and2s[0]._y"-
-~("t.de.atree_y[1].and2s[0].a"&"t.de.atree_y[1].and2s[0].b")->"t.de.atree_y[1].and2s[0]._y"+
-"t.de.atree_y[1].and2s[0]._y"->"t.de.atree_y[1].and2s[0].y"-
-~("t.de.atree_y[1].and2s[0]._y")->"t.de.atree_y[1].and2s[0].y"+
-= "t.de.atree_y[1].in[0]" "t.de.atree_y[1].and2s[0].a"
-= "t.de.atree_y[1].in[0]" "t.de.atree_y[1].tmp[0]"
-= "t.de.atree_y[1].in[1]" "t.de.atree_y[1].and2s[0].b"
-= "t.de.atree_y[1].in[1]" "t.de.atree_y[1].tmp[1]"
-= "t.de.atree_y[1].out" "t.de.atree_y[1].and2s[0].y"
-= "t.de.atree_y[1].out" "t.de.atree_y[1].tmp[2]"
-= "t.de.atree_y[2].supply.vdd" "t.de.atree_y[2].and2s[0].vdd"
-= "t.de.atree_y[2].supply.vss" "t.de.atree_y[2].and2s[0].vss"
-"t.de.atree_y[2].and2s[0].a"&"t.de.atree_y[2].and2s[0].b"->"t.de.atree_y[2].and2s[0]._y"-
-~("t.de.atree_y[2].and2s[0].a"&"t.de.atree_y[2].and2s[0].b")->"t.de.atree_y[2].and2s[0]._y"+
-"t.de.atree_y[2].and2s[0]._y"->"t.de.atree_y[2].and2s[0].y"-
-~("t.de.atree_y[2].and2s[0]._y")->"t.de.atree_y[2].and2s[0].y"+
-= "t.de.atree_y[2].in[0]" "t.de.atree_y[2].and2s[0].a"
-= "t.de.atree_y[2].in[0]" "t.de.atree_y[2].tmp[0]"
-= "t.de.atree_y[2].in[1]" "t.de.atree_y[2].and2s[0].b"
-= "t.de.atree_y[2].in[1]" "t.de.atree_y[2].tmp[1]"
-= "t.de.atree_y[2].out" "t.de.atree_y[2].and2s[0].y"
-= "t.de.atree_y[2].out" "t.de.atree_y[2].tmp[2]"
-= "t.de.atree_y[3].supply.vdd" "t.de.atree_y[3].and2s[0].vdd"
-= "t.de.atree_y[3].supply.vss" "t.de.atree_y[3].and2s[0].vss"
-"t.de.atree_y[3].and2s[0].a"&"t.de.atree_y[3].and2s[0].b"->"t.de.atree_y[3].and2s[0]._y"-
-~("t.de.atree_y[3].and2s[0].a"&"t.de.atree_y[3].and2s[0].b")->"t.de.atree_y[3].and2s[0]._y"+
-"t.de.atree_y[3].and2s[0]._y"->"t.de.atree_y[3].and2s[0].y"-
-~("t.de.atree_y[3].and2s[0]._y")->"t.de.atree_y[3].and2s[0].y"+
-= "t.de.atree_y[3].in[0]" "t.de.atree_y[3].and2s[0].a"
-= "t.de.atree_y[3].in[0]" "t.de.atree_y[3].tmp[0]"
-= "t.de.atree_y[3].in[1]" "t.de.atree_y[3].and2s[0].b"
-= "t.de.atree_y[3].in[1]" "t.de.atree_y[3].tmp[1]"
-= "t.de.atree_y[3].out" "t.de.atree_y[3].and2s[0].y"
-= "t.de.atree_y[3].out" "t.de.atree_y[3].tmp[2]"
-= "t.de.atree_y[3].in[0]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.atree_y[3].in[0]" "t.de.addr_buf.out.d.d[1].d[1]"
-= "t.de.atree_y[3].in[0]" "t.de.vtree_y.in.d[0].t"
-= "t.de.atree_y[3].in[0]" "t.de.vtree_y.in.d[0].d[1]"
-= "t.de.atree_y[3].in[0]" "t.de.atree_y[1].in[0]"
-= "t.de.atree_y[3].in[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.atree_y[3].in[1]" "t.de.addr_buf.out.d.d[2].d[1]"
-= "t.de.atree_y[3].in[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.atree_y[3].in[1]" "t.de.vtree_y.in.d[1].d[1]"
-= "t.de.atree_y[3].in[1]" "t.de.atree_y[2].in[1]"
-= "t.de.atree_y[2].in[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.atree_y[2].in[0]" "t.de.addr_buf.out.d.d[1].d[0]"
-= "t.de.atree_y[2].in[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.atree_y[2].in[0]" "t.de.vtree_y.in.d[0].d[0]"
-= "t.de.atree_y[2].in[0]" "t.de.atree_y[0].in[0]"
-= "t.de.atree_y[1].in[1]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.atree_y[1].in[1]" "t.de.addr_buf.out.d.d[2].d[0]"
-= "t.de.atree_y[1].in[1]" "t.de.vtree_y.in.d[1].f"
-= "t.de.atree_y[1].in[1]" "t.de.vtree_y.in.d[1].d[0]"
-= "t.de.atree_y[1].in[1]" "t.de.atree_y[0].in[1]"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-= "t.de.in.v" "t.de.addr_buf.in.v"
-= "t.de.in.a" "t.de.addr_buf.in.a"
-= "t.de.in.d.d[0].f" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.in.d.d[0].t" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].d[0]"
-= "t.de.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].d[1]"
-= "t.de.in.d.d[1].f" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.in.d.d[1].t" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].d[0]"
-= "t.de.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].d[1]"
-= "t.de.in.d.d[2].f" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.in.d.d[2].t" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].d[0]"
-= "t.de.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].d[1]"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-~"t.de.vtree_y.ct.C2Els[0].c1"&~"t.de.vtree_y.ct.C2Els[0].c2"->"t.de.vtree_y.ct.C2Els[0]._y"+
-"t.de.vtree_y.ct.C2Els[0].c1"&"t.de.vtree_y.ct.C2Els[0].c2"->"t.de.vtree_y.ct.C2Els[0]._y"-
-"t.de.vtree_y.ct.C2Els[0]._y"->"t.de.vtree_y.ct.C2Els[0].y"-
-~("t.de.vtree_y.ct.C2Els[0]._y")->"t.de.vtree_y.ct.C2Els[0].y"+
-= "t.de.vtree_y.ct.supply.vdd" "t.de.vtree_y.ct.C2Els[0].vdd"
-= "t.de.vtree_y.ct.supply.vss" "t.de.vtree_y.ct.C2Els[0].vss"
-= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.ct.C2Els[0].c1"
-= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.ct.tmp[0]"
-= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.ct.C2Els[0].c2"
-= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.ct.tmp[1]"
-= "t.de.vtree_y.ct.out" "t.de.vtree_y.ct.C2Els[0].y"
-= "t.de.vtree_y.ct.out" "t.de.vtree_y.ct.tmp[2]"
-= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.OR2_tf[0].y"
-= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.OR2_tf[1].y"
-"t.de.vtree_y.OR2_tf[0].a"|"t.de.vtree_y.OR2_tf[0].b"->"t.de.vtree_y.OR2_tf[0]._y"-
-~("t.de.vtree_y.OR2_tf[0].a"|"t.de.vtree_y.OR2_tf[0].b")->"t.de.vtree_y.OR2_tf[0]._y"+
-"t.de.vtree_y.OR2_tf[0]._y"->"t.de.vtree_y.OR2_tf[0].y"-
-~("t.de.vtree_y.OR2_tf[0]._y")->"t.de.vtree_y.OR2_tf[0].y"+
-"t.de.vtree_y.OR2_tf[1].a"|"t.de.vtree_y.OR2_tf[1].b"->"t.de.vtree_y.OR2_tf[1]._y"-
-~("t.de.vtree_y.OR2_tf[1].a"|"t.de.vtree_y.OR2_tf[1].b")->"t.de.vtree_y.OR2_tf[1]._y"+
-"t.de.vtree_y.OR2_tf[1]._y"->"t.de.vtree_y.OR2_tf[1].y"-
-~("t.de.vtree_y.OR2_tf[1]._y")->"t.de.vtree_y.OR2_tf[1].y"+
-= "t.de.vtree_y.supply.vss" "t.de.vtree_y.ct.supply.vss"
-= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.ct.supply.vdd"
-= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.OR2_tf[1].vdd"
-= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.OR2_tf[0].vdd"
-= "t.de.vtree_y.supply.vss" "t.de.vtree_y.OR2_tf[1].vss"
-= "t.de.vtree_y.supply.vss" "t.de.vtree_y.OR2_tf[0].vss"
-= "t.de.vtree_y.out" "t.de.vtree_y.ct.out"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.OR2_tf[1].b"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.OR2_tf[1].a"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.OR2_tf[0].b"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.OR2_tf[0].a"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
-= "t.de.outy[0]" "t.de.atree_y[0].out"
-= "t.de.outy[1]" "t.de.atree_y[1].out"
-= "t.de.outy[2]" "t.de.atree_y[2].out"
-= "t.de.outy[3]" "t.de.atree_y[3].out"
-= "t.de.outx[0]" "t.de.atree_x[0].out"
-= "t.de.outx[1]" "t.de.atree_x[1].out"
-= "t.de.reset_B" "t.de.addr_buf.reset_B"
-"t.de.addr_buf.out_a_B_buf_t.buf1.a"->"t.de.addr_buf.out_a_B_buf_t.buf1._y"-
-~("t.de.addr_buf.out_a_B_buf_t.buf1.a")->"t.de.addr_buf.out_a_B_buf_t.buf1._y"+
-"t.de.addr_buf.out_a_B_buf_t.buf1._y"->"t.de.addr_buf.out_a_B_buf_t.buf1.y"-
-~("t.de.addr_buf.out_a_B_buf_t.buf1._y")->"t.de.addr_buf.out_a_B_buf_t.buf1.y"+
-= "t.de.addr_buf.out_a_B_buf_t.supply.vdd" "t.de.addr_buf.out_a_B_buf_t.buf1.vdd"
-= "t.de.addr_buf.out_a_B_buf_t.supply.vss" "t.de.addr_buf.out_a_B_buf_t.buf1.vss"
-= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.out[2]"
-= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.out[1]"
-= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.buf1.y"
-= "t.de.addr_buf.out_a_B_buf_t.in" "t.de.addr_buf.out_a_B_buf_t.buf1.a"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.en_buf_f.out[0]"
-= "t.de.addr_buf._en_X_f[1]" "t.de.addr_buf.en_buf_f.out[1]"
-= "t.de.addr_buf._en_X_f[2]" "t.de.addr_buf.en_buf_f.out[2]"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[2].c1"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[1].c1"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[0].c1"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf._en_X_f[2]"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf._en_X_f[1]"
-~"t.de.addr_buf.inack_ctl.c1"&~"t.de.addr_buf.inack_ctl.c2"&~"t.de.addr_buf.inack_ctl.c3"|~"t.de.addr_buf.inack_ctl.pr_B"->"t.de.addr_buf.inack_ctl._y"+
-"t.de.addr_buf.inack_ctl.c1"&"t.de.addr_buf.inack_ctl.c2"&"t.de.addr_buf.inack_ctl.c3"&"t.de.addr_buf.inack_ctl.sr_B"->"t.de.addr_buf.inack_ctl._y"-
-"t.de.addr_buf.inack_ctl._y"->"t.de.addr_buf.inack_ctl.y"-
-~("t.de.addr_buf.inack_ctl._y")->"t.de.addr_buf.inack_ctl.y"+
-"t.de.addr_buf.reset_bufarray.buf1.a"->"t.de.addr_buf.reset_bufarray.buf1._y"-
-~("t.de.addr_buf.reset_bufarray.buf1.a")->"t.de.addr_buf.reset_bufarray.buf1._y"+
-"t.de.addr_buf.reset_bufarray.buf1._y"->"t.de.addr_buf.reset_bufarray.buf1.y"-
-~("t.de.addr_buf.reset_bufarray.buf1._y")->"t.de.addr_buf.reset_bufarray.buf1.y"+
-= "t.de.addr_buf.reset_bufarray.supply.vdd" "t.de.addr_buf.reset_bufarray.buf1.vdd"
-= "t.de.addr_buf.reset_bufarray.supply.vss" "t.de.addr_buf.reset_bufarray.buf1.vss"
-= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.out[2]"
-= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.out[1]"
-= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.buf1.y"
-= "t.de.addr_buf.reset_bufarray.in" "t.de.addr_buf.reset_bufarray.buf1.a"
-"t.de.addr_buf.in_v_buf.a"->"t.de.addr_buf.in_v_buf._y"-
-~("t.de.addr_buf.in_v_buf.a")->"t.de.addr_buf.in_v_buf._y"+
-"t.de.addr_buf.in_v_buf._y"->"t.de.addr_buf.in_v_buf.y"-
-~("t.de.addr_buf.in_v_buf._y")->"t.de.addr_buf.in_v_buf.y"+
-"t.de.addr_buf.out_a_inv.a"->"t.de.addr_buf.out_a_inv.y"-
-~("t.de.addr_buf.out_a_inv.a")->"t.de.addr_buf.out_a_inv.y"+
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_buf_f.supply.vss"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_buf_f.supply.vdd"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_buf_t.supply.vss"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_buf_t.supply.vdd"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.vc.supply.vss"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.vc.supply.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[2].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[2].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[1].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[1].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[0].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[0].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.in_v_buf.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.reset_buf.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_ctl.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.inack_ctl.vdd"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[2].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[2].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[1].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[1].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[0].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[0].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.in_v_buf.vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.reset_buf.vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_ctl.vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.inack_ctl.vss"
-~"t.de.addr_buf.vc.ct.C3Els[0].c1"&~"t.de.addr_buf.vc.ct.C3Els[0].c2"&~"t.de.addr_buf.vc.ct.C3Els[0].c3"->"t.de.addr_buf.vc.ct.C3Els[0]._y"+
-"t.de.addr_buf.vc.ct.C3Els[0].c1"&"t.de.addr_buf.vc.ct.C3Els[0].c2"&"t.de.addr_buf.vc.ct.C3Els[0].c3"->"t.de.addr_buf.vc.ct.C3Els[0]._y"-
-"t.de.addr_buf.vc.ct.C3Els[0]._y"->"t.de.addr_buf.vc.ct.C3Els[0].y"-
-~("t.de.addr_buf.vc.ct.C3Els[0]._y")->"t.de.addr_buf.vc.ct.C3Els[0].y"+
-= "t.de.addr_buf.vc.ct.supply.vdd" "t.de.addr_buf.vc.ct.C3Els[0].vdd"
-= "t.de.addr_buf.vc.ct.supply.vss" "t.de.addr_buf.vc.ct.C3Els[0].vss"
-= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.ct.C3Els[0].c1"
-= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.ct.tmp[0]"
-= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.ct.C3Els[0].c2"
-= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.ct.tmp[1]"
-= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.ct.C3Els[0].c3"
-= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.ct.tmp[2]"
-= "t.de.addr_buf.vc.ct.out" "t.de.addr_buf.vc.ct.C3Els[0].y"
-= "t.de.addr_buf.vc.ct.out" "t.de.addr_buf.vc.ct.tmp[3]"
-= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.OR2_tf[0].y"
-= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.OR2_tf[1].y"
-= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.OR2_tf[2].y"
-"t.de.addr_buf.vc.OR2_tf[0].a"|"t.de.addr_buf.vc.OR2_tf[0].b"->"t.de.addr_buf.vc.OR2_tf[0]._y"-
-~("t.de.addr_buf.vc.OR2_tf[0].a"|"t.de.addr_buf.vc.OR2_tf[0].b")->"t.de.addr_buf.vc.OR2_tf[0]._y"+
-"t.de.addr_buf.vc.OR2_tf[0]._y"->"t.de.addr_buf.vc.OR2_tf[0].y"-
-~("t.de.addr_buf.vc.OR2_tf[0]._y")->"t.de.addr_buf.vc.OR2_tf[0].y"+
-"t.de.addr_buf.vc.OR2_tf[1].a"|"t.de.addr_buf.vc.OR2_tf[1].b"->"t.de.addr_buf.vc.OR2_tf[1]._y"-
-~("t.de.addr_buf.vc.OR2_tf[1].a"|"t.de.addr_buf.vc.OR2_tf[1].b")->"t.de.addr_buf.vc.OR2_tf[1]._y"+
-"t.de.addr_buf.vc.OR2_tf[1]._y"->"t.de.addr_buf.vc.OR2_tf[1].y"-
-~("t.de.addr_buf.vc.OR2_tf[1]._y")->"t.de.addr_buf.vc.OR2_tf[1].y"+
-"t.de.addr_buf.vc.OR2_tf[2].a"|"t.de.addr_buf.vc.OR2_tf[2].b"->"t.de.addr_buf.vc.OR2_tf[2]._y"-
-~("t.de.addr_buf.vc.OR2_tf[2].a"|"t.de.addr_buf.vc.OR2_tf[2].b")->"t.de.addr_buf.vc.OR2_tf[2]._y"+
-"t.de.addr_buf.vc.OR2_tf[2]._y"->"t.de.addr_buf.vc.OR2_tf[2].y"-
-~("t.de.addr_buf.vc.OR2_tf[2]._y")->"t.de.addr_buf.vc.OR2_tf[2].y"+
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.ct.supply.vss"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.ct.supply.vdd"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[2].vdd"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[1].vdd"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[0].vdd"
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[2].vss"
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[1].vss"
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[0].vss"
-= "t.de.addr_buf.vc.out" "t.de.addr_buf.vc.ct.out"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.OR2_tf[2].b"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.OR2_tf[2].a"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.OR2_tf[1].b"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.OR2_tf[1].a"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.OR2_tf[0].b"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.OR2_tf[0].a"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.out_a_B_buf_t.out[0]"
-= "t.de.addr_buf._out_a_BX_f[1]" "t.de.addr_buf.out_a_B_buf_t.out[1]"
-= "t.de.addr_buf._out_a_BX_f[2]" "t.de.addr_buf.out_a_B_buf_t.out[2]"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[2].c2"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[1].c2"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[0].c2"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf._out_a_BX_f[2]"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf._out_a_BX_f[1]"
-"t.de.addr_buf.out_a_B_buf_f.buf1.a"->"t.de.addr_buf.out_a_B_buf_f.buf1._y"-
-~("t.de.addr_buf.out_a_B_buf_f.buf1.a")->"t.de.addr_buf.out_a_B_buf_f.buf1._y"+
-"t.de.addr_buf.out_a_B_buf_f.buf1._y"->"t.de.addr_buf.out_a_B_buf_f.buf1.y"-
-~("t.de.addr_buf.out_a_B_buf_f.buf1._y")->"t.de.addr_buf.out_a_B_buf_f.buf1.y"+
-= "t.de.addr_buf.out_a_B_buf_f.supply.vdd" "t.de.addr_buf.out_a_B_buf_f.buf1.vdd"
-= "t.de.addr_buf.out_a_B_buf_f.supply.vss" "t.de.addr_buf.out_a_B_buf_f.buf1.vss"
-= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.out[2]"
-= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.out[1]"
-= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.buf1.y"
-= "t.de.addr_buf.out_a_B_buf_f.in" "t.de.addr_buf.out_a_B_buf_f.buf1.a"
-= "t.de.addr_buf._en" "t.de.addr_buf.en_buf_f.in"
-= "t.de.addr_buf._en" "t.de.addr_buf.en_buf_t.in"
-= "t.de.addr_buf._en" "t.de.addr_buf.en_ctl.y"
-= "t.de.addr_buf._en" "t.de.addr_buf.inack_ctl.c1"
-~"t.de.addr_buf.en_ctl.p1"&~"t.de.addr_buf.en_ctl.c1"->"t.de.addr_buf.en_ctl.y"+
-"t.de.addr_buf.en_ctl.c1"->"t.de.addr_buf.en_ctl.y"-
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.out.a" "t.de.addr_buf.out_a_inv.a"
-= "t.de.addr_buf.out.v" "t.de.addr_buf.en_ctl.p1"
-= "t.de.addr_buf.out.v" "t.de.addr_buf.inack_ctl.c3"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.f_buf_func[2].y"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.t_buf_func[2].y"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.f_buf_func[1].y"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.t_buf_func[1].y"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.f_buf_func[0].y"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.t_buf_func[0].y"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.addr_buf.in.d.d[0].f" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.in.d.d[0].t" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].d[0]"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].d[1]"
-= "t.de.addr_buf.in.d.d[1].f" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.in.d.d[1].t" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].d[0]"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].d[1]"
-= "t.de.addr_buf.in.d.d[2].f" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.in.d.d[2].t" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].d[0]"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].d[1]"
-= "t.de.addr_buf.in.a" "t.de.addr_buf.en_ctl.c1"
-= "t.de.addr_buf.in.a" "t.de.addr_buf.inack_ctl.y"
-= "t.de.addr_buf.in.v" "t.de.addr_buf.in_v_buf.y"
-= "t.de.addr_buf.in.v" "t.de.addr_buf.inack_ctl.c2"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.f_buf_func[2].n1"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.t_buf_func[2].n1"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.f_buf_func[1].n1"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.t_buf_func[1].n1"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.f_buf_func[0].n1"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.t_buf_func[0].n1"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-"t.de.addr_buf.reset_buf.a"->"t.de.addr_buf.reset_buf._y"-
-~("t.de.addr_buf.reset_buf.a")->"t.de.addr_buf.reset_buf._y"+
-"t.de.addr_buf.reset_buf._y"->"t.de.addr_buf.reset_buf.y"-
-~("t.de.addr_buf.reset_buf._y")->"t.de.addr_buf.reset_buf.y"+
-= "t.de.addr_buf._in_v" "t.de.addr_buf.in_v_buf.a"
-= "t.de.addr_buf._in_v" "t.de.addr_buf.vc.out"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.reset_bufarray.in"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.reset_buf.y"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.inack_ctl.sr_B"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.inack_ctl.pr_B"
-= "t.de.addr_buf.reset_B" "t.de.addr_buf.reset_buf.a"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.out_a_B_buf_f.out[0]"
-= "t.de.addr_buf._out_a_BX_t[1]" "t.de.addr_buf.out_a_B_buf_f.out[1]"
-= "t.de.addr_buf._out_a_BX_t[2]" "t.de.addr_buf.out_a_B_buf_f.out[2]"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[2].c2"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[1].c2"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[0].c2"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf._out_a_BX_t[2]"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf._out_a_BX_t[1]"
-"t.de.addr_buf.en_buf_f.buf1.a"->"t.de.addr_buf.en_buf_f.buf1._y"-
-~("t.de.addr_buf.en_buf_f.buf1.a")->"t.de.addr_buf.en_buf_f.buf1._y"+
-"t.de.addr_buf.en_buf_f.buf1._y"->"t.de.addr_buf.en_buf_f.buf1.y"-
-~("t.de.addr_buf.en_buf_f.buf1._y")->"t.de.addr_buf.en_buf_f.buf1.y"+
-= "t.de.addr_buf.en_buf_f.supply.vdd" "t.de.addr_buf.en_buf_f.buf1.vdd"
-= "t.de.addr_buf.en_buf_f.supply.vss" "t.de.addr_buf.en_buf_f.buf1.vss"
-= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.out[2]"
-= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.out[1]"
-= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.buf1.y"
-= "t.de.addr_buf.en_buf_f.in" "t.de.addr_buf.en_buf_f.buf1.a"
-"t.de.addr_buf.en_buf_t.buf1.a"->"t.de.addr_buf.en_buf_t.buf1._y"-
-~("t.de.addr_buf.en_buf_t.buf1.a")->"t.de.addr_buf.en_buf_t.buf1._y"+
-"t.de.addr_buf.en_buf_t.buf1._y"->"t.de.addr_buf.en_buf_t.buf1.y"-
-~("t.de.addr_buf.en_buf_t.buf1._y")->"t.de.addr_buf.en_buf_t.buf1.y"+
-= "t.de.addr_buf.en_buf_t.supply.vdd" "t.de.addr_buf.en_buf_t.buf1.vdd"
-= "t.de.addr_buf.en_buf_t.supply.vss" "t.de.addr_buf.en_buf_t.buf1.vss"
-= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.out[2]"
-= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.out[1]"
-= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.buf1.y"
-= "t.de.addr_buf.en_buf_t.in" "t.de.addr_buf.en_buf_t.buf1.a"
-= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_B_buf_t.in"
-= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_B_buf_f.in"
-= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_inv.y"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.reset_bufarray.out[0]"
-= "t.de.addr_buf._reset_BXX[1]" "t.de.addr_buf.reset_bufarray.out[1]"
-= "t.de.addr_buf._reset_BXX[2]" "t.de.addr_buf.reset_bufarray.out[2]"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[2].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[2].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[2].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[2].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[1].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[1].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[1].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[1].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[0].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[0].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[0].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[0].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf._reset_BXX[2]"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf._reset_BXX[1]"
-~"t.de.addr_buf.t_buf_func[0].c1"&~"t.de.addr_buf.t_buf_func[0].c2"|~"t.de.addr_buf.t_buf_func[0].pr_B"->"t.de.addr_buf.t_buf_func[0]._y"+
-"t.de.addr_buf.t_buf_func[0].c1"&"t.de.addr_buf.t_buf_func[0].c2"&"t.de.addr_buf.t_buf_func[0].n1"&"t.de.addr_buf.t_buf_func[0].sr_B"->"t.de.addr_buf.t_buf_func[0]._y"-
-"t.de.addr_buf.t_buf_func[0]._y"->"t.de.addr_buf.t_buf_func[0].y"-
-~("t.de.addr_buf.t_buf_func[0]._y")->"t.de.addr_buf.t_buf_func[0].y"+
-~"t.de.addr_buf.t_buf_func[1].c1"&~"t.de.addr_buf.t_buf_func[1].c2"|~"t.de.addr_buf.t_buf_func[1].pr_B"->"t.de.addr_buf.t_buf_func[1]._y"+
-"t.de.addr_buf.t_buf_func[1].c1"&"t.de.addr_buf.t_buf_func[1].c2"&"t.de.addr_buf.t_buf_func[1].n1"&"t.de.addr_buf.t_buf_func[1].sr_B"->"t.de.addr_buf.t_buf_func[1]._y"-
-"t.de.addr_buf.t_buf_func[1]._y"->"t.de.addr_buf.t_buf_func[1].y"-
-~("t.de.addr_buf.t_buf_func[1]._y")->"t.de.addr_buf.t_buf_func[1].y"+
-~"t.de.addr_buf.t_buf_func[2].c1"&~"t.de.addr_buf.t_buf_func[2].c2"|~"t.de.addr_buf.t_buf_func[2].pr_B"->"t.de.addr_buf.t_buf_func[2]._y"+
-"t.de.addr_buf.t_buf_func[2].c1"&"t.de.addr_buf.t_buf_func[2].c2"&"t.de.addr_buf.t_buf_func[2].n1"&"t.de.addr_buf.t_buf_func[2].sr_B"->"t.de.addr_buf.t_buf_func[2]._y"-
-"t.de.addr_buf.t_buf_func[2]._y"->"t.de.addr_buf.t_buf_func[2].y"-
-~("t.de.addr_buf.t_buf_func[2]._y")->"t.de.addr_buf.t_buf_func[2].y"+
-~"t.de.addr_buf.f_buf_func[0].c1"&~"t.de.addr_buf.f_buf_func[0].c2"|~"t.de.addr_buf.f_buf_func[0].pr_B"->"t.de.addr_buf.f_buf_func[0]._y"+
-"t.de.addr_buf.f_buf_func[0].c1"&"t.de.addr_buf.f_buf_func[0].c2"&"t.de.addr_buf.f_buf_func[0].n1"&"t.de.addr_buf.f_buf_func[0].sr_B"->"t.de.addr_buf.f_buf_func[0]._y"-
-"t.de.addr_buf.f_buf_func[0]._y"->"t.de.addr_buf.f_buf_func[0].y"-
-~("t.de.addr_buf.f_buf_func[0]._y")->"t.de.addr_buf.f_buf_func[0].y"+
-~"t.de.addr_buf.f_buf_func[1].c1"&~"t.de.addr_buf.f_buf_func[1].c2"|~"t.de.addr_buf.f_buf_func[1].pr_B"->"t.de.addr_buf.f_buf_func[1]._y"+
-"t.de.addr_buf.f_buf_func[1].c1"&"t.de.addr_buf.f_buf_func[1].c2"&"t.de.addr_buf.f_buf_func[1].n1"&"t.de.addr_buf.f_buf_func[1].sr_B"->"t.de.addr_buf.f_buf_func[1]._y"-
-"t.de.addr_buf.f_buf_func[1]._y"->"t.de.addr_buf.f_buf_func[1].y"-
-~("t.de.addr_buf.f_buf_func[1]._y")->"t.de.addr_buf.f_buf_func[1].y"+
-~"t.de.addr_buf.f_buf_func[2].c1"&~"t.de.addr_buf.f_buf_func[2].c2"|~"t.de.addr_buf.f_buf_func[2].pr_B"->"t.de.addr_buf.f_buf_func[2]._y"+
-"t.de.addr_buf.f_buf_func[2].c1"&"t.de.addr_buf.f_buf_func[2].c2"&"t.de.addr_buf.f_buf_func[2].n1"&"t.de.addr_buf.f_buf_func[2].sr_B"->"t.de.addr_buf.f_buf_func[2]._y"-
-"t.de.addr_buf.f_buf_func[2]._y"->"t.de.addr_buf.f_buf_func[2].y"-
-~("t.de.addr_buf.f_buf_func[2]._y")->"t.de.addr_buf.f_buf_func[2].y"+
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.en_buf_t.out[0]"
-= "t.de.addr_buf._en_X_t[1]" "t.de.addr_buf.en_buf_t.out[1]"
-= "t.de.addr_buf._en_X_t[2]" "t.de.addr_buf.en_buf_t.out[2]"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[2].c1"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[1].c1"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[0].c1"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf._en_X_t[2]"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf._en_X_t[1]"
-"t.de.vtree_x.ct.b.a"->"t.de.vtree_x.ct.b._y"-
-~("t.de.vtree_x.ct.b.a")->"t.de.vtree_x.ct.b._y"+
-"t.de.vtree_x.ct.b._y"->"t.de.vtree_x.ct.b.y"-
-~("t.de.vtree_x.ct.b._y")->"t.de.vtree_x.ct.b.y"+
-= "t.de.vtree_x.ct.supply.vdd" "t.de.vtree_x.ct.b.vdd"
-= "t.de.vtree_x.ct.supply.vss" "t.de.vtree_x.ct.b.vss"
-= "t.de.vtree_x.ct.out" "t.de.vtree_x.ct.b.y"
-= "t.de.vtree_x.ct.in[0]" "t.de.vtree_x.ct.b.a"
-= "t.de.vtree_x.ct.in[0]" "t.de.vtree_x.OR2_tf[0].y"
-"t.de.vtree_x.OR2_tf[0].a"|"t.de.vtree_x.OR2_tf[0].b"->"t.de.vtree_x.OR2_tf[0]._y"-
-~("t.de.vtree_x.OR2_tf[0].a"|"t.de.vtree_x.OR2_tf[0].b")->"t.de.vtree_x.OR2_tf[0]._y"+
-"t.de.vtree_x.OR2_tf[0]._y"->"t.de.vtree_x.OR2_tf[0].y"-
-~("t.de.vtree_x.OR2_tf[0]._y")->"t.de.vtree_x.OR2_tf[0].y"+
-= "t.de.vtree_x.supply.vss" "t.de.vtree_x.ct.supply.vss"
-= "t.de.vtree_x.supply.vdd" "t.de.vtree_x.ct.supply.vdd"
-= "t.de.vtree_x.supply.vdd" "t.de.vtree_x.OR2_tf[0].vdd"
-= "t.de.vtree_x.supply.vss" "t.de.vtree_x.OR2_tf[0].vss"
-= "t.de.vtree_x.out" "t.de.vtree_x.ct.out"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.OR2_tf[0].b"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.OR2_tf[0].a"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
-= "Vdd" "t.de.supply.vdd"
-= "GND" "t.de.supply.vss"
-= "t.dly_cfg[0]" "t.de.dly_cfg[0]"
-= "t.dly_cfg[1]" "t.de.dly_cfg[1]"
-= "t.dly_cfg[2]" "t.de.dly_cfg[2]"
-= "t.dly_cfg[3]" "t.de.dly_cfg[3]"
-= "t.out[0]" "t.ag.out[0]"
-= "t.out[1]" "t.ag.out[1]"
-= "t.out[2]" "t.ag.out[2]"
-= "t.out[3]" "t.ag.out[3]"
-= "t.out[4]" "t.ag.out[4]"
-= "t.out[5]" "t.ag.out[5]"
-= "t.out[6]" "t.ag.out[6]"
-= "t.out[7]" "t.ag.out[7]"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
-= "t.in.v" "t.de.in.v"
-= "t.in.a" "t.de.in.a"
-= "t.in.d.d[0].f" "t.de.in.d.d[0].f"
-= "t.in.d.d[0].t" "t.de.in.d.d[0].t"
-= "t.in.d.d[0].d[0]" "t.de.in.d.d[0].d[0]"
-= "t.in.d.d[0].d[1]" "t.de.in.d.d[0].d[1]"
-= "t.in.d.d[1].f" "t.de.in.d.d[1].f"
-= "t.in.d.d[1].t" "t.de.in.d.d[1].t"
-= "t.in.d.d[1].d[0]" "t.de.in.d.d[1].d[0]"
-= "t.in.d.d[1].d[1]" "t.de.in.d.d[1].d[1]"
-= "t.in.d.d[2].f" "t.de.in.d.d[2].f"
-= "t.in.d.d[2].t" "t.de.in.d.d[2].t"
-= "t.in.d.d[2].d[0]" "t.de.in.d.d[2].d[0]"
-= "t.in.d.d[2].d[1]" "t.de.in.d.d[2].d[1]"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"

test/unit_tests/decoder_2d_hs/test.act

@@ -48,13 +48,10 @@ defproc decoder_2d_hs_2x4 (avMx1of2<3> in; a1of1 out[8]){
     supply.vdd = Vdd;
     supply.vss = GND;
 
-    decoder_2d_hs<1,2,2,4,3> decoder(.in = in, .out = out,
+    decoder_2d_hs<1,2,2,4> decoder(.in = in, .out = out,
         .reset_B = _reset_B, .supply = supply);
 
     // model the synapse as having automatic pulldown of ack.
-    // Needed since still have the timing assumption,
-    // that the synapse ack is pulled down pretty soon after its req is removed.
-    // Otherwise it starts fighting the line pull down.
     INV_X1 synapses[8];
     PULLDOWN_X4 synapses2[8];
     (i:8:

test/unit_tests/delayprog_4/run/prsim.out

@@ -1,134 +1,272 @@
-t.s[2] t.dp.dly[2].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.a t.s[0] t.dp.and2[2]._y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[11].y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[9].a t.dp.dly[1].y t.dp.dly[1].a t.dp.dly[4].a t.y t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[10].a t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[8].a t.dp.dly[0].a t.dp.dly[7].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.mu2[1]._s t.dp.dly[11].a t.dp.dly[14].a t.dp.dly[13].a t.dp.dly[13]._y t.dp.dly[7].y t.dp.dly[8]._y t.dp.mu2[2]._y t.dp.dly[3].y t.dp.dly[14].y t.dp.dly[0].y t.dp.dly[3]._y t.dp.dly[13].y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[10].y t.dp.dly[9].y t.dp.dly[4]._y t.dp.dly[12].y t.dp.dly[8].y t.dp.mu2[1]._y t.dp.dly[12].a t.dp.dly[10]._y 
+t.s[2] t.dp.dly[4].__y t.dp.dly[3].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.dp.dly[9].___y t.dp.dly[0].___y t.s[0] t.dp.dly[6].___y t.dp.dly[4].___y t.dp.and2[2]._y t.dp.dly[3].__y t.dp.dly[11].__y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp.dly[8].___y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[10].___y t.dp.dly[11].y t.dp.dly[8].__y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[11].___y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[12].___y t.dp.dly[8].y t.dp.dly[1].y t.dp.dly[5].__y t.dp.dly[1].a t.in t.dp.dly[7].a t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[9].y t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[7].y t.dp.dly[6].__y t.dp.dly[0].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.dly[13].___y t.out t.dp.mu2[3].b t.dp.mu2[1]._s t.dp.dly[10].y t.dp.dly[1].__y t.dp.dly[13].y t.dp.dly[12].y t.dp.dly[13]._y t.dp.dly[12].__y t.dp.dly[8]._y t.dp.dly[14].__y t.dp.dly[10].__y t.dp.mu2[2]._y t.dp.dly[5].___y t.dp.dly[9].__y t.dp.dly[3].y t.dp.dly[14].___y t.dp.dly[7].__y t.dp.dly[0].y t.dp.dly[2].__y t.dp.dly[3]._y t.dp.dly[3].___y t.dp.dly[2].___y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[13].__y t.dp.dly[1].___y t.dp.dly[4]._y t.dp.dly[7].___y t.dp.mu2[1]._y t.dp.dly[0].__y t.dp.dly[10]._y 
 0
-	         0 t.a : 0
+	         0 t.in : 0
 	         0 t.s[3] : 1
 	         0 t.s[1] : 1
 	         0 t.s[0] : 1
 	         0 t.s[2] : 1
-	         1 t.dp.and2[0]._y : 1  [by t.a:=0]
+	         1 t.dp.and2[0]._y : 1  [by t.in:=0]
 	         2 t.dp.mu2[0]._s : 0  [by t.s[0]:=1]
 	      1138 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
 	      1252 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
 	      4753 t.dp.mu2[2]._s : 0  [by t.s[2]:=1]
 	      7092 t.dp.mu2[3]._s : 0  [by t.s[3]:=1]
 	     10467 t.dp.mu2[1]._s : 0  [by t.s[1]:=1]
-	     66618 t.dp.dly[0].y : 0  [by t.dp.dly[0]._y:=1]
-	     68344 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
-	     68383 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	     68398 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
-	     68889 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
-	     68902 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
-	     68942 t.dp.dly[1].y : 0  [by t.dp.dly[1]._y:=1]
-	     69357 t.dp.mu2[1]._y : 1  [by t.dp.dly[1].y:=0]
-	     69377 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	     75438 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
-	     75485 t.dp.dly[2].a : 0  [by t.dp.and2[2]._y:=1]
-	     75501 t.dp.dly[2]._y : 1  [by t.dp.dly[2].a:=0]
-	    119599 t.dp.dly[2].y : 0  [by t.dp.dly[2]._y:=1]
-	    133323 t.dp.dly[3]._y : 1  [by t.dp.dly[2].y:=0]
-	    133327 t.dp.dly[3].y : 0  [by t.dp.dly[3]._y:=1]
-	    142456 t.dp.mu2[2]._y : 1  [by t.dp.dly[3].y:=0]
-	    142471 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    185719 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
-	    222650 t.dp.dly[4].a : 0  [by t.dp.and2[3]._y:=1]
-	    222705 t.dp.dly[4]._y : 1  [by t.dp.dly[4].a:=0]
-	    274358 t.dp.dly[4].y : 0  [by t.dp.dly[4]._y:=1]
-	    304138 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
-	    317987 t.dp.dly[5].y : 0  [by t.dp.dly[5]._y:=1]
-	    342799 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
-	    357142 t.dp.dly[6].y : 0  [by t.dp.dly[6]._y:=1]
-	    357564 t.dp.mu2[3]._y : 1  [by t.dp.dly[6].y:=0]
-	    406278 t.y : 0  [by t.dp.mu2[3]._y:=1]
+	     66618 t.dp.dly[0].__y : 0  [by t.dp.dly[0]._y:=1]
+	     68344 t.dp.dly[0].___y : 1  [by t.dp.dly[0].__y:=0]
+	     68383 t.dp.dly[0].y : 0  [by t.dp.dly[0].___y:=1]
+	     68398 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
+	     68889 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
+	     68902 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
+	     68942 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
+	     69357 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
+	     69377 t.dp.dly[1].__y : 0  [by t.dp.dly[1]._y:=1]
+	     75438 t.dp.dly[1].___y : 1  [by t.dp.dly[1].__y:=0]
+	     75485 t.dp.dly[1].y : 0  [by t.dp.dly[1].___y:=1]
+	     75501 t.dp.dly[2]._y : 1  [by t.dp.dly[1].y:=0]
+	    119599 t.dp.dly[2].__y : 0  [by t.dp.dly[2]._y:=1]
+	    133323 t.dp.dly[2].___y : 1  [by t.dp.dly[2].__y:=0]
+	    133327 t.dp.dly[2].y : 0  [by t.dp.dly[2].___y:=1]
+	    142456 t.dp.mu2[1]._y : 1  [by t.dp.dly[2].y:=0]
+	    142471 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
+	    185719 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
+	    222650 t.dp.dly[3].a : 0  [by t.dp.and2[2]._y:=1]
+	    222705 t.dp.dly[3]._y : 1  [by t.dp.dly[3].a:=0]
+	    274358 t.dp.dly[3].__y : 0  [by t.dp.dly[3]._y:=1]
+	    304138 t.dp.dly[3].___y : 1  [by t.dp.dly[3].__y:=0]
+	    317987 t.dp.dly[3].y : 0  [by t.dp.dly[3].___y:=1]
+	    342799 t.dp.dly[4]._y : 1  [by t.dp.dly[3].y:=0]
+	    357142 t.dp.dly[4].__y : 0  [by t.dp.dly[4]._y:=1]
+	    357564 t.dp.dly[4].___y : 1  [by t.dp.dly[4].__y:=0]
+	    406278 t.dp.dly[4].y : 0  [by t.dp.dly[4].___y:=1]
+	    406279 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
+	    406280 t.dp.dly[5].__y : 0  [by t.dp.dly[5]._y:=1]
+	    426485 t.dp.dly[5].___y : 1  [by t.dp.dly[5].__y:=0]
+	    426767 t.dp.dly[5].y : 0  [by t.dp.dly[5].___y:=1]
+	    427535 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
+	    427538 t.dp.dly[6].__y : 0  [by t.dp.dly[6]._y:=1]
+	    449979 t.dp.dly[6].___y : 1  [by t.dp.dly[6].__y:=0]
+	    450530 t.dp.dly[6].y : 0  [by t.dp.dly[6].___y:=1]
+	    451601 t.dp.mu2[2]._y : 1  [by t.dp.dly[6].y:=0]
+	    452555 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
+	    453636 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
+	    508106 t.dp.dly[7].a : 0  [by t.dp.and2[3]._y:=1]
+	    509088 t.dp.dly[7]._y : 1  [by t.dp.dly[7].a:=0]
+	    509106 t.dp.dly[7].__y : 0  [by t.dp.dly[7]._y:=1]
+	    513119 t.dp.dly[7].___y : 1  [by t.dp.dly[7].__y:=0]
+	    517122 t.dp.dly[7].y : 0  [by t.dp.dly[7].___y:=1]
+	    562023 t.dp.dly[8]._y : 1  [by t.dp.dly[7].y:=0]
+	    583607 t.dp.dly[8].__y : 0  [by t.dp.dly[8]._y:=1]
+	    588367 t.dp.dly[8].___y : 1  [by t.dp.dly[8].__y:=0]
+	    588869 t.dp.dly[8].y : 0  [by t.dp.dly[8].___y:=1]
+	    589072 t.dp.dly[9]._y : 1  [by t.dp.dly[8].y:=0]
+	    590926 t.dp.dly[9].__y : 0  [by t.dp.dly[9]._y:=1]
+	    591065 t.dp.dly[9].___y : 1  [by t.dp.dly[9].__y:=0]
+	    627411 t.dp.dly[9].y : 0  [by t.dp.dly[9].___y:=1]
+	    627480 t.dp.dly[10]._y : 1  [by t.dp.dly[9].y:=0]
+	    627491 t.dp.dly[10].__y : 0  [by t.dp.dly[10]._y:=1]
+	    679277 t.dp.dly[10].___y : 1  [by t.dp.dly[10].__y:=0]
+	    679481 t.dp.dly[10].y : 0  [by t.dp.dly[10].___y:=1]
+	    679496 t.dp.dly[11]._y : 1  [by t.dp.dly[10].y:=0]
+	    679497 t.dp.dly[11].__y : 0  [by t.dp.dly[11]._y:=1]
+	    679534 t.dp.dly[11].___y : 1  [by t.dp.dly[11].__y:=0]
+	    680273 t.dp.dly[11].y : 0  [by t.dp.dly[11].___y:=1]
+	    680385 t.dp.dly[12]._y : 1  [by t.dp.dly[11].y:=0]
+	    727897 t.dp.dly[12].__y : 0  [by t.dp.dly[12]._y:=1]
+	    727937 t.dp.dly[12].___y : 1  [by t.dp.dly[12].__y:=0]
+	    728194 t.dp.dly[12].y : 0  [by t.dp.dly[12].___y:=1]
+	    728281 t.dp.dly[13]._y : 1  [by t.dp.dly[12].y:=0]
+	    728575 t.dp.dly[13].__y : 0  [by t.dp.dly[13]._y:=1]
+	    728576 t.dp.dly[13].___y : 1  [by t.dp.dly[13].__y:=0]
+	    730382 t.dp.dly[13].y : 0  [by t.dp.dly[13].___y:=1]
+	    732389 t.dp.dly[14]._y : 1  [by t.dp.dly[13].y:=0]
+	    733598 t.dp.dly[14].__y : 0  [by t.dp.dly[14]._y:=1]
+	    734188 t.dp.dly[14].___y : 1  [by t.dp.dly[14].__y:=0]
+	    734366 t.dp.mu2[3].b : 0  [by t.dp.dly[14].___y:=1]
+	    735169 t.dp.mu2[3]._y : 1  [by t.dp.mu2[3].b:=0]
+	    735333 t.out : 0  [by t.dp.mu2[3]._y:=1]
 [] setting high
-	    406278 t.a : 1
-	    406279 t.dp.and2[0]._y : 0  [by t.a:=1]
-	    406280 t.dp.dly[0].a : 1  [by t.dp.and2[0]._y:=0]
-	    426485 t.dp.dly[0]._y : 0  [by t.dp.dly[0].a:=1]
-	    426767 t.dp.dly[0].y : 1  [by t.dp.dly[0]._y:=0]
-	    427535 t.dp.mu2[0]._y : 0  [by t.dp.dly[0].y:=1]
-	    427538 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
-	    449979 t.dp.and2[1]._y : 0  [by t.dp._a[1]:=1]
-	    450530 t.dp.dly[1].a : 1  [by t.dp.and2[1]._y:=0]
-	    451601 t.dp.dly[1]._y : 0  [by t.dp.dly[1].a:=1]
-	    452555 t.dp.dly[1].y : 1  [by t.dp.dly[1]._y:=0]
-	    453636 t.dp.mu2[1]._y : 0  [by t.dp.dly[1].y:=1]
-	    508106 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
-	    509088 t.dp.and2[2]._y : 0  [by t.dp._a[2]:=1]
-	    509106 t.dp.dly[2].a : 1  [by t.dp.and2[2]._y:=0]
-	    513119 t.dp.dly[2]._y : 0  [by t.dp.dly[2].a:=1]
-	    517122 t.dp.dly[2].y : 1  [by t.dp.dly[2]._y:=0]
-	    562023 t.dp.dly[3]._y : 0  [by t.dp.dly[2].y:=1]
-	    583607 t.dp.dly[3].y : 1  [by t.dp.dly[3]._y:=0]
-	    588367 t.dp.mu2[2]._y : 0  [by t.dp.dly[3].y:=1]
-	    588869 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
-	    589072 t.dp.and2[3]._y : 0  [by t.dp._a[3]:=1]
-	    590926 t.dp.dly[4].a : 1  [by t.dp.and2[3]._y:=0]
-	    591065 t.dp.dly[4]._y : 0  [by t.dp.dly[4].a:=1]
-	    627411 t.dp.dly[4].y : 1  [by t.dp.dly[4]._y:=0]
-	    627480 t.dp.dly[5]._y : 0  [by t.dp.dly[4].y:=1]
-	    627491 t.dp.dly[5].y : 1  [by t.dp.dly[5]._y:=0]
-	    679277 t.dp.dly[6]._y : 0  [by t.dp.dly[5].y:=1]
-	    679481 t.dp.dly[6].y : 1  [by t.dp.dly[6]._y:=0]
-	    679496 t.dp.mu2[3]._y : 0  [by t.dp.dly[6].y:=1]
-	    679497 t.y : 1  [by t.dp.mu2[3]._y:=0]
+	    735333 t.in : 1
+	    737528 t.dp.and2[0]._y : 0  [by t.in:=1]
+	    737550 t.dp.dly[0].a : 1  [by t.dp.and2[0]._y:=0]
+	    738397 t.dp.dly[0]._y : 0  [by t.dp.dly[0].a:=1]
+	    768525 t.dp.dly[0].__y : 1  [by t.dp.dly[0]._y:=0]
+	    768658 t.dp.dly[0].___y : 0  [by t.dp.dly[0].__y:=1]
+	    784320 t.dp.dly[0].y : 1  [by t.dp.dly[0].___y:=0]
+	    784679 t.dp.mu2[0]._y : 0  [by t.dp.dly[0].y:=1]
+	    798795 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
+	    799016 t.dp.and2[1]._y : 0  [by t.dp._a[1]:=1]
+	    799023 t.dp.dly[1].a : 1  [by t.dp.and2[1]._y:=0]
+	    799053 t.dp.dly[1]._y : 0  [by t.dp.dly[1].a:=1]
+	    805766 t.dp.dly[1].__y : 1  [by t.dp.dly[1]._y:=0]
+	    863227 t.dp.dly[1].___y : 0  [by t.dp.dly[1].__y:=1]
+	    863318 t.dp.dly[1].y : 1  [by t.dp.dly[1].___y:=0]
+	    865507 t.dp.dly[2]._y : 0  [by t.dp.dly[1].y:=1]
+	    865514 t.dp.dly[2].__y : 1  [by t.dp.dly[2]._y:=0]
+	    868301 t.dp.dly[2].___y : 0  [by t.dp.dly[2].__y:=1]
+	    868407 t.dp.dly[2].y : 1  [by t.dp.dly[2].___y:=0]
+	    868485 t.dp.mu2[1]._y : 0  [by t.dp.dly[2].y:=1]
+	    868760 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
+	    887756 t.dp.and2[2]._y : 0  [by t.dp._a[2]:=1]
+	    888211 t.dp.dly[3].a : 1  [by t.dp.and2[2]._y:=0]
+	    888223 t.dp.dly[3]._y : 0  [by t.dp.dly[3].a:=1]
+	    888627 t.dp.dly[3].__y : 1  [by t.dp.dly[3]._y:=0]
+	    888639 t.dp.dly[3].___y : 0  [by t.dp.dly[3].__y:=1]
+	    894555 t.dp.dly[3].y : 1  [by t.dp.dly[3].___y:=0]
+	    898831 t.dp.dly[4]._y : 0  [by t.dp.dly[3].y:=1]
+	    901730 t.dp.dly[4].__y : 1  [by t.dp.dly[4]._y:=0]
+	    906025 t.dp.dly[4].___y : 0  [by t.dp.dly[4].__y:=1]
+	    906027 t.dp.dly[4].y : 1  [by t.dp.dly[4].___y:=0]
+	    910562 t.dp.dly[5]._y : 0  [by t.dp.dly[4].y:=1]
+	    911811 t.dp.dly[5].__y : 1  [by t.dp.dly[5]._y:=0]
+	    915310 t.dp.dly[5].___y : 0  [by t.dp.dly[5].__y:=1]
+	    915476 t.dp.dly[5].y : 1  [by t.dp.dly[5].___y:=0]
+	    915551 t.dp.dly[6]._y : 0  [by t.dp.dly[5].y:=1]
+	    915896 t.dp.dly[6].__y : 1  [by t.dp.dly[6]._y:=0]
+	    916034 t.dp.dly[6].___y : 0  [by t.dp.dly[6].__y:=1]
+	    921297 t.dp.dly[6].y : 1  [by t.dp.dly[6].___y:=0]
+	    921299 t.dp.mu2[2]._y : 0  [by t.dp.dly[6].y:=1]
+	    965216 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
+	    965217 t.dp.and2[3]._y : 0  [by t.dp._a[3]:=1]
+	    965765 t.dp.dly[7].a : 1  [by t.dp.and2[3]._y:=0]
+	    965776 t.dp.dly[7]._y : 0  [by t.dp.dly[7].a:=1]
+	    966146 t.dp.dly[7].__y : 1  [by t.dp.dly[7]._y:=0]
+	    966213 t.dp.dly[7].___y : 0  [by t.dp.dly[7].__y:=1]
+	    968854 t.dp.dly[7].y : 1  [by t.dp.dly[7].___y:=0]
+	    968870 t.dp.dly[8]._y : 0  [by t.dp.dly[7].y:=1]
+	    973432 t.dp.dly[8].__y : 1  [by t.dp.dly[8]._y:=0]
+	    973960 t.dp.dly[8].___y : 0  [by t.dp.dly[8].__y:=1]
+	    976395 t.dp.dly[8].y : 1  [by t.dp.dly[8].___y:=0]
+	   1003275 t.dp.dly[9]._y : 0  [by t.dp.dly[8].y:=1]
+	   1027200 t.dp.dly[9].__y : 1  [by t.dp.dly[9]._y:=0]
+	   1040241 t.dp.dly[9].___y : 0  [by t.dp.dly[9].__y:=1]
+	   1040243 t.dp.dly[9].y : 1  [by t.dp.dly[9].___y:=0]
+	   1101201 t.dp.dly[10]._y : 0  [by t.dp.dly[9].y:=1]
+	   1101204 t.dp.dly[10].__y : 1  [by t.dp.dly[10]._y:=0]
+	   1101233 t.dp.dly[10].___y : 0  [by t.dp.dly[10].__y:=1]
+	   1101550 t.dp.dly[10].y : 1  [by t.dp.dly[10].___y:=0]
+	   1103151 t.dp.dly[11]._y : 0  [by t.dp.dly[10].y:=1]
+	   1103304 t.dp.dly[11].__y : 1  [by t.dp.dly[11]._y:=0]
+	   1103348 t.dp.dly[11].___y : 0  [by t.dp.dly[11].__y:=1]
+	   1106109 t.dp.dly[11].y : 1  [by t.dp.dly[11].___y:=0]
+	   1119792 t.dp.dly[12]._y : 0  [by t.dp.dly[11].y:=1]
+	   1119793 t.dp.dly[12].__y : 1  [by t.dp.dly[12]._y:=0]
+	   1120010 t.dp.dly[12].___y : 0  [by t.dp.dly[12].__y:=1]
+	   1120032 t.dp.dly[12].y : 1  [by t.dp.dly[12].___y:=0]
+	   1120033 t.dp.dly[13]._y : 0  [by t.dp.dly[12].y:=1]
+	   1121614 t.dp.dly[13].__y : 1  [by t.dp.dly[13]._y:=0]
+	   1130959 t.dp.dly[13].___y : 0  [by t.dp.dly[13].__y:=1]
+	   1131118 t.dp.dly[13].y : 1  [by t.dp.dly[13].___y:=0]
+	   1150794 t.dp.dly[14]._y : 0  [by t.dp.dly[13].y:=1]
+	   1152081 t.dp.dly[14].__y : 1  [by t.dp.dly[14]._y:=0]
+	   1154313 t.dp.dly[14].___y : 0  [by t.dp.dly[14].__y:=1]
+	   1154458 t.dp.mu2[3].b : 1  [by t.dp.dly[14].___y:=0]
+	   1157290 t.dp.mu2[3]._y : 0  [by t.dp.mu2[3].b:=1]
+	   1163644 t.out : 1  [by t.dp.mu2[3]._y:=0]
 [] setting low
-	    679497 t.a : 0
-	    679534 t.dp.and2[0]._y : 1  [by t.a:=0]
-	    680273 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
-	    680385 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
-	    727897 t.dp.dly[0].y : 0  [by t.dp.dly[0]._y:=1]
-	    727937 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
-	    728194 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	    728281 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
-	    728575 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
-	    728576 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
-	    730382 t.dp.dly[1].y : 0  [by t.dp.dly[1]._y:=1]
-	    732389 t.dp.mu2[1]._y : 1  [by t.dp.dly[1].y:=0]
-	    733598 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	    734188 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
-	    734366 t.dp.dly[2].a : 0  [by t.dp.and2[2]._y:=1]
-	    735169 t.dp.dly[2]._y : 1  [by t.dp.dly[2].a:=0]
-	    735333 t.dp.dly[2].y : 0  [by t.dp.dly[2]._y:=1]
-	    737528 t.dp.dly[3]._y : 1  [by t.dp.dly[2].y:=0]
-	    737550 t.dp.dly[3].y : 0  [by t.dp.dly[3]._y:=1]
-	    738397 t.dp.mu2[2]._y : 1  [by t.dp.dly[3].y:=0]
-	    768525 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    768658 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
-	    784320 t.dp.dly[4].a : 0  [by t.dp.and2[3]._y:=1]
-	    784679 t.dp.dly[4]._y : 1  [by t.dp.dly[4].a:=0]
-	    798795 t.dp.dly[4].y : 0  [by t.dp.dly[4]._y:=1]
-	    799016 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
-	    799023 t.dp.dly[5].y : 0  [by t.dp.dly[5]._y:=1]
-	    799053 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
-	    805766 t.dp.dly[6].y : 0  [by t.dp.dly[6]._y:=1]
-	    863227 t.dp.mu2[3]._y : 1  [by t.dp.dly[6].y:=0]
-	    863318 t.y : 0  [by t.dp.mu2[3]._y:=1]
+	   1163644 t.in : 0
+	   1163645 t.dp.and2[0]._y : 1  [by t.in:=0]
+	   1202929 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
+	   1203091 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
+	   1210460 t.dp.dly[0].__y : 0  [by t.dp.dly[0]._y:=1]
+	   1210474 t.dp.dly[0].___y : 1  [by t.dp.dly[0].__y:=0]
+	   1210481 t.dp.dly[0].y : 0  [by t.dp.dly[0].___y:=1]
+	   1210641 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
+	   1232198 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
+	   1232199 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
+	   1232200 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
+	   1232201 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
+	   1234444 t.dp.dly[1].__y : 0  [by t.dp.dly[1]._y:=1]
+	   1234631 t.dp.dly[1].___y : 1  [by t.dp.dly[1].__y:=0]
+	   1234632 t.dp.dly[1].y : 0  [by t.dp.dly[1].___y:=1]
+	   1238814 t.dp.dly[2]._y : 1  [by t.dp.dly[1].y:=0]
+	   1273596 t.dp.dly[2].__y : 0  [by t.dp.dly[2]._y:=1]
+	   1273597 t.dp.dly[2].___y : 1  [by t.dp.dly[2].__y:=0]
+	   1274450 t.dp.dly[2].y : 0  [by t.dp.dly[2].___y:=1]
+	   1274455 t.dp.mu2[1]._y : 1  [by t.dp.dly[2].y:=0]
+	   1275346 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
+	   1275347 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
+	   1275364 t.dp.dly[3].a : 0  [by t.dp.and2[2]._y:=1]
+	   1277937 t.dp.dly[3]._y : 1  [by t.dp.dly[3].a:=0]
+	   1286298 t.dp.dly[3].__y : 0  [by t.dp.dly[3]._y:=1]
+	   1286301 t.dp.dly[3].___y : 1  [by t.dp.dly[3].__y:=0]
+	   1287242 t.dp.dly[3].y : 0  [by t.dp.dly[3].___y:=1]
+	   1346204 t.dp.dly[4]._y : 1  [by t.dp.dly[3].y:=0]
+	   1346205 t.dp.dly[4].__y : 0  [by t.dp.dly[4]._y:=1]
+	   1346247 t.dp.dly[4].___y : 1  [by t.dp.dly[4].__y:=0]
+	   1349064 t.dp.dly[4].y : 0  [by t.dp.dly[4].___y:=1]
+	   1362797 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
+	   1362892 t.dp.dly[5].__y : 0  [by t.dp.dly[5]._y:=1]
+	   1363227 t.dp.dly[5].___y : 1  [by t.dp.dly[5].__y:=0]
+	   1363235 t.dp.dly[5].y : 0  [by t.dp.dly[5].___y:=1]
+	   1363269 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
+	   1377156 t.dp.dly[6].__y : 0  [by t.dp.dly[6]._y:=1]
+	   1378074 t.dp.dly[6].___y : 1  [by t.dp.dly[6].__y:=0]
+	   1378078 t.dp.dly[6].y : 0  [by t.dp.dly[6].___y:=1]
+	   1424456 t.dp.mu2[2]._y : 1  [by t.dp.dly[6].y:=0]
+	   1426854 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
+	   1430069 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
+	   1477188 t.dp.dly[7].a : 0  [by t.dp.and2[3]._y:=1]
+	   1477236 t.dp.dly[7]._y : 1  [by t.dp.dly[7].a:=0]
+	   1477239 t.dp.dly[7].__y : 0  [by t.dp.dly[7]._y:=1]
+	   1477417 t.dp.dly[7].___y : 1  [by t.dp.dly[7].__y:=0]
+	   1498394 t.dp.dly[7].y : 0  [by t.dp.dly[7].___y:=1]
+	   1510293 t.dp.dly[8]._y : 1  [by t.dp.dly[7].y:=0]
+	   1516244 t.dp.dly[8].__y : 0  [by t.dp.dly[8]._y:=1]
+	   1555729 t.dp.dly[8].___y : 1  [by t.dp.dly[8].__y:=0]
+	   1556556 t.dp.dly[8].y : 0  [by t.dp.dly[8].___y:=1]
+	   1556729 t.dp.dly[9]._y : 1  [by t.dp.dly[8].y:=0]
+	   1556913 t.dp.dly[9].__y : 0  [by t.dp.dly[9]._y:=1]
+	   1556914 t.dp.dly[9].___y : 1  [by t.dp.dly[9].__y:=0]
+	   1556987 t.dp.dly[9].y : 0  [by t.dp.dly[9].___y:=1]
+	   1556991 t.dp.dly[10]._y : 1  [by t.dp.dly[9].y:=0]
+	   1594279 t.dp.dly[10].__y : 0  [by t.dp.dly[10]._y:=1]
+	   1594375 t.dp.dly[10].___y : 1  [by t.dp.dly[10].__y:=0]
+	   1594511 t.dp.dly[10].y : 0  [by t.dp.dly[10].___y:=1]
+	   1594512 t.dp.dly[11]._y : 1  [by t.dp.dly[10].y:=0]
+	   1613558 t.dp.dly[11].__y : 0  [by t.dp.dly[11]._y:=1]
+	   1613799 t.dp.dly[11].___y : 1  [by t.dp.dly[11].__y:=0]
+	   1617758 t.dp.dly[11].y : 0  [by t.dp.dly[11].___y:=1]
+	   1617770 t.dp.dly[12]._y : 1  [by t.dp.dly[11].y:=0]
+	   1621670 t.dp.dly[12].__y : 0  [by t.dp.dly[12]._y:=1]
+	   1622699 t.dp.dly[12].___y : 1  [by t.dp.dly[12].__y:=0]
+	   1622700 t.dp.dly[12].y : 0  [by t.dp.dly[12].___y:=1]
+	   1622756 t.dp.dly[13]._y : 1  [by t.dp.dly[12].y:=0]
+	   1667762 t.dp.dly[13].__y : 0  [by t.dp.dly[13]._y:=1]
+	   1667763 t.dp.dly[13].___y : 1  [by t.dp.dly[13].__y:=0]
+	   1667800 t.dp.dly[13].y : 0  [by t.dp.dly[13].___y:=1]
+	   1691175 t.dp.dly[14]._y : 1  [by t.dp.dly[13].y:=0]
+	   1691176 t.dp.dly[14].__y : 0  [by t.dp.dly[14]._y:=1]
+	   1694740 t.dp.dly[14].___y : 1  [by t.dp.dly[14].__y:=0]
+	   1696432 t.dp.mu2[3].b : 0  [by t.dp.dly[14].___y:=1]
+	   1696445 t.dp.mu2[3]._y : 1  [by t.dp.mu2[3].b:=0]
+	   1713429 t.out : 0  [by t.dp.mu2[3]._y:=1]
 [] setting configs low
-	    863318 t.s[0] : 0
-	    863318 t.s[3] : 0
-	    863318 t.s[2] : 0
-	    863318 t.s[1] : 0
-	    863325 t.dp.mu2[3]._s : 1  [by t.s[3]:=0]
-	    863424 t.dp.mu2[1]._s : 1  [by t.s[1]:=0]
-	    865507 t.dp.mu2[0]._s : 1  [by t.s[0]:=0]
-	    866105 t.dp.mu2[2]._s : 1  [by t.s[2]:=0]
+	   1713429 t.s[0] : 0
+	   1713429 t.s[3] : 0
+	   1713429 t.s[2] : 0
+	   1713429 t.s[1] : 0
+	   1713430 t.dp.mu2[1]._s : 1  [by t.s[1]:=0]
+	   1713450 t.dp.mu2[2]._s : 1  [by t.s[2]:=0]
+	   1713454 t.dp.mu2[3]._s : 1  [by t.s[3]:=0]
+	   1713786 t.dp.mu2[0]._s : 1  [by t.s[0]:=0]
 [] setting high
-	    866105 t.a : 1
-	    866183 t.dp.mu2[0]._y : 0  [by t.a:=1]
-	    866458 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
-	    885454 t.dp.mu2[1]._y : 0  [by t.dp._a[1]:=1]
-	    885909 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
-	    885921 t.dp.mu2[2]._y : 0  [by t.dp._a[2]:=1]
-	    886325 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
-	    886337 t.dp.mu2[3]._y : 0  [by t.dp._a[3]:=1]
-	    892253 t.y : 1  [by t.dp.mu2[3]._y:=0]
+	   1713786 t.in : 1
+	   1723434 t.dp.mu2[0]._y : 0  [by t.in:=1]
+	   1723435 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
+	   1723436 t.dp.mu2[1]._y : 0  [by t.dp._a[1]:=1]
+	   1723597 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
+	   1724634 t.dp.mu2[2]._y : 0  [by t.dp._a[2]:=1]
+	   1724639 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
+	   1725220 t.dp.mu2[3]._y : 0  [by t.dp._a[3]:=1]
+	   1725628 t.out : 1  [by t.dp.mu2[3]._y:=0]
 [] setting low
-	    892253 t.a : 0
-	    896529 t.dp.mu2[0]._y : 1  [by t.a:=0]
-	    899428 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	    903723 t.dp.mu2[1]._y : 1  [by t.dp._a[1]:=0]
-	    903725 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	    908260 t.dp.mu2[2]._y : 1  [by t.dp._a[2]:=0]
-	    909509 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    913008 t.dp.mu2[3]._y : 1  [by t.dp._a[3]:=0]
-	    913174 t.y : 0  [by t.dp.mu2[3]._y:=1]
+	   1725628 t.in : 0
+	   1725639 t.dp.mu2[0]._y : 1  [by t.in:=0]
+	   1726686 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
+	   1726700 t.dp.mu2[1]._y : 1  [by t.dp._a[1]:=0]
+	   1726718 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
+	   1726722 t.dp.mu2[2]._y : 1  [by t.dp._a[2]:=0]
+	   1726826 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
+	   1758270 t.dp.mu2[3]._y : 1  [by t.dp._a[3]:=0]
+	   1759474 t.out : 0  [by t.dp.mu2[3]._y:=1]

test/unit_tests/delayprog_4/run/test.prs

@@ -1,11 +1,6 @@
 = "GND" "GND"
 = "Vdd" "Vdd"
 = "Reset" "Reset"
-= "t.y" "t.dp.y"
-= "t.a" "t.dp.a"
-= "t.dp.a" "t.dp.mu2[0].a"
-= "t.dp.a" "t.dp.and2[0].a"
-= "t.dp.a" "t.dp._a[0]"
 "t.dp.and2[0].a"&"t.dp.and2[0].b"->"t.dp.and2[0]._y"-
 ~("t.dp.and2[0].a"&"t.dp.and2[0].b")->"t.dp.and2[0]._y"+
 "t.dp.and2[0]._y"->"t.dp.and2[0].y"-
@@ -102,72 +97,140 @@
 ~("t.dp.mu2[3]._y")->"t.dp.mu2[3].y"+
 "t.dp.dly[0].a"->"t.dp.dly[0]._y"-
 ~("t.dp.dly[0].a")->"t.dp.dly[0]._y"+
-"t.dp.dly[0]._y"->"t.dp.dly[0].y"-
-~("t.dp.dly[0]._y")->"t.dp.dly[0].y"+
+"t.dp.dly[0]._y"->"t.dp.dly[0].__y"-
+~("t.dp.dly[0]._y")->"t.dp.dly[0].__y"+
+"t.dp.dly[0].__y"->"t.dp.dly[0].___y"-
+~("t.dp.dly[0].__y")->"t.dp.dly[0].___y"+
+"t.dp.dly[0].___y"->"t.dp.dly[0].y"-
+~("t.dp.dly[0].___y")->"t.dp.dly[0].y"+
 "t.dp.dly[1].a"->"t.dp.dly[1]._y"-
 ~("t.dp.dly[1].a")->"t.dp.dly[1]._y"+
-"t.dp.dly[1]._y"->"t.dp.dly[1].y"-
-~("t.dp.dly[1]._y")->"t.dp.dly[1].y"+
+"t.dp.dly[1]._y"->"t.dp.dly[1].__y"-
+~("t.dp.dly[1]._y")->"t.dp.dly[1].__y"+
+"t.dp.dly[1].__y"->"t.dp.dly[1].___y"-
+~("t.dp.dly[1].__y")->"t.dp.dly[1].___y"+
+"t.dp.dly[1].___y"->"t.dp.dly[1].y"-
+~("t.dp.dly[1].___y")->"t.dp.dly[1].y"+
 "t.dp.dly[2].a"->"t.dp.dly[2]._y"-
 ~("t.dp.dly[2].a")->"t.dp.dly[2]._y"+
-"t.dp.dly[2]._y"->"t.dp.dly[2].y"-
-~("t.dp.dly[2]._y")->"t.dp.dly[2].y"+
+"t.dp.dly[2]._y"->"t.dp.dly[2].__y"-
+~("t.dp.dly[2]._y")->"t.dp.dly[2].__y"+
+"t.dp.dly[2].__y"->"t.dp.dly[2].___y"-
+~("t.dp.dly[2].__y")->"t.dp.dly[2].___y"+
+"t.dp.dly[2].___y"->"t.dp.dly[2].y"-
+~("t.dp.dly[2].___y")->"t.dp.dly[2].y"+
 "t.dp.dly[3].a"->"t.dp.dly[3]._y"-
 ~("t.dp.dly[3].a")->"t.dp.dly[3]._y"+
-"t.dp.dly[3]._y"->"t.dp.dly[3].y"-
-~("t.dp.dly[3]._y")->"t.dp.dly[3].y"+
+"t.dp.dly[3]._y"->"t.dp.dly[3].__y"-
+~("t.dp.dly[3]._y")->"t.dp.dly[3].__y"+
+"t.dp.dly[3].__y"->"t.dp.dly[3].___y"-
+~("t.dp.dly[3].__y")->"t.dp.dly[3].___y"+
+"t.dp.dly[3].___y"->"t.dp.dly[3].y"-
+~("t.dp.dly[3].___y")->"t.dp.dly[3].y"+
 "t.dp.dly[4].a"->"t.dp.dly[4]._y"-
 ~("t.dp.dly[4].a")->"t.dp.dly[4]._y"+
-"t.dp.dly[4]._y"->"t.dp.dly[4].y"-
-~("t.dp.dly[4]._y")->"t.dp.dly[4].y"+
+"t.dp.dly[4]._y"->"t.dp.dly[4].__y"-
+~("t.dp.dly[4]._y")->"t.dp.dly[4].__y"+
+"t.dp.dly[4].__y"->"t.dp.dly[4].___y"-
+~("t.dp.dly[4].__y")->"t.dp.dly[4].___y"+
+"t.dp.dly[4].___y"->"t.dp.dly[4].y"-
+~("t.dp.dly[4].___y")->"t.dp.dly[4].y"+
 "t.dp.dly[5].a"->"t.dp.dly[5]._y"-
 ~("t.dp.dly[5].a")->"t.dp.dly[5]._y"+
-"t.dp.dly[5]._y"->"t.dp.dly[5].y"-
-~("t.dp.dly[5]._y")->"t.dp.dly[5].y"+
+"t.dp.dly[5]._y"->"t.dp.dly[5].__y"-
+~("t.dp.dly[5]._y")->"t.dp.dly[5].__y"+
+"t.dp.dly[5].__y"->"t.dp.dly[5].___y"-
+~("t.dp.dly[5].__y")->"t.dp.dly[5].___y"+
+"t.dp.dly[5].___y"->"t.dp.dly[5].y"-
+~("t.dp.dly[5].___y")->"t.dp.dly[5].y"+
 "t.dp.dly[6].a"->"t.dp.dly[6]._y"-
 ~("t.dp.dly[6].a")->"t.dp.dly[6]._y"+
-"t.dp.dly[6]._y"->"t.dp.dly[6].y"-
-~("t.dp.dly[6]._y")->"t.dp.dly[6].y"+
+"t.dp.dly[6]._y"->"t.dp.dly[6].__y"-
+~("t.dp.dly[6]._y")->"t.dp.dly[6].__y"+
+"t.dp.dly[6].__y"->"t.dp.dly[6].___y"-
+~("t.dp.dly[6].__y")->"t.dp.dly[6].___y"+
+"t.dp.dly[6].___y"->"t.dp.dly[6].y"-
+~("t.dp.dly[6].___y")->"t.dp.dly[6].y"+
 "t.dp.dly[7].a"->"t.dp.dly[7]._y"-
 ~("t.dp.dly[7].a")->"t.dp.dly[7]._y"+
-"t.dp.dly[7]._y"->"t.dp.dly[7].y"-
-~("t.dp.dly[7]._y")->"t.dp.dly[7].y"+
+"t.dp.dly[7]._y"->"t.dp.dly[7].__y"-
+~("t.dp.dly[7]._y")->"t.dp.dly[7].__y"+
+"t.dp.dly[7].__y"->"t.dp.dly[7].___y"-
+~("t.dp.dly[7].__y")->"t.dp.dly[7].___y"+
+"t.dp.dly[7].___y"->"t.dp.dly[7].y"-
+~("t.dp.dly[7].___y")->"t.dp.dly[7].y"+
 "t.dp.dly[8].a"->"t.dp.dly[8]._y"-
 ~("t.dp.dly[8].a")->"t.dp.dly[8]._y"+
-"t.dp.dly[8]._y"->"t.dp.dly[8].y"-
-~("t.dp.dly[8]._y")->"t.dp.dly[8].y"+
+"t.dp.dly[8]._y"->"t.dp.dly[8].__y"-
+~("t.dp.dly[8]._y")->"t.dp.dly[8].__y"+
+"t.dp.dly[8].__y"->"t.dp.dly[8].___y"-
+~("t.dp.dly[8].__y")->"t.dp.dly[8].___y"+
+"t.dp.dly[8].___y"->"t.dp.dly[8].y"-
+~("t.dp.dly[8].___y")->"t.dp.dly[8].y"+
 "t.dp.dly[9].a"->"t.dp.dly[9]._y"-
 ~("t.dp.dly[9].a")->"t.dp.dly[9]._y"+
-"t.dp.dly[9]._y"->"t.dp.dly[9].y"-
-~("t.dp.dly[9]._y")->"t.dp.dly[9].y"+
+"t.dp.dly[9]._y"->"t.dp.dly[9].__y"-
+~("t.dp.dly[9]._y")->"t.dp.dly[9].__y"+
+"t.dp.dly[9].__y"->"t.dp.dly[9].___y"-
+~("t.dp.dly[9].__y")->"t.dp.dly[9].___y"+
+"t.dp.dly[9].___y"->"t.dp.dly[9].y"-
+~("t.dp.dly[9].___y")->"t.dp.dly[9].y"+
 "t.dp.dly[10].a"->"t.dp.dly[10]._y"-
 ~("t.dp.dly[10].a")->"t.dp.dly[10]._y"+
-"t.dp.dly[10]._y"->"t.dp.dly[10].y"-
-~("t.dp.dly[10]._y")->"t.dp.dly[10].y"+
+"t.dp.dly[10]._y"->"t.dp.dly[10].__y"-
+~("t.dp.dly[10]._y")->"t.dp.dly[10].__y"+
+"t.dp.dly[10].__y"->"t.dp.dly[10].___y"-
+~("t.dp.dly[10].__y")->"t.dp.dly[10].___y"+
+"t.dp.dly[10].___y"->"t.dp.dly[10].y"-
+~("t.dp.dly[10].___y")->"t.dp.dly[10].y"+
 "t.dp.dly[11].a"->"t.dp.dly[11]._y"-
 ~("t.dp.dly[11].a")->"t.dp.dly[11]._y"+
-"t.dp.dly[11]._y"->"t.dp.dly[11].y"-
-~("t.dp.dly[11]._y")->"t.dp.dly[11].y"+
+"t.dp.dly[11]._y"->"t.dp.dly[11].__y"-
+~("t.dp.dly[11]._y")->"t.dp.dly[11].__y"+
+"t.dp.dly[11].__y"->"t.dp.dly[11].___y"-
+~("t.dp.dly[11].__y")->"t.dp.dly[11].___y"+
+"t.dp.dly[11].___y"->"t.dp.dly[11].y"-
+~("t.dp.dly[11].___y")->"t.dp.dly[11].y"+
 "t.dp.dly[12].a"->"t.dp.dly[12]._y"-
 ~("t.dp.dly[12].a")->"t.dp.dly[12]._y"+
-"t.dp.dly[12]._y"->"t.dp.dly[12].y"-
-~("t.dp.dly[12]._y")->"t.dp.dly[12].y"+
+"t.dp.dly[12]._y"->"t.dp.dly[12].__y"-
+~("t.dp.dly[12]._y")->"t.dp.dly[12].__y"+
+"t.dp.dly[12].__y"->"t.dp.dly[12].___y"-
+~("t.dp.dly[12].__y")->"t.dp.dly[12].___y"+
+"t.dp.dly[12].___y"->"t.dp.dly[12].y"-
+~("t.dp.dly[12].___y")->"t.dp.dly[12].y"+
 "t.dp.dly[13].a"->"t.dp.dly[13]._y"-
 ~("t.dp.dly[13].a")->"t.dp.dly[13]._y"+
-"t.dp.dly[13]._y"->"t.dp.dly[13].y"-
-~("t.dp.dly[13]._y")->"t.dp.dly[13].y"+
+"t.dp.dly[13]._y"->"t.dp.dly[13].__y"-
+~("t.dp.dly[13]._y")->"t.dp.dly[13].__y"+
+"t.dp.dly[13].__y"->"t.dp.dly[13].___y"-
+~("t.dp.dly[13].__y")->"t.dp.dly[13].___y"+
+"t.dp.dly[13].___y"->"t.dp.dly[13].y"-
+~("t.dp.dly[13].___y")->"t.dp.dly[13].y"+
 "t.dp.dly[14].a"->"t.dp.dly[14]._y"-
 ~("t.dp.dly[14].a")->"t.dp.dly[14]._y"+
-"t.dp.dly[14]._y"->"t.dp.dly[14].y"-
-~("t.dp.dly[14]._y")->"t.dp.dly[14].y"+
-= "t.dp.dly[6].y" "t.dp.mu2[3].b"
+"t.dp.dly[14]._y"->"t.dp.dly[14].__y"-
+~("t.dp.dly[14]._y")->"t.dp.dly[14].__y"+
+"t.dp.dly[14].__y"->"t.dp.dly[14].___y"-
+~("t.dp.dly[14].__y")->"t.dp.dly[14].___y"+
+"t.dp.dly[14].___y"->"t.dp.dly[14].y"-
+~("t.dp.dly[14].___y")->"t.dp.dly[14].y"+
+= "t.dp.dly[14].y" "t.dp.mu2[3].b"
+= "t.dp.dly[14].a" "t.dp.dly[13].y"
+= "t.dp.dly[13].a" "t.dp.dly[12].y"
+= "t.dp.dly[12].a" "t.dp.dly[11].y"
+= "t.dp.dly[11].a" "t.dp.dly[10].y"
+= "t.dp.dly[10].a" "t.dp.dly[9].y"
+= "t.dp.dly[9].a" "t.dp.dly[8].y"
+= "t.dp.dly[8].a" "t.dp.dly[7].y"
+= "t.dp.dly[7].a" "t.dp.and2[3].y"
+= "t.dp.dly[6].y" "t.dp.mu2[2].b"
 = "t.dp.dly[6].a" "t.dp.dly[5].y"
 = "t.dp.dly[5].a" "t.dp.dly[4].y"
-= "t.dp.dly[4].a" "t.dp.and2[3].y"
-= "t.dp.dly[3].y" "t.dp.mu2[2].b"
-= "t.dp.dly[3].a" "t.dp.dly[2].y"
-= "t.dp.dly[2].a" "t.dp.and2[2].y"
-= "t.dp.dly[1].y" "t.dp.mu2[1].b"
+= "t.dp.dly[4].a" "t.dp.dly[3].y"
+= "t.dp.dly[3].a" "t.dp.and2[2].y"
+= "t.dp.dly[2].y" "t.dp.mu2[1].b"
+= "t.dp.dly[2].a" "t.dp.dly[1].y"
 = "t.dp.dly[1].a" "t.dp.and2[1].y"
 = "t.dp.dly[0].y" "t.dp.mu2[0].b"
 = "t.dp.dly[0].a" "t.dp.and2[0].y"
@@ -180,10 +243,15 @@
 = "t.dp._a[3]" "t.dp.mu2[3].a"
 = "t.dp._a[3]" "t.dp.and2[3].a"
 = "t.dp._a[3]" "t.dp.mu2[2].y"
-= "t.dp.y" "t.dp.mu2[3].y"
-= "t.dp.y" "t.dp._a[4]"
+= "t.dp.out" "t.dp.mu2[3].y"
+= "t.dp.out" "t.dp._a[4]"
+= "t.dp.in" "t.dp.mu2[0].a"
+= "t.dp.in" "t.dp.and2[0].a"
+= "t.dp.in" "t.dp._a[0]"
 = "Vdd" "t.dp.supply.vdd"
 = "GND" "t.dp.supply.vss"
+= "t.out" "t.dp.out"
+= "t.in" "t.dp.in"
 = "t.s[0]" "t.dp.s[0]"
 = "t.s[1]" "t.dp.s[1]"
 = "t.s[2]" "t.dp.s[2]"

test/unit_tests/delayprog_4/test.act

@@ -31,8 +31,8 @@ import globals;
 
 open tmpl::dataflow_neuro;
 
-defproc delayprog_4 (bool? s[4], a; bool! y){
-    delayprog<4> dp(.a=a, .y=y, .s = s);
+defproc delayprog_4 (bool? s[4], in; bool! out){
+    delayprog<4> dp(.in=in, .out=out, .s = s);
     dp.supply.vss = GND;
     dp.supply.vdd = Vdd;
 

test/unit_tests/delayprog_4/test.prsim

@@ -2,7 +2,7 @@ watchall
 
 system "echo '0'"
 
-set t.a  0
+set t.in  0
 set t.s[0] 1
 set t.s[1] 1
 set t.s[2] 1
@@ -11,17 +11,17 @@ set t.s[3] 1
 cycle
 mode run
 
-assert t.y 0
+# assert t.out 0
 
 system "echo '[] setting high'"
-set t.a  1
+set t.in  1
 cycle
-assert t.y 1
+assert t.out 1
 
 system "echo '[] setting low'"
-set t.a  0
+set t.in  0
 cycle
-assert t.y 0
+assert t.out 0
 
 system "echo '[] setting configs low'"
 set t.s[0] 0
@@ -29,14 +29,14 @@ set t.s[1] 0
 set t.s[2] 0
 set t.s[3] 0
 cycle
-assert t.y 0
+assert t.out 0
 
 system "echo '[] setting high'"
-set t.a  1
+set t.in  1
 cycle
-assert t.y 1
+assert t.out 1
 
 system "echo '[] setting low'"
-set t.a  0
+set t.in  0
 cycle
-assert t.y 0
+assert t.out 0

test/unit_tests/demux_7/run/prsim.out

@@ -1,4 +1,4 @@
-my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.tmp[9] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux.vc.tmp[7] my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.C2Els[1]._y my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.tmp[6] my_demux.my_demux.vc.tmp[1] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.C2Els[0]._y my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux.vc.tmp[8] my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_c_v_ my_demux.out2.v my_demux.my_demux._in_v my_demux.my_demux.vc.tmp[4] my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.tmp[0] my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.my_demux.vc.tmp[5] my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux._out_v my_demux.my_demux.vc.C3Els[0]._y my_demux.in.v my_demux.my_demux.vc.C3Els[1]._y my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.tmp[3] my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.vc.tmp[2] my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y 
+my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.cond.v my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.ct.in[4] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.vc.ct.tmp[9] my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.ct.tmp[8] my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.ct.in[5] my_demux.my_demux.vc.ct.in[1] my_demux.my_demux.vc.ct.in[6] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.ct.in[2] my_demux.my_demux.vc.ct.tmp[7] my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_v my_demux.my_demux.vc.ct.C3Els[0]._y my_demux.my_demux.vc.ct.in[0] my_demux.out2.v my_demux.my_demux.vc.ct.C3Els[1]._y my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.ct.C2Els[0]._y my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux.vc.ct.in[3] my_demux.my_demux._out_v my_demux.in.v my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.ct.C2Els[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y 
 	    119199 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
 	    119199 my_demux.my_demux.c_buf_f.in : 0
 	    119199 my_demux.my_demux.c_buf_t.in : 0
@@ -26,7 +26,7 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
 	    119286 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
 	    119311 my_demux.my_demux._out1_a_B : 1  [by my_demux.out1.a:=0]
 	    119333 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    119378 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
+	    119378 my_demux.my_demux.vc.ct.in[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
 	    119403 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
 	    119456 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_f_buf_func[6].n1:=0]
 	    119493 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_f_buf_func[2].n1:=0]
@@ -36,35 +36,35 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
 	    119757 my_demux.my_demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux._en:=1]
 	    119790 my_demux.my_demux._c_f_buf[0] : 0  [by my_demux.my_demux.c_buf_f.buf2._y:=1]
 	    119848 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf2._y:=0]
-	    119852 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
+	    119852 my_demux.my_demux.vc.ct.in[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
 	    119938 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.c_buf_t.in:=0]
 	    120039 my_demux.my_demux._c_t_buf[0] : 0  [by my_demux.my_demux.c_buf_t.buf2._y:=1]
 	    120158 my_demux.my_demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
 	    120165 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
 	    120408 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
 	    121005 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    121111 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
+	    121111 my_demux.my_demux.vc.ct.in[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
 	    121206 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
-	    121284 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
-	    121481 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    121756 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[0]:=0]
+	    121284 my_demux.my_demux.vc.ct.in[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
+	    121481 my_demux.my_demux.vc.ct.in[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
+	    121756 my_demux.my_demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[0]:=0]
 	    122127 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    123195 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
-	    123650 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[3]:=0]
-	    123662 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
+	    123195 my_demux.my_demux.vc.ct.in[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
+	    123650 my_demux.my_demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.vc.ct.in[3]:=0]
+	    123662 my_demux.my_demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
 	    126256 my_demux.my_demux._en2_X_t[0] : 1  [by my_demux.my_demux.out2_en_buf_t.buf2._y:=0]
 	    133652 my_demux.my_demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux._en:=1]
 	    134056 my_demux.my_demux._en2_X_f[0] : 1  [by my_demux.my_demux.out2_en_buf_f.buf2._y:=0]
-	    135118 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    135130 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
-	    140752 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    141046 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    145322 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[9]:=0]
-	    148221 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
+	    135118 my_demux.my_demux.vc.ct.in[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
+	    135130 my_demux.my_demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[6]:=0]
+	    140752 my_demux.my_demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
+	    141046 my_demux.my_demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
+	    145322 my_demux.my_demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.vc.ct.tmp[9]:=0]
+	    148221 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
 	    148223 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._in_v:=0]
 	    149461 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
 	    152516 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    152758 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
+	    152758 my_demux.cond.v : 0  [by my_demux.my_demux.c_el._y:=1]
 	    153765 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
 	    166711 my_demux.my_demux._out2_a_B : 1  [by my_demux.out2.a:=0]
 	    166877 my_demux.my_demux.out2_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out2_a_B:=1]
@@ -94,7 +94,7 @@ Output neutral checked
 	    226364 my_demux.my_demux.vc.OR2_tf[4]._y : 0  [by my_demux.my_demux.out1_t_buf_func[4].n1:=1]
 	    226415 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
 	    226718 my_demux.my_demux.vc.OR2_tf[6]._y : 0  [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
-	    226720 my_demux.my_demux.vc.tmp[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
+	    226720 my_demux.my_demux.vc.ct.in[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
 	    226876 my_demux.my_demux.vc.OR2_tf[3]._y : 0  [by my_demux.my_demux.out1_t_buf_func[3].n1:=1]
 	    226896 my_demux.my_demux.c_buf_t.buf2._y : 0  [by my_demux.my_demux.c_buf_t.in:=1]
 	    226899 my_demux.my_demux._c_t_buf[0] : 1  [by my_demux.my_demux.c_buf_t.buf2._y:=0]
@@ -109,30 +109,30 @@ Output neutral checked
 	    228500 my_demux.my_demux.out1_t_buf_func[2]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
 	    228783 my_demux.my_demux.vc.OR2_tf[2]._y : 0  [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
 	    228989 my_demux.my_demux.vc.OR2_tf[5]._y : 0  [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
-	    229148 my_demux.my_demux.vc.tmp[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
+	    229148 my_demux.my_demux.vc.ct.in[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
 	    229660 my_demux.my_demux.out1_t_buf_func[5]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
 	    230081 my_demux.my_demux.out1_t_buf_func[2].y : 1  [by my_demux.my_demux.out1_t_buf_func[2]._y:=0]
 	    230910 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    232197 my_demux.my_demux.vc.tmp[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    238128 my_demux.my_demux.vc.tmp[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
-	    239456 my_demux.my_demux.vc.tmp[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
+	    232197 my_demux.my_demux.vc.ct.in[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
+	    238128 my_demux.my_demux.vc.ct.in[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
+	    239456 my_demux.my_demux.vc.ct.in[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
 	    240582 my_demux.my_demux.out1_t_buf_func[6]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
 	    240727 my_demux.my_demux.out1_t_buf_func[6].y : 1  [by my_demux.my_demux.out1_t_buf_func[6]._y:=0]
-	    241688 my_demux.my_demux.vc.C2Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[1]:=1]
-	    244520 my_demux.my_demux.vc.tmp[7] : 1  [by my_demux.my_demux.vc.C2Els[0]._y:=0]
+	    241688 my_demux.my_demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[1]:=1]
+	    244520 my_demux.my_demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
 	    249336 my_demux.my_demux.out1_t_buf_func[5].y : 1  [by my_demux.my_demux.out1_t_buf_func[5]._y:=0]
-	    250289 my_demux.my_demux.vc.tmp[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
+	    250289 my_demux.my_demux.vc.ct.in[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
 	    253239 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    256643 my_demux.my_demux.vc.C3Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[4]:=1]
-	    256644 my_demux.my_demux.vc.tmp[9] : 1  [by my_demux.my_demux.vc.C3Els[0]._y:=0]
-	    287834 my_demux.my_demux.vc.tmp[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
-	    327118 my_demux.my_demux.vc.C2Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[3]:=1]
-	    327280 my_demux.my_demux.vc.tmp[8] : 1  [by my_demux.my_demux.vc.C2Els[1]._y:=0]
-	    334649 my_demux.my_demux.vc.C3Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[8]:=1]
-	    334663 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.C3Els[1]._y:=0]
+	    256643 my_demux.my_demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[4]:=1]
+	    256644 my_demux.my_demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
+	    287834 my_demux.my_demux.vc.ct.in[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
+	    327118 my_demux.my_demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.vc.ct.in[3]:=1]
+	    327280 my_demux.my_demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
+	    334649 my_demux.my_demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.vc.ct.tmp[8]:=1]
+	    334663 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
 	    334670 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
 	    334823 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    334824 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
+	    334824 my_demux.cond.v : 1  [by my_demux.my_demux.c_el._y:=0]
 	    356227 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
 	    356227 my_demux.out1.v : 1
 	    356228 my_demux.my_demux.out_or._y : 0  [by my_demux.out1.v:=1]
@@ -158,25 +158,25 @@ Output neutral checked
 	    393460 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_t_buf_func[4].n1:=0]
 	    393462 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
 	    393501 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
-	    393596 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
+	    393596 my_demux.my_demux.vc.ct.in[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
 	    394400 my_demux.my_demux.vc.OR2_tf[5]._y : 1  [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
-	    394735 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
+	    394735 my_demux.my_demux.vc.ct.in[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
 	    396032 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    396040 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    396277 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
+	    396040 my_demux.my_demux.vc.ct.in[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
+	    396277 my_demux.my_demux.vc.ct.in[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
 	    401820 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
-	    401854 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    407195 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
-	    408113 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[2]:=0]
-	    408117 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
-	    415741 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
+	    401854 my_demux.my_demux.vc.ct.in[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
+	    407195 my_demux.my_demux.vc.ct.in[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
+	    408113 my_demux.my_demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.vc.ct.in[2]:=0]
+	    408117 my_demux.my_demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
+	    415741 my_demux.my_demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[6]:=0]
 	    452421 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    454819 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    458034 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[1]:=0]
-	    462119 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    505153 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    505201 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[7]:=0]
-	    505204 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
+	    454819 my_demux.my_demux.vc.ct.in[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
+	    458034 my_demux.my_demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[1]:=0]
+	    462119 my_demux.my_demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
+	    505153 my_demux.my_demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
+	    505201 my_demux.my_demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.vc.ct.tmp[7]:=0]
+	    505204 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
 	    505382 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
 	    526359 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
 First Cond Checked
@@ -214,7 +214,7 @@ Output neutral checked
 	    585101 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
 	    585114 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._c_v:=0]
 	    586919 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
-	    602098 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
+	    602098 my_demux.cond.v : 0  [by my_demux.my_demux.c_el._y:=1]
 	    606729 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
 	    607086 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
 	    628359 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
@@ -241,46 +241,46 @@ Output neutral checked
 	    639106 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_f_buf_func[1].n1:=1]
 	    639116 my_demux.my_demux.c_buf_f.buf2._y : 0  [by my_demux.my_demux.c_buf_f.in:=1]
 	    639120 my_demux.my_demux.vc.OR2_tf[6]._y : 0  [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
-	    639190 my_demux.my_demux.vc.tmp[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
+	    639190 my_demux.my_demux.vc.ct.in[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
 	    639206 my_demux.my_demux.vc.OR2_tf[5]._y : 0  [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
 	    639330 my_demux.my_demux.vc.OR2_tf[2]._y : 0  [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
-	    639341 my_demux.my_demux.vc.tmp[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
-	    639949 my_demux.my_demux.vc.tmp[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
+	    639341 my_demux.my_demux.vc.ct.in[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
+	    639949 my_demux.my_demux.vc.ct.in[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
 	    640149 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.c_buf_f.in:=1]
 	    640152 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
 	    640306 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_f_buf_func[0].n1:=1]
-	    640360 my_demux.my_demux.vc.tmp[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
+	    640360 my_demux.my_demux.vc.ct.in[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
 	    640575 my_demux.my_demux._c_f_buf[0] : 1  [by my_demux.my_demux.c_buf_f.buf2._y:=0]
 	    640656 my_demux.my_demux.out2_t_buf_func[6]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    640667 my_demux.my_demux.out2_f_buf_func[3]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    641280 my_demux.my_demux.out2_f_buf_func[3].y : 1  [by my_demux.my_demux.out2_f_buf_func[3]._y:=0]
-	    641508 my_demux.my_demux.vc.C2Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[0]:=1]
+	    641508 my_demux.my_demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[0]:=1]
 	    641736 my_demux.my_demux.out2_t_buf_func[2]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    641781 my_demux.my_demux.out2_t_buf_func[2].y : 1  [by my_demux.my_demux.out2_t_buf_func[2]._y:=0]
 	    642400 my_demux.my_demux.out2_t_buf_func[6].y : 1  [by my_demux.my_demux.out2_t_buf_func[6]._y:=0]
 	    647557 my_demux.my_demux.vc.OR2_tf[3]._y : 0  [by my_demux.my_demux.out1_f_buf_func[3].n1:=1]
-	    648554 my_demux.my_demux.vc.tmp[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
+	    648554 my_demux.my_demux.vc.ct.in[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
 	    648886 my_demux.my_demux.out2_f_buf_func[4]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    649227 my_demux.my_demux.out2_t_buf_func[5]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    649411 my_demux.my_demux.out2_f_buf_func[4].y : 1  [by my_demux.my_demux.out2_f_buf_func[4]._y:=0]
 	    650127 my_demux.my_demux.out2_t_buf_func[5].y : 1  [by my_demux.my_demux.out2_t_buf_func[5]._y:=0]
-	    650203 my_demux.my_demux.vc.C2Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[3]:=1]
-	    650255 my_demux.my_demux.vc.tmp[8] : 1  [by my_demux.my_demux.vc.C2Els[1]._y:=0]
+	    650203 my_demux.my_demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.vc.ct.in[3]:=1]
+	    650255 my_demux.my_demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
 	    651652 my_demux.my_demux.out2_f_buf_func[0]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    651659 my_demux.my_demux.out2_f_buf_func[0].y : 1  [by my_demux.my_demux.out2_f_buf_func[0]._y:=0]
-	    655530 my_demux.my_demux.vc.tmp[7] : 1  [by my_demux.my_demux.vc.C2Els[0]._y:=0]
+	    655530 my_demux.my_demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
 	    658558 my_demux.my_demux.out2_f_buf_func[1]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    670546 my_demux.my_demux.vc.OR2_tf[4]._y : 0  [by my_demux.my_demux.out1_f_buf_func[4].n1:=1]
 	    674170 my_demux.my_demux.out2_f_buf_func[1].y : 1  [by my_demux.my_demux.out2_f_buf_func[1]._y:=0]
-	    677013 my_demux.my_demux.vc.tmp[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
-	    689628 my_demux.my_demux.vc.tmp[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
-	    689630 my_demux.my_demux.vc.C3Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[5]:=1]
-	    689984 my_demux.my_demux.vc.tmp[9] : 1  [by my_demux.my_demux.vc.C3Els[0]._y:=0]
-	    690117 my_demux.my_demux.vc.C3Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[9]:=1]
-	    690118 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.C3Els[1]._y:=0]
+	    677013 my_demux.my_demux.vc.ct.in[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
+	    689628 my_demux.my_demux.vc.ct.in[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
+	    689630 my_demux.my_demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[5]:=1]
+	    689984 my_demux.my_demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
+	    690117 my_demux.my_demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.vc.ct.tmp[9]:=1]
+	    690118 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
 	    690122 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
 	    690664 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    690665 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
+	    690665 my_demux.cond.v : 1  [by my_demux.my_demux.c_el._y:=0]
 	    735685 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
 	    735685 my_demux.out2.v : 1
 	    748063 my_demux.my_demux.out_or._y : 0  [by my_demux.out2.v:=1]
@@ -305,26 +305,26 @@ Output neutral checked
 	    817979 my_demux.my_demux.out1_f_buf_func[3].n1 : 0
 	    817982 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_f_buf_func[3].n1:=0]
 	    817991 my_demux.my_demux.vc.OR2_tf[5]._y : 1  [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
-	    817992 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
-	    818020 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
+	    817992 my_demux.my_demux.vc.ct.in[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
+	    818020 my_demux.my_demux.vc.ct.in[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
 	    818022 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
 	    818106 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_f_buf_func[0].n1:=0]
 	    818148 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
-	    818198 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
+	    818198 my_demux.my_demux.vc.ct.in[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
 	    818212 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
-	    818214 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
+	    818214 my_demux.my_demux.vc.ct.in[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
 	    819258 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_f_buf_func[1].n1:=0]
-	    819259 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    820760 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[1]:=0]
-	    820762 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    820875 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    820893 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
-	    821012 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    830774 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
-	    836494 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[2]:=0]
-	    836502 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
-	    836556 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[8]:=0]
-	    887094 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
+	    819259 my_demux.my_demux.vc.ct.in[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
+	    820760 my_demux.my_demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[1]:=0]
+	    820762 my_demux.my_demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
+	    820875 my_demux.my_demux.vc.ct.in[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
+	    820893 my_demux.my_demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[6]:=0]
+	    821012 my_demux.my_demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
+	    830774 my_demux.my_demux.vc.ct.in[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
+	    836494 my_demux.my_demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.vc.ct.in[2]:=0]
+	    836502 my_demux.my_demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
+	    836556 my_demux.my_demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.vc.ct.tmp[8]:=0]
+	    887094 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
 	    887099 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
 	    888166 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
 Second Cond Checked

test/unit_tests/demux_7/run/test.prs

@@ -330,6 +330,7 @@
 = "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.vc.in.d[6].d[0]"
 = "my_demux.my_demux.in.d.d[6].d[1]" "my_demux.my_demux.vc.in.d[6].d[1]"
 = "my_demux.my_demux.in.a" "my_demux.my_demux.en_ctl.c1"
+= "my_demux.my_demux.in.a" "my_demux.my_demux.cond.a"
 = "my_demux.my_demux.in.a" "my_demux.my_demux.inack_ctl.y"
 = "my_demux.my_demux.in.v" "my_demux.my_demux.in_v_buf.y"
 = "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.out2_f_buf_func[6].n1"
@@ -426,8 +427,6 @@
 ~("my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b")->"my_demux.my_demux.out_or._y"+
 "my_demux.my_demux.out_or._y"->"my_demux.my_demux.out_or.y"-
 ~("my_demux.my_demux.out_or._y")->"my_demux.my_demux.out_or.y"+
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.c_el.y"
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.inack_ctl.c2"
 = "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_a_B_buf_f.out[0]"
 = "my_demux.my_demux._out1_a_BX_t[1]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
 = "my_demux.my_demux._out1_a_BX_t[2]" "my_demux.my_demux.out1_a_B_buf_f.out[2]"
@@ -854,12 +853,20 @@
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_f.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out2_en_buf_t.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_t.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_f.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_f.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_t.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_t.supply.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[6].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_f_buf_func[6].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[5].vdd"
@@ -930,22 +937,59 @@
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.en_ctl.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.inack_ctl.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
-~"my_demux.my_demux.vc.C2Els[0].c1"&~"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"+
-"my_demux.my_demux.vc.C2Els[0].c1"&"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"-
-"my_demux.my_demux.vc.C2Els[0]._y"->"my_demux.my_demux.vc.C2Els[0].y"-
-~("my_demux.my_demux.vc.C2Els[0]._y")->"my_demux.my_demux.vc.C2Els[0].y"+
-~"my_demux.my_demux.vc.C2Els[1].c1"&~"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"+
-"my_demux.my_demux.vc.C2Els[1].c1"&"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"-
-"my_demux.my_demux.vc.C2Els[1]._y"->"my_demux.my_demux.vc.C2Els[1].y"-
-~("my_demux.my_demux.vc.C2Els[1]._y")->"my_demux.my_demux.vc.C2Els[1].y"+
-~"my_demux.my_demux.vc.C3Els[0].c1"&~"my_demux.my_demux.vc.C3Els[0].c2"&~"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"+
-"my_demux.my_demux.vc.C3Els[0].c1"&"my_demux.my_demux.vc.C3Els[0].c2"&"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"-
-"my_demux.my_demux.vc.C3Els[0]._y"->"my_demux.my_demux.vc.C3Els[0].y"-
-~("my_demux.my_demux.vc.C3Els[0]._y")->"my_demux.my_demux.vc.C3Els[0].y"+
-~"my_demux.my_demux.vc.C3Els[1].c1"&~"my_demux.my_demux.vc.C3Els[1].c2"&~"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"+
-"my_demux.my_demux.vc.C3Els[1].c1"&"my_demux.my_demux.vc.C3Els[1].c2"&"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"-
-"my_demux.my_demux.vc.C3Els[1]._y"->"my_demux.my_demux.vc.C3Els[1].y"-
-~("my_demux.my_demux.vc.C3Els[1]._y")->"my_demux.my_demux.vc.C3Els[1].y"+
+~"my_demux.my_demux.vc.ct.C2Els[0].c1"&~"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"+
+"my_demux.my_demux.vc.ct.C2Els[0].c1"&"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"-
+"my_demux.my_demux.vc.ct.C2Els[0]._y"->"my_demux.my_demux.vc.ct.C2Els[0].y"-
+~("my_demux.my_demux.vc.ct.C2Els[0]._y")->"my_demux.my_demux.vc.ct.C2Els[0].y"+
+~"my_demux.my_demux.vc.ct.C2Els[1].c1"&~"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"+
+"my_demux.my_demux.vc.ct.C2Els[1].c1"&"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"-
+"my_demux.my_demux.vc.ct.C2Els[1]._y"->"my_demux.my_demux.vc.ct.C2Els[1].y"-
+~("my_demux.my_demux.vc.ct.C2Els[1]._y")->"my_demux.my_demux.vc.ct.C2Els[1].y"+
+~"my_demux.my_demux.vc.ct.C3Els[0].c1"&~"my_demux.my_demux.vc.ct.C3Els[0].c2"&~"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"+
+"my_demux.my_demux.vc.ct.C3Els[0].c1"&"my_demux.my_demux.vc.ct.C3Els[0].c2"&"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"-
+"my_demux.my_demux.vc.ct.C3Els[0]._y"->"my_demux.my_demux.vc.ct.C3Els[0].y"-
+~("my_demux.my_demux.vc.ct.C3Els[0]._y")->"my_demux.my_demux.vc.ct.C3Els[0].y"+
+~"my_demux.my_demux.vc.ct.C3Els[1].c1"&~"my_demux.my_demux.vc.ct.C3Els[1].c2"&~"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"+
+"my_demux.my_demux.vc.ct.C3Els[1].c1"&"my_demux.my_demux.vc.ct.C3Els[1].c2"&"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"-
+"my_demux.my_demux.vc.ct.C3Els[1]._y"->"my_demux.my_demux.vc.ct.C3Els[1].y"-
+~("my_demux.my_demux.vc.ct.C3Els[1]._y")->"my_demux.my_demux.vc.ct.C3Els[1].y"+
+= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C3Els[1].c1"
+= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C2Els[0].y"
+= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C3Els[1].c2"
+= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C2Els[1].y"
+= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[1].c3"
+= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[0].y"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[1].vdd"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[0].vdd"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[1].vdd"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[0].vdd"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[1].vss"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[0].vss"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[1].vss"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[0].vss"
+= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.C2Els[0].c1"
+= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.tmp[0]"
+= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.C2Els[0].c2"
+= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.tmp[1]"
+= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.C2Els[1].c1"
+= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.tmp[2]"
+= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.C2Els[1].c2"
+= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.tmp[3]"
+= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.C3Els[0].c1"
+= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.tmp[4]"
+= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.C3Els[0].c2"
+= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.tmp[5]"
+= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.C3Els[0].c3"
+= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.tmp[6]"
+= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.C3Els[1].y"
+= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.tmp[10]"
+= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
+= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
+= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
+= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
+= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
+= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
+= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
 "my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
 ~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
 "my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
@@ -974,30 +1018,8 @@
 ~("my_demux.my_demux.vc.OR2_tf[6].a"|"my_demux.my_demux.vc.OR2_tf[6].b")->"my_demux.my_demux.vc.OR2_tf[6]._y"+
 "my_demux.my_demux.vc.OR2_tf[6]._y"->"my_demux.my_demux.vc.OR2_tf[6].y"-
 ~("my_demux.my_demux.vc.OR2_tf[6]._y")->"my_demux.my_demux.vc.OR2_tf[6].y"+
-= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.C2Els[0].c1"
-= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
-= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.C2Els[0].c2"
-= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
-= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.C2Els[1].c1"
-= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
-= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.C2Els[1].c2"
-= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
-= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.C3Els[0].c1"
-= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
-= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.C3Els[0].c2"
-= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
-= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.C3Els[0].c3"
-= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
-= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C3Els[1].c1"
-= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C2Els[0].y"
-= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C3Els[1].c2"
-= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C2Els[1].y"
-= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[1].c3"
-= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[0].y"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[1].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[0].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[1].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[0].vdd"
+= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.ct.supply.vss"
+= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.ct.supply.vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[6].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[5].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[4].vdd"
@@ -1005,10 +1027,6 @@
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[2].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[1].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[0].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[1].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[0].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[6].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[5].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[4].vss"
@@ -1016,6 +1034,7 @@
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[2].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
+= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.ct.out"
 = "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
 = "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
 = "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
@@ -1072,8 +1091,6 @@
 = "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
 = "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.OR2_tf[0].a"
 = "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.C3Els[1].y"
-= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.tmp[10]"
 "my_demux.my_demux.out2_a_B_buf_f.buf2.a"->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"-
 ~("my_demux.my_demux.out2_a_B_buf_f.buf2.a")->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"+
 "my_demux.my_demux.out2_a_B_buf_f.buf2._y"->"my_demux.my_demux.out2_a_B_buf_f.buf2.y"-
@@ -1110,6 +1127,9 @@
 = "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
 = "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
+= "my_demux.my_demux.cond.v" "my_demux.my_demux.c_el.y"
+= "my_demux.my_demux.cond.v" "my_demux.my_demux.inack_ctl.c2"
+= "my_demux.my_demux.cond.v" "my_demux.my_demux._in_c_v_"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_f_c_t_or.b"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_buf_f.in"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
@@ -1386,6 +1406,7 @@
 = "my_demux.in.d.d[6].t" "my_demux.my_demux.in.d.d[6].t"
 = "my_demux.in.d.d[6].d[0]" "my_demux.my_demux.in.d.d[6].d[0]"
 = "my_demux.in.d.d[6].d[1]" "my_demux.my_demux.in.d.d[6].d[1]"
+= "my_demux.in.a" "my_demux.cond.a"
 = "my_demux.in.d.d[6].d[0]" "my_demux.in.d.d[6].f"
 = "my_demux.in.d.d[6].d[1]" "my_demux.in.d.d[6].t"
 = "my_demux.in.d.d[5].d[0]" "my_demux.in.d.d[5].f"

test/unit_tests/demux_7/test.prsim

@@ -18,6 +18,7 @@ mode run
 assert-qdi-channel-neutral "my_demux.out1" 7
 assert-qdi-channel-neutral "my_demux.out2" 7
 assert-qdi-channel-neutral "my_demux.in" 7
+assert my_demux.cond.v 0
 cycle
 
 system "echo 'Output neutral checked'"
@@ -28,6 +29,7 @@ set-qdi-channel-valid "my_demux.in" 7 127
 cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
+assert my_demux.cond.v 1
 
 assert-qdi-channel-valid "my_demux.out1" 7 127
 set my_demux.out1.v 1
@@ -68,6 +70,7 @@ set-qdi-channel-valid "my_demux.in" 7 100
 cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
+assert my_demux.cond.v 1
 
 assert-qdi-channel-valid "my_demux.out2" 7 100
 set my_demux.out2.v 1

test/unit_tests/demux_bit_7/run/prsim.out

@@ -0,0 +1,336 @@
+my_demux.in.d.d[5].t my_demux.my_demux.demux._en2_X_t[0] my_demux.in.d.d[2].f my_demux.my_demux.demux._out1_a_BX_f[0] my_demux.my_demux.demux._out2_a_BX_t[0] my_demux.in.d.d[5].f my_demux.my_demux.demux._out1_a_B my_demux.my_demux.demux._en1_X_t[0] my_demux.my_demux.demux._out_v my_demux.in.d.d[1].f my_demux.my_demux.demux._out2_a_BX_f[0] my_demux.my_demux.demux._en1_X_f[0] my_demux.in.d.d[6].f my_demux.in.d.d[2].t my_demux.my_demux.demux.vc.OR2_tf[2]._y my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y my_demux.in.d.d[0].f my_demux.my_demux.demux._c_f_buf[0] my_demux.my_demux.demux.vc.ct.in[1] my_demux.my_demux.demux._out1_a_BX_t[0] my_demux.my_demux.demux._c_t_buf[0] my_demux.out1.a my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[8] my_demux.in.d.d[4].f my_demux.in.d.d[4].t my_demux.my_demux.demux._in_c_v_ my_demux.my_demux.demux.out_or._y my_demux.my_demux.demux._c_v my_demux.my_demux.demux._en2_X_f[0] my_demux.my_demux.demux.vc.ct.in[6] my_demux.in.d.d[6].t my_demux.in.d.d[1].t my_demux.in.d.d[0].t my_demux.my_demux.demux._out2_a_B my_demux.in.d.d[3].f my_demux.out2.a my_demux.in.v my_demux.my_demux.demux.vc.OR2_tf[1]._y my_demux.my_demux.demux.vc.ct.C3Els[0]._y my_demux.my_demux.demux.vc.ct.C2Els[1]._y my_demux.my_demux.demux._en my_demux.in.d.d[3].t my_demux.my_demux.demux.vc.ct.tmp[9] my_demux.my_demux.demux.vc.ct.in[5] my_demux.my_demux.demux.vc.ct.in[4] my_demux.my_demux.demux.vc.ct.in[2] my_demux.out2.v my_demux.my_demux.demux.vc.ct.C3Els[1]._y my_demux.my_demux.demux.vc.ct.C2Els[0]._y my_demux.my_demux.demux.vc.OR2_tf[0]._y my_demux.my_demux.demux.vc.ct.in[3] my_demux.my_demux.demux.c_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[7] my_demux.my_demux.demux.vc.OR2_tf[6]._y my_demux.my_demux.demux.vc.ct.in[0] my_demux.my_demux.demux._in_v my_demux.my_demux.demux.c_buf_t.buf2._y my_demux.out1.v my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.demux.vc.OR2_tf[5]._y my_demux.my_demux.demux.c_el._y my_demux.my_demux.demux.out2_en_buf_t.buf2._y my_demux.my_demux.demux.in_v_buf._y my_demux.my_demux.demux.vc.OR2_tf[4]._y my_demux.my_demux.demux.c_f_c_t_or._y my_demux.my_demux.demux.out1_en_buf_f.buf2._y my_demux.my_demux.demux.out2_en_buf_f.buf2._y my_demux.my_demux.demux.out1_en_buf_t.buf2._y my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.OR2_tf[3]._y 
+	    119199 my_demux.in.d.d[0].f : 0
+	    119199 my_demux.in.d.d[0].t : 0
+	    119199 my_demux.in.d.d[1].f : 0
+	    119199 my_demux.in.d.d[3].f : 0
+	    119199 my_demux.in.d.d[7].f : 0
+	    119199 my_demux.in.d.d[6].t : 0
+	    119199 my_demux.out2.v : 0
+	    119199 my_demux.out2.a : 0
+	    119199 my_demux.out1.v : 0
+	    119199 my_demux.in.d.d[2].t : 0
+	    119199 my_demux.in.d.d[6].f : 0
+	    119199 my_demux.out1.a : 0
+	    119199 my_demux.in.d.d[5].t : 0
+	    119199 my_demux.in.d.d[7].t : 0
+	    119199 my_demux.in.d.d[2].f : 0
+	    119199 my_demux.in.d.d[5].f : 0
+	    119199 my_demux.in.d.d[4].t : 0
+	    119199 my_demux.in.d.d[1].t : 0
+	    119199 my_demux.in.d.d[4].f : 0
+	    119199 my_demux.in.d.d[3].t : 0
+	    119200 my_demux.my_demux.demux.c_buf_f.buf2._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    119200 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1  [by my_demux.in.d.d[5].f:=0]
+	    119236 my_demux.my_demux.demux.c_buf_t.buf2._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    119239 my_demux.my_demux.demux.out_or._y : 1  [by my_demux.out1.v:=0]
+	    119286 my_demux.my_demux.demux._out1_a_B : 1  [by my_demux.out1.a:=0]
+	    119308 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    119311 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    119378 my_demux.my_demux.demux.vc.ct.in[5] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
+	    119403 my_demux.my_demux.demux._out_v : 0  [by my_demux.my_demux.demux.out_or._y:=1]
+	    119456 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1  [by my_demux.in.d.d[6].f:=0]
+	    119493 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1  [by my_demux.in.d.d[2].f:=0]
+	    119536 my_demux.my_demux.demux._en : 1  [by my_demux.my_demux.demux._out_v:=0]
+	    119543 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    119566 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    119757 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    119790 my_demux.my_demux.demux._c_f_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
+	    119848 my_demux.my_demux.demux._en1_X_t[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
+	    119852 my_demux.my_demux.demux.vc.ct.in[2] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
+	    119938 my_demux.my_demux.demux.c_f_c_t_or._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    120039 my_demux.my_demux.demux._c_t_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
+	    120155 my_demux.my_demux.demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
+	    120408 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1  [by my_demux.in.d.d[3].t:=0]
+	    120415 my_demux.my_demux.demux.vc.ct.in[3] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
+	    121005 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1  [by my_demux.in.d.d[1].t:=0]
+	    121111 my_demux.my_demux.demux.vc.ct.in[1] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
+	    121206 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1  [by my_demux.in.d.d[4].f:=0]
+	    121284 my_demux.my_demux.demux.vc.ct.in[4] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
+	    121481 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    121756 my_demux.my_demux.demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
+	    122127 my_demux.my_demux.demux._c_v : 0  [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
+	    123202 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
+	    126256 my_demux.my_demux.demux._en2_X_t[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
+	    133652 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    134107 my_demux.my_demux.demux._en2_X_f[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
+	    135118 my_demux.my_demux.demux.vc.ct.in[6] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
+	    135130 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
+	    135534 my_demux.my_demux.demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
+	    142198 my_demux.my_demux.demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
+	    149439 my_demux.my_demux.demux.vc.ct.in[0] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
+	    149451 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
+	    155367 my_demux.my_demux.demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
+	    159643 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.tmp[7]:=0]
+	    162542 my_demux.my_demux.demux._in_v : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
+	    162544 my_demux.my_demux.demux.c_el._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    166711 my_demux.my_demux.demux._out2_a_B : 1  [by my_demux.out2.a:=0]
+	    166837 my_demux.my_demux.demux.in_v_buf._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    167003 my_demux.in.v : 0  [by my_demux.my_demux.demux.in_v_buf._y:=1]
+	    167079 my_demux.my_demux.demux._in_c_v_ : 0  [by my_demux.my_demux.demux.c_el._y:=1]
+	    167960 my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._out2_a_B:=1]
+	    168035 my_demux.my_demux.demux._out2_a_BX_f[0] : 1  [by my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y:=0]
+	    170210 my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._out2_a_B:=1]
+	    170555 my_demux.my_demux.demux._out2_a_BX_t[0] : 1  [by my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y:=0]
+	    177027 my_demux.my_demux.demux._en1_X_f[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
+System initialized
+	    177027 Reset : 0
+	    177165 my_demux._reset_B : 1  [by Reset:=0]
+	    182428 my_demux.my_demux.demux.reset_buf._y : 0  [by my_demux._reset_B:=1]
+	    182430 my_demux.my_demux.demux._reset_BX : 1  [by my_demux.my_demux.demux.reset_buf._y:=0]
+	    226347 my_demux.my_demux.demux.reset_bufarray.buf4._y : 0  [by my_demux.my_demux.demux._reset_BX:=1]
+	    226348 my_demux.my_demux.demux._reset_BXX[0] : 1  [by my_demux.my_demux.demux.reset_bufarray.buf4._y:=0]
+System reset completed
+
+Output neutral checked
+	    226348 my_demux.in.d.d[0].t : 1
+	    226348 my_demux.in.d.d[7].t : 1
+	    226348 my_demux.in.d.d[2].t : 1
+	    226348 my_demux.in.d.d[6].t : 1
+	    226348 my_demux.in.d.d[5].t : 1
+	    226348 my_demux.in.d.d[1].t : 1
+	    226348 my_demux.in.d.d[4].t : 1
+	    226348 my_demux.in.d.d[3].t : 1
+	    226359 my_demux.my_demux.demux.c_f_c_t_or._y : 0  [by my_demux.in.d.d[0].t:=1]
+	    226364 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0  [by my_demux.in.d.d[5].t:=1]
+	    226415 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0  [by my_demux.in.d.d[2].t:=1]
+	    226718 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0  [by my_demux.in.d.d[0].t:=1]
+	    226720 my_demux.my_demux.demux.vc.ct.in[0] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
+	    226876 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0  [by my_demux.in.d.d[4].t:=1]
+	    226896 my_demux.my_demux.demux.c_buf_t.buf2._y : 0  [by my_demux.in.d.d[0].t:=1]
+	    226899 my_demux.my_demux.demux._c_t_buf[0] : 1  [by my_demux.my_demux.demux.c_buf_t.buf2._y:=0]
+	    226928 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    226929 my_demux.out1.d.d[0].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=0]
+	    226943 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    227052 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    227074 my_demux.out1.d.d[3].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=0]
+	    227160 my_demux.out1.d.d[4].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=0]
+	    227216 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    227217 my_demux.out1.d.d[1].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=0]
+	    228500 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    228783 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0  [by my_demux.in.d.d[3].t:=1]
+	    228989 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0  [by my_demux.in.d.d[6].t:=1]
+	    229148 my_demux.my_demux.demux.vc.ct.in[6] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
+	    229660 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    230081 my_demux.out1.d.d[2].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=0]
+	    230910 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0  [by my_demux.in.d.d[1].t:=1]
+	    232197 my_demux.my_demux.demux.vc.ct.in[1] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
+	    234429 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
+	    234574 my_demux.my_demux.demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
+	    238128 my_demux.my_demux.demux.vc.ct.in[3] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
+	    239456 my_demux.my_demux.demux.vc.ct.in[2] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
+	    240582 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    242288 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
+	    242289 my_demux.my_demux.demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
+	    246936 my_demux.out1.d.d[6].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=0]
+	    249336 my_demux.out1.d.d[5].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=0]
+	    250289 my_demux.my_demux.demux.vc.ct.in[5] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
+	    253239 my_demux.my_demux.demux._c_v : 1  [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
+	    287834 my_demux.my_demux.demux.vc.ct.in[4] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
+	    327118 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[4]:=1]
+	    327280 my_demux.my_demux.demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
+	    334649 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
+	    334663 my_demux.my_demux.demux._in_v : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
+	    334670 my_demux.my_demux.demux.in_v_buf._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    334823 my_demux.my_demux.demux.c_el._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    334824 my_demux.my_demux.demux._in_c_v_ : 1  [by my_demux.my_demux.demux.c_el._y:=0]
+	    356227 my_demux.in.v : 1  [by my_demux.my_demux.demux.in_v_buf._y:=0]
+	    356227 my_demux.out1.v : 1
+	    356228 my_demux.my_demux.demux.out_or._y : 0  [by my_demux.out1.v:=1]
+	    356229 my_demux.my_demux.demux._out_v : 1  [by my_demux.my_demux.demux.out_or._y:=0]
+	    358472 my_demux.my_demux.demux.inack_ctl._y : 0  [by my_demux.my_demux.demux._out_v:=1]
+	    358659 my_demux.in.a : 1  [by my_demux.my_demux.demux.inack_ctl._y:=0]
+	    358660 my_demux.my_demux.demux._en : 0  [by my_demux.in.a:=1]
+	    358661 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    358666 my_demux.my_demux.demux._en2_X_t[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
+	    359513 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    360404 my_demux.my_demux.demux._en1_X_f[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
+	    362842 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    362843 my_demux.my_demux.demux._en2_X_f[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
+	    393442 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    393459 my_demux.my_demux.demux._en1_X_t[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
+	    393459 my_demux.in.d.d[0].t : 0
+	    393459 my_demux.in.d.d[7].t : 0
+	    393459 my_demux.in.d.d[2].t : 0
+	    393459 my_demux.in.d.d[6].t : 0
+	    393459 my_demux.in.d.d[5].t : 0
+	    393459 my_demux.in.d.d[1].t : 0
+	    393459 my_demux.in.d.d[4].t : 0
+	    393459 my_demux.in.d.d[3].t : 0
+	    393460 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1  [by my_demux.in.d.d[5].t:=0]
+	    393462 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    393501 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1  [by my_demux.in.d.d[1].t:=0]
+	    393509 my_demux.my_demux.demux.vc.ct.in[1] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
+	    393555 my_demux.my_demux.demux.vc.ct.in[5] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
+	    393797 my_demux.my_demux.demux.vc.ct.in[0] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
+	    393831 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
+	    394400 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1  [by my_demux.in.d.d[2].t:=0]
+	    395318 my_demux.my_demux.demux.vc.ct.in[2] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
+	    396032 my_demux.my_demux.demux.c_buf_t.buf2._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    396036 my_demux.my_demux.demux._c_t_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
+	    396276 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1  [by my_demux.in.d.d[4].t:=0]
+	    401820 my_demux.my_demux.demux.c_f_c_t_or._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    404218 my_demux.my_demux.demux._c_v : 0  [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
+	    407192 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1  [by my_demux.in.d.d[3].t:=0]
+	    407718 my_demux.my_demux.demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
+	    410407 my_demux.my_demux.demux.vc.ct.in[3] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
+	    442654 my_demux.my_demux.demux.vc.ct.in[4] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
+	    452421 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1  [by my_demux.in.d.d[6].t:=0]
+	    452469 my_demux.my_demux.demux.vc.ct.in[6] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
+	    452472 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
+	    452650 my_demux.my_demux.demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
+	    457526 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
+	    478503 my_demux.my_demux.demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
+	    490402 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.tmp[8]:=0]
+	    496353 my_demux.my_demux.demux._in_v : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
+	    497180 my_demux.my_demux.demux.c_el._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    497353 my_demux.my_demux.demux._in_c_v_ : 0  [by my_demux.my_demux.demux.c_el._y:=1]
+	    535838 my_demux.my_demux.demux.in_v_buf._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    536022 my_demux.in.v : 0  [by my_demux.my_demux.demux.in_v_buf._y:=1]
+First Cond Checked
+	    536022 my_demux.out1.a : 1
+	    536023 my_demux.my_demux.demux._out1_a_B : 0  [by my_demux.out1.a:=1]
+	    536027 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._out1_a_B:=0]
+	    536096 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._out1_a_B:=0]
+	    536192 my_demux.my_demux.demux._out1_a_BX_t[0] : 0  [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=1]
+	    536193 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    536204 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    536205 my_demux.out1.d.d[5].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=1]
+	    536328 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    536384 my_demux.out1.d.d[0].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=1]
+	    536433 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    537222 my_demux.out1.d.d[1].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=1]
+	    540092 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    540093 my_demux.out1.d.d[6].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=1]
+	    540151 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    540188 my_demux.out1.d.d[4].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=1]
+	    555238 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    573315 my_demux.my_demux.demux._out1_a_BX_f[0] : 0  [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=1]
+	    578613 my_demux.out1.d.d[2].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=1]
+	    581439 my_demux.out1.d.d[3].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=1]
+System reset completed
+
+Output neutral checked
+	    581439 my_demux.out1.a : 0
+	    581439 my_demux.out1.v : 0
+	    581440 my_demux.my_demux.demux._out1_a_B : 1  [by my_demux.out1.a:=0]
+	    581453 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    583132 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    583489 my_demux.my_demux.demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
+	    585003 my_demux.my_demux.demux.out_or._y : 1  [by my_demux.out1.v:=0]
+	    585028 my_demux.my_demux.demux._out_v : 0  [by my_demux.my_demux.demux.out_or._y:=1]
+	    585049 my_demux.my_demux.demux.inack_ctl._y : 1  [by my_demux.my_demux.demux._out_v:=0]
+	    585050 my_demux.in.a : 0  [by my_demux.my_demux.demux.inack_ctl._y:=1]
+	    594698 my_demux.my_demux.demux._en : 1  [by my_demux.in.a:=0]
+	    594699 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    594699 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    594704 my_demux.my_demux.demux._en2_X_f[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
+	    594859 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    595267 my_demux.my_demux.demux._en2_X_t[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
+	    595280 my_demux.my_demux.demux._en1_X_t[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
+	    595735 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    595746 my_demux.my_demux.demux._en1_X_f[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
+	    598437 my_demux.my_demux.demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
+	    598437 my_demux.in.d.d[0].f : 1
+	    598437 my_demux.in.d.d[7].f : 1
+	    598437 my_demux.in.d.d[2].t : 1
+	    598437 my_demux.in.d.d[6].t : 1
+	    598437 my_demux.in.d.d[5].t : 1
+	    598437 my_demux.in.d.d[1].f : 1
+	    598437 my_demux.in.d.d[4].f : 1
+	    598437 my_demux.in.d.d[3].f : 1
+	    598441 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0  [by my_demux.in.d.d[2].t:=1]
+	    598451 my_demux.my_demux.demux.c_buf_f.buf2._y : 0  [by my_demux.in.d.d[0].f:=1]
+	    598455 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0  [by my_demux.in.d.d[0].f:=1]
+	    598525 my_demux.my_demux.demux.vc.ct.in[0] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
+	    598541 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0  [by my_demux.in.d.d[6].t:=1]
+	    598665 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0  [by my_demux.in.d.d[3].f:=1]
+	    598676 my_demux.my_demux.demux.vc.ct.in[3] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
+	    599284 my_demux.my_demux.demux.vc.ct.in[2] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
+	    599287 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
+	    599341 my_demux.my_demux.demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
+	    599484 my_demux.my_demux.demux.c_f_c_t_or._y : 0  [by my_demux.in.d.d[0].f:=1]
+	    599641 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0  [by my_demux.in.d.d[1].f:=1]
+	    599910 my_demux.my_demux.demux._c_f_buf[0] : 1  [by my_demux.my_demux.demux.c_buf_f.buf2._y:=0]
+	    599991 my_demux.my_demux.demux.out2_t_buf_func[5]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    600002 my_demux.my_demux.demux.out2_f_buf_func[1]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    600604 my_demux.out2.d.d[5].t : 1  [by my_demux.my_demux.demux.out2_t_buf_func[5]._y:=0]
+	    600632 my_demux.my_demux.demux._c_v : 1  [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
+	    600802 my_demux.my_demux.demux.vc.ct.in[1] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
+	    600847 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
+	    601654 my_demux.my_demux.demux.out2_f_buf_func[4]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    601844 my_demux.my_demux.demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
+	    603303 my_demux.out2.d.d[4].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[4]._y:=0]
+	    606892 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0  [by my_demux.in.d.d[4].f:=1]
+	    607417 my_demux.my_demux.demux.vc.ct.in[4] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
+	    608221 my_demux.my_demux.demux.out2_f_buf_func[3]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    608562 my_demux.my_demux.demux.out2_t_buf_func[2]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    608614 my_demux.out2.d.d[2].t : 1  [by my_demux.my_demux.demux.out2_t_buf_func[2]._y:=0]
+	    609121 my_demux.out2.d.d[3].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[3]._y:=0]
+	    610987 my_demux.my_demux.demux.out2_t_buf_func[6]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    610994 my_demux.out2.d.d[6].t : 1  [by my_demux.my_demux.demux.out2_t_buf_func[6]._y:=0]
+	    614024 my_demux.out2.d.d[1].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[1]._y:=0]
+	    617893 my_demux.my_demux.demux.out2_f_buf_func[0]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    629881 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0  [by my_demux.in.d.d[5].t:=1]
+	    633505 my_demux.out2.d.d[0].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[0]._y:=0]
+	    636348 my_demux.my_demux.demux.vc.ct.in[5] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
+	    648963 my_demux.my_demux.demux.vc.ct.in[6] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
+	    648965 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[6]:=1]
+	    649319 my_demux.my_demux.demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
+	    649452 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
+	    649453 my_demux.my_demux.demux._in_v : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
+	    649457 my_demux.my_demux.demux.in_v_buf._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    649999 my_demux.my_demux.demux.c_el._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    650000 my_demux.my_demux.demux._in_c_v_ : 1  [by my_demux.my_demux.demux.c_el._y:=0]
+	    695020 my_demux.in.v : 1  [by my_demux.my_demux.demux.in_v_buf._y:=0]
+	    695020 my_demux.out2.v : 1
+	    707398 my_demux.my_demux.demux.out_or._y : 0  [by my_demux.out2.v:=1]
+	    707477 my_demux.my_demux.demux._out_v : 1  [by my_demux.my_demux.demux.out_or._y:=0]
+	    709910 my_demux.my_demux.demux.inack_ctl._y : 0  [by my_demux.my_demux.demux._out_v:=1]
+	    709998 my_demux.in.a : 1  [by my_demux.my_demux.demux.inack_ctl._y:=0]
+	    717780 my_demux.my_demux.demux._en : 0  [by my_demux.in.a:=1]
+	    717810 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    717839 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    719247 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    719932 my_demux.my_demux.demux._en1_X_f[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
+	    737223 my_demux.my_demux.demux._en1_X_t[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
+	    746107 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    762822 my_demux.my_demux.demux._en2_X_f[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
+	    777314 my_demux.my_demux.demux._en2_X_t[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
+	    777314 my_demux.in.d.d[0].f : 0
+	    777314 my_demux.in.d.d[6].t : 0
+	    777314 my_demux.in.d.d[2].t : 0
+	    777314 my_demux.in.d.d[5].t : 0
+	    777314 my_demux.in.d.d[1].f : 0
+	    777314 my_demux.in.d.d[4].f : 0
+	    777314 my_demux.in.d.d[3].f : 0
+	    777315 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1  [by my_demux.in.d.d[3].f:=0]
+	    777317 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1  [by my_demux.in.d.d[1].f:=0]
+	    777326 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1  [by my_demux.in.d.d[6].t:=0]
+	    777352 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1  [by my_demux.in.d.d[4].f:=0]
+	    777354 my_demux.my_demux.demux.vc.ct.in[4] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
+	    777357 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    777358 my_demux.my_demux.demux.vc.ct.in[0] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
+	    777409 my_demux.my_demux.demux.vc.ct.in[1] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
+	    777441 my_demux.my_demux.demux.c_f_c_t_or._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    777443 my_demux.my_demux.demux._c_v : 0  [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
+	    777483 my_demux.my_demux.demux.c_buf_f.buf2._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    777501 my_demux.my_demux.demux._c_f_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
+	    777547 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1  [by my_demux.in.d.d[5].t:=0]
+	    777666 my_demux.my_demux.demux.vc.ct.in[5] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
+	    778593 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1  [by my_demux.in.d.d[2].t:=0]
+	    778910 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[1]:=0]
+	    778918 my_demux.my_demux.demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
+	    780053 my_demux.my_demux.demux.vc.ct.in[6] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
+	    780107 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
+	    784313 my_demux.my_demux.demux.vc.ct.in[2] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
+	    790067 my_demux.my_demux.demux.vc.ct.in[3] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
+	    790072 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
+	    791139 my_demux.my_demux.demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
+	    830645 my_demux.my_demux.demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
+	    830646 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.tmp[9]:=0]
+	    830784 my_demux.my_demux.demux._in_v : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
+	    830785 my_demux.my_demux.demux.in_v_buf._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    830848 my_demux.my_demux.demux.c_el._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    830850 my_demux.my_demux.demux._in_c_v_ : 0  [by my_demux.my_demux.demux.c_el._y:=1]
+	    830908 my_demux.in.v : 0  [by my_demux.my_demux.demux.in_v_buf._y:=1]
+Second Cond Checked

test/unit_tests/demux_bit_7/test.act

@@ -0,0 +1,49 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+
+defproc demux_bit_7 (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
+
+    demux_bit<7,0> my_demux(.in=in, .out1=out1,.out2 = out2);
+    //Low active Reset 
+    bool _reset_B; 
+    prs {
+    	Reset => _reset_B-
+    }
+    my_demux.supply.vss = GND;
+    my_demux.supply.vdd = Vdd;
+    my_demux.reset_B = _reset_B;
+    
+}
+
+demux_bit_7 my_demux;

test/unit_tests/demux_bit_7/test.prsim

@@ -0,0 +1,77 @@
+watchall
+set-qdi-channel-neutral "my_demux.in" 8
+set my_demux.out1.a 0
+set my_demux.out1.v 0
+set my_demux.out2.a 0
+set my_demux.out2.v 0
+set my_demux.in.d.d[0].t 0
+set my_demux.in.d.d[0].f 0
+cycle
+system "echo 'System initialized'"
+
+set Reset 0
+cycle
+system "echo 'System reset completed'"
+status X
+mode run
+
+assert-qdi-channel-neutral "my_demux.out1" 7
+assert-qdi-channel-neutral "my_demux.out2" 7
+assert-qdi-channel-neutral "my_demux.in" 8
+cycle
+
+system "echo 'Output neutral checked'"
+
+set-qdi-channel-valid "my_demux.in" 8 255
+cycle
+assert my_demux.in.v 1
+assert my_demux.in.a 0
+
+assert-qdi-channel-valid "my_demux.out1" 7 127
+assert-qdi-channel-neutral "my_demux.out2" 7
+set my_demux.out1.v 1
+cycle
+assert my_demux.in.a 1
+set-qdi-channel-neutral "my_demux.in" 8
+cycle
+set my_demux.out1.a 1
+
+
+system "echo 'First Cond Checked'"
+
+
+set Reset 0
+cycle
+system "echo 'System reset completed'"
+status X
+mode run
+
+assert-qdi-channel-neutral "my_demux.out1" 7
+assert-qdi-channel-neutral "my_demux.out2" 7
+assert-qdi-channel-neutral "my_demux.in" 8
+cycle
+
+system "echo 'Output neutral checked'"
+
+set my_demux.out1.a 0
+set my_demux.out1.v 0
+set my_demux.out2.a 0
+set my_demux.out2.v 0
+cycle
+
+set-qdi-channel-valid "my_demux.in" 8 100
+cycle
+assert my_demux.in.v 1
+assert my_demux.in.a 0
+
+assert-qdi-channel-valid "my_demux.out2" 7 100
+set my_demux.out2.v 1
+cycle
+assert my_demux.in.a 1
+set-qdi-channel-neutral "my_demux.in" 7
+cycle
+
+
+system "echo 'Second Cond Checked'"
+
+

test/unit_tests/demux_td_2/run/test.prs

@@ -254,12 +254,15 @@
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_bufarray.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_bufarray.supply.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.token_buf.vdd"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.outt_a_inv.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[1].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[1].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[0].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[0].vdd"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_inv.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.in_v_buf.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_el.vdd"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_tk_inv.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_f.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_t.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_f_c_t_or.vdd"
@@ -269,12 +272,15 @@
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.inack_ctl.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out_or.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.token_buf.vss"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.outt_a_inv.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[1].vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[1].vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[0].vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[0].vss"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_inv.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.in_v_buf.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_el.vss"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_tk_inv.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_f.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_t.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_f_c_t_or.vss"

test/unit_tests/dropper_static/run/prsim.out

@@ -0,0 +1,383 @@
+b.b.and_f[0].b b.b.vt.ct.C2Els[0]._y b.b.and_f[3].a b.b.and_f[5].y b.b.and_t[1].a b.b.vt.OR2_tf[6]._y b.b.and_t[6].a b.b.and_f[2].y b.b.and_t[0].y b.b.vt.OR2_tf[4]._y b.b.and_f[2].a b.b.and_t[5].a b.b.and_f[5].a b.b.and_t[1].y b.drop b.b.and_t[4].y b.b.vt.ct.tmp[9] b.b.and_t[4].a b.b.and_f[6].a b.b.and_f[4].y b.b.vt.ct.tmp[7] b.b.vt.ct.in[2] b.b.and_t[0]._y b.b.vt.ct.in[5] b.b.vt.ct.C2Els[1]._y b.out.a b.b.and_t[3].a b.b.and_f[6].y b.in.v b.b.and_f[1].a b.b.and_f[0].c b.b.and_t[2].a b.b.and_t[6].y b.b.and_t[0].a b.b.and_f[1]._y b.b.sb_dropB.buf4._y b.b.and_t[3]._y b.b.or2.b b.b.vt.out b.b.and_f[4].a b.b.vt.OR2_tf[2]._y b.b.and_t[3].y b.b.and_f[1].y b.b._dropB b.b.vt.ct.in[0] b.b.and_t[6]._y b.b.vt.ct.tmp[8] b.b.and_t[2].y b.in.a b.b.and_f[0].a b.b.and_f[3].y b.b.or2.y b.b.vt.ct.in[1] b.b.and_t[5]._y b.b.and_f[0].y b.b.vt.ct.in[6] b.b.and_f[5]._y b.b.and_f[4]._y b.b.and2._y b.b.vt.ct.in[4] b.b.and_f[3]._y b.b.and_t[5].y b.b.vt.ct.in[3] b.b.ack_Cel._y b.b.vt.OR2_tf[3]._y b.b.vt.OR2_tf[5]._y b.b.and_t[4]._y b.b.and_t[2]._y b.b.vt.OR2_tf[1]._y b.b.and_f[0]._y b.b.and_t[1]._y b.b.and_f[2]._y b.b.vt.ct.C3Els[0]._y b.b.vt.ct.C3Els[1]._y b.b.in_v_buf._y b.b.or2._y b.b.vt.OR2_tf[0]._y b.b.and_f[6]._y b.b.sb_in_v.buf4._y 
+	         1 b.b.and_f[0].a : 0
+	         1 b.drop : 0
+	         1 b.b.and_f[1].a : 0
+	         1 b.b.and_f[3].a : 0
+	         1 b.out.a : 0
+	         1 b.b.and_t[6].a : 0
+	         1 b.b.and_t[2].a : 0
+	         1 b.b.and_f[6].a : 0
+	         1 b.b.and_t[5].a : 0
+	         1 b.b.and_t[0].a : 0
+	         1 b.b.and_f[2].a : 0
+	         1 b.b.and_f[5].a : 0
+	         1 b.b.and_t[4].a : 0
+	         1 b.b.and_t[1].a : 0
+	         1 b.b.and_f[4].a : 0
+	         1 b.b.and_t[3].a : 0
+	         1 b.out.v : 0
+	         3 b.b._dropB : 1  [by b.drop:=0]
+	         5 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	        14 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	        16 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_t[3].a:=0]
+	        16 b.b.and_t[5]._y : 1  [by b.b.and_t[5].a:=0]
+	        17 b.b.and_t[1]._y : 1  [by b.b.and_t[1].a:=0]
+	        21 b.b.and_f[5]._y : 1  [by b.b.and_f[5].a:=0]
+	        40 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	        41 b.b.and_f[2]._y : 1  [by b.b.and_f[2].a:=0]
+	        48 b.b.and_t[4]._y : 1  [by b.b.and_t[4].a:=0]
+	        69 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	       115 b.b.and_t[6]._y : 1  [by b.b.and_t[6].a:=0]
+	       116 b.b.and_t[6].y : 0  [by b.b.and_t[6]._y:=1]
+	       416 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_f[2].a:=0]
+	       417 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	       463 b.b.and_f[2].y : 0  [by b.b.and_f[2]._y:=1]
+	       492 b.b.and_t[0]._y : 1  [by b.b.and_t[0].a:=0]
+	      1138 b.b.and_f[3]._y : 1  [by b.b.and_f[3].a:=0]
+	      1420 b.b.and_f[3].y : 0  [by b.b.and_f[3]._y:=1]
+	      1727 b.b.and_f[6]._y : 1  [by b.b.and_f[6].a:=0]
+	      2495 b.b.and_f[6].y : 0  [by b.b.and_f[6]._y:=1]
+	      4754 b.b.and_f[1]._y : 1  [by b.b.and_f[1].a:=0]
+	      4757 b.b.and_f[1].y : 0  [by b.b.and_f[1]._y:=1]
+	      6062 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_f[5].a:=0]
+	      7093 b.b.and_f[0]._y : 1  [by b.b.and_f[0].a:=0]
+	      7644 b.b.and_f[0].y : 0  [by b.b.and_f[0]._y:=1]
+	      9130 b.b.and_t[3]._y : 1  [by b.b.and_t[3].a:=0]
+	     10201 b.b.and_t[3].y : 0  [by b.b.and_t[3]._y:=1]
+	     10468 b.b.and2._y : 1  [by b.drop:=0]
+	     11422 b.b.or2.b : 0  [by b.b.and2._y:=1]
+	     12503 b.b.or2._y : 1  [by b.b.or2.b:=0]
+	     13725 b.b.and_f[4]._y : 1  [by b.b.and_f[4].a:=0]
+	     13866 b.b.and_t[1].y : 0  [by b.b.and_t[1]._y:=1]
+	     14383 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	     14707 b.b.and_f[4].y : 0  [by b.b.and_f[4]._y:=1]
+	     20697 b.b.and_t[0].y : 0  [by b.b.and_t[0]._y:=1]
+	     24833 b.b.and_f[5].y : 0  [by b.b.and_f[5]._y:=1]
+	     28503 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	     29796 b.b.and_t[5].y : 0  [by b.b.and_t[5]._y:=1]
+	     36936 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	     36954 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[4]:=0]
+	     40967 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	     43251 b.b.sb_dropB.buf4._y : 0  [by b.b._dropB:=1]
+	     44099 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_t[1].a:=0]
+	     47254 b.b.and_f[0].b : 1  [by b.b.sb_dropB.buf4._y:=0]
+	     48762 b.b.and_t[4].y : 0  [by b.b.and_t[4]._y:=1]
+	     51669 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	     65367 b.b.and_t[2]._y : 1  [by b.b.and_t[2].a:=0]
+	     66973 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	     70127 b.b.and_t[2].y : 0  [by b.b.and_t[2]._y:=1]
+	     73253 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[3]:=0]
+	     73755 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	     89000 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	     89203 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[1]:=0]
+	     91057 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	     91196 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[7]:=0]
+	    127542 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	    127611 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	    127622 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    127826 b.b.ack_Cel._y : 1  [by b.in.v:=0]
+	    127841 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+	    179408 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	    179409 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]
+[] Set reset 0
+
+	    179409 Reset : 0
+	    179446 b._reset_B : 1  [by Reset:=0]
+
+[] Sending in valid data
+	    179446 b.b.and_t[0].a : 1
+	    179446 b.b.and_f[6].a : 1
+	    179446 b.b.and_t[2].a : 1
+	    179446 b.b.and_t[5].a : 1
+	    179446 b.b.and_f[1].a : 1
+	    179446 b.b.and_f[4].a : 1
+	    179446 b.b.and_t[3].a : 1
+	    179486 b.b.vt.OR2_tf[5]._y : 0  [by b.b.and_t[5].a:=1]
+	    179487 b.b.vt.ct.in[5] : 1  [by b.b.vt.OR2_tf[5]._y:=0]
+	    179533 b.b.vt.OR2_tf[4]._y : 0  [by b.b.and_f[4].a:=1]
+	    179558 b.b.vt.OR2_tf[6]._y : 0  [by b.b.and_f[6].a:=1]
+	    179703 b.b.vt.OR2_tf[1]._y : 0  [by b.b.and_f[1].a:=1]
+	    179740 b.b.vt.OR2_tf[3]._y : 0  [by b.b.and_t[3].a:=1]
+	    180185 b.b.vt.OR2_tf[0]._y : 0  [by b.b.and_t[0].a:=1]
+	    180330 b.b.vt.ct.in[3] : 1  [by b.b.vt.OR2_tf[3]._y:=0]
+	    180363 b.b.vt.ct.in[0] : 1  [by b.b.vt.OR2_tf[0]._y:=0]
+	    180912 b.b.vt.ct.in[1] : 1  [by b.b.vt.OR2_tf[1]._y:=0]
+	    181339 b.b.vt.ct.in[4] : 1  [by b.b.vt.OR2_tf[4]._y:=0]
+	    181565 b.b.vt.ct.in[6] : 1  [by b.b.vt.OR2_tf[6]._y:=0]
+	    181715 b.b.vt.ct.C2Els[0]._y : 0  [by b.b.vt.ct.in[1]:=1]
+	    181729 b.b.vt.ct.C3Els[0]._y : 0  [by b.b.vt.ct.in[6]:=1]
+	    181751 b.b.vt.ct.tmp[9] : 1  [by b.b.vt.ct.C3Els[0]._y:=0]
+	    183910 b.b.vt.ct.tmp[7] : 1  [by b.b.vt.ct.C2Els[0]._y:=0]
+	    226958 b.b.vt.OR2_tf[2]._y : 0  [by b.b.and_t[2].a:=1]
+	    227805 b.b.vt.ct.in[2] : 1  [by b.b.vt.OR2_tf[2]._y:=0]
+	    257933 b.b.vt.ct.C2Els[1]._y : 0  [by b.b.vt.ct.in[2]:=1]
+	    258066 b.b.vt.ct.tmp[8] : 1  [by b.b.vt.ct.C2Els[1]._y:=0]
+	    273728 b.b.vt.ct.C3Els[1]._y : 0  [by b.b.vt.ct.tmp[8]:=1]
+	    274087 b.b.vt.out : 1  [by b.b.vt.ct.C3Els[1]._y:=0]
+	    288203 b.b.in_v_buf._y : 0  [by b.b.vt.out:=1]
+	    288424 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+	    288431 b.b.sb_in_v.buf4._y : 0  [by b.in.v:=1]
+	    288461 b.b.and_f[0].c : 1  [by b.b.sb_in_v.buf4._y:=0]
+	    288468 b.b.and_t[2]._y : 0  [by b.b.and_f[0].c:=1]
+	    288546 b.b.and_t[2].y : 1  [by b.b.and_t[2]._y:=0]
+	    288552 b.b.and_f[4]._y : 0  [by b.b.and_f[0].c:=1]
+	    288567 b.b.and_t[5]._y : 0  [by b.b.and_f[0].c:=1]
+	    288827 b.b.and_f[4].y : 1  [by b.b.and_f[4]._y:=0]
+	    290650 b.b.and_t[0]._y : 0  [by b.b.and_f[0].c:=1]
+	    291105 b.b.and_t[0].y : 1  [by b.b.and_t[0]._y:=0]
+	    291248 b.b.and_t[3]._y : 0  [by b.b.and_f[0].c:=1]
+	    291260 b.b.and_t[3].y : 1  [by b.b.and_t[3]._y:=0]
+	    295174 b.b.and_f[6]._y : 0  [by b.b.and_f[0].c:=1]
+	    295578 b.b.and_f[6].y : 1  [by b.b.and_f[6]._y:=0]
+	    307563 b.b.and_t[5].y : 1  [by b.b.and_t[5]._y:=0]
+	    345922 b.b.and_f[1]._y : 0  [by b.b.and_f[0].c:=1]
+	    345934 b.b.and_f[1].y : 1  [by b.b.and_f[1]._y:=0]
+	    345934 b.out.a : 1
+	    351850 b.b.or2._y : 0  [by b.out.a:=1]
+	    356126 b.b.or2.y : 1  [by b.b.or2._y:=0]
+	    359025 b.b.ack_Cel._y : 0  [by b.b.or2.y:=1]
+	    363320 b.in.a : 1  [by b.b.ack_Cel._y:=0]
+[] Removing data
+	    363320 b.b.and_t[0].a : 0
+	    363320 b.b.and_f[6].a : 0
+	    363320 b.b.and_t[2].a : 0
+	    363320 b.b.and_t[5].a : 0
+	    363320 b.b.and_f[1].a : 0
+	    363320 b.b.and_f[4].a : 0
+	    363320 b.b.and_t[3].a : 0
+	    363321 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    363322 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    363322 b.b.and_t[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    363331 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_t[3].a:=0]
+	    363347 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	    363389 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	    363395 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    363458 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    363486 b.b.and_t[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    363665 b.b.and_t[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    363691 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	    363868 b.b.and_t[3]._y : 1  [by b.b.and_t[3].a:=0]
+	    363986 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	    364569 b.b.and_f[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    365921 b.b.and_t[2].y : 0  [by b.b.and_t[2]._y:=1]
+	    365963 b.b.and_t[0].y : 0  [by b.b.and_t[0]._y:=1]
+	    366819 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    366821 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	    367855 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    367858 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	    367887 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[0]:=0]
+	    367957 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	    368204 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	    368583 b.b.and_f[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    368736 b.b.and_f[1].y : 0  [by b.b.and_f[1]._y:=1]
+	    369558 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[2]:=0]
+	    369602 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	    377610 b.b.and_f[6].y : 0  [by b.b.and_f[6]._y:=1]
+	    387793 b.b.and_t[3].y : 0  [by b.b.and_t[3]._y:=1]
+	    390545 b.b.and_t[5].y : 0  [by b.b.and_t[5]._y:=1]
+	    407237 b.b.and_f[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    409998 b.b.and_f[4].y : 0  [by b.b.and_f[4]._y:=1]
+	    427779 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[6]:=0]
+	    441462 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	    441463 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[9]:=0]
+	    441680 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	    441702 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	    441703 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    443284 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	    452629 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]
+	    452629 b.out.a : 0
+	    452788 b.b.or2._y : 1  [by b.out.a:=0]
+	    472464 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	    473751 b.b.ack_Cel._y : 1  [by b.b.or2.y:=0]
+	    475983 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+[] Sending in valid data
+	    475983 b.b.and_t[0].a : 1
+	    475983 b.b.and_f[6].a : 1
+	    475983 b.b.and_t[2].a : 1
+	    475983 b.b.and_t[5].a : 1
+	    475983 b.b.and_f[1].a : 1
+	    475983 b.b.and_f[4].a : 1
+	    475983 b.b.and_f[3].a : 1
+	    475984 b.b.vt.OR2_tf[5]._y : 0  [by b.b.and_t[5].a:=1]
+	    475998 b.b.vt.ct.in[5] : 1  [by b.b.vt.OR2_tf[5]._y:=0]
+	    476128 b.b.vt.OR2_tf[0]._y : 0  [by b.b.and_t[0].a:=1]
+	    476135 b.b.vt.ct.in[0] : 1  [by b.b.vt.OR2_tf[0]._y:=0]
+	    476145 b.b.vt.OR2_tf[4]._y : 0  [by b.b.and_f[4].a:=1]
+	    476305 b.b.vt.ct.in[4] : 1  [by b.b.vt.OR2_tf[4]._y:=0]
+	    478815 b.b.vt.OR2_tf[6]._y : 0  [by b.b.and_f[6].a:=1]
+	    482337 b.b.vt.OR2_tf[2]._y : 0  [by b.b.and_t[2].a:=1]
+	    482338 b.b.vt.ct.in[2] : 1  [by b.b.vt.OR2_tf[2]._y:=0]
+	    483352 b.b.vt.OR2_tf[3]._y : 0  [by b.b.and_f[3].a:=1]
+	    483353 b.b.vt.ct.in[3] : 1  [by b.b.vt.OR2_tf[3]._y:=0]
+	    483354 b.b.vt.ct.C2Els[1]._y : 0  [by b.b.vt.ct.in[3]:=1]
+	    485597 b.b.vt.ct.tmp[8] : 1  [by b.b.vt.ct.C2Els[1]._y:=0]
+	    500372 b.b.vt.ct.in[6] : 1  [by b.b.vt.OR2_tf[6]._y:=0]
+	    500559 b.b.vt.ct.C3Els[0]._y : 0  [by b.b.vt.ct.in[6]:=1]
+	    500560 b.b.vt.ct.tmp[9] : 1  [by b.b.vt.ct.C3Els[0]._y:=0]
+	    515267 b.b.vt.OR2_tf[1]._y : 0  [by b.b.and_f[1].a:=1]
+	    519449 b.b.vt.ct.in[1] : 1  [by b.b.vt.OR2_tf[1]._y:=0]
+	    554231 b.b.vt.ct.C2Els[0]._y : 0  [by b.b.vt.ct.in[1]:=1]
+	    554232 b.b.vt.ct.tmp[7] : 1  [by b.b.vt.ct.C2Els[0]._y:=0]
+	    555085 b.b.vt.ct.C3Els[1]._y : 0  [by b.b.vt.ct.tmp[7]:=1]
+	    555090 b.b.vt.out : 1  [by b.b.vt.ct.C3Els[1]._y:=0]
+	    555981 b.b.in_v_buf._y : 0  [by b.b.vt.out:=1]
+	    555982 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+	    555999 b.b.sb_in_v.buf4._y : 0  [by b.in.v:=1]
+	    558572 b.b.and_f[0].c : 1  [by b.b.sb_in_v.buf4._y:=0]
+	    558573 b.b.and_t[0]._y : 0  [by b.b.and_f[0].c:=1]
+	    558575 b.b.and_f[1]._y : 0  [by b.b.and_f[0].c:=1]
+	    558614 b.b.and_t[2]._y : 0  [by b.b.and_f[0].c:=1]
+	    558670 b.b.and_f[1].y : 1  [by b.b.and_f[1]._y:=0]
+	    558949 b.b.and_t[2].y : 1  [by b.b.and_t[2]._y:=0]
+	    559513 b.b.and_f[3]._y : 0  [by b.b.and_f[0].c:=1]
+	    559521 b.b.and_f[3].y : 1  [by b.b.and_f[3]._y:=0]
+	    561389 b.b.and_t[5]._y : 0  [by b.b.and_f[0].c:=1]
+	    561423 b.b.and_t[5].y : 1  [by b.b.and_t[5]._y:=0]
+	    566933 b.b.and_f[6]._y : 0  [by b.b.and_f[0].c:=1]
+	    572306 b.b.and_t[0].y : 1  [by b.b.and_t[0]._y:=0]
+	    580820 b.b.and_f[6].y : 1  [by b.b.and_f[6]._y:=0]
+	    617534 b.b.and_f[4]._y : 0  [by b.b.and_f[0].c:=1]
+	    618452 b.b.and_f[4].y : 1  [by b.b.and_f[4]._y:=0]
+	    618452 b.out.a : 1
+	    618456 b.b.or2._y : 0  [by b.out.a:=1]
+	    664834 b.b.or2.y : 1  [by b.b.or2._y:=0]
+	    667232 b.b.ack_Cel._y : 0  [by b.b.or2.y:=1]
+	    670447 b.in.a : 1  [by b.b.ack_Cel._y:=0]
+[] Removing data
+	    670447 b.b.and_t[0].a : 0
+	    670447 b.b.and_f[6].a : 0
+	    670447 b.b.and_t[2].a : 0
+	    670447 b.b.and_t[5].a : 0
+	    670447 b.b.and_f[1].a : 0
+	    670447 b.b.and_f[4].a : 0
+	    670447 b.b.and_f[3].a : 0
+	    670448 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    670450 b.b.and_f[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    670451 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_f[3].a:=0]
+	    670495 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    670496 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	    670520 b.b.and_f[3]._y : 1  [by b.b.and_f[3].a:=0]
+	    670546 b.b.and_f[6].y : 0  [by b.b.and_f[6]._y:=1]
+	    670587 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	    670620 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    670625 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    670631 b.b.and_f[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    670643 b.b.and_f[4].y : 0  [by b.b.and_f[4]._y:=1]
+	    670861 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	    671274 b.b.and_f[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    672303 b.b.and_f[1].y : 0  [by b.b.and_f[1]._y:=1]
+	    674584 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	    674761 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[1]:=0]
+	    674762 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	    676398 b.b.and_t[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    676454 b.b.and_t[5].y : 0  [by b.b.and_t[5]._y:=1]
+	    682346 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    689566 b.b.and_f[3].y : 0  [by b.b.and_f[3]._y:=1]
+	    691424 b.b.and_t[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    691425 b.b.and_t[2].y : 0  [by b.b.and_t[2]._y:=1]
+	    707736 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	    709932 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    709969 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	    717566 b.b.and_t[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    717567 b.b.and_t[0].y : 0  [by b.b.and_t[0]._y:=1]
+	    727352 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	    730916 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[2]:=0]
+	    732608 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	    733344 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[5]:=0]
+	    733357 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	    750341 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[9]:=0]
+	    750698 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	    750723 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	    750744 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    750745 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	    760393 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]
+	    760393 b.out.a : 0
+	    760394 b.b.or2._y : 1  [by b.out.a:=0]
+	    760395 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	    760556 b.b.ack_Cel._y : 1  [by b.b.or2.y:=0]
+	    761593 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+[] Enabling drop
+	    761593 b.drop : 1
+	    761598 b.b._dropB : 0  [by b.drop:=1]
+	    762179 b.b.sb_dropB.buf4._y : 1  [by b.b._dropB:=0]
+	    762587 b.b.and_f[0].b : 0  [by b.b.sb_dropB.buf4._y:=1]
+[] Sending in valid data
+	    762587 b.b.and_t[0].a : 1
+	    762587 b.b.and_f[6].a : 1
+	    762587 b.b.and_t[2].a : 1
+	    762587 b.b.and_t[5].a : 1
+	    762587 b.b.and_f[1].a : 1
+	    762587 b.b.and_f[4].a : 1
+	    762587 b.b.and_t[3].a : 1
+	    762591 b.b.vt.OR2_tf[1]._y : 0  [by b.b.and_f[1].a:=1]
+	    762598 b.b.vt.OR2_tf[0]._y : 0  [by b.b.and_t[0].a:=1]
+	    762601 b.b.vt.OR2_tf[2]._y : 0  [by b.b.and_t[2].a:=1]
+	    762605 b.b.vt.OR2_tf[5]._y : 0  [by b.b.and_t[5].a:=1]
+	    762691 b.b.vt.OR2_tf[4]._y : 0  [by b.b.and_f[4].a:=1]
+	    762829 b.b.vt.ct.in[2] : 1  [by b.b.vt.OR2_tf[2]._y:=0]
+	    763448 b.b.vt.ct.in[5] : 1  [by b.b.vt.OR2_tf[5]._y:=0]
+	    763634 b.b.vt.OR2_tf[6]._y : 0  [by b.b.and_f[6].a:=1]
+	    763704 b.b.vt.ct.in[6] : 1  [by b.b.vt.OR2_tf[6]._y:=0]
+	    763795 b.b.vt.ct.in[1] : 1  [by b.b.vt.OR2_tf[1]._y:=0]
+	    764150 b.b.vt.ct.in[4] : 1  [by b.b.vt.OR2_tf[4]._y:=0]
+	    771053 b.b.vt.ct.in[0] : 1  [by b.b.vt.OR2_tf[0]._y:=0]
+	    771064 b.b.vt.ct.C2Els[0]._y : 0  [by b.b.vt.ct.in[0]:=1]
+	    771067 b.b.vt.ct.tmp[7] : 1  [by b.b.vt.ct.C2Els[0]._y:=0]
+	    794031 b.b.vt.OR2_tf[3]._y : 0  [by b.b.and_t[3].a:=1]
+	    794085 b.b.vt.ct.in[3] : 1  [by b.b.vt.OR2_tf[3]._y:=0]
+	    795233 b.b.vt.ct.C2Els[1]._y : 0  [by b.b.vt.ct.in[3]:=1]
+	    796394 b.b.vt.ct.tmp[8] : 1  [by b.b.vt.ct.C2Els[1]._y:=0]
+	    814572 b.b.vt.ct.C3Els[0]._y : 0  [by b.b.vt.ct.in[4]:=1]
+	    823224 b.b.vt.ct.tmp[9] : 1  [by b.b.vt.ct.C3Els[0]._y:=0]
+	    823305 b.b.vt.ct.C3Els[1]._y : 0  [by b.b.vt.ct.tmp[9]:=1]
+	    834382 b.b.vt.out : 1  [by b.b.vt.ct.C3Els[1]._y:=0]
+	    852365 b.b.in_v_buf._y : 0  [by b.b.vt.out:=1]
+	    852457 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+	    854201 b.b.sb_in_v.buf4._y : 0  [by b.in.v:=1]
+	    854814 b.b.and_f[0].c : 1  [by b.b.sb_in_v.buf4._y:=0]
+	    860768 b.b.and2._y : 0  [by b.in.v:=1]
+	    874790 b.b.or2.b : 1  [by b.b.and2._y:=0]
+	    874835 b.b.or2._y : 0  [by b.b.or2.b:=1]
+	    875832 b.b.or2.y : 1  [by b.b.or2._y:=0]
+	    877481 b.b.ack_Cel._y : 0  [by b.b.or2.y:=1]
+	    878006 b.in.a : 1  [by b.b.ack_Cel._y:=0]
+[] Removing data
+	    878006 b.b.and_t[0].a : 0
+	    878006 b.b.and_f[6].a : 0
+	    878006 b.b.and_t[2].a : 0
+	    878006 b.b.and_t[5].a : 0
+	    878006 b.b.and_f[1].a : 0
+	    878006 b.b.and_f[4].a : 0
+	    878006 b.b.and_t[3].a : 0
+	    878008 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    878013 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    878014 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	    878058 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    878062 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	    878141 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	    878360 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_t[3].a:=0]
+	    878906 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    878906 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	    878907 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[3]:=0]
+	    884473 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    884552 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	    891285 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	    893618 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    896051 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	    896139 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[5]:=0]
+	    903921 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	    924469 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	    952796 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[0]:=0]
+	    952855 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	    952885 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[7]:=0]
+	    954352 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	   1013856 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	   1033240 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	   1033925 b.b.and2._y : 1  [by b.in.v:=0]
+	   1034052 b.b.or2.b : 0  [by b.b.and2._y:=1]
+	   1034221 b.b.or2._y : 1  [by b.b.or2.b:=0]
+	   1034264 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	   1034276 b.b.ack_Cel._y : 1  [by b.b.or2.y:=0]
+	   1035555 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+	   1049955 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	   1050188 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]

test/unit_tests/dropper_static/run/test.prs

@@ -0,0 +1,717 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"Reset"->"b._reset_B"-
+~("Reset")->"b._reset_B"+
+= "b.b._dropB" "b.b.sb_dropB.in"
+= "b.b._dropB" "b.b.inv.y"
+"b.b.in_v_buf.a"->"b.b.in_v_buf._y"-
+~("b.b.in_v_buf.a")->"b.b.in_v_buf._y"+
+"b.b.in_v_buf._y"->"b.b.in_v_buf.y"-
+~("b.b.in_v_buf._y")->"b.b.in_v_buf.y"+
+"b.b.sb_dropB.buf4.a"->"b.b.sb_dropB.buf4._y"-
+~("b.b.sb_dropB.buf4.a")->"b.b.sb_dropB.buf4._y"+
+"b.b.sb_dropB.buf4._y"->"b.b.sb_dropB.buf4.y"-
+~("b.b.sb_dropB.buf4._y")->"b.b.sb_dropB.buf4.y"+
+= "b.b.sb_dropB.supply.vdd" "b.b.sb_dropB.buf4.vdd"
+= "b.b.sb_dropB.supply.vss" "b.b.sb_dropB.buf4.vss"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[13]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[12]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[11]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[10]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[9]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[8]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[7]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[6]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[5]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[4]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[3]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[2]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[1]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.buf4.y"
+= "b.b.sb_dropB.in" "b.b.sb_dropB.buf4.a"
+= "b.b.supply.vss" "b.b.sb_in_v.supply.vss"
+= "b.b.supply.vdd" "b.b.sb_in_v.supply.vdd"
+= "b.b.supply.vss" "b.b.sb_dropB.supply.vss"
+= "b.b.supply.vdd" "b.b.sb_dropB.supply.vdd"
+= "b.b.supply.vss" "b.b.vt.supply.vss"
+= "b.b.supply.vdd" "b.b.vt.supply.vdd"
+= "b.b.supply.vdd" "b.b.and_t[6].vdd"
+= "b.b.supply.vdd" "b.b.and_t[5].vdd"
+= "b.b.supply.vdd" "b.b.and_t[4].vdd"
+= "b.b.supply.vdd" "b.b.and_t[3].vdd"
+= "b.b.supply.vdd" "b.b.and_t[2].vdd"
+= "b.b.supply.vdd" "b.b.and_t[1].vdd"
+= "b.b.supply.vdd" "b.b.and_t[0].vdd"
+= "b.b.supply.vdd" "b.b.or2.vdd"
+= "b.b.supply.vdd" "b.b.and2.vdd"
+= "b.b.supply.vdd" "b.b.in_v_buf.vdd"
+= "b.b.supply.vdd" "b.b.inv.vdd"
+= "b.b.supply.vss" "b.b.and_t[6].vss"
+= "b.b.supply.vss" "b.b.and_t[5].vss"
+= "b.b.supply.vss" "b.b.and_t[4].vss"
+= "b.b.supply.vss" "b.b.and_t[3].vss"
+= "b.b.supply.vss" "b.b.and_t[2].vss"
+= "b.b.supply.vss" "b.b.and_t[1].vss"
+= "b.b.supply.vss" "b.b.and_t[0].vss"
+= "b.b.supply.vss" "b.b.or2.vss"
+= "b.b.supply.vss" "b.b.and2.vss"
+= "b.b.supply.vss" "b.b.in_v_buf.vss"
+= "b.b.supply.vss" "b.b.inv.vss"
+= "b.b.cond" "b.b.and2.a"
+= "b.b.cond" "b.b._drop"
+= "b.b.cond" "b.b.inv.a"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.a" "b.b.or2.a"
+= "b.b.out.d.d[6].d[0]" "b.b.and_f[6].y"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.and_t[6].y"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[5].d[0]" "b.b.and_f[5].y"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.and_t[5].y"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[4].d[0]" "b.b.and_f[4].y"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.and_t[4].y"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.and_f[3].y"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.and_t[3].y"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.and_f[2].y"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.and_t[2].y"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.and_f[1].y"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.and_t[1].y"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.and_f[0].y"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.and_t[0].y"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[0].f" "b.b.vt.in.d[0].f"
+= "b.b.in.d.d[0].t" "b.b.vt.in.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.vt.in.d[0].d[0]"
+= "b.b.in.d.d[0].d[1]" "b.b.vt.in.d[0].d[1]"
+= "b.b.in.d.d[1].f" "b.b.vt.in.d[1].f"
+= "b.b.in.d.d[1].t" "b.b.vt.in.d[1].t"
+= "b.b.in.d.d[1].d[0]" "b.b.vt.in.d[1].d[0]"
+= "b.b.in.d.d[1].d[1]" "b.b.vt.in.d[1].d[1]"
+= "b.b.in.d.d[2].f" "b.b.vt.in.d[2].f"
+= "b.b.in.d.d[2].t" "b.b.vt.in.d[2].t"
+= "b.b.in.d.d[2].d[0]" "b.b.vt.in.d[2].d[0]"
+= "b.b.in.d.d[2].d[1]" "b.b.vt.in.d[2].d[1]"
+= "b.b.in.d.d[3].f" "b.b.vt.in.d[3].f"
+= "b.b.in.d.d[3].t" "b.b.vt.in.d[3].t"
+= "b.b.in.d.d[3].d[0]" "b.b.vt.in.d[3].d[0]"
+= "b.b.in.d.d[3].d[1]" "b.b.vt.in.d[3].d[1]"
+= "b.b.in.d.d[4].f" "b.b.vt.in.d[4].f"
+= "b.b.in.d.d[4].t" "b.b.vt.in.d[4].t"
+= "b.b.in.d.d[4].d[0]" "b.b.vt.in.d[4].d[0]"
+= "b.b.in.d.d[4].d[1]" "b.b.vt.in.d[4].d[1]"
+= "b.b.in.d.d[5].f" "b.b.vt.in.d[5].f"
+= "b.b.in.d.d[5].t" "b.b.vt.in.d[5].t"
+= "b.b.in.d.d[5].d[0]" "b.b.vt.in.d[5].d[0]"
+= "b.b.in.d.d[5].d[1]" "b.b.vt.in.d[5].d[1]"
+= "b.b.in.d.d[6].f" "b.b.vt.in.d[6].f"
+= "b.b.in.d.d[6].t" "b.b.vt.in.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.vt.in.d[6].d[0]"
+= "b.b.in.d.d[6].d[1]" "b.b.vt.in.d[6].d[1]"
+= "b.b.in.a" "b.b.ack_Cel.y"
+= "b.b.in.v" "b.b.sb_in_v.in"
+= "b.b.in.v" "b.b.ack_Cel.c2"
+= "b.b.in.v" "b.b.and2.b"
+= "b.b.in.v" "b.b.in_v_buf.y"
+= "b.b.in.v" "b.b._in_vX"
+= "b.b.in.d.d[6].d[0]" "b.b.and_f[6].a"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.and_t[6].a"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.and_f[5].a"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.and_t[5].a"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.and_f[4].a"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.and_t[4].a"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.and_f[3].a"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.and_t[3].a"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.and_f[2].a"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.and_t[2].a"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.and_f[1].a"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.and_t[1].a"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.and_f[0].a"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.and_t[0].a"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+"b.b.or2.a"|"b.b.or2.b"->"b.b.or2._y"-
+~("b.b.or2.a"|"b.b.or2.b")->"b.b.or2._y"+
+"b.b.or2._y"->"b.b.or2.y"-
+~("b.b.or2._y")->"b.b.or2.y"+
+= "b.b.or2.y" "b.b.ack_Cel.c1"
+= "b.b.or2.b" "b.b.and2.y"
+"b.b.and2.a"&"b.b.and2.b"->"b.b.and2._y"-
+~("b.b.and2.a"&"b.b.and2.b")->"b.b.and2._y"+
+"b.b.and2._y"->"b.b.and2.y"-
+~("b.b.and2._y")->"b.b.and2.y"+
+"b.b.sb_in_v.buf4.a"->"b.b.sb_in_v.buf4._y"-
+~("b.b.sb_in_v.buf4.a")->"b.b.sb_in_v.buf4._y"+
+"b.b.sb_in_v.buf4._y"->"b.b.sb_in_v.buf4.y"-
+~("b.b.sb_in_v.buf4._y")->"b.b.sb_in_v.buf4.y"+
+= "b.b.sb_in_v.supply.vdd" "b.b.sb_in_v.buf4.vdd"
+= "b.b.sb_in_v.supply.vss" "b.b.sb_in_v.buf4.vss"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[13]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[12]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[11]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[10]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[9]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[8]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[7]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[6]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[5]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[4]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[3]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[2]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[1]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.buf4.y"
+= "b.b.sb_in_v.in" "b.b.sb_in_v.buf4.a"
+"b.b.and_f[0].a"&"b.b.and_f[0].b"&"b.b.and_f[0].c"->"b.b.and_f[0]._y"-
+~("b.b.and_f[0].a"&"b.b.and_f[0].b"&"b.b.and_f[0].c")->"b.b.and_f[0]._y"+
+"b.b.and_f[0]._y"->"b.b.and_f[0].y"-
+~("b.b.and_f[0]._y")->"b.b.and_f[0].y"+
+"b.b.and_f[1].a"&"b.b.and_f[1].b"&"b.b.and_f[1].c"->"b.b.and_f[1]._y"-
+~("b.b.and_f[1].a"&"b.b.and_f[1].b"&"b.b.and_f[1].c")->"b.b.and_f[1]._y"+
+"b.b.and_f[1]._y"->"b.b.and_f[1].y"-
+~("b.b.and_f[1]._y")->"b.b.and_f[1].y"+
+"b.b.and_f[2].a"&"b.b.and_f[2].b"&"b.b.and_f[2].c"->"b.b.and_f[2]._y"-
+~("b.b.and_f[2].a"&"b.b.and_f[2].b"&"b.b.and_f[2].c")->"b.b.and_f[2]._y"+
+"b.b.and_f[2]._y"->"b.b.and_f[2].y"-
+~("b.b.and_f[2]._y")->"b.b.and_f[2].y"+
+"b.b.and_f[3].a"&"b.b.and_f[3].b"&"b.b.and_f[3].c"->"b.b.and_f[3]._y"-
+~("b.b.and_f[3].a"&"b.b.and_f[3].b"&"b.b.and_f[3].c")->"b.b.and_f[3]._y"+
+"b.b.and_f[3]._y"->"b.b.and_f[3].y"-
+~("b.b.and_f[3]._y")->"b.b.and_f[3].y"+
+"b.b.and_f[4].a"&"b.b.and_f[4].b"&"b.b.and_f[4].c"->"b.b.and_f[4]._y"-
+~("b.b.and_f[4].a"&"b.b.and_f[4].b"&"b.b.and_f[4].c")->"b.b.and_f[4]._y"+
+"b.b.and_f[4]._y"->"b.b.and_f[4].y"-
+~("b.b.and_f[4]._y")->"b.b.and_f[4].y"+
+"b.b.and_f[5].a"&"b.b.and_f[5].b"&"b.b.and_f[5].c"->"b.b.and_f[5]._y"-
+~("b.b.and_f[5].a"&"b.b.and_f[5].b"&"b.b.and_f[5].c")->"b.b.and_f[5]._y"+
+"b.b.and_f[5]._y"->"b.b.and_f[5].y"-
+~("b.b.and_f[5]._y")->"b.b.and_f[5].y"+
+"b.b.and_f[6].a"&"b.b.and_f[6].b"&"b.b.and_f[6].c"->"b.b.and_f[6]._y"-
+~("b.b.and_f[6].a"&"b.b.and_f[6].b"&"b.b.and_f[6].c")->"b.b.and_f[6]._y"+
+"b.b.and_f[6]._y"->"b.b.and_f[6].y"-
+~("b.b.and_f[6]._y")->"b.b.and_f[6].y"+
+= "b.b.and_f[6].b" "b.b.and_t[6].b"
+= "b.b.and_f[6].b" "b.b.and_t[5].b"
+= "b.b.and_f[6].b" "b.b.and_t[4].b"
+= "b.b.and_f[6].b" "b.b.and_t[3].b"
+= "b.b.and_f[6].b" "b.b.and_t[2].b"
+= "b.b.and_f[6].b" "b.b.and_t[1].b"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[13]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[12]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[11]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[10]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[9]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[8]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[7]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[6]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[5]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[4]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[3]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[2]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[1]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[0]"
+= "b.b.and_f[6].b" "b.b.and_t[0].b"
+= "b.b.and_f[6].b" "b.b.and_f[0].b"
+= "b.b.and_f[6].b" "b.b.and_f[1].b"
+= "b.b.and_f[6].b" "b.b.and_f[2].b"
+= "b.b.and_f[6].b" "b.b.and_f[3].b"
+= "b.b.and_f[6].b" "b.b.and_f[4].b"
+= "b.b.and_f[6].b" "b.b.and_f[5].b"
+= "b.b.and_f[6].c" "b.b.and_t[6].c"
+= "b.b.and_f[6].c" "b.b.and_t[5].c"
+= "b.b.and_f[6].c" "b.b.and_t[4].c"
+= "b.b.and_f[6].c" "b.b.and_t[3].c"
+= "b.b.and_f[6].c" "b.b.and_t[2].c"
+= "b.b.and_f[6].c" "b.b.and_t[1].c"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[13]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[12]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[11]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[10]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[9]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[8]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[7]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[6]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[5]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[4]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[3]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[2]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[1]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[0]"
+= "b.b.and_f[6].c" "b.b.and_t[0].c"
+= "b.b.and_f[6].c" "b.b.and_f[0].c"
+= "b.b.and_f[6].c" "b.b.and_f[1].c"
+= "b.b.and_f[6].c" "b.b.and_f[2].c"
+= "b.b.and_f[6].c" "b.b.and_f[3].c"
+= "b.b.and_f[6].c" "b.b.and_f[4].c"
+= "b.b.and_f[6].c" "b.b.and_f[5].c"
+"b.b.and_t[0].a"&"b.b.and_t[0].b"&"b.b.and_t[0].c"->"b.b.and_t[0]._y"-
+~("b.b.and_t[0].a"&"b.b.and_t[0].b"&"b.b.and_t[0].c")->"b.b.and_t[0]._y"+
+"b.b.and_t[0]._y"->"b.b.and_t[0].y"-
+~("b.b.and_t[0]._y")->"b.b.and_t[0].y"+
+"b.b.and_t[1].a"&"b.b.and_t[1].b"&"b.b.and_t[1].c"->"b.b.and_t[1]._y"-
+~("b.b.and_t[1].a"&"b.b.and_t[1].b"&"b.b.and_t[1].c")->"b.b.and_t[1]._y"+
+"b.b.and_t[1]._y"->"b.b.and_t[1].y"-
+~("b.b.and_t[1]._y")->"b.b.and_t[1].y"+
+"b.b.and_t[2].a"&"b.b.and_t[2].b"&"b.b.and_t[2].c"->"b.b.and_t[2]._y"-
+~("b.b.and_t[2].a"&"b.b.and_t[2].b"&"b.b.and_t[2].c")->"b.b.and_t[2]._y"+
+"b.b.and_t[2]._y"->"b.b.and_t[2].y"-
+~("b.b.and_t[2]._y")->"b.b.and_t[2].y"+
+"b.b.and_t[3].a"&"b.b.and_t[3].b"&"b.b.and_t[3].c"->"b.b.and_t[3]._y"-
+~("b.b.and_t[3].a"&"b.b.and_t[3].b"&"b.b.and_t[3].c")->"b.b.and_t[3]._y"+
+"b.b.and_t[3]._y"->"b.b.and_t[3].y"-
+~("b.b.and_t[3]._y")->"b.b.and_t[3].y"+
+"b.b.and_t[4].a"&"b.b.and_t[4].b"&"b.b.and_t[4].c"->"b.b.and_t[4]._y"-
+~("b.b.and_t[4].a"&"b.b.and_t[4].b"&"b.b.and_t[4].c")->"b.b.and_t[4]._y"+
+"b.b.and_t[4]._y"->"b.b.and_t[4].y"-
+~("b.b.and_t[4]._y")->"b.b.and_t[4].y"+
+"b.b.and_t[5].a"&"b.b.and_t[5].b"&"b.b.and_t[5].c"->"b.b.and_t[5]._y"-
+~("b.b.and_t[5].a"&"b.b.and_t[5].b"&"b.b.and_t[5].c")->"b.b.and_t[5]._y"+
+"b.b.and_t[5]._y"->"b.b.and_t[5].y"-
+~("b.b.and_t[5]._y")->"b.b.and_t[5].y"+
+"b.b.and_t[6].a"&"b.b.and_t[6].b"&"b.b.and_t[6].c"->"b.b.and_t[6]._y"-
+~("b.b.and_t[6].a"&"b.b.and_t[6].b"&"b.b.and_t[6].c")->"b.b.and_t[6]._y"+
+"b.b.and_t[6]._y"->"b.b.and_t[6].y"-
+~("b.b.and_t[6]._y")->"b.b.and_t[6].y"+
+"b.b.inv.a"->"b.b.inv.y"-
+~("b.b.inv.a")->"b.b.inv.y"+
+~"b.b.vt.ct.C2Els[0].c1"&~"b.b.vt.ct.C2Els[0].c2"->"b.b.vt.ct.C2Els[0]._y"+
+"b.b.vt.ct.C2Els[0].c1"&"b.b.vt.ct.C2Els[0].c2"->"b.b.vt.ct.C2Els[0]._y"-
+"b.b.vt.ct.C2Els[0]._y"->"b.b.vt.ct.C2Els[0].y"-
+~("b.b.vt.ct.C2Els[0]._y")->"b.b.vt.ct.C2Els[0].y"+
+~"b.b.vt.ct.C2Els[1].c1"&~"b.b.vt.ct.C2Els[1].c2"->"b.b.vt.ct.C2Els[1]._y"+
+"b.b.vt.ct.C2Els[1].c1"&"b.b.vt.ct.C2Els[1].c2"->"b.b.vt.ct.C2Els[1]._y"-
+"b.b.vt.ct.C2Els[1]._y"->"b.b.vt.ct.C2Els[1].y"-
+~("b.b.vt.ct.C2Els[1]._y")->"b.b.vt.ct.C2Els[1].y"+
+~"b.b.vt.ct.C3Els[0].c1"&~"b.b.vt.ct.C3Els[0].c2"&~"b.b.vt.ct.C3Els[0].c3"->"b.b.vt.ct.C3Els[0]._y"+
+"b.b.vt.ct.C3Els[0].c1"&"b.b.vt.ct.C3Els[0].c2"&"b.b.vt.ct.C3Els[0].c3"->"b.b.vt.ct.C3Els[0]._y"-
+"b.b.vt.ct.C3Els[0]._y"->"b.b.vt.ct.C3Els[0].y"-
+~("b.b.vt.ct.C3Els[0]._y")->"b.b.vt.ct.C3Els[0].y"+
+~"b.b.vt.ct.C3Els[1].c1"&~"b.b.vt.ct.C3Els[1].c2"&~"b.b.vt.ct.C3Els[1].c3"->"b.b.vt.ct.C3Els[1]._y"+
+"b.b.vt.ct.C3Els[1].c1"&"b.b.vt.ct.C3Els[1].c2"&"b.b.vt.ct.C3Els[1].c3"->"b.b.vt.ct.C3Els[1]._y"-
+"b.b.vt.ct.C3Els[1]._y"->"b.b.vt.ct.C3Els[1].y"-
+~("b.b.vt.ct.C3Els[1]._y")->"b.b.vt.ct.C3Els[1].y"+
+= "b.b.vt.ct.tmp[7]" "b.b.vt.ct.C3Els[1].c1"
+= "b.b.vt.ct.tmp[7]" "b.b.vt.ct.C2Els[0].y"
+= "b.b.vt.ct.tmp[8]" "b.b.vt.ct.C3Els[1].c2"
+= "b.b.vt.ct.tmp[8]" "b.b.vt.ct.C2Els[1].y"
+= "b.b.vt.ct.tmp[9]" "b.b.vt.ct.C3Els[1].c3"
+= "b.b.vt.ct.tmp[9]" "b.b.vt.ct.C3Els[0].y"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C3Els[1].vdd"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C3Els[0].vdd"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C2Els[1].vdd"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C2Els[0].vdd"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C3Els[1].vss"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C3Els[0].vss"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C2Els[1].vss"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C2Els[0].vss"
+= "b.b.vt.ct.in[0]" "b.b.vt.ct.C2Els[0].c1"
+= "b.b.vt.ct.in[0]" "b.b.vt.ct.tmp[0]"
+= "b.b.vt.ct.in[1]" "b.b.vt.ct.C2Els[0].c2"
+= "b.b.vt.ct.in[1]" "b.b.vt.ct.tmp[1]"
+= "b.b.vt.ct.in[2]" "b.b.vt.ct.C2Els[1].c1"
+= "b.b.vt.ct.in[2]" "b.b.vt.ct.tmp[2]"
+= "b.b.vt.ct.in[3]" "b.b.vt.ct.C2Els[1].c2"
+= "b.b.vt.ct.in[3]" "b.b.vt.ct.tmp[3]"
+= "b.b.vt.ct.in[4]" "b.b.vt.ct.C3Els[0].c1"
+= "b.b.vt.ct.in[4]" "b.b.vt.ct.tmp[4]"
+= "b.b.vt.ct.in[5]" "b.b.vt.ct.C3Els[0].c2"
+= "b.b.vt.ct.in[5]" "b.b.vt.ct.tmp[5]"
+= "b.b.vt.ct.in[6]" "b.b.vt.ct.C3Els[0].c3"
+= "b.b.vt.ct.in[6]" "b.b.vt.ct.tmp[6]"
+= "b.b.vt.ct.out" "b.b.vt.ct.C3Els[1].y"
+= "b.b.vt.ct.out" "b.b.vt.ct.tmp[10]"
+= "b.b.vt.ct.in[0]" "b.b.vt.OR2_tf[0].y"
+= "b.b.vt.ct.in[1]" "b.b.vt.OR2_tf[1].y"
+= "b.b.vt.ct.in[2]" "b.b.vt.OR2_tf[2].y"
+= "b.b.vt.ct.in[3]" "b.b.vt.OR2_tf[3].y"
+= "b.b.vt.ct.in[4]" "b.b.vt.OR2_tf[4].y"
+= "b.b.vt.ct.in[5]" "b.b.vt.OR2_tf[5].y"
+= "b.b.vt.ct.in[6]" "b.b.vt.OR2_tf[6].y"
+"b.b.vt.OR2_tf[0].a"|"b.b.vt.OR2_tf[0].b"->"b.b.vt.OR2_tf[0]._y"-
+~("b.b.vt.OR2_tf[0].a"|"b.b.vt.OR2_tf[0].b")->"b.b.vt.OR2_tf[0]._y"+
+"b.b.vt.OR2_tf[0]._y"->"b.b.vt.OR2_tf[0].y"-
+~("b.b.vt.OR2_tf[0]._y")->"b.b.vt.OR2_tf[0].y"+
+"b.b.vt.OR2_tf[1].a"|"b.b.vt.OR2_tf[1].b"->"b.b.vt.OR2_tf[1]._y"-
+~("b.b.vt.OR2_tf[1].a"|"b.b.vt.OR2_tf[1].b")->"b.b.vt.OR2_tf[1]._y"+
+"b.b.vt.OR2_tf[1]._y"->"b.b.vt.OR2_tf[1].y"-
+~("b.b.vt.OR2_tf[1]._y")->"b.b.vt.OR2_tf[1].y"+
+"b.b.vt.OR2_tf[2].a"|"b.b.vt.OR2_tf[2].b"->"b.b.vt.OR2_tf[2]._y"-
+~("b.b.vt.OR2_tf[2].a"|"b.b.vt.OR2_tf[2].b")->"b.b.vt.OR2_tf[2]._y"+
+"b.b.vt.OR2_tf[2]._y"->"b.b.vt.OR2_tf[2].y"-
+~("b.b.vt.OR2_tf[2]._y")->"b.b.vt.OR2_tf[2].y"+
+"b.b.vt.OR2_tf[3].a"|"b.b.vt.OR2_tf[3].b"->"b.b.vt.OR2_tf[3]._y"-
+~("b.b.vt.OR2_tf[3].a"|"b.b.vt.OR2_tf[3].b")->"b.b.vt.OR2_tf[3]._y"+
+"b.b.vt.OR2_tf[3]._y"->"b.b.vt.OR2_tf[3].y"-
+~("b.b.vt.OR2_tf[3]._y")->"b.b.vt.OR2_tf[3].y"+
+"b.b.vt.OR2_tf[4].a"|"b.b.vt.OR2_tf[4].b"->"b.b.vt.OR2_tf[4]._y"-
+~("b.b.vt.OR2_tf[4].a"|"b.b.vt.OR2_tf[4].b")->"b.b.vt.OR2_tf[4]._y"+
+"b.b.vt.OR2_tf[4]._y"->"b.b.vt.OR2_tf[4].y"-
+~("b.b.vt.OR2_tf[4]._y")->"b.b.vt.OR2_tf[4].y"+
+"b.b.vt.OR2_tf[5].a"|"b.b.vt.OR2_tf[5].b"->"b.b.vt.OR2_tf[5]._y"-
+~("b.b.vt.OR2_tf[5].a"|"b.b.vt.OR2_tf[5].b")->"b.b.vt.OR2_tf[5]._y"+
+"b.b.vt.OR2_tf[5]._y"->"b.b.vt.OR2_tf[5].y"-
+~("b.b.vt.OR2_tf[5]._y")->"b.b.vt.OR2_tf[5].y"+
+"b.b.vt.OR2_tf[6].a"|"b.b.vt.OR2_tf[6].b"->"b.b.vt.OR2_tf[6]._y"-
+~("b.b.vt.OR2_tf[6].a"|"b.b.vt.OR2_tf[6].b")->"b.b.vt.OR2_tf[6]._y"+
+"b.b.vt.OR2_tf[6]._y"->"b.b.vt.OR2_tf[6].y"-
+~("b.b.vt.OR2_tf[6]._y")->"b.b.vt.OR2_tf[6].y"+
+= "b.b.vt.supply.vss" "b.b.vt.ct.supply.vss"
+= "b.b.vt.supply.vdd" "b.b.vt.ct.supply.vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[6].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[5].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[4].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[3].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[2].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[1].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[0].vdd"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[6].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[5].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[4].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[3].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[2].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[1].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[0].vss"
+= "b.b.vt.out" "b.b.vt.ct.out"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.OR2_tf[6].b"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.OR2_tf[6].a"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.OR2_tf[5].b"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.OR2_tf[5].a"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.OR2_tf[4].b"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.OR2_tf[4].a"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.OR2_tf[3].b"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.OR2_tf[3].a"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.OR2_tf[2].b"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.OR2_tf[2].a"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.OR2_tf[1].b"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.OR2_tf[1].a"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.OR2_tf[0].b"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.OR2_tf[0].a"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
+= "b.b.vt.out" "b.b.in_v_buf.a"
+~"b.b.ack_Cel.c1"&~"b.b.ack_Cel.c2"->"b.b.ack_Cel._y"+
+"b.b.ack_Cel.c1"&"b.b.ack_Cel.c2"->"b.b.ack_Cel._y"-
+"b.b.ack_Cel._y"->"b.b.ack_Cel.y"-
+~("b.b.ack_Cel._y")->"b.b.ack_Cel.y"+
+= "b.supply.vss" "b.b.supply.vss"
+= "b.supply.vdd" "b.b.supply.vdd"
+= "Vdd" "b.supply.vdd"
+= "GND" "b.supply.vss"
+= "b.drop" "b.b.cond"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.v" "b.b.out.v"
+= "b.out.a" "b.b.out.a"
+= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
+= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
+= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
+= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
+= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
+= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
+= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
+= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
+= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
+= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
+= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
+= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
+= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
+= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
+= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
+= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
+= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
+= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
+= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
+= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
+= "b.out.d.d[5].f" "b.b.out.d.d[5].f"
+= "b.out.d.d[5].t" "b.b.out.d.d[5].t"
+= "b.out.d.d[5].d[0]" "b.b.out.d.d[5].d[0]"
+= "b.out.d.d[5].d[1]" "b.b.out.d.d[5].d[1]"
+= "b.out.d.d[6].f" "b.b.out.d.d[6].f"
+= "b.out.d.d[6].t" "b.b.out.d.d[6].t"
+= "b.out.d.d[6].d[0]" "b.b.out.d.d[6].d[0]"
+= "b.out.d.d[6].d[1]" "b.b.out.d.d[6].d[1]"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.v" "b.b.in.v"
+= "b.in.a" "b.b.in.a"
+= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
+= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
+= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
+= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
+= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
+= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
+= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
+= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
+= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
+= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
+= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
+= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
+= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
+= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
+= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
+= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
+= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
+= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
+= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
+= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
+= "b.in.d.d[5].f" "b.b.in.d.d[5].f"
+= "b.in.d.d[5].t" "b.b.in.d.d[5].t"
+= "b.in.d.d[5].d[0]" "b.b.in.d.d[5].d[0]"
+= "b.in.d.d[5].d[1]" "b.b.in.d.d[5].d[1]"
+= "b.in.d.d[6].f" "b.b.in.d.d[6].f"
+= "b.in.d.d[6].t" "b.b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.b.in.d.d[6].d[0]"
+= "b.in.d.d[6].d[1]" "b.b.in.d.d[6].d[1]"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

test/unit_tests/dropper_static/test.act

@@ -0,0 +1,52 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc dropper_static_7 (avMx1of2<7> in; avMx1of2<7> out; bool? drop){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    dropper_static<7, true> b(.in = in, .out = out, .cond = drop, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+dropper_static_7 b;

test/unit_tests/dropper_static/test.prsim

@@ -0,0 +1,73 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 7
+set b.out.a 0
+set b.out.v 0
+set b.drop 0
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+status X
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 45
+cycle
+assert-qdi-channel-valid "b.out" 7 45
+assert b.in.v 1
+cycle
+set b.out.a 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+set b.out.a 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 37
+cycle
+assert-qdi-channel-valid "b.out" 7 37
+assert b.in.v 1
+cycle
+set b.out.a 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+set b.out.a 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Enabling drop'"
+set b.drop 1
+cycle
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 45
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 1
+assert b.in.a 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+assert b.in.a 0

test/unit_tests/encoder1d_7/run/prsim.in

@@ -0,0 +1,268 @@
+random_seed 99
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+watchall
+
+system "echo '[] Set Reset 1'"
+
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 0
+set e.out.v 0
+set Reset 1
+
+cycle
+status X
+system "echo '[] Set Reset 0'"
+set Reset 0
+cycle
+status X
+
+
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 6 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 1
+cycle
+assert-qdi-channel-valid "e.out" 3 6
+assert e.in[6].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[6].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+

test/unit_tests/encoder1d_7/test.act

@@ -0,0 +1,54 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc encoder1d_simple_test(a1of1 in[7]; avMx1of2<3> out){
+    power supply;
+    supply.vss = GND;
+    supply.vdd = Vdd; 
+
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    
+    encoder1d_simple<3,7> e(.in = in, .supply = supply, .reset_B = _reset_B);
+
+    fifo<3, 5> fifo_post(.in = e.out, .out = out, .supply = supply, .reset_B = _reset_B);
+
+
+}
+
+encoder1d_simple_test e;

test/unit_tests/encoder1d_7/test.prsim

@@ -0,0 +1,257 @@
+watchall
+
+system "echo '[] Set Reset 1'"
+
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 0
+set e.out.v 0
+set Reset 1
+
+cycle
+status X
+system "echo '[] Set Reset 0'"
+set Reset 0
+cycle
+status X
+
+
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 6 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 1
+cycle
+assert-qdi-channel-valid "e.out" 3 6
+assert e.in[6].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[6].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+

test/unit_tests/encoder1d_bd/run/prsim.in

@@ -0,0 +1,92 @@
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+watchall
+
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+set c.in[4].r 0
+set c.in[5].r 0
+set c.in[6].r 0
+
+set c.out.a 0
+
+set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set Reset 0
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 3
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+assert c.in[4].a 0
+assert c.in[5].a 0
+assert c.in[6].a 0
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 3 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 3
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 3 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 6
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+

test/unit_tests/encoder1d_bd/test.act

@@ -0,0 +1,61 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+pint N = 7;
+pint Nc = std::ceil_log2(N);
+pint N_BUFFERS = 5;
+pint N_BD_DLY_CFG = 4;
+
+defproc _encoder1d_bd (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
+
+    bool _reset_B;
+    prs {
+       Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+    encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
+        .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+_encoder1d_bd c; 

test/unit_tests/encoder1d_bd/test.prsim

@@ -0,0 +1,82 @@
+watchall
+
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+set c.in[4].r 0
+set c.in[5].r 0
+set c.in[6].r 0
+
+set c.out.a 0
+
+set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set Reset 0
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 3
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+assert c.in[4].a 0
+assert c.in[5].a 0
+assert c.in[6].a 0
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 3 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 3
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 3 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 6
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+

test/unit_tests/fifo-decoder-neurons-encoder-fifo/test.act

@@ -71,28 +71,5 @@ defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool
 }
 
 
-
-// defproc fifo_decoder_and (avMx1of2<7> in; bool! out[8*16]; bool? dly_cfg[6]){
-//     bool _reset_B; 
-//     prs {
-//         Reset => _reset_B-
-//     }
-//     power supply;
-//     supply.vdd = Vdd;
-//     supply.vss = GND;
-
-//     pint NxC,NyC,Nx,Ny;
-//     NxC = 4;
-//     NyC = 3;
-//     Nx = 1<<NxC;
-//     Ny = 1<<NyC;
-
-//     fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
-//     decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg, 
-//         .reset_B = _reset_B, .supply = supply);
-//     and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .out = out, .supply = supply);
-//     nrn_hs_2D_array<Nx,Ny,16> nrn_array(.reset_B = _reset_B, .supply = supply);
-// }
-
 // fifo_decoder_neurons_encoder_fifo e;
 fifo_decoder_neurons_encoder_fifo e; 

test/unit_tests/fifo-register-fifo/test.act

@@ -0,0 +1,59 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_reg_fifo_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of2<8> out){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    fifo<9,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+
+    // Make a register array with 3 bit address (-> 8 registers), 
+    // each register holding 5 bits.
+    registerA_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
+        .reset_B = _reset_B, .supply = supply);
+
+    fifo<8,5> fifo_post(.in = reg.out, .out = out, .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_reg_fifo_3x5x8 b;

test/unit_tests/fifo-register-fifo/test.prsim

@@ -0,0 +1,199 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 9
+set b.out.a 0
+set b.out.v 0
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-qdi-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-qdi-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 01100=12 to reg0'"
+set-qdi-channel-valid "b.in" 9 352
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 12
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 12
+
+
+system "echo '[] Sending packet write 0s to reg1'"
+set-qdi-channel-valid "b.in" 9 257
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[1]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg2'"
+set-qdi-channel-valid "b.in" 9 258
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[2]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[2]" 5 0
+
+system "echo '[] Sending packet write 0s to reg3'"
+set-qdi-channel-valid "b.in" 9 259
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg4'"
+set-qdi-channel-valid "b.in" 9 260
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg5'"
+set-qdi-channel-valid "b.in" 9 261
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg6'"
+set-qdi-channel-valid "b.in" 9 262
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg7'"
+set-qdi-channel-valid "b.in" 9 263
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+assert-var-int "b.data[2]" 5 0
+assert-var-int "b.data[3]" 5 0
+assert-var-int "b.data[4]" 5 0
+assert-var-int "b.data[5]" 5 0
+assert-var-int "b.data[6]" 5 0
+assert-var-int "b.data[7]" 5 0
+
+
+system "echo '[] Reading register 0'"
+set-qdi-channel-valid "b.in" 9 0
+cycle
+assert-qdi-channel-valid "b.out" 8 96
+assert b.in.v 1
+assert b.in.a 1
+
+set b.out.a 1
+set b.out.v 1
+cycle
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert-qdi-channel-neutral "b.out" 8
+set b.out.a 0
+set b.out.v 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+
+
+system "echo '[] Reading register 1'"
+set-qdi-channel-valid "b.in" 9 1
+cycle
+assert-qdi-channel-valid "b.out" 8 1
+assert b.in.v 1
+assert b.in.a 1
+
+set b.out.a 1
+set b.out.v 1
+cycle
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert-qdi-channel-neutral "b.out" 8
+set b.out.a 0
+set b.out.v 0
+cycle
+assert b.in.a 0
+assert b.in.v 0

test/unit_tests/fifo_demux_bit_7_fifo/test.act

@@ -0,0 +1,60 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+
+defproc fifo_demux_bit_7_fifo (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+
+    fifo<8,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+
+    demux_bit<7,0> demux(.in = fifo_pre.out);
+    //Low active Reset 
+
+    demux.supply.vss = GND;
+    demux.supply.vdd = Vdd;
+    demux.reset_B = _reset_B;
+
+    fifo<7,5> fifo_post1(.in = demux.out1, .out=out1, .reset_B = _reset_B, .supply = supply);
+    fifo<7,5> fifo_post2(.in = demux.out2, .out=out2, .reset_B = _reset_B, .supply = supply);
+
+
+}
+
+fifo_demux_bit_7_fifo b;

test/unit_tests/fifo_demux_bit_7_fifo/test.prsim

@@ -0,0 +1,70 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 8
+set b.out1.a 0
+set b.out1.v 0
+set b.out2.a 0
+set b.out2.v 0
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+set-qdi-channel-valid "b.in" 8 255
+cycle
+assert b.in.v 1
+assert b.in.a 1
+
+assert-qdi-channel-valid "b.out1" 7 127
+assert-qdi-channel-neutral "b.out2" 7
+set b.out1.v 1
+cycle
+assert b.in.a 1
+set-qdi-channel-neutral "b.in" 8
+cycle
+set b.out1.a 1
+
+
+system "echo 'First Cond Checked'"
+
+
+set Reset 0
+cycle
+system "echo 'System reset completed'"
+status X
+mode run
+
+assert-qdi-channel-neutral "b.out1" 7
+assert-qdi-channel-neutral "b.out2" 7
+assert-qdi-channel-neutral "b.in" 8
+cycle
+
+system "echo 'Output neutral checked'"
+
+set b.out1.a 0
+set b.out1.v 0
+set b.out2.a 0
+set b.out2.v 0
+cycle
+
+set-qdi-channel-valid "b.in" 8 100
+cycle
+assert b.in.v 1
+assert b.in.a 1
+
+assert-qdi-channel-valid "b.out2" 7 100
+assert-qdi-channel-neutral "b.out1" 7
+set b.out2.v 1
+cycle
+assert b.in.a 1
+set-qdi-channel-neutral "b.in" 7
+cycle
+
+
+system "echo 'Second Cond Checked'"

test/unit_tests/helper.scm

@@ -188,7 +188,7 @@
     )
   )
 
-  (define set-bd-channel-neutral
+(define set-bd-channel-neutral
   (lambda (ch width)
     (letrec ((ch-name (string-append ch ".d"))
          (helper
@@ -235,4 +235,27 @@
       )
     )
   )
+)
+
+(define set-bd-data-valid
+  (lambda (ch width val)
+    (letrec ((ch-name (string-append ch ".d"))
+         (helper
+          (lambda (i v)
+            (cond
+              ((=? i width) #t)
+              (#t (let ((tmp (string-append ch (string-append ".d[" (string-append (number->string i)  "]")))))
+                (begin
+                  (set tmp (% v 2))
+                  (helper (+ 1 i) (truncate (/ v 2)))
+                )
+              ))
+            )
+         )
+        ))
+      (begin
+        (helper 0 val)
+      )
+    )
+  )
 )

test/unit_tests/init_qdi.prsim

@@ -8,4 +8,3 @@ set Reset 1
 mode reset
 cycle
 status U
-

test/unit_tests/nrn_hs_2d.v

@@ -0,0 +1,204 @@
+//
+// Verilog module for: INV_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2P_U_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4(p1, p2, y);
+   input p1;
+   input p2;
+   output y;
+
+// -- signals ---
+   reg y;
+   wire p2;
+   wire p1;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: INV_X2<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0INV__X2(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C1N_RB_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1(y, c1, c2, n1, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input n1;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   wire sr_B;
+   reg y;
+   wire c2;
+   wire c1;
+   reg _y;
+   wire pr_B;
+   wire n1;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X2<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X2(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   reg _y;
+   wire a;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_1C1P_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
+   output y;
+   input c1;
+   input p1;
+
+// -- signals ---
+   wire c1;
+   wire p1;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C1P1N_RB_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1(y, c1, c2, p1, n1, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input p1;
+   input n1;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   wire sr_B;
+   wire n1;
+   wire p1;
+   wire c2;
+   reg y;
+   wire c1;
+   reg _y;
+   wire pr_B;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_3P_U_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4(p1, p2, p3, y);
+   input p1;
+   input p2;
+   input p3;
+   output y;
+
+// -- signals ---
+   wire p2;
+   wire p3;
+   wire p1;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: nrn_hs_2d<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B);
+   input \in.d.d[0] ;
+   output \in.a ;
+   output \outx.d.d[0] ;
+   input \outx.a ;
+   output \outy.d.d[0] ;
+   input \outy.a ;
+   input reset_B;
+
+// -- signals ---
+   reg \outx.d.d[0] ;
+   reg \in.a ;
+   reg _reqB;
+   reg \outy.d.d[0] ;
+   wire reset_B;
+   reg _y_a_B;
+   wire \outy.a ;
+   reg _x_a_B;
+   reg _reset_BX;
+   wire \in.d.d[0] ;
+   wire \outx.a ;
+   reg _en;
+   reg _req;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \req_inv  (.y(_reqB), .a(_req));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4 \pu_y  (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_x  (.y(_x_a_B), .a(\outx.a ));
+_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_y  (.y(_y_a_B), .a(\outy.a ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1 \A_ack  (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X2 \reset_buf  (.y(_reset_BX), .a(reset_B));
+_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \A_en  (.y(_en), .c1(\in.a ), .p1(_req));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1 \A_req  (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4 \pu_x  (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ));
+endmodule
+
+//
+// Verilog module for: nrn_hs_2d_inst<>
+//
+module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a );
+   input \in.d.d[0] ;
+   output \in.a ;
+   output \outx.d.d[0] ;
+   input \outx.a ;
+   output \outy.d.d[0] ;
+   input \outy.a ;
+
+// -- signals ---
+   reg \outx.d.d[0] ;
+   wire \outy.a ;
+   wire \in.d.d[0] ;
+   reg \outy.d.d[0] ;
+   reg _reset_B;
+   wire \outx.a ;
+   reg \in.a ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b  (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B));
+endmodule
+

test/unit_tests/nrn_hs_2d/test.act

@@ -0,0 +1,46 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc nrn_hs_2d_inst(a1of1 in; a1of1 outx, outy)
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+  nrn_hs_2d b(.in = in, .outx = outx, .outy = outy);
+  b.supply.vdd = Vdd;
+  b.supply.vss = GND; 
+  b.reset_B = _reset_B;
+}
+
+nrn_hs_2d_inst b;

test/unit_tests/nrn_hs_2d/test.prsim

@@ -0,0 +1,202 @@
+watchall
+
+set b.in[0].r 0
+set b.in[1].r 0
+set b.in[2].r 0
+set b.in[3].r 0
+set b.in[4].r 0
+set b.in[5].r 0
+set b.in[6].r 0
+set b.in[7].r 0
+set b.in[8].r 0
+set b.in[9].r 0
+set b.in[10].r 0
+set b.in[11].r 0
+set b.in[12].r 0
+set b.in[13].r 0
+set b.in[14].r 0
+
+set b.outx[0].a 0
+set b.outx[1].a 0
+set b.outx[2].a 0
+
+set b.outy[0].a 0
+set b.outy[1].a 0
+set b.outy[2].a 0
+set b.outy[3].a 0
+set b.outy[4].a 0
+
+set b.outx[0].r 1
+set b.outx[1].r 1
+set b.outx[2].r 1
+
+set b.outy[0].r 1
+set b.outy[1].r 1
+set b.outy[2].r 1
+set b.outy[3].r 1
+set b.outy[4].r 0
+
+set b.b.neurons[0]._en 0
+set b.b.neurons[0]._req 1
+
+# set Reset 0
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+status X
+
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+
+system "echo '[] Neurons 0,1,3 spike'"
+set b.in[0].r 1
+set b.in[1].r 1
+set b.in[3].r 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 1
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+assert b.in[0].a 1
+assert b.in[1].a 1
+assert b.in[3].a 1
+
+system "echo '[] removing in reqs'"
+set b.in[0].r 0
+set b.in[1].r 0
+set b.in[3].r 0
+cycle
+assert b.in[0].a 0
+assert b.in[1].a 0
+assert b.in[3].a 0
+
+
+system "echo '[] y0 chosen, give ack'"
+set b.outy[0].a 1
+cycle
+assert b.outx[0].r 1
+assert b.outx[1].r 1
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] x0 chosen, give ack'"
+set b.outx[0].a 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 1
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] remove x ack'"
+set b.outx[0].a 0
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 1
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] x1 remaining, give ack'"
+set b.outx[1].a 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] remove acks'"
+set b.outx[1].a 0
+set b.outy[0].a 0
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] y1 remaining, give ack'"
+set b.outy[1].a 1
+cycle
+assert b.outx[0].r 1
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] x0 req, give ack'"
+set b.outx[0].a 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+
+system "echo '[] remove acks'"
+set b.outx[0].a 0
+set b.outy[1].a 0
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+

test/unit_tests/nrn_hs_2d_clean.v

@@ -0,0 +1,107 @@
+//
+// Verilog module for: INV_X1<>
+//
+
+
+//
+// Verilog module for: A_2P_U_X4<>
+//
+
+
+//
+// Verilog module for: INV_X2<>
+//
+
+
+//
+// Verilog module for: A_2C1N_RB_X1<>
+//
+
+
+//
+// Verilog module for: BUF_X2<>
+//
+
+
+//
+// Verilog module for: A_1C1P_X1<>
+//
+
+
+//
+// Verilog module for: A_2C1P1N_RB_X1<>
+//
+
+
+//
+// Verilog module for: A_3P_U_X4<>
+//
+
+
+//
+// Verilog module for: nrn_hs_2d<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input \in.d.d[0] ;
+   output \in.a ;
+   output \outx.d.d[0] ;
+   input \outx.a ;
+   output \outy.d.d[0] ;
+   input \outy.a ;
+   input reset_B;
+
+// -- signals ---
+   reg \outx.d.d[0] ;
+   reg \in.a ;
+   reg _reqB;
+   reg \outy.d.d[0] ;
+   wire reset_B;
+   reg _y_a_B;
+   wire \outy.a ;
+   reg _x_a_B;
+   reg _reset_BX;
+   wire \in.d.d[0] ;
+   wire \outx.a ;
+   reg _en;
+   reg _req;
+
+// --- instances
+INV_X1 \req_inv  (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));
+A_2P_U_X4 \pu_y  (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ), .vdd(vdd), .vss(vss));
+INV_X2 \inv_x  (.y(_x_a_B), .a(\outx.a ), .vdd(vdd), .vss(vss));
+INV_X2 \inv_y  (.y(_y_a_B), .a(\outy.a ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X1 \A_ack  (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+BUF_X2 \reset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+A_1C1P_X1 \A_en  (.y(_en), .c1(\in.a ), .p1(_req), .vdd(vdd), .vss(vss));
+A_2C1P1N_RB_X1 \A_req  (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+A_3P_U_X4 \pu_x  (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ), .vdd(vdd), .vss(vss));
+endmodule
+
+//
+// Verilog module for: nrn_hs_2d_inst<>
+//
+module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , vdd, vss); 
+   input vdd;
+   input vss;
+   input \in.d.d[0] ;
+   output \in.a ;
+   output \outx.d.d[0] ;
+   input \outx.a ;
+   output \outy.d.d[0] ;
+   input \outy.a ;
+
+// -- signals ---
+   reg \outx.d.d[0] ;
+   wire \outy.a ;
+   wire \in.d.d[0] ;
+   reg \outy.d.d[0] ;
+   reg _reset_B;
+   wire \outx.a ;
+   reg \in.a ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b  (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
+endmodule
+

test/unit_tests/registerA_w/run/prsim.out

@@ -0,0 +1,418 @@
+b.b.gandalf_f[3].a b.b.gandalf_t[1].a b.b.gandalf_f[5].a b.b.gandalf_f[1].a b.b.gandalf_t[2].a b.b.gandalf_f[6].a b.b.gandalf_f[4].a b.b.gandalf_t[6].a b.b.gandalf_t[3].a b.b.gandalf_f[0].a b.b.gandalf_t[0].a b.b.gandalf_t[4].a b.b.gandalf_t[5].a b.b._w b.b.gandalf_f[2].a 
+	    169671 b.b.gandalf_f[0].a : 0
+	    169671 b.b._w : 0
+	    169671 b.in.d.d[7].f : 0
+	    169671 b.b.gandalf_t[6].a : 0
+	    169671 b.b.gandalf_f[6].a : 0
+	    169671 b.b.gandalf_t[5].a : 0
+	    169671 b.b.gandalf_f[5].a : 0
+	    169671 b.b.gandalf_t[4].a : 0
+	    169671 b.b.gandalf_f[4].a : 0
+	    169671 b.b.gandalf_t[3].a : 0
+	    169671 b.b.gandalf_f[3].a : 0
+	    169671 b.b.gandalf_t[2].a : 0
+	    169671 b.b.gandalf_f[2].a : 0
+	    169671 b.b.gandalf_t[1].a : 0
+	    169671 b.b.gandalf_f[1].a : 0
+	    169671 b.b.gandalf_t[0].a : 0
+[] Set reset 0
+
+	    169671 Reset : 0
+	    170041 b._reset_B : 1  [by Reset:=0]
+	    170108 b.b.buf.reset_buf._y : 0  [by b._reset_B:=1]
+	    170124 b.b.buf._reset_BX : 1  [by b.b.buf.reset_buf._y:=0]
+	    172682 b.b.buf._reset : 0  [by b._reset_B:=1]
+	    174686 b.b.buf.reset_bufarray.buf2._y : 0  [by b.b.buf._reset_BX:=1]
+	    175214 b.b.buf._reset_BXX[0] : 1  [by b.b.buf.reset_bufarray.buf2._y:=0]
+[] Sending in 127
+	    175214 b.b.gandalf_t[0].a : 1
+	    175214 b.b._w : 1
+	    175214 b.b.gandalf_t[6].a : 1
+	    175214 b.b.gandalf_t[2].a : 1
+	    175214 b.b.gandalf_t[5].a : 1
+	    175214 b.b.gandalf_t[4].a : 1
+	    175214 b.b.gandalf_t[3].a : 1
+	    175214 b.b.gandalf_t[1].a : 1
+	    177649 b.b.A_flush._y : 0  [by b.b._w:=1]
+	    204529 b.b._flush : 1  [by b.b.A_flush._y:=0]
+	    217570 b.b.buf._flushB : 0  [by b.b._flush:=1]
+	    217572 b.b.buf.t_buf_func[0]._y : 1  [by b.b.buf._flushB:=0]
+	    217573 b.b.buf.t_buf_func[2]._y : 1  [by b.b.buf._flushB:=0]
+	    217599 b.b.buf.t_buf_func[3]._y : 1  [by b.b.buf._flushB:=0]
+	    217616 b.out.d[0].t : 0  [by b.b.buf.t_buf_func[0]._y:=1]
+	    217617 b.b.out_valid.OR2_tf[0]._y : 1  [by b.out.d[0].t:=0]
+	    217723 b.b.buf.t_buf_func[6]._y : 1  [by b.b.buf._flushB:=0]
+	    217745 b.out.d[6].t : 0  [by b.b.buf.t_buf_func[6]._y:=1]
+	    217746 b.b.out_valid.OR2_tf[6]._y : 1  [by b.out.d[6].t:=0]
+	    217834 b.b.out_valid.ct.in[0] : 0  [by b.b.out_valid.OR2_tf[0]._y:=1]
+	    217887 b.b.buf.t_buf_func[4]._y : 1  [by b.b.buf._flushB:=0]
+	    219171 b.b.buf.t_buf_func[5]._y : 1  [by b.b.buf._flushB:=0]
+	    219327 b.b.out_valid.ct.in[6] : 0  [by b.b.out_valid.OR2_tf[6]._y:=1]
+	    219330 b.out.d[5].t : 0  [by b.b.buf.t_buf_func[5]._y:=1]
+	    220334 b.out.d[2].t : 0  [by b.b.buf.t_buf_func[2]._y:=1]
+	    221621 b.b.out_valid.OR2_tf[2]._y : 1  [by b.out.d[2].t:=0]
+	    223853 b.b.out_valid.ct.in[2] : 0  [by b.b.out_valid.OR2_tf[2]._y:=1]
+	    227232 b.out.d[4].t : 0  [by b.b.buf.t_buf_func[4]._y:=1]
+	    227377 b.b.out_valid.OR2_tf[4]._y : 1  [by b.out.d[4].t:=0]
+	    228454 b.b._flushB : 0  [by b.b._flush:=1]
+	    230209 b.b.out_valid.ct.in[4] : 0  [by b.b.out_valid.OR2_tf[4]._y:=1]
+	    231282 b.out.d[3].t : 0  [by b.b.buf.t_buf_func[3]._y:=1]
+	    237636 b.b.out_valid.OR2_tf[3]._y : 1  [by b.out.d[3].t:=0]
+	    237637 b.b.out_valid.ct.in[3] : 0  [by b.b.out_valid.OR2_tf[3]._y:=1]
+	    239006 b.b.out_valid.OR2_tf[5]._y : 1  [by b.out.d[5].t:=0]
+	    239168 b.b.out_valid.ct.in[5] : 0  [by b.b.out_valid.OR2_tf[5]._y:=1]
+	    246537 b.b.out_valid.ct.C3Els[0]._y : 1  [by b.b.out_valid.ct.in[5]:=0]
+	    246551 b.b.out_valid.ct.tmp[9] : 0  [by b.b.out_valid.ct.C3Els[0]._y:=1]
+	    276921 b.b.out_valid.ct.C2Els[1]._y : 1  [by b.b.out_valid.ct.in[3]:=0]
+	    276928 b.b.out_valid.ct.tmp[8] : 0  [by b.b.out_valid.ct.C2Els[1]._y:=1]
+	    278528 b.b.buf.t_buf_func[1]._y : 1  [by b.b.buf._flushB:=0]
+	    278688 b.out.d[1].t : 0  [by b.b.buf.t_buf_func[1]._y:=1]
+	    300245 b.b.out_valid.OR2_tf[1]._y : 1  [by b.out.d[1].t:=0]
+	    300246 b.b.out_valid.ct.in[1] : 0  [by b.b.out_valid.OR2_tf[1]._y:=1]
+	    300247 b.b.out_valid.ct.C2Els[0]._y : 1  [by b.b.out_valid.ct.in[1]:=0]
+	    300248 b.b.out_valid.ct.tmp[7] : 0  [by b.b.out_valid.ct.C2Els[0]._y:=1]
+	    302491 b.b.out_valid.ct.C3Els[1]._y : 1  [by b.b.out_valid.ct.tmp[7]:=0]
+	    302678 b.b._out_v : 0  [by b.b.out_valid.ct.C3Els[1]._y:=1]
+	    302679 b.b._out_vB : 1  [by b.b._out_v:=0]
+	    306861 b.b._en2 : 0  [by b.b._out_vB:=1]
+	    341643 b.b.A_flush._y : 1  [by b.b._en2:=0]
+	    341644 b.b._flush : 0  [by b.b.A_flush._y:=1]
+	    341649 b.b._flushB : 1  [by b.b._flush:=0]
+	    342497 b.b.pass.y : 1  [by b.b._flush:=0]
+	    342498 b.b.gandalf_t[0]._y : 0  [by b.b.pass.y:=1]
+	    342499 b.b.gandalf_t[0].y : 1  [by b.b.gandalf_t[0]._y:=0]
+	    342500 b.b.gandalf_t[4]._y : 0  [by b.b.pass.y:=1]
+	    342514 b.b.gandalf_t[1]._y : 0  [by b.b.pass.y:=1]
+	    342535 b.b.buf._flushB : 1  [by b.b._flush:=0]
+	    342541 b.b.buf.vc.OR2_tf[0]._y : 0  [by b.b.gandalf_t[0].y:=1]
+	    342630 b.b.buf.t_buf_func[0]._y : 0  [by b.b.buf._flushB:=1]
+	    342638 b.out.d[0].t : 1  [by b.b.buf.t_buf_func[0]._y:=0]
+	    342672 b.b.out_valid.OR2_tf[0]._y : 0  [by b.out.d[0].t:=1]
+	    342876 b.b.buf.vc.ct.in[0] : 1  [by b.b.buf.vc.OR2_tf[0]._y:=0]
+	    343438 b.b.gandalf_t[5]._y : 0  [by b.b.pass.y:=1]
+	    344356 b.b.gandalf_t[5].y : 1  [by b.b.gandalf_t[5]._y:=0]
+	    344360 b.b.buf.vc.OR2_tf[5]._y : 0  [by b.b.gandalf_t[5].y:=1]
+	    345070 b.b.gandalf_t[2]._y : 0  [by b.b.pass.y:=1]
+	    345317 b.b.gandalf_t[4].y : 1  [by b.b.gandalf_t[4]._y:=0]
+	    345365 b.b.buf.t_buf_func[4]._y : 0  [by b.b.gandalf_t[4].y:=1]
+	    345368 b.out.d[4].t : 1  [by b.b.buf.t_buf_func[4]._y:=0]
+	    345546 b.b.out_valid.OR2_tf[4]._y : 0  [by b.out.d[4].t:=1]
+	    346758 b.b.buf.vc.ct.in[5] : 1  [by b.b.buf.vc.OR2_tf[5]._y:=0]
+	    348285 b.b.gandalf_t[2].y : 1  [by b.b.gandalf_t[2]._y:=0]
+	    350858 b.b.gandalf_t[3]._y : 0  [by b.b.pass.y:=1]
+	    354236 b.b.buf.t_buf_func[2]._y : 0  [by b.b.gandalf_t[2].y:=1]
+	    355063 b.out.d[2].t : 1  [by b.b.buf.t_buf_func[2]._y:=0]
+	    355236 b.b.out_valid.OR2_tf[2]._y : 0  [by b.out.d[2].t:=1]
+	    355420 b.b.out_valid.ct.in[2] : 1  [by b.b.out_valid.OR2_tf[2]._y:=0]
+	    356247 b.b.gandalf_t[1].y : 1  [by b.b.gandalf_t[1]._y:=0]
+	    356248 b.b.buf.vc.OR2_tf[1]._y : 0  [by b.b.gandalf_t[1].y:=1]
+	    356252 b.b.buf.vc.ct.in[1] : 1  [by b.b.buf.vc.OR2_tf[1]._y:=0]
+	    356320 b.b.buf.t_buf_func[1]._y : 0  [by b.b.gandalf_t[1].y:=1]
+	    356416 b.out.d[1].t : 1  [by b.b.buf.t_buf_func[1]._y:=0]
+	    356552 b.b.out_valid.OR2_tf[1]._y : 0  [by b.out.d[1].t:=1]
+	    356553 b.b.out_valid.ct.in[1] : 1  [by b.b.out_valid.OR2_tf[1]._y:=0]
+	    356559 b.b.out_valid.ct.in[0] : 1  [by b.b.out_valid.OR2_tf[0]._y:=0]
+	    360184 b.b.buf.vc.OR2_tf[2]._y : 0  [by b.b.gandalf_t[2].y:=1]
+	    360425 b.b.buf.vc.ct.in[2] : 1  [by b.b.buf.vc.OR2_tf[2]._y:=0]
+	    366523 b.b.out_valid.ct.in[4] : 1  [by b.b.out_valid.OR2_tf[4]._y:=0]
+	    375605 b.b.out_valid.ct.C2Els[0]._y : 0  [by b.b.out_valid.ct.in[0]:=1]
+	    379564 b.b.out_valid.ct.tmp[7] : 1  [by b.b.out_valid.ct.C2Els[0]._y:=0]
+	    390343 b.b.gandalf_t[3].y : 1  [by b.b.gandalf_t[3]._y:=0]
+	    390355 b.b.buf.vc.OR2_tf[3]._y : 0  [by b.b.gandalf_t[3].y:=1]
+	    390734 b.b.buf.t_buf_func[5]._y : 0  [by b.b.gandalf_t[5].y:=1]
+	    390735 b.out.d[5].t : 1  [by b.b.buf.t_buf_func[5]._y:=0]
+	    390791 b.b.out_valid.OR2_tf[5]._y : 0  [by b.out.d[5].t:=1]
+	    391384 b.b.buf.vc.ct.in[3] : 1  [by b.b.buf.vc.OR2_tf[3]._y:=0]
+	    391385 b.b.buf.vc.ct.C2Els[1]._y : 0  [by b.b.buf.vc.ct.in[3]:=1]
+	    391422 b.b.buf.vc.ct.tmp[8] : 1  [by b.b.buf.vc.ct.C2Els[1]._y:=0]
+	    392436 b.b.buf.vc.OR2_tf[4]._y : 0  [by b.b.gandalf_t[4].y:=1]
+	    393540 b.b.buf.vc.ct.C2Els[0]._y : 0  [by b.b.buf.vc.ct.in[1]:=1]
+	    393541 b.b.buf.vc.ct.tmp[7] : 1  [by b.b.buf.vc.ct.C2Els[0]._y:=0]
+	    394243 b.b.buf.t_buf_func[3]._y : 0  [by b.b.gandalf_t[3].y:=1]
+	    397807 b.out.d[3].t : 1  [by b.b.buf.t_buf_func[3]._y:=0]
+	    399499 b.b.out_valid.OR2_tf[3]._y : 0  [by b.out.d[3].t:=1]
+	    399512 b.b.out_valid.ct.in[3] : 1  [by b.b.out_valid.OR2_tf[3]._y:=0]
+	    401459 b.b.gandalf_t[6]._y : 0  [by b.b.pass.y:=1]
+	    401816 b.b.gandalf_t[6].y : 1  [by b.b.gandalf_t[6]._y:=0]
+	    401837 b.b.buf.t_buf_func[6]._y : 0  [by b.b.gandalf_t[6].y:=1]
+	    401838 b.out.d[6].t : 1  [by b.b.buf.t_buf_func[6]._y:=0]
+	    401841 b.b.buf.vc.OR2_tf[6]._y : 0  [by b.b.gandalf_t[6].y:=1]
+	    401842 b.b.buf.vc.ct.in[6] : 1  [by b.b.buf.vc.OR2_tf[6]._y:=0]
+	    411486 b.b.out_valid.OR2_tf[6]._y : 0  [by b.out.d[6].t:=1]
+	    411487 b.b.out_valid.ct.in[6] : 1  [by b.b.out_valid.OR2_tf[6]._y:=0]
+	    415811 b.b.buf.vc.ct.in[4] : 1  [by b.b.buf.vc.OR2_tf[4]._y:=0]
+	    415972 b.b.buf.vc.ct.C3Els[0]._y : 0  [by b.b.buf.vc.ct.in[4]:=1]
+	    416496 b.b.out_valid.ct.C2Els[1]._y : 0  [by b.b.out_valid.ct.in[3]:=1]
+	    416501 b.b.out_valid.ct.tmp[8] : 1  [by b.b.out_valid.ct.C2Els[1]._y:=0]
+	    417009 b.b.buf.vc.ct.tmp[9] : 1  [by b.b.buf.vc.ct.C3Els[0]._y:=0]
+	    417590 b.b.buf.vc.ct.C3Els[1]._y : 0  [by b.b.buf.vc.ct.tmp[9]:=1]
+	    417998 b.b.buf._in_v : 1  [by b.b.buf.vc.ct.C3Els[1]._y:=0]
+	    418009 b.b.buf.in_v_buf._y : 0  [by b.b.buf._in_v:=1]
+	    419056 b.in.v : 1  [by b.b.buf.in_v_buf._y:=0]
+	    435797 b.b.out_valid.ct.in[5] : 1  [by b.b.out_valid.OR2_tf[5]._y:=0]
+	    435811 b.b.out_valid.ct.C3Els[0]._y : 0  [by b.b.out_valid.ct.in[5]:=1]
+	    435829 b.b.out_valid.ct.tmp[9] : 1  [by b.b.out_valid.ct.C3Els[0]._y:=0]
+	    435833 b.b.out_valid.ct.C3Els[1]._y : 0  [by b.b.out_valid.ct.tmp[9]:=1]
+	    435937 b.b._out_v : 1  [by b.b.out_valid.ct.C3Els[1]._y:=0]
+	    437141 b.b.buf._en : 0  [by b.b._out_v:=1]
+	    437369 b.b.buf.en_buf_f.buf2._y : 1  [by b.b.buf._en:=0]
+	    437984 b.b.buf.en_buf_t.buf2._y : 1  [by b.b.buf._en:=0]
+	    438054 b.b.buf._en_X_t[0] : 0  [by b.b.buf.en_buf_t.buf2._y:=1]
+	    438828 b.b.buf._en_X_f[0] : 0  [by b.b.buf.en_buf_f.buf2._y:=1]
+	    445596 b.b.in_ack_inv.a : 1  [by b.b.buf._en:=0]
+	    467381 b.b._out_vB : 0  [by b.b._out_v:=1]
+	    496018 b.b.in_ack_inv.y : 0  [by b.b.in_ack_inv.a:=1]
+	    496029 b.in.a : 1  [by b.b.in_ack_inv.y:=0]
+[] Removing input
+	    496029 b.b.gandalf_t[0].a : 0
+	    496029 b.b._w : 0
+	    496029 b.b.gandalf_t[2].a : 0
+	    496029 b.b.gandalf_t[6].a : 0
+	    496029 b.b.gandalf_t[5].a : 0
+	    496029 b.b.gandalf_t[1].a : 0
+	    496029 b.b.gandalf_t[4].a : 0
+	    496029 b.b.gandalf_t[3].a : 0
+	    496032 b.b.gandalf_t[0]._y : 1  [by b.b.gandalf_t[0].a:=0]
+	    496083 b.b._en2 : 1  [by b.b._w:=0]
+	    496110 b.b.gandalf_t[1]._y : 1  [by b.b.gandalf_t[1].a:=0]
+	    496124 b.b.gandalf_t[0].y : 0  [by b.b.gandalf_t[0]._y:=1]
+	    496737 b.b.buf.vc.OR2_tf[0]._y : 1  [by b.b.gandalf_t[0].y:=0]
+	    497177 b.b.gandalf_t[2]._y : 1  [by b.b.gandalf_t[2].a:=0]
+	    497190 b.b.gandalf_t[6]._y : 1  [by b.b.gandalf_t[6].a:=0]
+	    497222 b.b.gandalf_t[2].y : 0  [by b.b.gandalf_t[2]._y:=1]
+	    497854 b.b.gandalf_t[1].y : 0  [by b.b.gandalf_t[1]._y:=1]
+	    498187 b.b.gandalf_t[6].y : 0  [by b.b.gandalf_t[6]._y:=1]
+	    498379 b.b.buf.vc.OR2_tf[1]._y : 1  [by b.b.gandalf_t[1].y:=0]
+	    498431 b.b.buf.vc.ct.in[1] : 0  [by b.b.buf.vc.OR2_tf[1]._y:=1]
+	    498871 b.b.buf.vc.OR2_tf[2]._y : 1  [by b.b.gandalf_t[2].y:=0]
+	    498878 b.b.buf.vc.ct.in[2] : 0  [by b.b.buf.vc.OR2_tf[2]._y:=1]
+	    499087 b.b.buf.vc.OR2_tf[6]._y : 1  [by b.b.gandalf_t[6].y:=0]
+	    504394 b.b.pass.y : 0  [by b.b._en2:=1]
+	    504681 b.b.gandalf_t[5]._y : 1  [by b.b.gandalf_t[5].a:=0]
+	    507106 b.b.gandalf_t[4]._y : 1  [by b.b.gandalf_t[4].a:=0]
+	    507108 b.b.gandalf_t[4].y : 0  [by b.b.gandalf_t[4]._y:=1]
+	    507462 b.b.buf.vc.OR2_tf[4]._y : 1  [by b.b.gandalf_t[4].y:=0]
+	    507595 b.b.buf.vc.ct.in[4] : 0  [by b.b.buf.vc.OR2_tf[4]._y:=1]
+	    510759 b.b.buf.vc.ct.in[0] : 0  [by b.b.buf.vc.OR2_tf[0]._y:=1]
+	    510760 b.b.buf.vc.ct.C2Els[0]._y : 1  [by b.b.buf.vc.ct.in[0]:=0]
+	    510764 b.b.buf.vc.ct.tmp[7] : 0  [by b.b.buf.vc.ct.C2Els[0]._y:=1]
+	    511148 b.b.gandalf_t[5].y : 0  [by b.b.gandalf_t[5]._y:=1]
+	    511694 b.b.buf.vc.OR2_tf[5]._y : 1  [by b.b.gandalf_t[5].y:=0]
+	    514012 b.b.gandalf_t[3]._y : 1  [by b.b.gandalf_t[3].a:=0]
+	    514013 b.b.gandalf_t[3].y : 0  [by b.b.gandalf_t[3]._y:=1]
+	    514699 b.b.buf.vc.ct.in[6] : 0  [by b.b.buf.vc.OR2_tf[6]._y:=1]
+	    526391 b.b.buf.vc.OR2_tf[3]._y : 1  [by b.b.gandalf_t[3].y:=0]
+	    526470 b.b.buf.vc.ct.in[3] : 0  [by b.b.buf.vc.OR2_tf[3]._y:=1]
+	    528903 b.b.buf.vc.ct.C2Els[1]._y : 1  [by b.b.buf.vc.ct.in[3]:=0]
+	    528991 b.b.buf.vc.ct.tmp[8] : 0  [by b.b.buf.vc.ct.C2Els[1]._y:=1]
+	    557257 b.b.buf.vc.ct.in[5] : 0  [by b.b.buf.vc.OR2_tf[5]._y:=1]
+	    565039 b.b.buf.vc.ct.C3Els[0]._y : 1  [by b.b.buf.vc.ct.in[5]:=0]
+	    593366 b.b.buf.vc.ct.tmp[9] : 0  [by b.b.buf.vc.ct.C3Els[0]._y:=1]
+	    593425 b.b.buf.vc.ct.C3Els[1]._y : 1  [by b.b.buf.vc.ct.tmp[9]:=0]
+	    593455 b.b.buf._in_v : 0  [by b.b.buf.vc.ct.C3Els[1]._y:=1]
+	    594922 b.b.buf.in_v_buf._y : 1  [by b.b.buf._in_v:=0]
+	    654426 b.in.v : 0  [by b.b.buf.in_v_buf._y:=1]
+	    673810 b.b.buf._en : 1  [by b.in.v:=0]
+	    673937 b.b.buf.en_buf_t.buf2._y : 0  [by b.b.buf._en:=1]
+	    674106 b.b.buf._en_X_t[0] : 1  [by b.b.buf.en_buf_t.buf2._y:=0]
+	    674495 b.b.in_ack_inv.a : 0  [by b.b.buf._en:=1]
+	    674538 b.b.in_ack_inv.y : 1  [by b.b.in_ack_inv.a:=0]
+	    674550 b.in.a : 0  [by b.b.in_ack_inv.y:=1]
+	    690525 b.b.buf.en_buf_f.buf2._y : 0  [by b.b.buf._en:=1]
+	    691804 b.b.buf._en_X_f[0] : 1  [by b.b.buf.en_buf_f.buf2._y:=0]
+[] Sending in 35
+	    691804 b.b.gandalf_t[0].a : 1
+	    691804 b.b._w : 1
+	    691804 b.b.gandalf_f[6].a : 1
+	    691804 b.b.gandalf_f[2].a : 1
+	    691804 b.b.gandalf_t[5].a : 1
+	    691804 b.b.gandalf_f[4].a : 1
+	    691804 b.b.gandalf_f[3].a : 1
+	    691804 b.b.gandalf_t[1].a : 1
+	    692037 b.b.A_flush._y : 0  [by b.b._w:=1]
+	    692040 b.b._flush : 1  [by b.b.A_flush._y:=0]
+	    692041 b.b.buf._flushB : 0  [by b.b._flush:=1]
+	    692042 b.b.buf.t_buf_func[4]._y : 1  [by b.b.buf._flushB:=0]
+	    692043 b.b.buf.t_buf_func[3]._y : 1  [by b.b.buf._flushB:=0]
+	    692043 b.b.buf.t_buf_func[6]._y : 1  [by b.b.buf._flushB:=0]
+	    692060 b.out.d[4].t : 0  [by b.b.buf.t_buf_func[4]._y:=1]
+	    692068 b.b.out_valid.OR2_tf[4]._y : 1  [by b.out.d[4].t:=0]
+	    692078 b.b._flushB : 0  [by b.b._flush:=1]
+	    692122 b.b.out_valid.ct.in[4] : 0  [by b.b.out_valid.OR2_tf[4]._y:=1]
+	    692133 b.b.buf.t_buf_func[1]._y : 1  [by b.b.buf._flushB:=0]
+	    692162 b.out.d[3].t : 0  [by b.b.buf.t_buf_func[3]._y:=1]
+	    692167 b.b.out_valid.OR2_tf[3]._y : 1  [by b.out.d[3].t:=0]
+	    693234 b.b.out_valid.ct.in[3] : 0  [by b.b.out_valid.OR2_tf[3]._y:=1]
+	    693542 b.b.buf.t_buf_func[5]._y : 1  [by b.b.buf._flushB:=0]
+	    693543 b.out.d[5].t : 0  [by b.b.buf.t_buf_func[5]._y:=1]
+	    693681 b.b.out_valid.OR2_tf[5]._y : 1  [by b.out.d[5].t:=0]
+	    693682 b.b.out_valid.ct.in[5] : 0  [by b.b.out_valid.OR2_tf[5]._y:=1]
+	    694768 b.b.buf.t_buf_func[2]._y : 1  [by b.b.buf._flushB:=0]
+	    694832 b.out.d[2].t : 0  [by b.b.buf.t_buf_func[2]._y:=1]
+	    694955 b.b.out_valid.OR2_tf[2]._y : 1  [by b.out.d[2].t:=0]
+	    694957 b.b.out_valid.ct.in[2] : 0  [by b.b.out_valid.OR2_tf[2]._y:=1]
+	    694994 b.b.out_valid.ct.C2Els[1]._y : 1  [by b.b.out_valid.ct.in[2]:=0]
+	    695137 b.b.out_valid.ct.tmp[8] : 0  [by b.b.out_valid.ct.C2Els[1]._y:=1]
+	    697763 b.out.d[6].t : 0  [by b.b.buf.t_buf_func[6]._y:=1]
+	    697814 b.b.out_valid.OR2_tf[6]._y : 1  [by b.out.d[6].t:=0]
+	    698256 b.b.out_valid.ct.in[6] : 0  [by b.b.out_valid.OR2_tf[6]._y:=1]
+	    698267 b.b.out_valid.ct.C3Els[0]._y : 1  [by b.b.out_valid.ct.in[6]:=0]
+	    698268 b.b.out_valid.ct.tmp[9] : 0  [by b.b.out_valid.ct.C3Els[0]._y:=1]
+	    704793 b.b.buf.t_buf_func[0]._y : 1  [by b.b.buf._flushB:=0]
+	    704802 b.out.d[0].t : 0  [by b.b.buf.t_buf_func[0]._y:=1]
+	    704827 b.b.out_valid.OR2_tf[0]._y : 1  [by b.out.d[0].t:=0]
+	    715080 b.b.out_valid.ct.in[0] : 0  [by b.b.out_valid.OR2_tf[0]._y:=1]
+	    742671 b.out.d[1].t : 0  [by b.b.buf.t_buf_func[1]._y:=1]
+	    746192 b.b.out_valid.OR2_tf[1]._y : 1  [by b.out.d[1].t:=0]
+	    746337 b.b.out_valid.ct.in[1] : 0  [by b.b.out_valid.OR2_tf[1]._y:=1]
+	    762505 b.b.out_valid.ct.C2Els[0]._y : 1  [by b.b.out_valid.ct.in[1]:=0]
+	    762735 b.b.out_valid.ct.tmp[7] : 0  [by b.b.out_valid.ct.C2Els[0]._y:=1]
+	    763426 b.b.out_valid.ct.C3Els[1]._y : 1  [by b.b.out_valid.ct.tmp[7]:=0]
+	    763440 b.b._out_v : 0  [by b.b.out_valid.ct.C3Els[1]._y:=1]
+	    764983 b.b._out_vB : 1  [by b.b._out_v:=0]
+	    766594 b.b._en2 : 0  [by b.b._out_vB:=1]
+	    784106 b.b.A_flush._y : 1  [by b.b._en2:=0]
+	    784117 b.b._flush : 0  [by b.b.A_flush._y:=1]
+	    784118 b.b.pass.y : 1  [by b.b._flush:=0]
+	    784118 b.b._flushB : 1  [by b.b._flush:=0]
+	    784119 b.b.gandalf_f[6]._y : 0  [by b.b.pass.y:=1]
+	    784122 b.b.gandalf_f[6].y : 1  [by b.b.gandalf_f[6]._y:=0]
+	    784135 b.b.gandalf_t[0]._y : 0  [by b.b.pass.y:=1]
+	    784141 b.b.gandalf_t[0].y : 1  [by b.b.gandalf_t[0]._y:=0]
+	    784250 b.b.gandalf_f[4]._y : 0  [by b.b.pass.y:=1]
+	    784270 b.b.gandalf_t[1]._y : 0  [by b.b.pass.y:=1]
+	    784546 b.b.buf.vc.OR2_tf[6]._y : 0  [by b.b.gandalf_f[6].y:=1]
+	    784757 b.b.gandalf_f[2]._y : 0  [by b.b.pass.y:=1]
+	    784759 b.b.gandalf_f[2].y : 1  [by b.b.gandalf_f[2]._y:=0]
+	    784953 b.b.buf.vc.OR2_tf[2]._y : 0  [by b.b.gandalf_f[2].y:=1]
+	    785100 b.b.gandalf_t[1].y : 1  [by b.b.gandalf_t[1]._y:=0]
+	    785238 b.b.buf.vc.OR2_tf[1]._y : 0  [by b.b.gandalf_t[1].y:=1]
+	    785255 b.b.buf.vc.ct.in[1] : 1  [by b.b.buf.vc.OR2_tf[1]._y:=0]
+	    785556 b.b.buf.vc.ct.in[2] : 1  [by b.b.buf.vc.OR2_tf[2]._y:=0]
+	    785911 b.b.gandalf_f[3]._y : 0  [by b.b.pass.y:=1]
+	    785928 b.b.gandalf_f[3].y : 1  [by b.b.gandalf_f[3]._y:=0]
+	    786354 b.b.buf.vc.OR2_tf[3]._y : 0  [by b.b.gandalf_f[3].y:=1]
+	    786355 b.b.buf.vc.ct.in[3] : 1  [by b.b.buf.vc.OR2_tf[3]._y:=0]
+	    786356 b.b.buf.vc.ct.C2Els[1]._y : 0  [by b.b.buf.vc.ct.in[3]:=1]
+	    786711 b.b.gandalf_f[4].y : 1  [by b.b.gandalf_f[4]._y:=0]
+	    786712 b.b.buf.vc.OR2_tf[4]._y : 0  [by b.b.gandalf_f[4].y:=1]
+	    786729 b.b.buf.vc.OR2_tf[0]._y : 0  [by b.b.gandalf_t[0].y:=1]
+	    786731 b.b.buf.vc.ct.in[4] : 1  [by b.b.buf.vc.OR2_tf[4]._y:=0]
+	    786897 b.b.buf.vc.ct.in[0] : 1  [by b.b.buf.vc.OR2_tf[0]._y:=0]
+	    787101 b.b.gandalf_t[5]._y : 0  [by b.b.pass.y:=1]
+	    787262 b.b.gandalf_t[5].y : 1  [by b.b.gandalf_t[5]._y:=0]
+	    787382 b.b.buf.vc.ct.tmp[8] : 1  [by b.b.buf.vc.ct.C2Els[1]._y:=0]
+	    787435 b.b.buf.vc.OR2_tf[5]._y : 0  [by b.b.gandalf_t[5].y:=1]
+	    787436 b.b.buf.vc.ct.C2Els[0]._y : 0  [by b.b.buf.vc.ct.in[0]:=1]
+	    789982 b.b.buf.vc.ct.in[5] : 1  [by b.b.buf.vc.OR2_tf[5]._y:=0]
+	    790618 b.b.buf._flushB : 1  [by b.b._flush:=0]
+	    790619 b.b.buf.t_buf_func[0]._y : 0  [by b.b.buf._flushB:=1]
+	    790619 b.b.buf.t_buf_func[1]._y : 0  [by b.b.buf._flushB:=1]
+	    790623 b.out.d[1].t : 1  [by b.b.buf.t_buf_func[1]._y:=0]
+	    790625 b.b.buf.f_buf_func[6]._y : 0  [by b.b.buf._flushB:=1]
+	    790646 b.b.buf.f_buf_func[4]._y : 0  [by b.b.buf._flushB:=1]
+	    790812 b.out.d[4].f : 1  [by b.b.buf.f_buf_func[4]._y:=0]
+	    790825 b.b.buf.f_buf_func[2]._y : 0  [by b.b.buf._flushB:=1]
+	    791008 b.b.buf.t_buf_func[5]._y : 0  [by b.b.buf._flushB:=1]
+	    791033 b.out.d[0].t : 1  [by b.b.buf.t_buf_func[0]._y:=0]
+	    791451 b.b.buf.f_buf_func[3]._y : 0  [by b.b.buf._flushB:=1]
+	    791590 b.out.d[3].f : 1  [by b.b.buf.f_buf_func[3]._y:=0]
+	    791889 b.b.out_valid.OR2_tf[0]._y : 0  [by b.out.d[0].t:=1]
+	    791941 b.out.d[5].t : 1  [by b.b.buf.t_buf_func[5]._y:=0]
+	    791943 b.b.out_valid.OR2_tf[5]._y : 0  [by b.out.d[5].t:=1]
+	    792084 b.b.out_valid.ct.in[0] : 1  [by b.b.out_valid.OR2_tf[0]._y:=0]
+	    792402 b.b.out_valid.OR2_tf[1]._y : 0  [by b.out.d[1].t:=1]
+	    792408 b.b.out_valid.ct.in[1] : 1  [by b.b.out_valid.OR2_tf[1]._y:=0]
+	    792662 b.b.out_valid.ct.C2Els[0]._y : 0  [by b.b.out_valid.ct.in[1]:=1]
+	    792670 b.b.out_valid.ct.tmp[7] : 1  [by b.b.out_valid.ct.C2Els[0]._y:=0]
+	    799470 b.out.d[2].f : 1  [by b.b.buf.f_buf_func[2]._y:=0]
+	    799471 b.b.out_valid.OR2_tf[2]._y : 0  [by b.out.d[2].f:=1]
+	    799477 b.b.out_valid.ct.in[2] : 1  [by b.b.out_valid.OR2_tf[2]._y:=0]
+	    802497 b.b.buf.vc.ct.tmp[7] : 1  [by b.b.buf.vc.ct.C2Els[0]._y:=0]
+	    807478 b.b.buf.vc.ct.in[6] : 1  [by b.b.buf.vc.OR2_tf[6]._y:=0]
+	    813499 b.out.d[6].f : 1  [by b.b.buf.f_buf_func[6]._y:=0]
+	    816589 b.b.out_valid.OR2_tf[6]._y : 0  [by b.out.d[6].f:=1]
+	    816815 b.b.out_valid.ct.in[6] : 1  [by b.b.out_valid.OR2_tf[6]._y:=0]
+	    817799 b.b.out_valid.OR2_tf[3]._y : 0  [by b.out.d[3].f:=1]
+	    818618 b.b.out_valid.ct.in[3] : 1  [by b.b.out_valid.OR2_tf[3]._y:=0]
+	    818619 b.b.out_valid.ct.C2Els[1]._y : 0  [by b.b.out_valid.ct.in[3]:=1]
+	    818625 b.b.out_valid.ct.tmp[8] : 1  [by b.b.out_valid.ct.C2Els[1]._y:=0]
+	    830682 b.b.out_valid.OR2_tf[4]._y : 0  [by b.out.d[4].f:=1]
+	    830684 b.b.out_valid.ct.in[4] : 1  [by b.b.out_valid.OR2_tf[4]._y:=0]
+	    845392 b.b.out_valid.ct.in[5] : 1  [by b.b.out_valid.OR2_tf[5]._y:=0]
+	    848954 b.b.out_valid.ct.C3Els[0]._y : 0  [by b.b.out_valid.ct.in[5]:=1]
+	    848969 b.b.out_valid.ct.tmp[9] : 1  [by b.b.out_valid.ct.C3Els[0]._y:=0]
+	    858514 b.b.buf.vc.ct.C3Els[0]._y : 0  [by b.b.buf.vc.ct.in[6]:=1]
+	    858621 b.b.buf.vc.ct.tmp[9] : 1  [by b.b.buf.vc.ct.C3Els[0]._y:=0]
+	    858714 b.b.buf.vc.ct.C3Els[1]._y : 0  [by b.b.buf.vc.ct.tmp[9]:=1]
+	    860366 b.b.buf._in_v : 1  [by b.b.buf.vc.ct.C3Els[1]._y:=0]
+	    864305 b.b.buf.in_v_buf._y : 0  [by b.b.buf._in_v:=1]
+	    865063 b.in.v : 1  [by b.b.buf.in_v_buf._y:=0]
+	    869770 b.b.out_valid.ct.C3Els[1]._y : 0  [by b.b.out_valid.ct.tmp[9]:=1]
+	    872393 b.b._out_v : 1  [by b.b.out_valid.ct.C3Els[1]._y:=0]
+	    872394 b.b.buf._en : 0  [by b.b._out_v:=1]
+	    872395 b.b.buf.en_buf_f.buf2._y : 1  [by b.b.buf._en:=0]
+	    873109 b.b._out_vB : 0  [by b.b._out_v:=1]
+	    874134 b.b.in_ack_inv.a : 1  [by b.b.buf._en:=0]
+	    874135 b.b.in_ack_inv.y : 0  [by b.b.in_ack_inv.a:=1]
+	    874141 b.in.a : 1  [by b.b.in_ack_inv.y:=0]
+	    884546 b.b.buf.en_buf_t.buf2._y : 1  [by b.b.buf._en:=0]
+	    884547 b.b.buf._en_X_t[0] : 0  [by b.b.buf.en_buf_t.buf2._y:=1]
+	    900594 b.b.buf._en_X_f[0] : 0  [by b.b.buf.en_buf_f.buf2._y:=1]
+[] Removing input
+	    900594 b.b.gandalf_t[0].a : 0
+	    900594 b.b._w : 0
+	    900594 b.b.gandalf_f[2].a : 0
+	    900594 b.b.gandalf_f[6].a : 0
+	    900594 b.b.gandalf_t[5].a : 0
+	    900594 b.b.gandalf_t[1].a : 0
+	    900594 b.b.gandalf_f[4].a : 0
+	    900594 b.b.gandalf_f[3].a : 0
+	    900601 b.b.gandalf_t[5]._y : 1  [by b.b.gandalf_t[5].a:=0]
+	    900607 b.b.gandalf_f[4]._y : 1  [by b.b.gandalf_f[4].a:=0]
+	    900616 b.b.gandalf_f[2]._y : 1  [by b.b.gandalf_f[2].a:=0]
+	    900617 b.b.gandalf_f[2].y : 0  [by b.b.gandalf_f[2]._y:=1]
+	    900618 b.b.buf.vc.OR2_tf[2]._y : 1  [by b.b.gandalf_f[2].y:=0]
+	    900648 b.b.gandalf_f[4].y : 0  [by b.b.gandalf_f[4]._y:=1]
+	    900659 b.b.gandalf_t[1]._y : 1  [by b.b.gandalf_t[1].a:=0]
+	    900660 b.b.gandalf_t[1].y : 0  [by b.b.gandalf_t[1]._y:=1]
+	    900705 b.b.gandalf_t[5].y : 0  [by b.b.gandalf_t[5]._y:=1]
+	    901718 b.b.gandalf_f[3]._y : 1  [by b.b.gandalf_f[3].a:=0]
+	    902544 b.b.gandalf_f[3].y : 0  [by b.b.gandalf_f[3]._y:=1]
+	    903841 b.b.buf.vc.OR2_tf[5]._y : 1  [by b.b.gandalf_t[5].y:=0]
+	    904377 b.b.buf.vc.OR2_tf[3]._y : 1  [by b.b.gandalf_f[3].y:=0]
+	    904435 b.b.buf.vc.ct.in[3] : 0  [by b.b.buf.vc.OR2_tf[3]._y:=1]
+	    913820 b.b.buf.vc.OR2_tf[4]._y : 1  [by b.b.gandalf_f[4].y:=0]
+	    916263 b.b.buf.vc.ct.in[4] : 0  [by b.b.buf.vc.OR2_tf[4]._y:=1]
+	    920389 b.b.buf.vc.ct.in[5] : 0  [by b.b.buf.vc.OR2_tf[5]._y:=1]
+	    920485 b.b.buf.vc.OR2_tf[1]._y : 1  [by b.b.gandalf_t[1].y:=0]
+	    922193 b.b._en2 : 1  [by b.b._w:=0]
+	    923102 b.b.gandalf_f[6]._y : 1  [by b.b.gandalf_f[6].a:=0]
+	    923116 b.b.gandalf_f[6].y : 0  [by b.b.gandalf_f[6]._y:=1]
+	    923472 b.b.buf.vc.OR2_tf[6]._y : 1  [by b.b.gandalf_f[6].y:=0]
+	    937258 b.b.buf.vc.ct.in[1] : 0  [by b.b.buf.vc.OR2_tf[1]._y:=1]
+	    940083 b.b.gandalf_t[0]._y : 1  [by b.b.gandalf_t[0].a:=0]
+	    940188 b.b.gandalf_t[0].y : 0  [by b.b.gandalf_t[0]._y:=1]
+	    940297 b.b.buf.vc.OR2_tf[0]._y : 1  [by b.b.gandalf_t[0].y:=0]
+	    940298 b.b.buf.vc.ct.in[0] : 0  [by b.b.buf.vc.OR2_tf[0]._y:=1]
+	    940307 b.b.buf.vc.ct.C2Els[0]._y : 1  [by b.b.buf.vc.ct.in[0]:=0]
+	    959310 b.b.buf.vc.ct.in[6] : 0  [by b.b.buf.vc.OR2_tf[6]._y:=1]
+	    959311 b.b.buf.vc.ct.C3Els[0]._y : 1  [by b.b.buf.vc.ct.in[6]:=0]
+	    959392 b.b.pass.y : 0  [by b.b._en2:=1]
+	    964996 b.b.buf.vc.ct.in[2] : 0  [by b.b.buf.vc.OR2_tf[2]._y:=1]
+	    964997 b.b.buf.vc.ct.C2Els[1]._y : 1  [by b.b.buf.vc.ct.in[2]:=0]
+	    968086 b.b.buf.vc.ct.tmp[8] : 0  [by b.b.buf.vc.ct.C2Els[1]._y:=1]
+	    978260 b.b.buf.vc.ct.tmp[7] : 0  [by b.b.buf.vc.ct.C2Els[0]._y:=1]
+	    995705 b.b.buf.vc.ct.tmp[9] : 0  [by b.b.buf.vc.ct.C3Els[0]._y:=1]
+	   1044431 b.b.buf.vc.ct.C3Els[1]._y : 1  [by b.b.buf.vc.ct.tmp[9]:=0]
+	   1045181 b.b.buf._in_v : 0  [by b.b.buf.vc.ct.C3Els[1]._y:=1]
+	   1051936 b.b.buf.in_v_buf._y : 1  [by b.b.buf._in_v:=0]
+	   1051987 b.in.v : 0  [by b.b.buf.in_v_buf._y:=1]
+	   1051997 b.b.buf._en : 1  [by b.in.v:=0]
+	   1051998 b.b.buf.en_buf_t.buf2._y : 0  [by b.b.buf._en:=1]
+	   1051999 b.b.buf._en_X_t[0] : 1  [by b.b.buf.en_buf_t.buf2._y:=0]
+	   1052317 b.b.in_ack_inv.a : 0  [by b.b.buf._en:=1]
+	   1054047 b.b.in_ack_inv.y : 1  [by b.b.in_ack_inv.a:=0]
+	   1055734 b.in.a : 0  [by b.b.in_ack_inv.y:=1]
+	   1059579 b.b.buf.en_buf_f.buf2._y : 0  [by b.b.buf._en:=1]
+	   1059594 b.b.buf._en_X_f[0] : 1  [by b.b.buf.en_buf_f.buf2._y:=0]

test/unit_tests/registerA_w/test.act

@@ -0,0 +1,52 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc registerA_w (avMx1of2<8> in; Mx1of2<7> out){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    registerA<7> b(.in = in, .out = out, .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+registerA_w b;

test/unit_tests/registerA_w/test.prsim

@@ -0,0 +1,42 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 8
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending in 127'"
+set-qdi-channel-valid "b.in" 8 255
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 127
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 8
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 127
+
+system "echo '[] Sending in 35'"
+set-qdi-channel-valid "b.in" 8 163
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 35
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 8
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 35
+

test/unit_tests/registerA_w_array/test.act

@@ -0,0 +1,54 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc registerA_w_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    // Make a register array with 3 bit address (-> 8 registers), 
+    // each register holding 5 bits.
+    registerA_w_array<3,5,8> b(.in = in, .data = data, .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+registerA_w_array_3x5x8 b;