regenned with cores having new names

dataflow_neuro/cell_lib_async.act

@@ -26,6 +26,30 @@
 
 namespace tmpl {
     namespace dataflow_neuro{
+        export defcell KEEP (bool y; bool vdd, vss) {
+            bool _y;
+             prs{
+                 // y => _y-
+            //     [weak=1] _y -> y-
+            //     [weak=1] ~_y -> y+
+
+                 }
+        }
+
+        export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
+            bool _y;
+            prs{
+                (~c1)|~pr_B -> _y+
+                c1 & n1 & n2 & sr_B -> _y-
+                _y => y-
+                }
+            sizing {
+                    leak_adjust <- 1; 
+                    p_n_mode <- 1;
+                    y {-1}; _y{-1} 
+                    }
+        }
+
         export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
             bool _y;
             prs{
@@ -41,6 +65,22 @@ namespace tmpl {
                     }
         }
 
+
+        export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
+            bool _y;
+            prs{
+                (~p1 & ~c1 & ~c2)|~pr_B -> _y+
+                c1 & c2 & n1 & sr_B -> _y-
+                _y => y-
+
+                }
+            sizing {
+                    leak_adjust <- 1; 
+                    p_n_mode <- 1;
+                    y {-1}; _y{-1} 
+                    }
+        }
+
         export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
             prs{
                 (~p1 & ~c1)|~pr_B -> y-
@@ -90,6 +130,94 @@ namespace tmpl {
             y {-1}}
         }
 
+        export defcell A_1C1N_X1 (bool! y; bool? c1, n1; bool vdd, vss)
+        {
+        prs{
+            ~c1 -> y+
+            c1&n1-> y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-1}}
+        }
+
+        // export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 | ~pr_B-> _y+
+        //     c1&n1&sr_B -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+        // export defcell A_1C1N_SB_X4 (bool! y; bool? c1, n1, pr, sr; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 & ~sr-> _y+
+        //     c1&n1 | pr -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+        export defcell A_1C2N_R_X1 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
+        {
+        prs{
+            ~c1 | ~pr_B-> y+
+            c1&n1&n2&sr_B -> y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}}
+        }
+
+        export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 | ~pr_B-> _y+
+            c1&n1&n2&sr_B -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+        export defcell A_1C2N_SB_X4 (bool! y; bool? c1, n1, n2, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~sr-> _y+
+            c1&n1&n2 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+        export defcell A_2C1N_SB_X4 (bool! y; bool? c1, c2, n1, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~c2 & ~sr-> _y+
+            c1&c2&n1 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+
         export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
         {
         prs{
@@ -137,12 +265,12 @@ namespace tmpl {
             y {-1}}
         }
 
-        export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss)
+        export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, na1, na2, nb1, nb2, pr_B, sr_B; bool vdd, vss)
         {
         bool _y;
         prs{
             (~c1 & ~c2) | ~pr_B -> _y+
-            c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
+            c1 & c2 & ((na1 & na2) | (nb1 & nb2)) & sr_B -> _y-
             _y => y-
         }
         sizing {    
@@ -314,6 +442,19 @@ namespace tmpl {
                 p_n_mode <- 1;
             y {-1}; _y{-1}}
         }
+
+        export defcell A_2C1N_R_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
+        {
+        prs{
+            (~c1 & ~c2) | ~pr_B -> y+
+            c1 & c2 & n1 & sr_B -> y-
+        }
+        sizing {    
+                leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-1}}
+        }
+
         export defcell A_2C1N_RB_X4(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
         {
             bool _y;
@@ -482,11 +623,11 @@ namespace tmpl {
             y {-1}; _y{-1} }
         }
 
-        export defcell A_4P1N1N_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
+        export defcell A_4P1N1N_X1 (bool! y; bool? na1, nb1, p1, p2, p3, p4; bool? vdd, vss)
         {
         prs{
             ~p1 & ~p2 & ~p3 & ~p4 -> y+
-            n1 | n2 -> y-
+            na1 | nb1 -> y-
             }
         sizing {leak_adjust <- 1; 
                 p_n_mode <- 1;
@@ -524,20 +665,56 @@ namespace tmpl {
             mk_excllo(_y1, _y2)
           }
         }
-        defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss)
+        export
+        defproc A_1N_U_X4(bool? n1; bool! y; bool? vdd, vss)
         {
         prs{
-        [keeper=0] a -> y-
+        [keeper=0] n1 -> y-
+        }
+        }
+
+        export
+        defproc A_2N_U_X4(bool? n1, n2; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] n1 & n2 -> y-
         }
         }
         
-        defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss)
+        export
+        defproc A_1P_U_X4(bool? p1; bool! y; bool? vdd, vss)
         {
         prs{
-        [keeper=0] ~a -> y+
+        [keeper=0] ~p1 -> y+
         }
         }
 
+        export
+        defproc A_2P_U_X4(bool? p1, p2; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] ~p1 & ~p2 -> y+
+        }
+        }
+
+        export
+        defproc A_3P_U_X4(bool? p1, p2, p3; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] ~p1 & ~p2 & ~p3-> y+
+        }
+        }
+
+        export
+        defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
+            A_1N_U_X4 cell(.n1 = a, .y = y, .vdd = vdd, .vss = vss);
+        }
+
+        export
+        defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) {
+            A_1P_U_X4 cell(.p1 = a, .y = y, .vdd = vdd, .vss = vss);
+        }
+
         defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
             bool _y;
             prs{

dataflow_neuro/cell_lib_std.act

@@ -27,14 +27,29 @@
 namespace tmpl {
   namespace dataflow_neuro {
 
+
+    // We have to add a pretend buffer in here
+    // to ensure that act2v doesn't simplify things
+    // and just connect y to vss/vdd lol
     export defproc TIELO_X1(bool! y; bool vdd, vss)
     {
-      y = vss;
+      bool _y, a;
+      a = vss;
+      prs {
+        a => _y-
+        _y => y-
+      }
+
     }
 
     export defproc TIEHI_X1(bool! y; bool vdd, vss)
     {
-      y = vdd;
+      bool _y, a;
+      a = vdd;
+      prs {
+        a => _y-
+        _y => y-
+      }      
     }
 
     /*-- inverters --*/
@@ -94,7 +109,19 @@ namespace tmpl {
     {
       sizing { _y {-4,2}; y {-8,4} }
     }
-        export defcell BUF_X12<: buf()
+    export defcell BUF_X12<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X16<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X24<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X32<: buf()
     {
       sizing { _y {-6,2}; y {-12,4} }
     }
@@ -102,15 +129,23 @@ namespace tmpl {
     /*-- delay cells --*/
     // TODO properly
 
+    // export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
+    // {
+    //   bool _y, __y, ___y;
+    //   prs {
+    //     a => _y-
+    //     _y => __y-
+    //     __y => ___y-
+    //     ___y => y-
+    //   }
+    // }
+
     export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
     {
-      bool _y, __y, ___y;
-      prs {
-        a => _y-
-        _y => __y-
-        __y => ___y-
-        ___y => y-
-      }
+        BUF_X1 bufchain[16];
+        (i:0..14: bufchain[i].y = bufchain[i+1].a;)
+        bufchain[0].a = a;
+        bufchain[15].y = y;
     }
 
       
@@ -275,6 +310,8 @@ namespace tmpl {
     export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
     {
       // y = !( S ? b : a )
+      // Actually looks more like
+      // if s = 0 -> use A
       // Adjusted to fit the XFAB Muxes
       bool _s;
       bool _y;
@@ -356,8 +393,8 @@ namespace tmpl {
       prs {
         en => _en-
 
-      ~a & ~_en -> y+
-        a & en -> y-
+      ~a & ~_en -> y-
+        a & en -> y+
       }
       sizing { _en{-1}; y{-1} }
     }
@@ -368,11 +405,24 @@ namespace tmpl {
       prs {
         en => _en-
 
-      ~a & ~_en -> y+
-        a & en -> y-
+      ~a & ~_en -> y-
+        a & en -> y+
       }
       sizing { _en{-2}; y{-2,2} }
     }
+
+    export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
+    {
+      bool _en;
+      prs {
+        en => _en-
+
+      ~a & ~_en -> y-
+        a & en -> y+
+      }
+      sizing { _en{-4}; y{-4,4} }
+    }
+
     export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
     {
       bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;

dataflow_neuro/chips.act

@@ -0,0 +1,793 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_core (avMx1of2<N_IN> in, out;
+    Mx1of2<REG_NCW> reg_data[REG_M];
+
+    // Dummy synapses and neurons in the handshake blocks
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
+    reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+    // Onwards
+    fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Register
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
+    register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
+        .supply = supply, .reset_B = reset_reg_B);
+    fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Spike Decoder
+    pint NC_SYN;
+    NC_SYN = NC_SYN_X + NC_SYN_Y;
+    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
+    fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
+    decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
+        .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
+        .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
+        .supply = supply, .reset_B = _reset_BX);
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    )
+
+    // Synapse handshake circuits, to be removed for innovus
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    //     .synapses = synapses,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
+    //     .to_pu = syn_pu,
+    //     .out_ackB_decoder = dec_ackB,
+    //     .supply = supply);
+
+    // Neurons + encoder
+    pint NC_NRN;
+    NC_NRN = NC_NRN_X + NC_NRN_Y;
+    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
+    fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Neuron handshake circuits, to be removed for innovus
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    //     .outx = enc_inx, .outy = enc_iny,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
+    //     .supply = supply, .reset_B = _reset_BX);
+
+
+
+    // Merge
+    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
+    append<N_IN-2, 2, 2> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
+    merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+
+    // Output
+    fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // Neuron/synapse monitor targeters
+    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
+    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
+    pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
+    pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
+
+    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
+    nrn_mon_dec_x.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_X:
+        nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
+    )
+    sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
+    nrn_mon_dec_y.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_Y:
+        nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
+    )
+    sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
+        .supply = supply);
+    syn_mon_dec_x.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_X:
+        syn_mon_dec_x.in.d[i] = register.data[3].d[i];
+    )
+    sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
+    syn_mon_dec_y.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_Y:
+        syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
+    )
+    sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
+
+    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
+    // Stops the possibility of dev_mon being high while some other sig is high.
+    // Otherwise boom.
+    // Also the 4th monitor line to each synapse is active LOW, needs inverter.
+    bool DEV_DEBUG;
+    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
+    sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+        .supply = supply);
+    DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    INV_X1 syn_targ_set_high_inv[NSMX4];
+    [NSMX4 >= 1 ->
+        AND2_X1 ands_devmon[NSMX4];
+        (i:NSMX4:
+            ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
+            ands_devmon[i].b = DEV_DEBUG;
+            ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
+            ands_devmon[i].vdd = supply.vdd;
+            ands_devmon[i].vss = supply.vss;
+
+            syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
+            syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
+            syn_targ_set_high_inv[i].vdd = supply.vdd;
+            syn_targ_set_high_inv[i].vss = supply.vss;
+
+        )
+        // Wire up the remaining lines.
+        (i:N_SYN_MON_X:
+            [(~(i%4 = 1)) & (~(i%4=3))->
+                syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
+            ]
+        )
+    ]
+
+    // Create TBUFs for each synapse column,
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
+    KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
+    sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
+    (j:N_MON_AMZO_PER_SYN:
+        (i:N_SYN_X:
+            index = i*N_MON_AMZO_PER_SYN + j;
+            syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
+            syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
+            syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
+        )
+
+        syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
+        syn_AMZO_keeps[j].vdd = supply.vdd;
+        syn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+
+    // Create TBUFs for each neuron column, and add keeps.
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
+    KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
+    sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply); 
+    (j:N_MON_AMZO_PER_NRN:
+        (i:N_NRN_X:
+            index = i*N_MON_AMZO_PER_NRN + j;
+            nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
+            nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
+            nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
+        )
+
+        nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
+        nrn_AMZO_keeps[j].vdd = supply.vdd;
+        nrn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+    // Create buffered signals from register to nrns.
+    sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
+    (i:N_FLAGS_PER_NRN:
+        sb_nrn_EFO.in[i] = register.data[5].d[i].t;
+    )
+
+    // Create  buffered signals from register to synapses.
+    // Includes safety on the first 3 flags with dev mon.
+    sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
+    (i:3..N_FLAGS_PER_SYN-1:
+        sb_syn_EFO.in[i] = register.data[4].d[i].t;
+    )  
+    AND2_X1 syn_flags_dev_safety[3];
+    (i:0..2:
+        syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
+        syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
+
+        syn_flags_dev_safety[i].vdd = supply.vdd;
+        syn_flags_dev_safety[i].vss = supply.vss;
+    )
+
+    // Create non-buffered reset signals for the neuron/syn handshakes
+    // Since sigs are buffered before each neuron.
+    sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
+    sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
+    sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
+    INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
+    sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
+
+}
+
+
+
+
+export template<pint N_IN,	// Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_singlecore (bd<N_IN> in, out;
+	Mx1of2<REG_NCW> reg_data[REG_M];
+	// a1of1 synapses[N_SYN_X * N_SYN_Y];
+	// a1of1 neurons[N_NRN_X * N_NRN_Y];
+    
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+	bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+	bool? loopback_en;
+	power supply;
+	bool? reset_B){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+	bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+	fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+	fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+	// Loopback
+	fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+	dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+		.supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+	// Onwards to core
+	fifo<N_IN,N_BUFFERS> fifo_fork2core(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+
+    texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core(.in = fifo_fork2core.out,
+            .reg_data = reg_data,
+            // .synapses = synapses,
+            // .neurons = neurons,
+            .nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
+            .syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
+            .syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
+            .syn_mon_AMZO = syn_mon_AMZO, .nrn_mon_AMZO = nrn_mon_AMZO,
+            .syn_flags_EFO = syn_flags_EFO, .nrn_flags_EFO = nrn_flags_EFO,
+
+            .reset_B = _reset_BX,
+            .supply = supply
+            );
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_core2mrg(.in = core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    
+
+    // merge core output and loopback
+    merge<N_IN> merge_drop8core(.in1 = fifo_core2mrg.out, .in2 = fifo_drop2mrg.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = merge_drop8core.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+
+
+}
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+   
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+    // Merge cores and loopback
+    merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore_mapper (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+
+    // MAPPER STUFF
+
+    bool? mapper_en;
+    avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
+    avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
+    avMx1of2<29> in_sram_r; // Readout packets from SRAM
+    avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
+
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+
+    // dmx to SRAM
+    bool is_to_sram, is_to_cores;
+    fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
+    demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX);
+    sram_dmx.cond.d.d[0].t = is_to_sram;
+    sram_dmx.cond.d.d[0].f = is_to_cores;
+    AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t,
+        .y = is_to_sram,
+        .vdd = supply.vdd, .vss = supply.vss);
+    OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f,
+        .y = is_to_cores,
+        .vdd = supply.vdd, .vss = supply.vss);
+    slice_data<32, 0, 30> pre_sram_slice(.supply = supply);
+    pre_sram_slice.in.a = sram_dmx.out2.a;
+    pre_sram_slice.in.v = sram_dmx.out2.v;
+    (i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
+    pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
+    pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
+    pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
+    fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // spikes from sram
+    // requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]
+    fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply);
+    append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply);
+    merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    merge_dmx8spk.in2.a = sram_spk_in_append.out.a;
+    merge_dmx8spk.in2.v = sram_spk_in_append.out.v;
+    (i:13: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i];)
+    merge_dmx8spk.in2.d.d[31] = sram_spk_in_append.out.d.d[13];
+    (i:13..30: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i+1];)
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = merge_dmx8spk.out, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+
+    // fork after core merge then go to mapper if its a spike
+    fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
+    fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply);
+    // Need to have it then drop the spike if its from a register.
+    demux_td<32, true> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data
+    drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30];
+    drop_if_reg.token.r  = drop_if_reg.token.a;
+
+    slice_data<32,0,8> slice_to_sram(.supply = supply);
+    // And move the msb (core bit) to just after the neuron address...
+    slice_to_sram.in.a = drop_if_reg.out.a;
+    slice_to_sram.in.v = drop_if_reg.out.v;
+    (i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];)
+    slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31];
+    (i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];)
+
+    fifo<8,N_BUFFERS> fifo_out_sram_spk(.in = slice_to_sram.out, .out = out_sram_spk,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // merge from cores and sram read in
+    fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply);
+    fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply);
+    append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply);
+    merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Merge cores and loopback
+    fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply);
+    merge<N_IN> merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+}
+}
+

dataflow_neuro/chips_noread.act

@@ -0,0 +1,467 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_core (avMx1of2<N_IN> in, out;
+    Mx1of2<REG_NCW> reg_data[REG_M];
+
+    // Dummy synapses and neurons in the handshake blocks
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
+    reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+    // Onwards
+    fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Register
+    slice_data<N_IN-1, 0,REG_NCW+REG_NCA> slice_pre_reg(.in = _demux.out2, .supply = supply);
+    fifo<REG_NCW+REG_NCA,N_BUFFERS> fifo_dmx2reg(.in = slice_pre_reg.out, .reset_B = _reset_BX, .supply = supply);
+    register_w_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
+        .supply = supply, .reset_B = reset_reg_B);
+
+
+    // Spike Decoder
+    pint NC_SYN;
+    NC_SYN = NC_SYN_X + NC_SYN_Y;
+    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
+    fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
+    decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
+        .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
+        .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
+        .supply = supply, .reset_B = _reset_BX);
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    )
+
+    // Synapse handshake circuits, to be removed for innovus
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    //     .synapses = synapses,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
+    //     .to_pu = syn_pu,
+    //     .out_ackB_decoder = dec_ackB,
+    //     .supply = supply);
+
+    // Neurons + encoder
+    pint NC_NRN;
+    NC_NRN = NC_NRN_X + NC_NRN_Y;
+    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
+    fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Neuron handshake circuits, to be removed for innovus
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    //     .outx = enc_inx, .outy = enc_iny,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
+    //     .supply = supply, .reset_B = _reset_BX);
+
+
+
+    // Merge
+    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
+
+    // Output
+    fifo<N_IN, N_BUFFERS> fifo_out(.in = append_enc.out, .out = out,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // Neuron/synapse monitor targeters
+    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
+    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
+    pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
+    pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
+
+    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
+    nrn_mon_dec_x.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_X:
+        nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
+    )
+    sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
+    nrn_mon_dec_y.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_Y:
+        nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
+    )
+    sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
+        .supply = supply);
+    syn_mon_dec_x.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_X:
+        syn_mon_dec_x.in.d[i] = register.data[3].d[i];
+    )
+    sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
+    syn_mon_dec_y.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_Y:
+        syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
+    )
+    sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
+
+    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
+    // Stops the possibility of dev_mon being high while some other sig is high.
+    // Otherwise boom.
+    // Also the 4th monitor line to each synapse is active LOW, needs inverter.
+    bool DEV_DEBUG;
+    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
+    sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+        .supply = supply);
+    DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    INV_X1 syn_targ_set_high_inv[NSMX4];
+    [NSMX4 >= 1 ->
+        AND2_X1 ands_devmon[NSMX4];
+        (i:NSMX4:
+            ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
+            ands_devmon[i].b = DEV_DEBUG;
+            ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
+            ands_devmon[i].vdd = supply.vdd;
+            ands_devmon[i].vss = supply.vss;
+
+            syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
+            syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
+            syn_targ_set_high_inv[i].vdd = supply.vdd;
+            syn_targ_set_high_inv[i].vss = supply.vss;
+
+        )
+        // Wire up the remaining lines.
+        (i:N_SYN_MON_X:
+            [(~(i%4 = 1)) & (~(i%4=3))->
+                syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
+            ]
+        )
+    ]
+
+    // Create TBUFs for each synapse column,
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
+    KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
+    sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
+    (j:N_MON_AMZO_PER_SYN:
+        (i:N_SYN_X:
+            index = i*N_MON_AMZO_PER_SYN + j;
+            syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
+            syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
+            syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
+        )
+
+        syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
+        syn_AMZO_keeps[j].vdd = supply.vdd;
+        syn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+
+    // Create TBUFs for each neuron column, and add keeps.
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
+    KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
+    sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply); 
+    (j:N_MON_AMZO_PER_NRN:
+        (i:N_NRN_X:
+            index = i*N_MON_AMZO_PER_NRN + j;
+            nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
+            nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
+            nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
+        )
+
+        nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
+        nrn_AMZO_keeps[j].vdd = supply.vdd;
+        nrn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+    // Create buffered signals from register to nrns.
+    sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
+    (i:N_FLAGS_PER_NRN:
+        sb_nrn_EFO.in[i] = register.data[5].d[i].t;
+    )
+
+    // Create  buffered signals from register to synapses.
+    // Includes safety on the first 3 flags with dev mon.
+    sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
+    (i:3..N_FLAGS_PER_SYN-1:
+        sb_syn_EFO.in[i] = register.data[4].d[i].t;
+    )  
+    AND2_X1 syn_flags_dev_safety[3];
+    (i:0..2:
+        syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
+        syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
+
+        syn_flags_dev_safety[i].vdd = supply.vdd;
+        syn_flags_dev_safety[i].vss = supply.vss;
+    )
+
+    // Create non-buffered reset signals for the neuron/syn handshakes
+    // Since sigs are buffered before each neuron.
+    sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
+    sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
+    sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
+    INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
+    sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
+
+}
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+   
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+    // Merge cores and loopback
+    merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+}
+}
+

dataflow_neuro/dummy.act

@@ -0,0 +1,94 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+/**
+ * Creates a synapse-neuron dummy block, 
+ * where any synapse being triggered makes the neuron "spike".
+ */
+export template<pint N_SYN>
+defproc dummy_neuron_block (a1of1 synapses[N_SYN], neuron; power supply){
+    // OR over reqs from syn in to neuron out
+    ortree<N_SYN> _ortree(.out = neuron.r, .supply = supply);
+    (i:N_SYN: _ortree.in[i] = synapses[i].r;)
+
+    // ANDs piping the ack back to the proper synapse
+
+    BUF_X12 nrn_ack_buf(.a = neuron.a, .vdd = supply.vdd, .vss = supply.vss);
+
+    AND2_X1 ands[N_SYN];
+    (i:N_SYN:
+        ands[i].a = nrn_ack_buf.y;
+        ands[i].b = synapses[i].r;
+        ands[i].y = synapses[i].a;
+
+        ands[i].vss = supply.vss;
+        ands[i].vdd = supply.vdd;
+    )
+}
+
+/**
+ * Create an array of neuron dummy blocks.
+ * Note that this is custom made for the indexing on the texel chip.
+ * And so should be reused *with care*.
+ */
+export template<pint N_SYN_PER_NRN, N_NRN, N_NRN_X>
+defproc dummy_neuron_core (a1of1 synapses[N_SYN_PER_NRN * N_NRN], neurons[N_NRN]; power supply){
+    dummy_neuron_block<N_SYN_PER_NRN> blocks[N_NRN];
+    pint Xn, Yn, Xs, Ys;
+    (i:N_NRN:
+        Yn = i/N_NRN_X;
+        Xn = i-Yn*N_NRN_X;
+        neurons[i] = blocks[i].neuron;
+        blocks[i].supply = supply;
+        (j:N_SYN_PER_NRN: // moron, need to think about neuron indexxing too
+            Xs = Xn;
+            Ys = Yn*N_SYN_PER_NRN + j;
+            blocks[i].synapses[j] = synapses[Ys*N_NRN_X + Xs];
+        )
+    )
+}
+
+
+
+
+}
+}

dataflow_neuro/dynapse.act

@@ -0,0 +1,66 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export
+defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
+	bool _en;
+	bool _out_a_B;
+
+	INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
+
+	A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_1C1P_X1 A_en(.c1 = in.a, .p1 =  out.r, .y = _en,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+}
+
+}
+}
+

dataflow_neuro/interfaces.act

@@ -0,0 +1,174 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import std::channel;
+open std::channel;
+
+// import std::func;
+open std;
+
+import std::data;
+open std::data;
+
+
+namespace tmpl {
+	namespace dataflow_neuro {
+
+		/**
+		 * Bundled data (non dual rail, with req)
+		 * 2
+		 * quasi delay insensitive channel (dual rail).
+		 * Basically a buffer with a bitwise conversion in front of it.
+		 */
+		export template<pint N, N_dly_cfg, N_dly_cfg2>
+		defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
+			power supply; bool? reset_B) {
+			
+			// Delay on req_in
+			bool _req;
+			delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
+
+			// sig buff the reset signal
+			bool _reset_BX, _reset_BXX[N*2];
+			BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+            sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
+
+            // sig buff the req
+			bool _reqX, _reqXX[N*2];
+			BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
+        	sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
+
+			// For reasons of pure spice, the control circuitry 
+			// requires a req signal that FALLS SLOWER than the req going to the function block.
+			// Thus need another delay prog.
+			bool _req_slowfall;
+			delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
+			OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
+				.vss = supply.vss, .vdd = supply.vdd);
+
+            // bd2qdi conversion
+            // Each line goes to a t pin, its not to an f.
+            bool _inB[N];
+            INV_X1 input_invs[N];
+            (i:N:
+            	input_invs[i].a = in.d[i];
+            	input_invs[i].y = _inB[i];
+            	input_invs[i].vss = supply.vss;
+            	input_invs[i].vdd = supply.vdd;
+            )
+
+			// BUFFER
+			// Basically the buffer_s but with the validity tree ripped out
+			// and just connected to in_req instead.
+
+			// And probably need a delay on the in_ack to ensure en has time to disable
+			// before the inputs go to another state.
+			// Actually apparently no: there is a fixed, huge delay, already incurred
+			// by communicating with pads-> uC -> windows 95 and back again.
+
+            // Since the input is never invalid, also need a mechanism
+            // for the output to become invalid, when an out_ack is received. 
+
+            //control
+            bool _en;
+            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+            A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
+
+            //function
+            bool _out_a_B;
+            A_2C2N_RB_X4 f_buf_func[N];
+            A_2C2N_RB_X4 t_buf_func[N];
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
+            INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
+            // check if you can also do single var to array connect a=b[N]
+            // and remove them from the loop
+            (i:N: 
+                f_buf_func[i].y=out.d.d[i].f;
+                t_buf_func[i].y=out.d.d[i].t;
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=out_a_B_buf.out[i];
+                t_buf_func[i].c2=out_a_B_buf.out[i+N];
+                f_buf_func[i].n1=_inB[i];
+                t_buf_func[i].n1=in.d[i];
+                f_buf_func[i].n2=_reqXX[i];
+                t_buf_func[i].n2=_reqXX[i+N];
+                f_buf_func[i].vdd=supply.vdd;
+                t_buf_func[i].vdd=supply.vdd;
+                f_buf_func[i].vss=supply.vss;
+                t_buf_func[i].vss=supply.vss;
+                t_buf_func[i].pr_B = _reset_BXX[i];
+                t_buf_func[i].sr_B = _reset_BXX[i];
+                f_buf_func[i].pr_B = _reset_BXX[i+N];
+                f_buf_func[i].sr_B = _reset_BXX[i+N];
+            )
+
+		}
+
+
+		
+		/**
+		 * quasi delay insensitive channel (dual rail).
+		 * 2
+		 * Bundled data (non dual rail, with req)
+		 */
+		export template<pint N, N_dly_cfg>
+		defproc qdi2bd(avMx1of2<N> in; bd<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
+
+            // Buffer
+            buffer<N> buf(.in = in, .supply = supply, .reset_B = reset_B);
+            buf.out.a = out.a;
+            
+            // Vtree
+            vtree<N> out_vtree(.supply = supply);
+            (i:N:
+            	out_vtree.in.d[i].t = buf.out.d.d[i].t;
+            	out_vtree.in.d[i].f = buf.out.d.d[i].f;
+            )
+            buf.out.v = out_vtree.out;
+
+            // Delay
+            delayprog<N_dly_cfg> dly(.in = out_vtree.out, .out = out.r, .s = dly_cfg, .supply = supply);
+            out_vtree.out = dly.in;
+
+            // Wire output data bits to buffer True lines
+            (i:N:
+            	buf.out.d.d[i].t = out.d[i];
+            )
+
+		}
+
+
+
+	}
+
+}

dataflow_neuro/primitives.act

@@ -33,6 +33,9 @@ import "../../dataflow_neuro/treegates.act";
 import std::channel;
 open std::channel;
 
+// import std::func;
+
+
 namespace tmpl {
     namespace dataflow_neuro {
 
@@ -75,8 +78,8 @@ namespace tmpl {
               [(&i:M: d.d[i].t | d.d[i].f)];
               self := 0;
               (;i:M: [ d.d[i].t -> self := self | (1 << i)
-        	     [] else -> skip
-        	     ]
+               [] else -> skip
+               ]
               )
             }
         
@@ -108,37 +111,35 @@ namespace tmpl {
         export template<pint N>
         defproc buffer (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
             //control
-            bool _en, _reset_BX,_reset_BXX[N];
+            bool _en, _reset_BX,_reset_BXX[N*2];
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
 
 
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-	          sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
-	    
+            sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
+      
             //validity
             bool _in_v;
             vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
             BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
             
             //function
-            bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
+            bool _out_a_BX[N*2],_out_a_B;
             A_2C1N_RB_X4 f_buf_func[N];
             A_2C1N_RB_X4 t_buf_func[N];
-            sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
-            sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
             INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B,.out=_out_a_BX, .supply = supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
                 f_buf_func[i].y=out.d.d[i].f;
                 t_buf_func[i].y=out.d.d[i].t;
-                f_buf_func[i].c1=_en_X_f[i];
-                t_buf_func[i].c1=_en_X_t[i];
-                f_buf_func[i].c2=_out_a_BX_f[i];
-                t_buf_func[i].c2=_out_a_BX_t[i];
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=_out_a_BX[i];
+                t_buf_func[i].c2=_out_a_BX[i+N];
                 f_buf_func[i].n1=in.d.d[i].f;
                 t_buf_func[i].n1=in.d.d[i].t;
                 f_buf_func[i].vdd=supply.vdd;
@@ -147,8 +148,8 @@ namespace tmpl {
                 t_buf_func[i].vss=supply.vss;
                 t_buf_func[i].pr_B = _reset_BXX[i];
                 t_buf_func[i].sr_B = _reset_BXX[i];
-                f_buf_func[i].pr_B = _reset_BXX[i];
-                f_buf_func[i].sr_B = _reset_BXX[i];
+                f_buf_func[i].pr_B = _reset_BXX[i+N];
+                f_buf_func[i].sr_B = _reset_BXX[i+N];
             )
         }
         // A template creating a FIFO of M buffers with N bits each
@@ -165,7 +166,7 @@ namespace tmpl {
             fifo_element[i].supply = supply;
             fifo_element[i].reset_B = _reset_BXX[i];
           )
-          fifo_element[N-1].out = out;
+          fifo_element[M-1].out = out;
 
           // reset buffers
           bool _reset_BX;
@@ -193,33 +194,31 @@ namespace tmpl {
             sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
         
             //validity
-            bool _in_v, _in_vX[N];
+            bool _in_v;
             vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
             BUF_X4 in_v_buf4(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N> in_v_bufN(.in = in.v, .out = _in_vX, .supply = supply);
+            sigbuf<N*2> in_v_bufN(.in = in.v, .supply = supply);
 
             //function
-            bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
+            bool _out_a_B;
             A_2C2N_RB_X4 f_buf_func[N];
             A_2C2N_RB_X4 t_buf_func[N];
-            sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
-            sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
             INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
                 f_buf_func[i].y=out.d.d[i].f;
                 t_buf_func[i].y=out.d.d[i].t;
-                f_buf_func[i].c1=_en_X_f[i];
-                t_buf_func[i].c1=_en_X_t[i];
-                f_buf_func[i].c2=_out_a_BX_f[i];
-                t_buf_func[i].c2=_out_a_BX_t[i];
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=out_a_B_buf.out[i];
+                t_buf_func[i].c2=out_a_B_buf.out[i+N];
                 f_buf_func[i].n1=in.d.d[i].f;
                 t_buf_func[i].n1=in.d.d[i].t;
-                f_buf_func[i].n2=_in_vX[i];
-                t_buf_func[i].n2=_in_vX[i];
+                f_buf_func[i].n2=in_v_bufN.out[i];
+                t_buf_func[i].n2=in_v_bufN.out[i+N];
                 f_buf_func[i].vdd=supply.vdd;
                 t_buf_func[i].vdd=supply.vdd;
                 f_buf_func[i].vss=supply.vss;
@@ -238,7 +237,8 @@ namespace tmpl {
             
             OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-            cond.a = in.a;
+            cond.a = in.a; // THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
+            cond.v = _in_c_v_;
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
@@ -257,21 +257,19 @@ namespace tmpl {
             
             //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C2N_RB_X4 out1_f_buf_func[N];
             A_2C2N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
-            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
+            sigbuf<N*4> out_en_buf(.in=_en, .supply=supply);
+            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vdd = supply.vdd, .vss = supply.vss);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out_en_buf.out[i];
+                out1_t_buf_func[i].c1=out_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -282,38 +280,36 @@ namespace tmpl {
                 out1_t_buf_func[i].sr_B = _reset_BXX[i];
                 out1_f_buf_func[i].pr_B = _reset_BXX[i];
                 out1_f_buf_func[i].sr_B = _reset_BXX[i];
-                out1_f_buf_func[i].n2=_c_t_buf[i];
-                out1_t_buf_func[i].n2=_c_t_buf[i];
+                out1_f_buf_func[i].n2=_c_f_buf[i];
+                out1_t_buf_func[i].n2=_c_f_buf[i];
             )
 
             //func buffer out2
-            bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
+            bool _out2_a_B;
             A_2C2N_RB_X4 out2_f_buf_func[N];
             A_2C2N_RB_X4 out2_t_buf_func[N];
-            sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
-            sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
-            INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
-            sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
-            sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
+            // sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
+            INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B, .vdd = supply.vdd, .vss = supply.vss);
+            sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
             (i:N: 
                 out2_f_buf_func[i].y=out2.d.d[i].f;
                 out2_t_buf_func[i].y=out2.d.d[i].t;
-                out2_f_buf_func[i].c1=_en2_X_f[i];
-                out2_t_buf_func[i].c1=_en2_X_t[i];
-                out2_f_buf_func[i].c2=_out2_a_BX_f[i];
-                out2_t_buf_func[i].c2=_out2_a_BX_t[i];
+                out2_f_buf_func[i].c1=out_en_buf.out[i+2*N];
+                out2_t_buf_func[i].c1=out_en_buf.out[i+3*N];
+                out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
+                out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
                 out2_f_buf_func[i].n1=in.d.d[i].f;
                 out2_t_buf_func[i].n1=in.d.d[i].t;
                 out2_f_buf_func[i].vdd=supply.vdd;
                 out2_t_buf_func[i].vdd=supply.vdd;
                 out2_f_buf_func[i].vss=supply.vss;
                 out2_t_buf_func[i].vss=supply.vss;
-                out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].n2=_c_f_buf[i];
-                out2_t_buf_func[i].n2=_c_f_buf[i];
+                out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
+                out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].n2=_c_t_buf[i];
+                out2_t_buf_func[i].n2=_c_t_buf[i];
             )
         }
 
@@ -338,21 +334,19 @@ namespace tmpl {
 
           //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C1N_RB_X4 out1_f_buf_func[N];
             A_2C1N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
+            sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
             INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out1_en_buf.out[i];
+                out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -365,39 +359,42 @@ namespace tmpl {
                 out1_f_buf_func[i].sr_B = _reset_BXX[i];
             )
             //func buffer out2
-            bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
+            bool _out2_a_B;
             A_2C1N_RB_X4 out2_f_buf_func[N];
             A_2C1N_RB_X4 out2_t_buf_func[N];
-            sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
-            sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
+            sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
             INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
-            sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
-            sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
+            sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
             (i:N: 
                 out2_f_buf_func[i].y=out2.d.d[i].f;
                 out2_t_buf_func[i].y=out2.d.d[i].t;
-                out2_f_buf_func[i].c1=_en2_X_f[i];
-                out2_t_buf_func[i].c1=_en2_X_t[i];
-                out2_f_buf_func[i].c2=_out2_a_BX_f[i];
-                out2_t_buf_func[i].c2=_out2_a_BX_t[i];
+                out2_f_buf_func[i].c1=out2_en_buf.out[i];
+                out2_t_buf_func[i].c1=out2_en_buf.out[i+N];
+                out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
+                out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
                 out2_f_buf_func[i].n1=in.d.d[i].f;
                 out2_t_buf_func[i].n1=in.d.d[i].t;
                 out2_f_buf_func[i].vdd=supply.vdd;
                 out2_t_buf_func[i].vdd=supply.vdd;
                 out2_f_buf_func[i].vss=supply.vss;
                 out2_t_buf_func[i].vss=supply.vss;
-                out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
+                out2_t_buf_func[i].pr_B = _reset_BXX[i];
+                out2_t_buf_func[i].sr_B = _reset_BXX[i];
+                out2_f_buf_func[i].pr_B = _reset_BXX[i];
+                out2_f_buf_func[i].sr_B = _reset_BXX[i];
             )
         }
         
         // Demux 
         export template<pint N; pbool CONDITION_SIGN>
-        defproc demux_td (avMx1of2<N> in; avMx1of2<N> out1; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
+        // WARNING WARNING WARNING
+        // With a False CONDITION_SIGN, this is wrong.
+        // the c.t/f just need to be swapped, not inverted!!!
+        defproc demux_td (avMx1of2<N> in; avMx1of2<N> out; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
             //control
             bool _en, _reset_BX,_reset_BXX[N], _out_v, _in_c_v_, _reset_BXt;
+            avMx1of2<N> out1 = out;
+
             
             OR2_X1 out_or(.a=out1.v, .b=token.r, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
@@ -407,6 +404,10 @@ namespace tmpl {
             sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
             //validity
             bool _in_v, _c_tk_buf, _c_d_buf[N], _c_v, cond_inv_t, cond_inv_f;
+
+
+            cond.a = in.a;
+            cond.v = _c_v;
             
             OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
             
@@ -430,21 +431,19 @@ namespace tmpl {
             
             //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C2N_RB_X4 out1_f_buf_func[N];
             A_2C2N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
+            sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
             INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vss = supply.vss, .vdd = supply.vdd);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out1_en_buf.out[i];
+                out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -477,6 +476,64 @@ namespace tmpl {
           token_buf.pr_B = _reset_BXt;
           token_buf.sr_B = _reset_BXt;
         }
+
+        /** 
+         * Drops a packet if condition is met, otherwise passes it on.
+         * This is a very lazy implementation, where the cond MUST NOT CHANGE DURING OPERATION.
+         * Means that this should be used in a very small set of circumstances.
+         * 
+         * params:
+         * N: size of packet
+         * CONDITION_DROP: value of cond when packets are dropped.
+         */
+        export template<pint N; pbool CONDITION_DROP>
+        defproc dropper_static (avMx1of2<N> in; avMx1of2<N> out; bool? cond; power supply) {
+            bool _drop, _dropB;
+            INV_X1 inv(.a = cond, .vss = supply.vss, .vdd = supply.vdd);
+
+            [~CONDITION_DROP ->
+                _dropB = cond;
+                _drop = inv.y;
+            [] CONDITION_DROP ->
+                _drop = cond;
+                _dropB = inv.y;
+            ]
+
+            bool _in_vX;
+            vtree<N> vt(.in = in.d, .supply = supply);
+            BUF_X4 in_v_buf(.a = vt.out, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
+            AND2_X1 and2(.a = _drop, .b = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
+            OR2_X1 or2(.a = out.a, .b = and2.y, .vss = supply.vss, .vdd = supply.vdd);
+            A_2C_B_X1 ack_Cel(.c1 = or2.y, .c2 = _in_vX, .y = in.a);
+            // _in_vX = in.v;
+
+            // Sigbufs
+            sigbuf<N*2> sb_dropB(.in = _dropB, .supply = supply);
+            sigbuf<N*2+1> sb_in_v(.in = _in_vX, .supply = supply);
+            sb_in_v.out[2*N] = in.v;
+
+            AND3_X1 and_t[N];
+            AND3_X1 and_f[N];
+            (i:N:
+                and_t[i].a = in.d.d[i].t;
+                and_f[i].a = in.d.d[i].f;
+
+                and_t[i].y = out.d.d[i].t;
+                and_f[i].y = out.d.d[i].f;
+                
+                and_t[i].b = sb_dropB.out[i];
+                and_f[i].b = sb_dropB.out[i+N];
+
+                and_t[i].c = sb_in_v.out[i];
+                and_f[i].c = sb_in_v.out[i+N];
+
+                and_t[i].vss = supply.vss;
+                and_t[i].vdd = supply.vdd;
+            )
+
+
+
+        }
         
         
         export 
@@ -491,23 +548,23 @@ namespace tmpl {
           
         }
         //The buffer_t_valid doesn't work
-        export 
-        defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
-        {
-            //control
-            bool _en, _reset_BX;
-            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-            A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
+        // export 
+        // defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
+        // {
+        //     //control
+        //     bool _en, _reset_BX;
+        //     A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+        //     A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
             
-            //function
-            bool _out_a_B;
-            INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
-            A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
+        //     //function
+        //     bool _out_a_B;
+        //     INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
+        //     A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
 
             
-            //reset buffers
-            BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-        }
+        //     //reset buffers
+        //     BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+        // }
 
         
 
@@ -524,7 +581,7 @@ namespace tmpl {
           bool _in1_arb,_in2_arb,_in1_arb_X[2*N],_in2_arb_X[2*N];
           A_4C_RB_X4 in1ack_ctl(.c1=_in1_arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
           A_4C_RB_X4 in2ack_ctl(.c1=_in2_arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-          A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .n1 = in1.a,.n2 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
+          A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .na1 = in1.a,.nb1 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
           sigbuf<2*N> en_buffer(.in = _en,.out = _en_X,.supply=supply);
           INV_X1 in1ack_ctl_inv(.a=in1.a,.y=_in1_a_B,.vdd=supply.vdd,.vss=supply.vss);
           INV_X1 in2ack_ctl_inv(.a=in2.a,.y=_in2_a_B,.vdd=supply.vdd,.vss=supply.vss);
@@ -555,10 +612,10 @@ namespace tmpl {
           (i:N: 
             merge_func_t[i].c1 = _en_X[i];
             merge_func_t[i].c2 = _out_a_BX[i];
-            merge_func_t[i].n1 = _in1_arb_X[i];
-            merge_func_t[i].n2 = in1.d.d[i].t;
-            merge_func_t[i].n3 = _in2_arb_X[i];
-            merge_func_t[i].n4 = in2.d.d[i].t;
+            merge_func_t[i].na1 = _in1_arb_X[i];
+            merge_func_t[i].na2 = in1.d.d[i].t;
+            merge_func_t[i].nb1 = _in2_arb_X[i];
+            merge_func_t[i].nb2 = in2.d.d[i].t;
             merge_func_t[i].y = out.d.d[i].t;
             merge_func_t[i].vdd=supply.vdd;
             merge_func_t[i].vss=supply.vss;
@@ -567,10 +624,10 @@ namespace tmpl {
 
             merge_func_f[i].c1 = _en_X[i+N];
             merge_func_f[i].c2 = _out_a_BX[i+N];
-            merge_func_f[i].n1 = _in1_arb_X[i+N];
-            merge_func_f[i].n2 = in1.d.d[i].f;
-            merge_func_f[i].n3 = _in2_arb_X[i+N];
-            merge_func_f[i].n4 = in2.d.d[i].f;
+            merge_func_f[i].na1 = _in1_arb_X[i+N];
+            merge_func_f[i].na2 = in1.d.d[i].f;
+            merge_func_f[i].nb1 = _in2_arb_X[i+N];
+            merge_func_f[i].nb2 = in2.d.d[i].f;
             merge_func_f[i].y = out.d.d[i].f;
             merge_func_f[i].vdd=supply.vdd;
             merge_func_f[i].vss=supply.vss;
@@ -685,26 +742,175 @@ namespace tmpl {
             (i:((1<<N)-1):dly[i].vss = supply.vss;)
         }
 
-        export
-        defproc line_end_pull_up (a1of1 in; bool? reset_B; power supply; bool! out)
-        {
-          bool _out, __out, nor_out;
-          BUF_X4 buf1(.a=in.a, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
-          BUF_X4 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
+        // Non programmable delays
+        // N is number of delays to have in series (not log!!).
+        // Is useful for testing purposes.
+        // But should probably remove before running innovus etc.
+        export template<pint N>
+        defproc delay_chain (bool out; bool in; power supply) {
+            { N >= 0 : "What?" };
+            [N >= 1 ->
+              DLY4_X1 dly[N];
 
-          NOR2_X1 aenor(.a=_out, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
+              dly[0].vdd = supply.vdd;
+              dly[0].vss = supply.vss;
+              dly[0].a = in;
 
-          PULLUP_X4 pull_up(.a=nor_out, .y=out);
+              (i:1..N-1:
+                  dly[i].vdd = supply.vdd;
+                  dly[i].vss = supply.vss;
+                  dly[i].a = dly[i-1].y;
+              )
+
+              dly[N-1].vdd = supply.vdd;
+              dly[N-1].vss = supply.vss;
+              dly[N-1].y = out;
+            [] N = 0 ->
+              in = out;
+            ]
+            
         }
 
-        defproc line_end_pull_down (a1of1 in; bool? reset_B; power supply; bool! out)
+
+        /**
+         * Appends a hard-coded word "VAL" to an input.
+         * Works by piping through all sigs, but adding
+         * some extra sigs when the input is valid.
+         * N is size of channel to pipe through.
+         * NVAL is size of word to be put on output.
+         * VAL is word to be put on output.
+         * Output looks like
+         * 0..............N........N+NVAL-1
+         * --input_data----LSB....MSB
+         *
+         */
+        export template<pint N, NVAL, VAL>
+        defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
         {
-          bool _out, __out, nor_out;
-          BUF_X4 buf1(.a=in.a, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
-          BUF_X4 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
+            { N >= 0 : "What?" };
+            { NVAL >= 0 : "What?" };
+            { VAL < 1<<NVAL : "VAL too big!" };
 
-          NOR2_X1 aenor(.a=_out, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
+            // valid tree
+            vtree<N> in_val(.supply = supply);
+            (i:N:
+                in_val.in.d[i].t = in.d.d[i].t;
+                in_val.in.d[i].f = in.d.d[i].f;
+            )
+
+            // wire through most signals
+            (i:N:
+                in.d.d[i].t = out.d.d[i].t;
+                in.d.d[i].f = out.d.d[i].f;
+            )
+            in.a = out.a;
+            in.v = out.v;
+
+            // appender
+            pint bitval;
+            sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
+            TIELO_X1 tielows[NVAL];
+            (i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
+            (i:0..NVAL-1:
+                bitval = (VAL & ( 1 << i )) >> i;
+                [  bitval = 1 ->
+                    out.d.d[i+N].t = sb.out[i];
+                    out.d.d[i+N].f = tielows[i].y;
+                [] bitval = 0 ->
+                    out.d.d[i+N].f = sb.out[i];
+                    out.d.d[i+N].t = tielows[i].y;
+                [] bitval >= 2 -> {false : "fuck"};        
+                ]
+            )
 
-          PULLUP_X4 pull_down(.a=nor_out, .y=out);
         }
+/**
+* Drops bits. Slices lines. Crop in. Enhance.
+* Useful if say, have an 8 bit packet coming in, but 
+* receiver only needs 3 of them.
+* KEEPS all bits between the two bounds.
+* e.g. drop_lines(8, 0, 3) would keep lines [0,1,2]
+**/
+export template<pint N, N0, N1>
+defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out; power supply) {
+    // {N0 >= 0 : "N0 can be minimum 0!"};
+    // {N1 <= N : "N1 can be maximum N"};
+
+    pint _N1, _N0;
+
+    _N1 = std::min(N1,N);
+    _N0 = std::max(N0,0);
+
+    [_N0 = 0 & _N1 = N ->
+      in = out;
+    [] _N0 != 0 | _N1 != N ->
+
+      vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
+      (i:_N1-_N0:
+          in.d.d[i + _N0] = out.d.d[i];
+      )
+
+      // in.a = out.a;
+
+      A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
+
+    ]
+
+
+
+}
+
+
+  export template<pint N; pint CONDITION_BIT>
+        defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
+        {
+            demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
+
+            in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
+            in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
+
+            A_2C_B_X1 val_Cel(.c1 = demux.in.v, .c2 = demux.cond.v, .y = in.v,
+                .vdd = supply.vdd, .vss = supply.vss);
+
+            // Not actually needed bc the current version of demux
+            // Something like below should be added once the handshakes are properly decoupled.
+            // wires the data and cond ack lines together anyway.
+            // A_2C_B_X1 ack_Cel(.c1 = demux.in.a, .c2 = demux.cond.a, .y = in.a,
+            //     .vdd = supply.vdd, .vss = supply.vss);
+
+            // in.v = demux.in.v;
+            in.a = demux.in.a;
+
+            (i:0..CONDITION_BIT-1:
+                in.d.d[i].f = demux.in.d.d[i].f;
+                in.d.d[i].t = demux.in.d.d[i].t;)
+
+            (i:CONDITION_BIT+1..N:
+                in.d.d[i].f = demux.in.d.d[i-1].f;
+                in.d.d[i].t = demux.in.d.d[i-1].t;)
+
+        }
+
+      export template<pint N>
+        defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
+        {
+            demux_bit<N,N> demux(.in = in, .out1 = out1, .out2 = out2, .reset_B = reset_B, .out1=out1, .out2=out2);
+        }
+
+/**
+* Create M sigbufs to buffer an M bool array to N strength.
+* Done lazily.
+**/
+export template<pint M, N>
+defproc sigbuf_boolarray(bool? in[M]; bool! out[M]; power supply) {
+    sigbuf<N> sb[M];
+    (i:M:
+        sb[i].in = in[i];
+        sb[i].out[0] = out[i];
+        sb[i].supply = supply;
+    )
+
+}
+
+
 }}

dataflow_neuro/registers.act

@@ -39,211 +39,309 @@ open std::channel;
 
 namespace tmpl {
     namespace dataflow_neuro {
-// Circuit for storing registers using AER
-// The block has the parameters:
-// lognw -> log2(number of words), parameters you can store
-// wl -> word length, length of each word 
-// N_dly_cfg -> the number of config bits in the ACK delay line
-// The block has the pins:
-// in -> input data,
-//        - the first bit is write/read_B
-//        - the next lognw bits describe the location, 
-//        - the last wl the word to write
-// data -> the data saved in the flip flop, sized wl x nw
-export template<pint lognw,wl,N_dly_cfg>
-defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
-    bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
-    pint nw = 1<<lognw;
-    //Validation of the input 
-    vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
-    sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
-    // Generation of the fake clock pulse (inverted because the ff clocks are low_active)
-    delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
-    INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
-    sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
-    // Sending back to the ackowledge
-    delayprog<N_dly_cfg> ack_dly(.in = _clock_temp_inv, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
-    sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
-    //Reset Buffers
-    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
-    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
-    // Creating the different flip flop arrays
-    bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
-    andtree<lognw> atree[nw];
-    AND2_X1 and_encoder[nw];
-    sigbuf<wl> clock_buffer[nw];
-    DFFQ_R_X1 ff[nw*wl];
-    pint bitval;
-    (k:nw:atree[k].supply = supply;)
-    (word_idx:nw:
-        // Decoding the bit pattern to understand which word we are looking at
-        (pin_idx:lognw:
-            bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
-            [bitval = 1 -> 
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
-            [] bitval = 0 ->
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
-            []bitval >= 2 -> {false : "fuck"};
-            ]
-        )
-        // Activating the fake clock for the right word
-        atree[word_idx].out = _out_encoder[word_idx];    
-        and_encoder[word_idx].a = _out_encoder[word_idx];
-        and_encoder[word_idx].b = _clock;
-        and_encoder[word_idx].y = _clock_word_temp[word_idx];
-        and_encoder[word_idx].vdd = supply.vdd;
-        and_encoder[word_idx].vss = supply.vss;
-        clock_buffer[word_idx].in = _clock_word_temp[word_idx];
-        clock_buffer[word_idx].supply = supply;
-        // Describing all the FF and their connection
-        (bit_idx:wl:
-            ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
-            ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
-            ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
-            ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
-            ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
-            ff[bit_idx+word_idx*(wl)].vss = supply.vss;
-        )
+
+
+/**
+ * A single register made out of A cells.
+ * MSB is whether to read or write.
+ * Currently only handles writing.
+ * NOTE: this does not handle in.v properly, and instead has in.v = in.a
+ */
+export template<pint N>
+defproc register_acells_improved(avMx1of2<N+1> in; Mx1of2<N> out;
+    bool? reset_B; power supply) {
+
+bool _resetX[N], _reset_BX[N];
+bool _en, _enBX;
+bool _flush, _flushBX;
+bool _out_v, _out_vB;
+bool _w = in.d.d[N].t;
+
+INV_X2 out_val_inv(.a = _out_v, .y = _out_vB,
+    .vdd = supply.vdd, .vss= supply.vss);
+
+// Reset sigs
+INV_X1 reset_inv(.a = reset_B, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N> reset_sb(.in = reset_inv.y, .out = _resetX, .supply = supply);
+sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
+
+A_2C1N_RB_X1 A_flush(.c1 = _en, .c2 = _out_v, .n1 = _w, .y = _flush,
+    .vdd = supply.vdd, .vss = supply.vss, .pr_B = _reset_BX[0], .sr_B = _reset_BX[0]);
+
+A_2C_X1 A_en(.c1  = _w, .c2 = _out_vB, .y = _en,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+INV_X1 flush_inv(.a = _flush, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_flushB(.in = flush_inv.y, .supply = supply);
+sb_flushB.out[0] = _flushBX;
+
+INV_X1 en_inv(.a = _en, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_enB(.in = en_inv.y, .supply = supply);
+sb_enB.out[0] = _enBX;
+
+vtree<N> vc(.in = out, .out = _out_v, .supply = supply);
+
+// WARNING WARNING
+in.v = in.a;
+
+A_1C1P_X1 A_ack(.c1 = _en, .p1 = _out_vB, .y = in.a,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+//function
+A_2C1N_SB_X4 f_buf_func[N];
+A_2C1N_RB_X4 t_buf_func[N];
+(i:N: 
+    f_buf_func[i].y=out.d[i].f;
+    t_buf_func[i].y=out.d[i].t;
+
+    f_buf_func[i].c1=_flushBX;
+    t_buf_func[i].c1=_flushBX;
+
+    f_buf_func[i].c2=_enBX;
+    t_buf_func[i].c2=_enBX;
+    
+    f_buf_func[i].n1=in.d.d[i].f;
+    t_buf_func[i].n1=in.d.d[i].t;
+
+    f_buf_func[i].vdd=supply.vdd;
+    t_buf_func[i].vdd=supply.vdd;
+    f_buf_func[i].vss=supply.vss;
+    t_buf_func[i].vss=supply.vss;
+    
+    f_buf_func[i].pr = _resetX[i];
+    f_buf_func[i].sr = _resetX[i];
+    t_buf_func[i].pr_B = _reset_BX[i];
+    t_buf_func[i].sr_B = _reset_BX[i];
+)
+
+}
+
+
+
+
+/** 
+ * Array of registers made out of A-cells
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * [-addr-][-word-][r/w]
+ */
+export template<pint NcA, NcW, M>
+defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
+    bool? reset_B; power supply) {
+
+
+// Input valid tree
+vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+bool _write_ack;
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+// Bit to join the acks either from read or write
+bool _read_ack;
+_read_ack = out.a;
+OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
+    .vdd = supply.vdd, .vss = supply.vss);
+A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
+
+// Write bit selector
+bool _w = in.d.d[NcA+NcW].t;
+bool _wX[M];
+sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
+A_2C_B_X1 write_selectors[M];
+(i:M:
+    write_selectors[i].c1 = _wX[i];
+    write_selectors[i].c2 = decoder.out[i];
+    write_selectors[i].vdd = supply.vdd;
+    write_selectors[i].vss = supply.vss;
+)
+
+
+// Registers
+register_acells_improved<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
     )
-    }
 
-// Circuit for storing  and reading registers using AER
-// The block has the parameters:
-// lognw -> log2(number of words), parameters you can store
-// wl -> word length, length of each word 
-// N_dly_cfg -> the number of config bits in the ACK delay line
-// The block has the pins:
-// in -> input data,
-//        - the MSB is write/read_B
-//        - the next MSB bits (size lognw) are the location, 
-//        - the LSB (size wl) are the word to write
-// out -> in case a reading phase is required, the output is used to show the stored data
-//        - the MSB bits (size lognw) tell the read register
-//        - the LSB bits (size wl) tell the word read
-// data -> the data saved in the flip flop, sized wl x nw
-export template<pint lognw,wl,N_dly_cfg>
-defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
-    pint nw = 1<<lognw;
-    bool _in_v_temp,_in_a_temp,_clock_temp,_clock[nw],_clock_temp_inv, _in_a_write, _in_a_read;
-    //Validation of the input 
-    vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
-    sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
-    // Acknowledgment
-    OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y =  _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
-    sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
-    // WRITE
-        // Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
-        bool _in_v_temp_write;
-        AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f, .y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
-        delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
-        INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
-        sigbuf<nw> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
-        sigbuf<wl> clock_buffer[nw];
-        bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
-        // Sending back to the ackowledge
-        bool _in_a_write_temp;
-        delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
-        AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
-    // READ
-        //Outputing the word to read
-        AND2_X1 word_to_read[nw];
-        sigbuf<wl*2> word_to_read_X[nw];
-        ortree<nw> bitselector_t[wl];
-        ortree<nw> bitselector_f[wl];
-        AND2_X1 word_selector_t[nw*wl];
-        AND2_X1 word_selector_f[nw*wl];
-        bool _out_word_to_read[2*nw*wl];
-        buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
-        AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
-        // Outputting the address if the read is true
-        (i:lognw:
-            address_propagator_t[i].a = in.d.d[lognw+wl].t;
-            address_propagator_t[i].b = in.d.d[i+wl].t;
-            address_propagator_t[i].y = output_buf.in.d.d[i+wl].t;
-            address_propagator_t[i].vdd = supply.vdd;
-            address_propagator_t[i].vss = supply.vss;
-            
-            address_propagator_f[i].a = in.d.d[lognw+wl].t;
-            address_propagator_f[i].b = in.d.d[i+wl].f;
-            address_propagator_f[i].y = output_buf.in.d.d[i+wl].f;
-            address_propagator_f[i].vdd = supply.vdd;
-            address_propagator_f[i].vss = supply.vss;
-        )
-        AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
-    //Reset Buffers
-    bool _reset_BX, _reset_BXX[nw],_reset_mem_BX,_reset_mem_BXX[nw*wl];
-    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<nw*wl> reset_mem_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
-    sigbuf<nw> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcW].t = write_selectors[i].y;
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
 
-    //Creating the encoder
-    andtree<lognw> atree[nw];
-    OR2_X1 or_encoder[nw];
-    INV_X1 inv_encoder[nw];
-    // Creating the different flip flop arrays
-    bool _out_encoder[nw];
-    DFFQ_R_X1 ff[nw*wl];
-    // For loop for assigning the different components
-    pint bitval;
-    (k:nw:atree[k].supply = supply;)
-    (word_idx:nw:
-        // Decoding the bit pattern to understand which word we are looking at
-        (pin_idx:lognw:
-            bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
-            [bitval = 1 -> 
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
-            [] bitval = 0 ->
-                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
-            []bitval >= 2 -> {false : "fuck"};
-            ]
-        )
-        // WRITE: Activating the fake clock for the right word
-        atree[word_idx].out = _out_encoder[word_idx];    
-        inv_encoder[word_idx].a = _out_encoder[word_idx];
-        inv_encoder[word_idx].y = or_encoder[word_idx].a;
-        inv_encoder[word_idx].vdd = supply.vdd;
-        inv_encoder[word_idx].vss = supply.vss;
-        or_encoder[word_idx].b = _clock[word_idx];
-        or_encoder[word_idx].y = _clock_word_temp[word_idx];
-        or_encoder[word_idx].vdd = supply.vdd;
-        or_encoder[word_idx].vss = supply.vss;
-        clock_buffer[word_idx].in = _clock_word_temp[word_idx];
-        clock_buffer[word_idx].supply = supply;
-        // READ: Selecting the right word to read if read is high
-        word_to_read[word_idx].a = in.d.d[lognw+wl].t;
-        word_to_read[word_idx].b = _out_encoder[word_idx];
-        word_to_read[word_idx].y = word_to_read_X[word_idx].in;
-        word_to_read[word_idx].vdd = supply.vdd;
-        word_to_read[word_idx].vss = supply.vss;
-        word_to_read_X[word_idx].supply = supply;
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
 
+    // Connect outputs
+    data[i] = registers[i].out;
 
-        
-        (bit_idx:wl:
-            // Describing all the FF and their connection
-            ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
-            ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
-            ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
-            ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
-            ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
-            ff[bit_idx+word_idx*(wl)].vss = supply.vss;
-            // READ: creating the selectors for propagating the right word
-            word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+word_idx*(wl)].a;
-            word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+word_idx*(wl)].a;
-            word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q;
-            word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
-            word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q_B;
-            word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
-            bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
-            bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
-            bitselector_t[bit_idx].supply = supply;
-            bitselector_f[bit_idx].supply = supply;
-        )
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+// Read bit selector
+bool _r = in.d.d[NcA+NcW].f;
+bool _rX[M+NcA];
+sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
+A_2C_B_X1 read_selectors[M];
+sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
+(i:M:
+    read_selectors[i].c1 = _rX[i];
+    read_selectors[i].c2 = decoder.out[i];
+    read_selectors[i].vdd = supply.vdd;
+    read_selectors[i].vss = supply.vss;
+
+    read_selectorsX.in[i] = read_selectors[i].y;
+)
+
+// OrTrees for each output word bit on read
+ortree<M> out_ortrees_t[NcW];
+ortree<M> out_ortrees_f[NcW];
+(i:NcW:
+    out_ortrees_t[i].out = out.d.d[i+NcA].t;
+    out_ortrees_f[i].out = out.d.d[i+NcA].f;
+
+    out_ortrees_t[i].supply = supply;
+    out_ortrees_f[i].supply = supply;
+)
+
+// ANDs over each reg's data
+// and whether it is selected for read.
+AND2_X1 and_reads_t[NcW * M];
+AND2_X1 and_reads_f[NcW * M];
+pint index;
+(i:NcW:
+    (j:M:
+        index = i + j*NcW;
+
+        and_reads_t[index].a = data[j].d[i].t;
+        and_reads_t[index].b = read_selectorsX.out[j];
+        and_reads_f[index].a = data[j].d[i].f;
+        and_reads_f[index].b = read_selectorsX.out[j];
+
+        and_reads_t[index].y = out_ortrees_t[i].in[j];
+        and_reads_f[index].y = out_ortrees_f[i].in[j];
+
+        and_reads_t[index].vss = supply.vss;
+        and_reads_t[index].vdd = supply.vdd;
+        and_reads_f[index].vss = supply.vss;
+        and_reads_f[index].vdd = supply.vdd;
     )
-    }
+
+)
+
+// C elements passing address to out on read.
+A_2C_B_X1 addr_read_t[NcA];
+A_2C_B_X1 addr_read_f[NcA];
+(i:NcA:
+    addr_read_t[i].c1 = in.d.d[i].t;
+    addr_read_f[i].c1 = in.d.d[i].f;
+
+    addr_read_t[i].c2 = _rX[M+i];
+    addr_read_f[i].c2 = _rX[M+i];
+
+    addr_read_t[i].y = out.d.d[i].t;
+    addr_read_f[i].y = out.d.d[i].f;
+
+    addr_read_t[i].vdd = supply.vdd;
+    addr_read_t[i].vss = supply.vss;
+    addr_read_f[i].vdd = supply.vdd;
+    addr_read_f[i].vss = supply.vss;
+
+
+)
+
+
+
+}
+
+
+
+
+
+
+/** 
+ * Array of registers made out of A-cells.
+ * !!!Registers ONLY have write functionality!!!
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * LSB [-addr-][-word-] MSB
+ */
+export template<pint NcA, NcW, M>
+defproc register_w_array(avMx1of2<NcA + NcW> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
+    bool? reset_B; power supply) {
+
+
+// Input valid tree
+vtree<NcA + NcW> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+bool _write_ack;
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+A_2C_B_X1 ack_safety(.c1 = _write_ack, .c2 = in.v, .y = in.a);
+
+
+// Registers
+register_acells_improved<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
+    )
+
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcW].t = decoder.out[i];
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
+
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
+
+    // Connect outputs
+    data[i] = registers[i].out;
+
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+
+}
 
 
 

dataflow_neuro/treegates.act

@@ -418,7 +418,7 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
 {
 
   { N >= 0 : "sigbuf: parameter error" };
-  { N <= 43 : "sigbuf: parameter error, N too big" };
+//  { N <= 43 : "sigbuf: parameter error, N too big" };
 
 	  /* -- just use in sized driver here -- */
     [ N <= 4 ->
@@ -433,8 +433,18 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
     BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
    [] N >= 19 & N <= 29 -> 
     BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
-   [] N >= 30 & N <= 42 -> 
+   [] N >= 30 & N<= 48-> 
     BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 49 & N <= 64 -> 
+    BUF_X16 buf16 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 65 & N <= 96 -> 
+    BUF_X24 buf24 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 97 -> 
+    BUF_X32 buf32 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+  //  [] N >= 129 & N <=192 -> 
+  //   BUF_X48 buf48 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+  // [] N >= 193 & N <= 256-> 
+  //   BUF_X64 buf64 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
    ]
    (i:1..N-1:out[i]=out[0];)
 }
@@ -445,7 +455,7 @@ defproc sigbuf_1output (bool? in; bool! out; power supply)
 {
 
   { N >= 0 : "sigbuf: parameter error" };
-  { N <= 43 : "sigbuf: parameter error, N too big" };
+  { N <= 43 : "sigbuf: parameter error, N too big" }; 
 
     /* -- just use in sized driver here -- */
     [ N <= 4 ->

test/prsim_plot.py

@@ -1,4 +1,4 @@
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 import sys
 import glob
@@ -99,10 +99,18 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 		if len(r) >= 1:
 			include_all_times = True
 
+
+	# Check if user gave "nowarn" flag
+	plot_warn = True
+	for arg in argv:
+		r = re.findall(r'(-nowarn?)', arg)
+		if len(r) >= 1:
+			plot_warn = False
+
 	# Get list of all times (before filtering)
 	unique_times = np.unique([int(e[0]) for e in entries])
 
-	assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
+	# assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
 	if include_given: print(f"Including signals that match regex {include_re}")
 	if exclude_given: print(f"Excluding signals that match regex {exclude_re}")
 
@@ -225,8 +233,8 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 		ax.text(time_to_index(time), num_sigs, time, ha = "center", va = "top", size = 10, rotation = 90)
 
 	# Find and plot wrong Assert statements
-	asserts = re.findall(r"\t *(\d+) .*\nWRONG ASSERT:\t(.+)", f)
-	if len(asserts): print("Failed asserts found!")
+	asserts = re.findall(r"\t *(\d+) .*\n(WRONG ASSERT|WARNING):\t?(.+)", f)
+	if len(asserts): print("Warnings found!")
 	for a in asserts:
 		print(a)
 		time = int(a[0])
@@ -234,11 +242,12 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 			try:
 				time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
 			except:
-				print(f"Couldn't find an appropriate time for assert {a}")
+				print(f"Couldn't find an appropriate time for warning {a}")
 				continue
 		index = time_to_index(time)
-		ax.axvline(index+0.5, c = "red", lw = 2)
-		ax.text(index+0.5, -1, a[1], rotation = 90, ha = "center", va = "bottom", c = "red")
+		if plot_warn:
+			ax.axvline(index+0.5, c = "red", lw = 2)
+			ax.text(index+0.5, -1, a[2], rotation = 90, ha = "center", va = "bottom", c = "red")
 
 	# Find echoed statements of the form "[digits] text"
 	echoes = re.findall(r"\t *(\d+) [^\t]*\n(\[\d*\].+)", f)

test/repeat_unit.sh

@@ -1,85 +1,94 @@
-# repeatedly run prsim on one unit_test's PRs
+#!/bin/sh
 
+fail=0
+faildirs=""
+proc=""
 bold=$(tput bold)
 normal=$(tput sgr0)
 und=$(tput smul)
-i=${unit}
-proc="$i<>"
 
-echo ""
-echo "${bold}******************************************"
-echo "* ${i} repetitions , show warnings=${warning}*"
-echo "******************************************${normal}"
+faildirs=""
+failed=0
+iteration=0
+numberofruns=100
+
+#
+#  run_test name [option]
+#
+run_test () {
+    echo "Testing ${bold}$1 ${normal} for $2 random delay runs"
+    # clear run directory
+    if [ -d $1/run ]; then
+	    rm -rf $1/run
+    fi
+    mkdir $1/run
+    cp init.prs $1/run/test.prs
+    if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
+            echo "random_seed $2" > $1/run/prsim.in
+	    cat init_qdi.prsim $1/test.prsim >> $1/run/prsim.in
+	    cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
+	    if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
+	        echo "${bold}*** simulation failed seed: $2 ***${normal}"
+	        faildirs="${faildirs} ${1}-sim($2)"
+	        failed=1
+	        echo	
+	    fi
+    else
+	    echo "${bold}*** circuit construction failed ***${normal}"
+	    faildirs="${faildirs} ${1}-ckt"
+	    failed=1
+        echo
+    fi
+}
+
+if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
+    echo "${bold}Error:${bold} aflat & prsim necessary for tests."
+    exit 1
+fi
+
+if [ ! -d "unit_tests" ];
+then
+    echo "${bold}Error:${bold} no unit_tests directory."
+    exit 1
+fi    
 
 cd "unit_tests"
-echo "${bold}... checking aflat${normal}"
 
-# check aflat
-if ($ACT_HOME/bin/aflat "$i/test_final.act" > "$i/test.prs");
-then
-    echo "${bold}... aflat complete, checking in prsim${normal}"
-    
-  # run prsim on prs
-    (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test.prsim") > "$i/prsim.out");
-    if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found")
-    then
-        echo "FAILED in first prsim"
-    else
-        
-        # show warnings setting
-        if [ "${warning}" = "1" ];
-        then
-          echo "${bold}Exit on prsim warnings turned ON${normal}"
-        else
-          echo "${bold}Exit on prsim warnings turned OFF${normal}"
-        fi
-        echo ""
-        
-        # begin prsim test loop
-        has_failed=0
-        iter=0
-        echo "${bold}using random_seed${normal}"
-        echo "\nusing random_seed" >> "$i/prsim.out"
-        while [ has_failed=0 ]
-        do
-            # write prsim test file with random seed appended to top of file
-            (echo "random_seed $iter \nrandom" > "$i/test_rand.prsim");
-            (cat "$i/test.prsim" >> "$i/test_rand.prsim");
-            (echo "\nTEST $iter\n" >> "$i/prsim.out");
-            
-            # validate prsim output
-            if (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test_rand.prsim") >> "$i/prsim.out");
-            then
-                if [ "${warning}" = "1" ];
-                then
-                  if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found" -e "WARNING:");
-                  then
-                      echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
-                      has_failed=1
-                      exit 0
-                  else
-                      echo "==> passed test #${iter}"
-                      iter=$(($iter + 1))
-                  fi
-                else
-                  if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found");
-                  then
-                      echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
-                      has_failed=1
-                      exit 0
-                  else
-                      echo "==> passed test #${iter}"
-                      iter=$(($iter + 1))
-                  fi
-                fi
-            else
-                has_failed=1
-                exit 0
-            fi
-        done
-        (cd ".."; pwd);
-        exit 1
-    fi
-else
-    echo "FAILED in aflat conversion"
+# run all test except single one is specified
+if [ ! -z $3 ]; then 
+  iteration=$3
 fi
+if [ ! -z $2 ]; then 
+  numberofruns=$2
+fi
+  
+if [ -z $1 ]; then
+    for i in *
+    do
+        if [ -d $i -a -f $i/test.act ]; then
+        	while [ $iteration -lt $numberofruns ]
+        	do
+	        	run_test $iteration
+                iteration=$iteration+1
+	        done 
+        fi
+    done
+else
+       while [ $iteration -lt $numberofruns ]
+       do
+	       run_test $1 $iteration
+           iteration=$((iteration+1))
+       done 
+    
+fi
+
+if [ $failed -eq 1 ]; then
+    echo ""
+    echo "${bold}*********************************"
+    echo "* FAILED DIRECTORIES:${normal}$faildirs ${bold}*"
+    echo "*********************************${normal}"
+fi
+
+exit $failed
+
+

test/run.sh

@@ -22,7 +22,8 @@ run_test () {
     mkdir $1/run
     cp init.prs $1/run/test.prs
     if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
-	    cat init_qdi.prsim $1/test.prsim | prsim -r $1/run/test.prs > $1/run/prsim.out
+	    cat init_qdi.prsim $1/test.prsim > $1/run/prsim.in
+	    cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
 	    if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
 	        echo "${bold}*** simulation failed ***${normal}"
 	        faildirs="${faildirs} ${1}-sim"

test/unit_tests/append_5_3_2/test.act

@@ -0,0 +1,53 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ *  It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc append_5_3_2(avMx1of2<5> in; avMx1of2<8> out)
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+
+  fifo<5,4> fifo_pre(.in = in, .reset_B = _reset_B);
+  append<5,3,3> app(.in = fifo_pre.out);
+  fifo<5+3,4> fifo_post(.in = app.out, .out = out, .reset_B = _reset_B);
+
+  app.supply.vdd = Vdd;
+  app.supply.vss = GND;
+  fifo_pre.supply.vdd = Vdd;
+  fifo_pre.supply.vss = GND;
+  fifo_post.supply.vdd = Vdd;
+  fifo_post.supply.vss = GND;
+}
+
+append_5_3_2 b;

test/unit_tests/append_5_3_2/test.prsim

@@ -0,0 +1,78 @@
+watchall
+
+set b.out.a 0
+set b.out.v 0
+set Reset 0
+set-qdi-channel-neutral "b.in" 5
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+status X
+assert-qdi-channel-neutral "b.out" 8
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] sending in a 31'"
+set-qdi-channel-valid "b.in" 5 31
+cycle
+assert-qdi-channel-valid "b.out" 8 127
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] removing input'"
+set-qdi-channel-neutral "b.in" 5
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] sending in a 0'"
+set-qdi-channel-valid "b.in" 5 0
+cycle
+# assert-qdi-channel-valid "b.out" 8 96
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] removing input'"
+set-qdi-channel-neutral "b.in" 5
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+
+system "echo '[] receiving out ack/val'"
+set b.out.a 1
+set b.out.v 1
+cycle
+assert-qdi-channel-neutral "b.out" 8
+
+
+system "echo '[] removing out ack/val'"
+set b.out.a 0
+set b.out.v 0
+cycle
+assert-qdi-channel-valid "b.out" 8 96
+
+
+system "echo '[] receiving out ack/val'"
+set b.out.a 1
+set b.out.v 1
+cycle
+assert-qdi-channel-neutral "b.out" 8
+
+
+system "echo '[] removing out ack/val'"
+set b.out.a 0
+set b.out.v 0
+cycle
+assert-qdi-channel-neutral "b.out" 8
+
+
+
+

test/unit_tests/arbtree_5/run/prsim.out

@@ -1,85 +1,2 @@
-t.in[0] t.out t.in[2] t.in[3] t.at.tmp[6] t.at.tmp[5] t.at.tmp[8] t.in[4] t.at.arbs[1]._y t.in[1] t.at.arbs[2]._y t.at.arbs[3]._y t.at.arbs[0]._y 
+t.at.arbs[2]._y1_arb t.in[2].r t.at.arbs[0].ack_cell1._y t.at.arbs[0]._y1_arb t.at.tmp[6].a t.at.arbs[1]._y1_arb t.at.arbs[3]._y1_arb t.in[1].a t.out.r t.in[4].r t.at.tmp[8].a t.at.tmp[5].r t.in[1].r t.in[3].r t.in[0].r t.at.tmp[6].r t.at.arbs[0].ack_cell2._y t.in[3].a t.at.tmp[8].r t.at.tmp[5].a t.at.arbs[2]._y2_arb t.in[0].a t.at.arbs[2].arbiter._y1 t.at.arbs[3]._y2_arb t.in[2].a t.out.a t.at.arbs[1].arbiter._y2 t.at.arbs[0].arbiter._y1 t.in[4].a t.at.arbs[2].arbiter._y2 t.at.arbs[0]._y2_arb t.at.arbs[3].ack_cell2._y t.at.arbs[2].ack_cell2._y t.at.arbs[1]._y2_arb t.at.arbs[1].or_cell._y t.at.arbs[1].arbiter._y1 t.at.arbs[3].arbiter._y1 t.at.arbs[3].ack_cell1._y t.at.arbs[0].or_cell._y t.at.arbs[1].ack_cell2._y t.at.arbs[2].ack_cell1._y t.at.arbs[3].arbiter._y2 t.at.arbs[0].arbiter._y2 t.at.arbs[2].or_cell._y t.at.arbs[1].ack_cell1._y t.at.arbs[3].or_cell._y 
 0
-1
-	         0 t.in[0] : 0
-	         0 t.in[4] : 0
-	         0 t.in[3] : 0
-	         0 t.in[2] : 0
-	         0 t.in[1] : 0
-	         1 t.at.arbs[1]._y : 1  [by t.in[2]:=0]
-	      7092 t.at.arbs[0]._y : 1  [by t.in[1]:=0]
-	      7094 t.at.tmp[5] : 0  [by t.at.arbs[0]._y:=1]
-	     10468 t.at.tmp[6] : 0  [by t.at.arbs[1]._y:=1]
-	     15221 t.at.arbs[2]._y : 1  [by t.at.tmp[6]:=0]
-	     16358 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	     16472 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	     81838 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting all low
-[] setting bit 0 high
-	     81838 t.in[0] : 1
-	     83564 t.at.arbs[0]._y : 0  [by t.in[0]:=1]
-	     83603 t.at.tmp[5] : 1  [by t.at.arbs[0]._y:=0]
-	     83618 t.at.arbs[2]._y : 0  [by t.at.tmp[5]:=1]
-	     84109 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	     84122 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	     84162 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	     84162 t.in[0] : 0
-	     84577 t.at.arbs[0]._y : 1  [by t.in[0]:=0]
-	     84597 t.at.tmp[5] : 0  [by t.at.arbs[0]._y:=1]
-	     90658 t.at.arbs[2]._y : 1  [by t.at.tmp[5]:=0]
-	     90705 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	     90721 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    134819 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 1 high
-	    134819 t.in[1] : 1
-	    148543 t.at.arbs[0]._y : 0  [by t.in[1]:=1]
-	    148547 t.at.tmp[5] : 1  [by t.at.arbs[0]._y:=0]
-	    157676 t.at.arbs[2]._y : 0  [by t.at.tmp[5]:=1]
-	    157691 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	    200939 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	    237870 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	    237870 t.in[1] : 0
-	    237925 t.at.arbs[0]._y : 1  [by t.in[1]:=0]
-	    289578 t.at.tmp[5] : 0  [by t.at.arbs[0]._y:=1]
-	    319358 t.at.arbs[2]._y : 1  [by t.at.tmp[5]:=0]
-	    333207 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	    358019 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    372362 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 2 high
-	    372362 t.in[2] : 1
-	    372784 t.at.arbs[1]._y : 0  [by t.in[2]:=1]
-	    421498 t.at.tmp[6] : 1  [by t.at.arbs[1]._y:=0]
-	    421499 t.at.arbs[2]._y : 0  [by t.at.tmp[6]:=1]
-	    421500 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	    441705 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	    441987 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	    441987 t.in[2] : 0
-	    442755 t.at.arbs[1]._y : 1  [by t.in[2]:=0]
-	    442758 t.at.tmp[6] : 0  [by t.at.arbs[1]._y:=1]
-	    465199 t.at.arbs[2]._y : 1  [by t.at.tmp[6]:=0]
-	    465750 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	    466821 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    467775 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 3 high
-	    467775 t.in[3] : 1
-	    468856 t.at.arbs[1]._y : 0  [by t.in[3]:=1]
-	    523326 t.at.tmp[6] : 1  [by t.at.arbs[1]._y:=0]
-	    524308 t.at.arbs[2]._y : 0  [by t.at.tmp[6]:=1]
-	    524326 t.at.tmp[8] : 1  [by t.at.arbs[2]._y:=0]
-	    528339 t.at.arbs[3]._y : 0  [by t.at.tmp[8]:=1]
-	    532342 t.out : 1  [by t.at.arbs[3]._y:=0]
-[] setting all low
-	    532342 t.in[3] : 0
-	    577243 t.at.arbs[1]._y : 1  [by t.in[3]:=0]
-	    598827 t.at.tmp[6] : 0  [by t.at.arbs[1]._y:=1]
-	    603587 t.at.arbs[2]._y : 1  [by t.at.tmp[6]:=0]
-	    604089 t.at.tmp[8] : 0  [by t.at.arbs[2]._y:=1]
-	    604292 t.at.arbs[3]._y : 1  [by t.at.tmp[8]:=0]
-	    606146 t.out : 0  [by t.at.arbs[3]._y:=1]
-[] setting bit 4 high
-	    606146 t.in[4] : 1
-	    606285 t.at.arbs[3]._y : 0  [by t.in[4]:=1]
-	    642631 t.out : 1  [by t.at.arbs[3]._y:=0]

test/unit_tests/arbtree_5/run/test.prs

@@ -1,55 +1,321 @@
 = "GND" "GND"
 = "Vdd" "Vdd"
 = "Reset" "Reset"
-"t.at.arbs[0].a"|"t.at.arbs[0].b"->"t.at.arbs[0]._y"-
-~("t.at.arbs[0].a"|"t.at.arbs[0].b")->"t.at.arbs[0]._y"+
-"t.at.arbs[0]._y"->"t.at.arbs[0].y"-
-~("t.at.arbs[0]._y")->"t.at.arbs[0].y"+
-"t.at.arbs[1].a"|"t.at.arbs[1].b"->"t.at.arbs[1]._y"-
-~("t.at.arbs[1].a"|"t.at.arbs[1].b")->"t.at.arbs[1]._y"+
-"t.at.arbs[1]._y"->"t.at.arbs[1].y"-
-~("t.at.arbs[1]._y")->"t.at.arbs[1].y"+
-"t.at.arbs[2].a"|"t.at.arbs[2].b"->"t.at.arbs[2]._y"-
-~("t.at.arbs[2].a"|"t.at.arbs[2].b")->"t.at.arbs[2]._y"+
-"t.at.arbs[2]._y"->"t.at.arbs[2].y"-
-~("t.at.arbs[2]._y")->"t.at.arbs[2].y"+
-"t.at.arbs[3].a"|"t.at.arbs[3].b"->"t.at.arbs[3]._y"-
-~("t.at.arbs[3].a"|"t.at.arbs[3].b")->"t.at.arbs[3]._y"+
-"t.at.arbs[3]._y"->"t.at.arbs[3].y"-
-~("t.at.arbs[3]._y")->"t.at.arbs[3].y"+
-= "t.at.tmp[5]" "t.at.arbs[2].a"
-= "t.at.tmp[5]" "t.at.arbs[0].y"
-= "t.at.tmp[6]" "t.at.arbs[2].b"
-= "t.at.tmp[6]" "t.at.arbs[1].y"
-= "t.at.tmp[8]" "t.at.arbs[3].a"
-= "t.at.tmp[8]" "t.at.arbs[2].y"
-= "t.at.supply.vdd" "t.at.arbs[3].vdd"
-= "t.at.supply.vdd" "t.at.arbs[2].vdd"
-= "t.at.supply.vdd" "t.at.arbs[1].vdd"
-= "t.at.supply.vdd" "t.at.arbs[0].vdd"
-= "t.at.supply.vss" "t.at.arbs[3].vss"
-= "t.at.supply.vss" "t.at.arbs[2].vss"
-= "t.at.supply.vss" "t.at.arbs[1].vss"
-= "t.at.supply.vss" "t.at.arbs[0].vss"
-= "t.at.in[0]" "t.at.arbs[0].a"
-= "t.at.in[0]" "t.at.tmp[0]"
-= "t.at.in[1]" "t.at.arbs[0].b"
-= "t.at.in[1]" "t.at.tmp[1]"
-= "t.at.in[2]" "t.at.arbs[1].a"
-= "t.at.in[2]" "t.at.tmp[2]"
-= "t.at.in[3]" "t.at.arbs[1].b"
-= "t.at.in[3]" "t.at.tmp[3]"
-= "t.at.in[4]" "t.at.arbs[3].b"
-= "t.at.in[4]" "t.at.tmp[9]"
-= "t.at.in[4]" "t.at.tmp[7]"
-= "t.at.in[4]" "t.at.tmp[4]"
-= "t.at.out" "t.at.arbs[3].y"
-= "t.at.out" "t.at.tmp[10]"
+= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
+= "t.at.arbs[0].in1.a" "t.at.arbs[0].arbiter.d"
+= "t.at.arbs[0].in1.a" "t.at.arbs[0].ack_cell1.y"
+= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].arbiter.a"
+= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
+~"t.at.arbs[0].ack_cell1.c1"&~"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"+
+"t.at.arbs[0].ack_cell1.c1"&"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"-
+"t.at.arbs[0].ack_cell1._y"->"t.at.arbs[0].ack_cell1.y"-
+~("t.at.arbs[0].ack_cell1._y")->"t.at.arbs[0].ack_cell1.y"+
+= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
+= "t.at.arbs[0].in2.a" "t.at.arbs[0].arbiter.c"
+= "t.at.arbs[0].in2.a" "t.at.arbs[0].ack_cell2.y"
+= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].arbiter.b"
+= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].arbiter.vdd"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].or_cell.vdd"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell2.vdd"
+= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell1.vdd"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].arbiter.vss"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].or_cell.vss"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell2.vss"
+= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell1.vss"
+"t.at.arbs[0].arbiter.a"&"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"-
+~"t.at.arbs[0].arbiter.a"|~"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"+
+"t.at.arbs[0].arbiter.b"&"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"-
+~"t.at.arbs[0].arbiter.b"|~"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"+
+"t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c"->"t.at.arbs[0].arbiter.y1"-
+~("t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c")->"t.at.arbs[0].arbiter.y1"+
+"t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d"->"t.at.arbs[0].arbiter.y2"-
+~("t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d")->"t.at.arbs[0].arbiter.y2"+
+mk_excllo("t.at.arbs[0].arbiter._y1","t.at.arbs[0].arbiter._y2")
+= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].arbiter.y1"
+= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].or_cell.a"
+= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].ack_cell1.c2"
+~"t.at.arbs[0].ack_cell2.c1"&~"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"+
+"t.at.arbs[0].ack_cell2.c1"&"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"-
+"t.at.arbs[0].ack_cell2._y"->"t.at.arbs[0].ack_cell2.y"-
+~("t.at.arbs[0].ack_cell2._y")->"t.at.arbs[0].ack_cell2.y"+
+"t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b"->"t.at.arbs[0].or_cell._y"-
+~("t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b")->"t.at.arbs[0].or_cell._y"+
+"t.at.arbs[0].or_cell._y"->"t.at.arbs[0].or_cell.y"-
+~("t.at.arbs[0].or_cell._y")->"t.at.arbs[0].or_cell.y"+
+= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
+= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell2.c1"
+= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell1.c1"
+= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].or_cell.y"
+= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
+= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].arbiter.y2"
+= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].or_cell.b"
+= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].ack_cell2.c2"
+= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
+= "t.at.arbs[1].in1.a" "t.at.arbs[1].arbiter.d"
+= "t.at.arbs[1].in1.a" "t.at.arbs[1].ack_cell1.y"
+= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].arbiter.a"
+= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
+~"t.at.arbs[1].ack_cell1.c1"&~"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"+
+"t.at.arbs[1].ack_cell1.c1"&"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"-
+"t.at.arbs[1].ack_cell1._y"->"t.at.arbs[1].ack_cell1.y"-
+~("t.at.arbs[1].ack_cell1._y")->"t.at.arbs[1].ack_cell1.y"+
+= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
+= "t.at.arbs[1].in2.a" "t.at.arbs[1].arbiter.c"
+= "t.at.arbs[1].in2.a" "t.at.arbs[1].ack_cell2.y"
+= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].arbiter.b"
+= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].arbiter.vdd"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].or_cell.vdd"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell2.vdd"
+= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell1.vdd"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].arbiter.vss"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].or_cell.vss"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell2.vss"
+= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell1.vss"
+"t.at.arbs[1].arbiter.a"&"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"-
+~"t.at.arbs[1].arbiter.a"|~"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"+
+"t.at.arbs[1].arbiter.b"&"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"-
+~"t.at.arbs[1].arbiter.b"|~"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"+
+"t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c"->"t.at.arbs[1].arbiter.y1"-
+~("t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c")->"t.at.arbs[1].arbiter.y1"+
+"t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d"->"t.at.arbs[1].arbiter.y2"-
+~("t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d")->"t.at.arbs[1].arbiter.y2"+
+mk_excllo("t.at.arbs[1].arbiter._y1","t.at.arbs[1].arbiter._y2")
+= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].arbiter.y1"
+= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].or_cell.a"
+= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].ack_cell1.c2"
+~"t.at.arbs[1].ack_cell2.c1"&~"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"+
+"t.at.arbs[1].ack_cell2.c1"&"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"-
+"t.at.arbs[1].ack_cell2._y"->"t.at.arbs[1].ack_cell2.y"-
+~("t.at.arbs[1].ack_cell2._y")->"t.at.arbs[1].ack_cell2.y"+
+"t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b"->"t.at.arbs[1].or_cell._y"-
+~("t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b")->"t.at.arbs[1].or_cell._y"+
+"t.at.arbs[1].or_cell._y"->"t.at.arbs[1].or_cell.y"-
+~("t.at.arbs[1].or_cell._y")->"t.at.arbs[1].or_cell.y"+
+= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
+= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell2.c1"
+= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell1.c1"
+= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].or_cell.y"
+= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
+= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].arbiter.y2"
+= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].or_cell.b"
+= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].ack_cell2.c2"
+= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
+= "t.at.arbs[2].in1.a" "t.at.arbs[2].arbiter.d"
+= "t.at.arbs[2].in1.a" "t.at.arbs[2].ack_cell1.y"
+= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].arbiter.a"
+= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
+~"t.at.arbs[2].ack_cell1.c1"&~"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"+
+"t.at.arbs[2].ack_cell1.c1"&"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"-
+"t.at.arbs[2].ack_cell1._y"->"t.at.arbs[2].ack_cell1.y"-
+~("t.at.arbs[2].ack_cell1._y")->"t.at.arbs[2].ack_cell1.y"+
+= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
+= "t.at.arbs[2].in2.a" "t.at.arbs[2].arbiter.c"
+= "t.at.arbs[2].in2.a" "t.at.arbs[2].ack_cell2.y"
+= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].arbiter.b"
+= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].arbiter.vdd"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].or_cell.vdd"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell2.vdd"
+= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell1.vdd"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].arbiter.vss"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].or_cell.vss"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell2.vss"
+= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell1.vss"
+"t.at.arbs[2].arbiter.a"&"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"-
+~"t.at.arbs[2].arbiter.a"|~"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"+
+"t.at.arbs[2].arbiter.b"&"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"-
+~"t.at.arbs[2].arbiter.b"|~"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"+
+"t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c"->"t.at.arbs[2].arbiter.y1"-
+~("t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c")->"t.at.arbs[2].arbiter.y1"+
+"t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d"->"t.at.arbs[2].arbiter.y2"-
+~("t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d")->"t.at.arbs[2].arbiter.y2"+
+mk_excllo("t.at.arbs[2].arbiter._y1","t.at.arbs[2].arbiter._y2")
+= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].arbiter.y1"
+= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].or_cell.a"
+= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].ack_cell1.c2"
+~"t.at.arbs[2].ack_cell2.c1"&~"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"+
+"t.at.arbs[2].ack_cell2.c1"&"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"-
+"t.at.arbs[2].ack_cell2._y"->"t.at.arbs[2].ack_cell2.y"-
+~("t.at.arbs[2].ack_cell2._y")->"t.at.arbs[2].ack_cell2.y"+
+"t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b"->"t.at.arbs[2].or_cell._y"-
+~("t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b")->"t.at.arbs[2].or_cell._y"+
+"t.at.arbs[2].or_cell._y"->"t.at.arbs[2].or_cell.y"-
+~("t.at.arbs[2].or_cell._y")->"t.at.arbs[2].or_cell.y"+
+= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
+= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell2.c1"
+= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell1.c1"
+= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].or_cell.y"
+= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
+= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].arbiter.y2"
+= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].or_cell.b"
+= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].ack_cell2.c2"
+= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
+= "t.at.arbs[3].in1.a" "t.at.arbs[3].arbiter.d"
+= "t.at.arbs[3].in1.a" "t.at.arbs[3].ack_cell1.y"
+= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].arbiter.a"
+= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
+~"t.at.arbs[3].ack_cell1.c1"&~"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"+
+"t.at.arbs[3].ack_cell1.c1"&"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"-
+"t.at.arbs[3].ack_cell1._y"->"t.at.arbs[3].ack_cell1.y"-
+~("t.at.arbs[3].ack_cell1._y")->"t.at.arbs[3].ack_cell1.y"+
+= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
+= "t.at.arbs[3].in2.a" "t.at.arbs[3].arbiter.c"
+= "t.at.arbs[3].in2.a" "t.at.arbs[3].ack_cell2.y"
+= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].arbiter.b"
+= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].arbiter.vdd"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].or_cell.vdd"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell2.vdd"
+= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell1.vdd"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].arbiter.vss"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].or_cell.vss"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell2.vss"
+= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell1.vss"
+"t.at.arbs[3].arbiter.a"&"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"-
+~"t.at.arbs[3].arbiter.a"|~"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"+
+"t.at.arbs[3].arbiter.b"&"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"-
+~"t.at.arbs[3].arbiter.b"|~"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"+
+"t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c"->"t.at.arbs[3].arbiter.y1"-
+~("t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c")->"t.at.arbs[3].arbiter.y1"+
+"t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d"->"t.at.arbs[3].arbiter.y2"-
+~("t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d")->"t.at.arbs[3].arbiter.y2"+
+mk_excllo("t.at.arbs[3].arbiter._y1","t.at.arbs[3].arbiter._y2")
+= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].arbiter.y1"
+= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].or_cell.a"
+= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].ack_cell1.c2"
+~"t.at.arbs[3].ack_cell2.c1"&~"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"+
+"t.at.arbs[3].ack_cell2.c1"&"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"-
+"t.at.arbs[3].ack_cell2._y"->"t.at.arbs[3].ack_cell2.y"-
+~("t.at.arbs[3].ack_cell2._y")->"t.at.arbs[3].ack_cell2.y"+
+"t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b"->"t.at.arbs[3].or_cell._y"-
+~("t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b")->"t.at.arbs[3].or_cell._y"+
+"t.at.arbs[3].or_cell._y"->"t.at.arbs[3].or_cell.y"-
+~("t.at.arbs[3].or_cell._y")->"t.at.arbs[3].or_cell.y"+
+= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
+= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell2.c1"
+= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell1.c1"
+= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].or_cell.y"
+= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
+= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].arbiter.y2"
+= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].or_cell.b"
+= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].ack_cell2.c2"
+= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
+= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
+= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
+= "t.at.tmp[5].r" "t.at.arbs[2].in1.r"
+= "t.at.tmp[5].a" "t.at.arbs[2].in1.a"
+= "t.at.tmp[5].d.d[0]" "t.at.arbs[2].in1.d.d[0]"
+= "t.at.tmp[5].r" "t.at.arbs[0].out.r"
+= "t.at.tmp[5].a" "t.at.arbs[0].out.a"
+= "t.at.tmp[5].d.d[0]" "t.at.arbs[0].out.d.d[0]"
+= "t.at.tmp[6].r" "t.at.arbs[2].in2.r"
+= "t.at.tmp[6].a" "t.at.arbs[2].in2.a"
+= "t.at.tmp[6].d.d[0]" "t.at.arbs[2].in2.d.d[0]"
+= "t.at.tmp[6].r" "t.at.arbs[1].out.r"
+= "t.at.tmp[6].a" "t.at.arbs[1].out.a"
+= "t.at.tmp[6].d.d[0]" "t.at.arbs[1].out.d.d[0]"
+= "t.at.tmp[8].r" "t.at.arbs[3].in1.r"
+= "t.at.tmp[8].a" "t.at.arbs[3].in1.a"
+= "t.at.tmp[8].d.d[0]" "t.at.arbs[3].in1.d.d[0]"
+= "t.at.tmp[8].r" "t.at.arbs[2].out.r"
+= "t.at.tmp[8].a" "t.at.arbs[2].out.a"
+= "t.at.tmp[8].d.d[0]" "t.at.arbs[2].out.d.d[0]"
+= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
+= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
+= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
+= "t.at.supply.vss" "t.at.arbs[3].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[3].supply.vdd"
+= "t.at.supply.vss" "t.at.arbs[2].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[2].supply.vdd"
+= "t.at.supply.vss" "t.at.arbs[1].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[1].supply.vdd"
+= "t.at.supply.vss" "t.at.arbs[0].supply.vss"
+= "t.at.supply.vdd" "t.at.arbs[0].supply.vdd"
+= "t.at.in[0].d.d[0]" "t.at.in[0].r"
+= "t.at.in[1].d.d[0]" "t.at.in[1].r"
+= "t.at.in[2].d.d[0]" "t.at.in[2].r"
+= "t.at.in[3].d.d[0]" "t.at.in[3].r"
+= "t.at.in[4].d.d[0]" "t.at.in[4].r"
+= "t.at.in[0].r" "t.at.arbs[0].in1.r"
+= "t.at.in[0].a" "t.at.arbs[0].in1.a"
+= "t.at.in[0].d.d[0]" "t.at.arbs[0].in1.d.d[0]"
+= "t.at.in[0].r" "t.at.tmp[0].r"
+= "t.at.in[0].a" "t.at.tmp[0].a"
+= "t.at.in[0].d.d[0]" "t.at.tmp[0].d.d[0]"
+= "t.at.in[1].r" "t.at.arbs[0].in2.r"
+= "t.at.in[1].a" "t.at.arbs[0].in2.a"
+= "t.at.in[1].d.d[0]" "t.at.arbs[0].in2.d.d[0]"
+= "t.at.in[1].r" "t.at.tmp[1].r"
+= "t.at.in[1].a" "t.at.tmp[1].a"
+= "t.at.in[1].d.d[0]" "t.at.tmp[1].d.d[0]"
+= "t.at.in[2].r" "t.at.arbs[1].in1.r"
+= "t.at.in[2].a" "t.at.arbs[1].in1.a"
+= "t.at.in[2].d.d[0]" "t.at.arbs[1].in1.d.d[0]"
+= "t.at.in[2].r" "t.at.tmp[2].r"
+= "t.at.in[2].a" "t.at.tmp[2].a"
+= "t.at.in[2].d.d[0]" "t.at.tmp[2].d.d[0]"
+= "t.at.in[3].r" "t.at.arbs[1].in2.r"
+= "t.at.in[3].a" "t.at.arbs[1].in2.a"
+= "t.at.in[3].d.d[0]" "t.at.arbs[1].in2.d.d[0]"
+= "t.at.in[3].r" "t.at.tmp[3].r"
+= "t.at.in[3].a" "t.at.tmp[3].a"
+= "t.at.in[3].d.d[0]" "t.at.tmp[3].d.d[0]"
+= "t.at.in[4].r" "t.at.arbs[3].in2.r"
+= "t.at.in[4].a" "t.at.arbs[3].in2.a"
+= "t.at.in[4].d.d[0]" "t.at.arbs[3].in2.d.d[0]"
+= "t.at.in[4].r" "t.at.tmp[9].r"
+= "t.at.in[4].a" "t.at.tmp[9].a"
+= "t.at.in[4].d.d[0]" "t.at.tmp[9].d.d[0]"
+= "t.at.in[4].r" "t.at.tmp[7].r"
+= "t.at.in[4].a" "t.at.tmp[7].a"
+= "t.at.in[4].d.d[0]" "t.at.tmp[7].d.d[0]"
+= "t.at.in[4].r" "t.at.tmp[4].r"
+= "t.at.in[4].a" "t.at.tmp[4].a"
+= "t.at.in[4].d.d[0]" "t.at.tmp[4].d.d[0]"
+= "t.at.in[4].d.d[0]" "t.at.in[4].r"
+= "t.at.in[3].d.d[0]" "t.at.in[3].r"
+= "t.at.in[2].d.d[0]" "t.at.in[2].r"
+= "t.at.in[1].d.d[0]" "t.at.in[1].r"
+= "t.at.in[0].d.d[0]" "t.at.in[0].r"
+= "t.at.out.d.d[0]" "t.at.out.r"
+= "t.at.out.r" "t.at.arbs[3].out.r"
+= "t.at.out.a" "t.at.arbs[3].out.a"
+= "t.at.out.d.d[0]" "t.at.arbs[3].out.d.d[0]"
+= "t.at.out.r" "t.at.tmp[10].r"
+= "t.at.out.a" "t.at.tmp[10].a"
+= "t.at.out.d.d[0]" "t.at.tmp[10].d.d[0]"
+= "t.at.out.d.d[0]" "t.at.out.r"
 = "Vdd" "t.at.supply.vdd"
 = "GND" "t.at.supply.vss"
-= "t.out" "t.at.out"
-= "t.in[0]" "t.at.in[0]"
-= "t.in[1]" "t.at.in[1]"
-= "t.in[2]" "t.at.in[2]"
-= "t.in[3]" "t.at.in[3]"
-= "t.in[4]" "t.at.in[4]"
+= "t.out.d.d[0]" "t.out.r"
+= "t.out.r" "t.at.out.r"
+= "t.out.a" "t.at.out.a"
+= "t.out.d.d[0]" "t.at.out.d.d[0]"
+= "t.out.d.d[0]" "t.out.r"
+= "t.in[0].d.d[0]" "t.in[0].r"
+= "t.in[1].d.d[0]" "t.in[1].r"
+= "t.in[2].d.d[0]" "t.in[2].r"
+= "t.in[3].d.d[0]" "t.in[3].r"
+= "t.in[4].d.d[0]" "t.in[4].r"
+= "t.in[0].r" "t.at.in[0].r"
+= "t.in[1].r" "t.at.in[1].r"
+= "t.in[2].r" "t.at.in[2].r"
+= "t.in[3].r" "t.at.in[3].r"
+= "t.in[4].r" "t.at.in[4].r"
+= "t.in[0].a" "t.at.in[0].a"
+= "t.in[1].a" "t.at.in[1].a"
+= "t.in[2].a" "t.at.in[2].a"
+= "t.in[3].a" "t.at.in[3].a"
+= "t.in[4].a" "t.at.in[4].a"
+= "t.in[0].d.d[0]" "t.at.in[0].d.d[0]"
+= "t.in[1].d.d[0]" "t.at.in[1].d.d[0]"
+= "t.in[2].d.d[0]" "t.at.in[2].d.d[0]"
+= "t.in[3].d.d[0]" "t.at.in[3].d.d[0]"
+= "t.in[4].d.d[0]" "t.at.in[4].d.d[0]"
+= "t.in[4].d.d[0]" "t.in[4].r"
+= "t.in[3].d.d[0]" "t.in[3].r"
+= "t.in[2].d.d[0]" "t.in[2].r"
+= "t.in[1].d.d[0]" "t.in[1].r"
+= "t.in[0].d.d[0]" "t.in[0].r"

test/unit_tests/arbtree_5/test.act

@@ -25,17 +25,29 @@
  *
  **************************************************************************
  */
-
-import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/coders.act";
 import globals;
-
 open tmpl::dataflow_neuro;
-
-defproc arbtree_5 (bool? in[5]; bool! out){
-    arbtree<5> at(.in=in, .out=out);
-    at.supply.vss = GND;
-    at.supply.vdd = Vdd;
-
+defproc arbtree (a1of1 in[5]; a1of1 out)
+{
+    a1of1 _in[5];
+    power _supply
+    _supply.vdd = Vdd;
+    _supply.vss = GND;
+    fifo_t<2> fifo_to_tree[5];
+    (i:5:
+        fifo_to_tree[i].in = in[i];
+        fifo_to_tree[i].out = _in[i];
+        fifo_to_tree.supply = _supply;
+        fifo_to_tree.reset_B = _reset_B;
+    )
+    arbtree<5> at(.in=_in, .out = out);
+    //Low active Reset
+    bool _reset_B;
+    prs {
+        Reset => _reset_B-
+    }
+    at.supply = _supply;
+    
 }
-
-arbtree_5 t;
+arbtree t;

test/unit_tests/arbtree_5/test.prsim

@@ -1,88 +1,127 @@
 watchall
 
-system "echo '0'"
+system "echo '[] setting channels neutral'"
 
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-
-system "echo '1'"
+set t.in[0].r 0
+set t.in[1].r 0
+set t.in[2].r 0
+set t.in[3].r 0
+set t.in[4].r 0
+set t.out.a 0
 
 cycle
 mode run
+assert t.out.r 0
 
-# assert t.out 0
+assert t.in[0].a 0
+assert t.in[1].a 0
+assert t.in[2].a 0
+assert t.in[3].a 0
+assert t.in[4].a 0
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
+
+system "echo '[] setting some reqs high'"
+set t.in[0].r 1
+set t.in[1].r 1
+set t.in[2].r 1
 cycle
+assert t.out.r 1
 
-system "echo '[] setting bit 0 high'"
-set t.in[0] 1
+system "echo '[] receiving ack'"
+set t.out.a 1
 cycle
+assert t.in.a 1
 
-
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
+system "echo '[] removing first req (guess)'"
+set t.in[0].r 0
 cycle
+assert t.out.r
 
 
-system "echo '[] setting bit 1 high'"
-set t.in[0] 0
-set t.in[1] 1
-cycle
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-cycle
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+
+# system "echo '1'"
+
+# cycle
+# mode run
+
+# # assert t.out 0
 
 
-system "echo '[] setting bit 2 high'"
-set t.in[1] 0
-set t.in[2] 1
-cycle
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
+
+# system "echo '[] setting bit 0 high'"
+# set t.in[0] 1
+# cycle
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-cycle
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
 
 
-system "echo '[] setting bit 3 high'"
-set t.in[2] 0
-set t.in[3] 1
-cycle
+# system "echo '[] setting bit 1 high'"
+# set t.in[0] 0
+# set t.in[1] 1
+# cycle
 
 
-system "echo '[] setting all low'"
-set t.in[0] 0
-set t.in[1] 0
-set t.in[2] 0
-set t.in[3] 0
-set t.in[4] 0
-cycle
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
 
-system "echo '[] setting bit 4 high'"
-set t.in[3] 0
-set t.in[4] 1
-cycle
+
+# system "echo '[] setting bit 2 high'"
+# set t.in[1] 0
+# set t.in[2] 1
+# cycle
+
+
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
+
+
+# system "echo '[] setting bit 3 high'"
+# set t.in[2] 0
+# set t.in[3] 1
+# cycle
+
+
+# system "echo '[] setting all low'"
+# set t.in[0] 0
+# set t.in[1] 0
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+# cycle
+
+# system "echo '[] setting bit 4 high'"
+# set t.in[3] 0
+# set t.in[4] 1
+# cycle

test/unit_tests/bd-fifo-register-fifo-bd/test.act

@@ -0,0 +1,64 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/interfaces.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    bd2qdi<9,4> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
+
+    fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);
+
+    // Make a register array with 3 bit address (-> 8 registers), 
+    // each register holding 5 bits.
+    registerA_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
+        .reset_B = _reset_B, .supply = supply);
+
+    fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);
+
+    qdi2bd<8,4> _qdi2bd(.in = fifo_post.out, .out = out, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_reg_fifo_3x5x8 b;

test/unit_tests/bd-fifo-register-fifo-bd/test.prsim

@@ -0,0 +1,202 @@
+watchall
+
+set-bd-channel-neutral "b.in" 9
+# set b.in.r 0
+set b.out.a 0
+
+set b.dly_cfg[0] 1
+set b.dly_cfg[1] 1
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
+
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert-bd-channel-neutral "b.out" 8
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-bd-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+# assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+# assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+# system "echo '[] Sending packet write 0s to reg0'"
+# set-qdi-channel-valid "b.in" 9 256
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+# assert-var-int "b.data[0]" 5 0
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+# assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 01100=12 to reg0'"
+set-bd-channel-valid "b.in" 9 352
+cycle
+assert b.in.a 1
+# assert b.in.v 1
+assert-var-int "b.data[0]" 5 12
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+# assert b.in.v 0
+assert-var-int "b.data[0]" 5 12
+
+
+# system "echo '[] Sending packet write 0s to reg1'"
+# set-qdi-channel-valid "b.in" 9 257
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+# assert-var-int "b.data[1]" 5 0
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg2'"
+# set-qdi-channel-valid "b.in" 9 258
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+# assert-var-int "b.data[2]" 5 0
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+# assert-var-int "b.data[2]" 5 0
+
+# system "echo '[] Sending packet write 0s to reg3'"
+# set-qdi-channel-valid "b.in" 9 259
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg4'"
+# set-qdi-channel-valid "b.in" 9 260
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg5'"
+# set-qdi-channel-valid "b.in" 9 261
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg6'"
+# set-qdi-channel-valid "b.in" 9 262
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# system "echo '[] Sending packet write 0s to reg7'"
+# set-qdi-channel-valid "b.in" 9 263
+# cycle
+# assert b.in.a 1
+# assert b.in.v 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0
+
+# assert-var-int "b.data[2]" 5 0
+# assert-var-int "b.data[3]" 5 0
+# assert-var-int "b.data[4]" 5 0
+# assert-var-int "b.data[5]" 5 0
+# assert-var-int "b.data[6]" 5 0
+# assert-var-int "b.data[7]" 5 0
+
+
+system "echo '[] Reading register 0'"
+set-bd-channel-valid "b.in" 9 0
+cycle
+assert-bd-channel-valid "b.out" 8 96
+assert b.out.r 1
+# assert b.in.v 1
+assert b.in.a 1
+
+set b.out.a 1
+cycle
+assert-bd-channel-neutral "b.out" 8
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+set b.out.a 0
+cycle
+
+
+# system "echo '[] Reading register 1'"
+# set-qdi-channel-valid "b.in" 9 1
+# cycle
+# assert-qdi-channel-valid "b.out" 8 1
+# assert b.in.v 1
+# assert b.in.a 1
+
+# set b.out.a 1
+# set b.out.v 1
+# cycle
+# assert b.in.a 1
+
+# system "echo '[] Removing input'"
+# set-qdi-channel-neutral "b.in" 9
+# cycle
+# assert-qdi-channel-neutral "b.out" 8
+# set b.out.a 0
+# set b.out.v 0
+# cycle
+# assert b.in.a 0
+# assert b.in.v 0

test/unit_tests/bd2qdi_5/run/prsim.out

@@ -0,0 +1,615 @@
+b.b._out_a_BX_f[0] b.b.dly.dly[5].__y b.b.dly.mu2[0]._s b.b._inB[1] b.b.dly.dly[9].__y b.in.r b.b._inB[4] b.b.dly.dly[6].y b.in.d[1] b.b.dly.dly[3].a b.in.d[4] b.b.dly.dly[11].__y b.b._reqX b.b._en_X_f[0] b.b.dly.dly[13].y b.b.dly.dly[4]._y b.dly_cfg[3] b.in.d[2] b.b.dly.dly[11].y b.b.dly.dly[0].a b.b._en_X_t[0] b.b.dly.mu2[3].b b.dly_cfg[2] b.b._out_a_BX_t[0] b.b._reqXX[0] b.out.v b.b.dly.dly[7].___y b.b._out_a_B b.b._inB[2] b.b._inB[0] b.b.dly._a[1] b.dly_cfg[1] b.b.dly.dly[8].__y b.b.dly.dly[4].___y b.in.d[0] b.b.dly.dly[8]._y b.b.dly.dly[0].__y b.dly_cfg[0] b.b.dly.dly[7].a b.b.req_buf._y b.b.dly.dly[8].y b.b.en_buf_f.buf2._y b.b.dly.dly[10].y b.b.dly.dly[3].___y b.b.dly.mu2[1]._y b.b.dly.dly[5].y b.b.dly._a[2] b.b.dly.dly[6]._y b.b.dly.mu2[3]._s b.b.dly.dly[7].y b.b.en_buf_t.buf2._y b.b._en b.b.dly._a[3] b.b.dly.dly[1].___y b.out.a b.in.d[3] b.b.dly.dly[2]._y b.b.dly.dly[7].__y b.b._req b.b.dly.dly[12].___y b.b.dly.dly[12].y b.b.dly.dly[8].___y b.b.dly.dly[1].a b.b.dly.dly[9].___y b.b.dly.dly[3].y b.b.dly.dly[2].y b.b.dly.dly[14].___y b.b._inB[3] b.b.dly.mu2[0]._y b.b.dly.dly[6].___y b.b.dly.and2[0]._y b.b.dly.dly[3]._y b.b.dly.dly[10].__y b.b.out_a_B_buf_t.buf2._y b.b.dly.mu2[3]._y b.b.req_bufarray.buf2._y b.b.dly.dly[5]._y b.b.dly.mu2[1]._s b.b.dly.dly[4].y b.b.dly.dly[1]._y b.b.dly.and2[3]._y b.b.dly.dly[13].___y b.b.dly.dly[0]._y b.b.dly.dly[11]._y b.b.dly.dly[14].__y b.b.dly.dly[1].__y b.b.dly.mu2[2]._y b.b.dly.and2[1]._y b.b.out_a_B_buf_f.buf2._y b.b.dly.dly[9].y b.b.dly.dly[0].___y b.b.dly.dly[7]._y b.b.dly.dly[13]._y b.b.dly.dly[4].__y b.b.dly.and2[2]._y b.b.dly.dly[12].__y b.b.dly.dly[11].___y b.b.dly.dly[1].y b.b.dly.dly[12]._y b.b.dly.dly[2].__y b.b.dly.dly[14]._y b.b.dly.dly[5].___y b.b.dly.dly[2].___y b.b.dly.dly[0].y b.b.dly.dly[3].__y b.b.dly.mu2[2]._s b.b.dly.dly[13].__y b.b.dly.dly[10].___y b.b.dly.dly[9]._y b.b.dly.dly[6].__y b.b.dly.dly[10]._y 
+	     87848 b.out.a : 0
+	     87848 Reset : 0
+	     87848 b.in.r : 0
+	     87848 b.dly_cfg[3] : 1
+	     87848 b.dly_cfg[2] : 1
+	     87848 b.in.d[4] : 0
+	     87848 b.out.v : 0
+	     87848 b.dly_cfg[1] : 1
+	     87848 b.in.d[3] : 1
+	     87848 b.in.d[2] : 0
+	     87848 b.dly_cfg[0] : 1
+	     87848 b.in.d[1] : 0
+	     87848 b.in.d[0] : 1
+	     87849 b.b.dly.mu2[1]._s : 0  [by b.dly_cfg[1]:=1]
+	     87849 b.b._inB[3] : 0  [by b.in.d[3]:=1]
+	     87851 b.b._inB[0] : 0  [by b.in.d[0]:=1]
+	     88130 b.b.dly.mu2[0]._s : 0  [by b.dly_cfg[0]:=1]
+	     88270 b.b._inB[4] : 1  [by b.in.d[4]:=0]
+	     88616 b.b._inB[1] : 1  [by b.in.d[1]:=0]
+	    101697 b.b.dly.and2[0]._y : 1  [by b.in.r:=0]
+	    102191 b.b.dly.mu2[2]._s : 0  [by b.dly_cfg[2]:=1]
+	    108053 b.b._inB[2] : 1  [by b.in.d[2]:=0]
+	    112660 b.b.dly.mu2[3]._s : 0  [by b.dly_cfg[3]:=1]
+	    117628 b._reset_B : 1  [by Reset:=0]
+	    118179 b.b.reset_buf._y : 0  [by b._reset_B:=1]
+	    119250 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
+	    120204 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
+	    121285 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]
+	    121303 b.b.f_buf_func[4]._y : X  [by b.b._reset_BXX[0]:=1]
+	    122267 b.b.f_buf_func[2]._y : X  [by b.b._reset_BXX[0]:=1]
+	    124138 b.b.dly.dly[0].a : 0  [by b.b.dly.and2[0]._y:=1]
+	    125288 b.b.t_buf_func[3]._y : X  [by b.b._reset_BXX[0]:=1]
+	    125298 b.b.t_buf_func[0]._y : X  [by b.b._reset_BXX[0]:=1]
+	    125501 b.b.t_buf_func[0].y : X  [by b.b.t_buf_func[0]._y:=X]
+	    125790 b.b.t_buf_func[3].y : X  [by b.b.t_buf_func[3]._y:=X]
+	    128898 b.b.dly.dly[0]._y : 1  [by b.b.dly.dly[0].a:=0]
+	    130752 b.b.dly.dly[0].__y : 0  [by b.b.dly.dly[0]._y:=1]
+	    130891 b.b.dly.dly[0].___y : 1  [by b.b.dly.dly[0].__y:=0]
+	    136562 b.b._en : 1  [by b.out.v:=0]
+	    136573 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	    136631 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	    136835 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+	    139501 b.b._out_a_B : 1  [by b.out.a:=0]
+	    139502 b.b.out_a_B_buf_f.buf2._y : 0  [by b.b._out_a_B:=1]
+	    139516 b.b.out_a_B_buf_t.buf2._y : 0  [by b.b._out_a_B:=1]
+	    139539 b.b._out_a_BX_t[0] : 1  [by b.b.out_a_B_buf_f.buf2._y:=0]
+	    140255 b.b._out_a_BX_f[0] : 1  [by b.b.out_a_B_buf_t.buf2._y:=0]
+	    143851 b.b.f_buf_func[2].y : X  [by b.b.f_buf_func[2]._y:=X]
+	    166204 b.b.f_buf_func[4].y : X  [by b.b.f_buf_func[4]._y:=X]
+	    167237 b.b.dly.dly[0].y : 0  [by b.b.dly.dly[0].___y:=1]
+	    167349 b.b.dly.mu2[0]._y : 1  [by b.b.dly.dly[0].y:=0]
+	    175755 b.b.f_buf_func[1]._y : X  [by b.b._reset_BXX[0]:=1]
+	    175795 b.b.f_buf_func[1].y : X  [by b.b.f_buf_func[1]._y:=X]
+	    188359 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+	    214861 b.b.dly._a[1] : 0  [by b.b.dly.mu2[0]._y:=1]
+	    215118 b.b.dly.and2[1]._y : 1  [by b.b.dly._a[1]:=0]
+	    215205 b.b.dly.dly[1].a : 0  [by b.b.dly.and2[1]._y:=1]
+	    215499 b.b.dly.dly[1]._y : 1  [by b.b.dly.dly[1].a:=0]
+	    215500 b.b.dly.dly[1].__y : 0  [by b.b.dly.dly[1]._y:=1]
+	    217306 b.b.dly.dly[1].___y : 1  [by b.b.dly.dly[1].__y:=0]
+	    219313 b.b.dly.dly[1].y : 0  [by b.b.dly.dly[1].___y:=1]
+	    220522 b.b.dly.dly[2]._y : 1  [by b.b.dly.dly[1].y:=0]
+	    221112 b.b.dly.dly[2].__y : 0  [by b.b.dly.dly[2]._y:=1]
+	    221290 b.b.dly.dly[2].___y : 1  [by b.b.dly.dly[2].__y:=0]
+	    222093 b.b.dly.dly[2].y : 0  [by b.b.dly.dly[2].___y:=1]
+	    222257 b.b.dly.mu2[1]._y : 1  [by b.b.dly.dly[2].y:=0]
+	    224452 b.b.dly._a[2] : 0  [by b.b.dly.mu2[1]._y:=1]
+	    224474 b.b.dly.and2[2]._y : 1  [by b.b.dly._a[2]:=0]
+	    225321 b.b.dly.dly[3].a : 0  [by b.b.dly.and2[2]._y:=1]
+	    255449 b.b.dly.dly[3]._y : 1  [by b.b.dly.dly[3].a:=0]
+	    255582 b.b.dly.dly[3].__y : 0  [by b.b.dly.dly[3]._y:=1]
+	    271244 b.b.dly.dly[3].___y : 1  [by b.b.dly.dly[3].__y:=0]
+	    271603 b.b.dly.dly[3].y : 0  [by b.b.dly.dly[3].___y:=1]
+	    285719 b.b.dly.dly[4]._y : 1  [by b.b.dly.dly[3].y:=0]
+	    285940 b.b.dly.dly[4].__y : 0  [by b.b.dly.dly[4]._y:=1]
+	    285947 b.b.dly.dly[4].___y : 1  [by b.b.dly.dly[4].__y:=0]
+	    285977 b.b.dly.dly[4].y : 0  [by b.b.dly.dly[4].___y:=1]
+	    292690 b.b.dly.dly[5]._y : 1  [by b.b.dly.dly[4].y:=0]
+	    350151 b.b.dly.dly[5].__y : 0  [by b.b.dly.dly[5]._y:=1]
+	    350242 b.b.dly.dly[5].___y : 1  [by b.b.dly.dly[5].__y:=0]
+	    352431 b.b.dly.dly[5].y : 0  [by b.b.dly.dly[5].___y:=1]
+	    352438 b.b.dly.dly[6]._y : 1  [by b.b.dly.dly[5].y:=0]
+	    355225 b.b.dly.dly[6].__y : 0  [by b.b.dly.dly[6]._y:=1]
+	    355331 b.b.dly.dly[6].___y : 1  [by b.b.dly.dly[6].__y:=0]
+	    355409 b.b.dly.dly[6].y : 0  [by b.b.dly.dly[6].___y:=1]
+	    355684 b.b.dly.mu2[2]._y : 1  [by b.b.dly.dly[6].y:=0]
+	    374680 b.b.dly._a[3] : 0  [by b.b.dly.mu2[2]._y:=1]
+	    375135 b.b.dly.and2[3]._y : 1  [by b.b.dly._a[3]:=0]
+	    375147 b.b.dly.dly[7].a : 0  [by b.b.dly.and2[3]._y:=1]
+	    375551 b.b.dly.dly[7]._y : 1  [by b.b.dly.dly[7].a:=0]
+	    375563 b.b.dly.dly[7].__y : 0  [by b.b.dly.dly[7]._y:=1]
+	    381479 b.b.dly.dly[7].___y : 1  [by b.b.dly.dly[7].__y:=0]
+	    385755 b.b.dly.dly[7].y : 0  [by b.b.dly.dly[7].___y:=1]
+	    388654 b.b.dly.dly[8]._y : 1  [by b.b.dly.dly[7].y:=0]
+	    392949 b.b.dly.dly[8].__y : 0  [by b.b.dly.dly[8]._y:=1]
+	    392951 b.b.dly.dly[8].___y : 1  [by b.b.dly.dly[8].__y:=0]
+	    397486 b.b.dly.dly[8].y : 0  [by b.b.dly.dly[8].___y:=1]
+	    398735 b.b.dly.dly[9]._y : 1  [by b.b.dly.dly[8].y:=0]
+	    402234 b.b.dly.dly[9].__y : 0  [by b.b.dly.dly[9]._y:=1]
+	    402400 b.b.dly.dly[9].___y : 1  [by b.b.dly.dly[9].__y:=0]
+	    402475 b.b.dly.dly[9].y : 0  [by b.b.dly.dly[9].___y:=1]
+	    402820 b.b.dly.dly[10]._y : 1  [by b.b.dly.dly[9].y:=0]
+	    402958 b.b.dly.dly[10].__y : 0  [by b.b.dly.dly[10]._y:=1]
+	    408221 b.b.dly.dly[10].___y : 1  [by b.b.dly.dly[10].__y:=0]
+	    408223 b.b.dly.dly[10].y : 0  [by b.b.dly.dly[10].___y:=1]
+	    452140 b.b.dly.dly[11]._y : 1  [by b.b.dly.dly[10].y:=0]
+	    452141 b.b.dly.dly[11].__y : 0  [by b.b.dly.dly[11]._y:=1]
+	    452689 b.b.dly.dly[11].___y : 1  [by b.b.dly.dly[11].__y:=0]
+	    452700 b.b.dly.dly[11].y : 0  [by b.b.dly.dly[11].___y:=1]
+	    453070 b.b.dly.dly[12]._y : 1  [by b.b.dly.dly[11].y:=0]
+	    453137 b.b.dly.dly[12].__y : 0  [by b.b.dly.dly[12]._y:=1]
+	    455778 b.b.dly.dly[12].___y : 1  [by b.b.dly.dly[12].__y:=0]
+	    455794 b.b.dly.dly[12].y : 0  [by b.b.dly.dly[12].___y:=1]
+	    460356 b.b.dly.dly[13]._y : 1  [by b.b.dly.dly[12].y:=0]
+	    460884 b.b.dly.dly[13].__y : 0  [by b.b.dly.dly[13]._y:=1]
+	    463319 b.b.dly.dly[13].___y : 1  [by b.b.dly.dly[13].__y:=0]
+	    490199 b.b.dly.dly[13].y : 0  [by b.b.dly.dly[13].___y:=1]
+	    514124 b.b.dly.dly[14]._y : 1  [by b.b.dly.dly[13].y:=0]
+	    527165 b.b.dly.dly[14].__y : 0  [by b.b.dly.dly[14]._y:=1]
+	    527167 b.b.dly.dly[14].___y : 1  [by b.b.dly.dly[14].__y:=0]
+	    588125 b.b.dly.mu2[3].b : 0  [by b.b.dly.dly[14].___y:=1]
+	    588128 b.b.dly.mu2[3]._y : 1  [by b.b.dly.mu2[3].b:=0]
+	    588157 b.b._req : 0  [by b.b.dly.mu2[3]._y:=1]
+	    588474 b.b.req_buf._y : 1  [by b.b._req:=0]
+	    590075 b.b._reqX : 0  [by b.b.req_buf._y:=1]
+	    590228 b.b.req_bufarray.buf2._y : 1  [by b.b._reqX:=0]
+	    590272 b.b._reqXX[0] : 0  [by b.b.req_bufarray.buf2._y:=1]
+[] set Reset 1
+	    590272 Reset : 1
+	    593033 b._reset_B : 0  [by Reset:=1]
+	    606716 b.b.reset_buf._y : 1  [by b._reset_B:=0]
+	    606717 b.b._reset_BX : 0  [by b.b.reset_buf._y:=1]
+	    606934 b.b.reset_bufarray.buf2._y : 1  [by b.b._reset_BX:=0]
+	    606956 b.b._reset_BXX[0] : 0  [by b.b.reset_bufarray.buf2._y:=1]
+	    606957 b.b.f_buf_func[1]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    607115 b.b.t_buf_func[0]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    608244 b.b.f_buf_func[1].y : 0  [by b.b.f_buf_func[1]._y:=1]
+	    608537 b.b.f_buf_func[2]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    608682 b.b.f_buf_func[2].y : 0  [by b.b.f_buf_func[2]._y:=1]
+	    609347 b.b.t_buf_func[0].y : 0  [by b.b.t_buf_func[0]._y:=1]
+	    616301 b.b.f_buf_func[4]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    619133 b.b.f_buf_func[4].y : 0  [by b.b.f_buf_func[4]._y:=1]
+	    626632 b.b.t_buf_func[3]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    632986 b.b.t_buf_func[3].y : 0  [by b.b.t_buf_func[3]._y:=1]
+[] set Reset 0
+	    632986 Reset : 0
+	    632987 b._reset_B : 1  [by Reset:=0]
+	    672271 b.b.reset_buf._y : 0  [by b._reset_B:=1]
+	    672433 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
+	    679802 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
+	    679816 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]
+
+[] Reset finished, setting data
+	    679816 b.in.d[0] : 0
+	    679816 b.in.d[4] : 1
+	    679816 b.in.d[2] : 1
+	    679816 b.in.d[1] : 1
+	    679816 b.in.d[3] : 0
+	    679817 b.b._inB[1] : 0  [by b.in.d[1]:=1]
+	    679817 b.b._inB[3] : 1  [by b.in.d[3]:=0]
+	    679823 b.b._inB[0] : 1  [by b.in.d[0]:=0]
+	    679976 b.b._inB[4] : 0  [by b.in.d[4]:=1]
+	    701373 b.b._inB[2] : 0  [by b.in.d[2]:=1]
+[] Reset finished, setting req 1
+	    701373 b.in.r : 1
+	    701374 b.b.dly.and2[0]._y : 0  [by b.in.r:=1]
+	    703617 b.b.dly.dly[0].a : 1  [by b.b.dly.and2[0]._y:=0]
+	    703804 b.b.dly.dly[0]._y : 0  [by b.b.dly.dly[0].a:=1]
+	    703805 b.b.dly.dly[0].__y : 1  [by b.b.dly.dly[0]._y:=0]
+	    707987 b.b.dly.dly[0].___y : 0  [by b.b.dly.dly[0].__y:=1]
+	    742769 b.b.dly.dly[0].y : 1  [by b.b.dly.dly[0].___y:=0]
+	    742770 b.b.dly.mu2[0]._y : 0  [by b.b.dly.dly[0].y:=1]
+	    743623 b.b.dly._a[1] : 1  [by b.b.dly.mu2[0]._y:=0]
+	    743628 b.b.dly.and2[1]._y : 0  [by b.b.dly._a[1]:=1]
+	    744519 b.b.dly.dly[1].a : 1  [by b.b.dly.and2[1]._y:=0]
+	    744520 b.b.dly.dly[1]._y : 0  [by b.b.dly.dly[1].a:=1]
+	    744537 b.b.dly.dly[1].__y : 1  [by b.b.dly.dly[1]._y:=0]
+	    747110 b.b.dly.dly[1].___y : 0  [by b.b.dly.dly[1].__y:=1]
+	    755471 b.b.dly.dly[1].y : 1  [by b.b.dly.dly[1].___y:=0]
+	    755474 b.b.dly.dly[2]._y : 0  [by b.b.dly.dly[1].y:=1]
+	    756415 b.b.dly.dly[2].__y : 1  [by b.b.dly.dly[2]._y:=0]
+	    815377 b.b.dly.dly[2].___y : 0  [by b.b.dly.dly[2].__y:=1]
+	    815378 b.b.dly.dly[2].y : 1  [by b.b.dly.dly[2].___y:=0]
+	    815420 b.b.dly.mu2[1]._y : 0  [by b.b.dly.dly[2].y:=1]
+	    818237 b.b.dly._a[2] : 1  [by b.b.dly.mu2[1]._y:=0]
+	    831970 b.b.dly.and2[2]._y : 0  [by b.b.dly._a[2]:=1]
+	    832065 b.b.dly.dly[3].a : 1  [by b.b.dly.and2[2]._y:=0]
+	    832400 b.b.dly.dly[3]._y : 0  [by b.b.dly.dly[3].a:=1]
+	    832408 b.b.dly.dly[3].__y : 1  [by b.b.dly.dly[3]._y:=0]
+	    832442 b.b.dly.dly[3].___y : 0  [by b.b.dly.dly[3].__y:=1]
+	    846329 b.b.dly.dly[3].y : 1  [by b.b.dly.dly[3].___y:=0]
+	    847247 b.b.dly.dly[4]._y : 0  [by b.b.dly.dly[3].y:=1]
+	    847251 b.b.dly.dly[4].__y : 1  [by b.b.dly.dly[4]._y:=0]
+	    893629 b.b.dly.dly[4].___y : 0  [by b.b.dly.dly[4].__y:=1]
+	    896027 b.b.dly.dly[4].y : 1  [by b.b.dly.dly[4].___y:=0]
+	    899242 b.b.dly.dly[5]._y : 0  [by b.b.dly.dly[4].y:=1]
+	    946361 b.b.dly.dly[5].__y : 1  [by b.b.dly.dly[5]._y:=0]
+	    946409 b.b.dly.dly[5].___y : 0  [by b.b.dly.dly[5].__y:=1]
+	    946412 b.b.dly.dly[5].y : 1  [by b.b.dly.dly[5].___y:=0]
+	    946590 b.b.dly.dly[6]._y : 0  [by b.b.dly.dly[5].y:=1]
+	    967567 b.b.dly.dly[6].__y : 1  [by b.b.dly.dly[6]._y:=0]
+	    979466 b.b.dly.dly[6].___y : 0  [by b.b.dly.dly[6].__y:=1]
+	    985417 b.b.dly.dly[6].y : 1  [by b.b.dly.dly[6].___y:=0]
+	   1024902 b.b.dly.mu2[2]._y : 0  [by b.b.dly.dly[6].y:=1]
+	   1025729 b.b.dly._a[3] : 1  [by b.b.dly.mu2[2]._y:=0]
+	   1025902 b.b.dly.and2[3]._y : 0  [by b.b.dly._a[3]:=1]
+	   1026086 b.b.dly.dly[7].a : 1  [by b.b.dly.and2[3]._y:=0]
+	   1026087 b.b.dly.dly[7]._y : 0  [by b.b.dly.dly[7].a:=1]
+	   1026160 b.b.dly.dly[7].__y : 1  [by b.b.dly.dly[7]._y:=0]
+	   1026164 b.b.dly.dly[7].___y : 0  [by b.b.dly.dly[7].__y:=1]
+	   1063452 b.b.dly.dly[7].y : 1  [by b.b.dly.dly[7].___y:=0]
+	   1063548 b.b.dly.dly[8]._y : 0  [by b.b.dly.dly[7].y:=1]
+	   1063684 b.b.dly.dly[8].__y : 1  [by b.b.dly.dly[8]._y:=0]
+	   1063685 b.b.dly.dly[8].___y : 0  [by b.b.dly.dly[8].__y:=1]
+	   1082731 b.b.dly.dly[8].y : 1  [by b.b.dly.dly[8].___y:=0]
+	   1082972 b.b.dly.dly[9]._y : 0  [by b.b.dly.dly[8].y:=1]
+	   1086931 b.b.dly.dly[9].__y : 1  [by b.b.dly.dly[9]._y:=0]
+	   1086943 b.b.dly.dly[9].___y : 0  [by b.b.dly.dly[9].__y:=1]
+	   1090843 b.b.dly.dly[9].y : 1  [by b.b.dly.dly[9].___y:=0]
+	   1091872 b.b.dly.dly[10]._y : 0  [by b.b.dly.dly[9].y:=1]
+	   1091873 b.b.dly.dly[10].__y : 1  [by b.b.dly.dly[10]._y:=0]
+	   1091929 b.b.dly.dly[10].___y : 0  [by b.b.dly.dly[10].__y:=1]
+	   1136935 b.b.dly.dly[10].y : 1  [by b.b.dly.dly[10].___y:=0]
+	   1136936 b.b.dly.dly[11]._y : 0  [by b.b.dly.dly[10].y:=1]
+	   1136973 b.b.dly.dly[11].__y : 1  [by b.b.dly.dly[11]._y:=0]
+	   1160348 b.b.dly.dly[11].___y : 0  [by b.b.dly.dly[11].__y:=1]
+	   1160349 b.b.dly.dly[11].y : 1  [by b.b.dly.dly[11].___y:=0]
+	   1163913 b.b.dly.dly[12]._y : 0  [by b.b.dly.dly[11].y:=1]
+	   1165605 b.b.dly.dly[12].__y : 1  [by b.b.dly.dly[12]._y:=0]
+	   1165618 b.b.dly.dly[12].___y : 0  [by b.b.dly.dly[12].__y:=1]
+	   1182602 b.b.dly.dly[12].y : 1  [by b.b.dly.dly[12].___y:=0]
+	   1182959 b.b.dly.dly[13]._y : 0  [by b.b.dly.dly[12].y:=1]
+	   1182984 b.b.dly.dly[13].__y : 1  [by b.b.dly.dly[13]._y:=0]
+	   1183005 b.b.dly.dly[13].___y : 0  [by b.b.dly.dly[13].__y:=1]
+	   1183006 b.b.dly.dly[13].y : 1  [by b.b.dly.dly[13].___y:=0]
+	   1192654 b.b.dly.dly[14]._y : 0  [by b.b.dly.dly[13].y:=1]
+	   1192655 b.b.dly.dly[14].__y : 1  [by b.b.dly.dly[14]._y:=0]
+	   1192656 b.b.dly.dly[14].___y : 0  [by b.b.dly.dly[14].__y:=1]
+	   1192817 b.b.dly.mu2[3].b : 1  [by b.b.dly.dly[14].___y:=0]
+	   1193854 b.b.dly.mu2[3]._y : 0  [by b.b.dly.mu2[3].b:=1]
+	   1193859 b.b._req : 1  [by b.b.dly.mu2[3]._y:=0]
+	   1194440 b.b.req_buf._y : 0  [by b.b._req:=1]
+	   1194848 b.b._reqX : 1  [by b.b.req_buf._y:=0]
+	   1194859 b.b.req_bufarray.buf2._y : 0  [by b.b._reqX:=1]
+	   1195906 b.b._reqXX[0] : 1  [by b.b.req_bufarray.buf2._y:=0]
+	   1195910 b.b.t_buf_func[1]._y : 0  [by b.b._reqXX[0]:=1]
+	   1195920 b.b.f_buf_func[0]._y : 0  [by b.b._reqXX[0]:=1]
+	   1195924 b.b.f_buf_func[3]._y : 0  [by b.b._reqXX[0]:=1]
+	   1196010 b.b.t_buf_func[2]._y : 0  [by b.b._reqXX[0]:=1]
+	   1196152 b.b.f_buf_func[3].y : 1  [by b.b.f_buf_func[3]._y:=0]
+	   1196853 b.b.t_buf_func[2].y : 1  [by b.b.t_buf_func[2]._y:=0]
+	   1197114 b.b.t_buf_func[1].y : 1  [by b.b.t_buf_func[1]._y:=0]
+	   1204375 b.b.f_buf_func[0].y : 1  [by b.b.f_buf_func[0]._y:=0]
+	   1227350 b.b.t_buf_func[4]._y : 0  [by b.b._reqXX[0]:=1]
+	   1228809 b.b.t_buf_func[4].y : 1  [by b.b.t_buf_func[4]._y:=0]
+[] Receiving val out
+	   1228809 b.out.v : 1
+	   1228879 b.b.inack_ctl._y : 0  [by b.out.v:=1]
+	   1279301 b.in.a : 1  [by b.b.inack_ctl._y:=0]
+	   1279312 b.b._en : 0  [by b.in.a:=1]
+	   1279315 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	   1279366 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	   1280463 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+	   1280527 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+[] Changing some input data
+	   1280527 b.in.d[0] : 1
+	   1289179 b.b._inB[0] : 0  [by b.in.d[0]:=1]
+[] Removing req
+[] Changing more data
+	   1289179 b.in.r : 0
+	   1289179 b.in.d[4] : 0
+	   1289260 b.b.dly.and2[0]._y : 1  [by b.in.r:=0]
+	   1300256 b.b._inB[4] : 1  [by b.in.d[4]:=0]
+	   1307243 b.b.dly.dly[0].a : 0  [by b.b.dly.and2[0]._y:=1]
+	   1307335 b.b.dly.dly[0]._y : 1  [by b.b.dly.dly[0].a:=0]
+	   1315646 b.b.dly.dly[0].__y : 0  [by b.b.dly.dly[0]._y:=1]
+	   1317390 b.b.dly.dly[0].___y : 1  [by b.b.dly.dly[0].__y:=0]
+	   1318003 b.b.dly.dly[0].y : 0  [by b.b.dly.dly[0].___y:=1]
+	   1332025 b.b.dly.mu2[0]._y : 1  [by b.b.dly.dly[0].y:=0]
+	   1332070 b.b.dly._a[1] : 0  [by b.b.dly.mu2[0]._y:=1]
+	   1333067 b.b.dly.and2[1]._y : 1  [by b.b.dly._a[1]:=0]
+	   1334716 b.b.dly.dly[1].a : 0  [by b.b.dly.and2[1]._y:=1]
+	   1335241 b.b.dly.dly[1]._y : 1  [by b.b.dly.dly[1].a:=0]
+	   1336141 b.b.dly.dly[1].__y : 0  [by b.b.dly.dly[1]._y:=1]
+	   1336193 b.b.dly.dly[1].___y : 1  [by b.b.dly.dly[1].__y:=0]
+	   1336200 b.b.dly.dly[1].y : 0  [by b.b.dly.dly[1].___y:=1]
+	   1351812 b.b.dly.dly[2]._y : 1  [by b.b.dly.dly[1].y:=0]
+	   1358279 b.b.dly.dly[2].__y : 0  [by b.b.dly.dly[2]._y:=1]
+	   1358281 b.b.dly.dly[2].___y : 1  [by b.b.dly.dly[2].__y:=0]
+	   1358635 b.b.dly.dly[2].y : 0  [by b.b.dly.dly[2].___y:=1]
+	   1358768 b.b.dly.mu2[1]._y : 1  [by b.b.dly.dly[2].y:=0]
+	   1358769 b.b.dly._a[2] : 0  [by b.b.dly.mu2[1]._y:=1]
+	   1358773 b.b.dly.and2[2]._y : 1  [by b.b.dly._a[2]:=0]
+	   1359319 b.b.dly.dly[3].a : 0  [by b.b.dly.and2[2]._y:=1]
+	   1404882 b.b.dly.dly[3]._y : 1  [by b.b.dly.dly[3].a:=0]
+	   1404883 b.b.dly.dly[3].__y : 0  [by b.b.dly.dly[3]._y:=1]
+	   1417261 b.b.dly.dly[3].___y : 1  [by b.b.dly.dly[3].__y:=0]
+	   1417340 b.b.dly.dly[3].y : 0  [by b.b.dly.dly[3].___y:=1]
+	   1419773 b.b.dly.dly[4]._y : 1  [by b.b.dly.dly[3].y:=0]
+	   1419861 b.b.dly.dly[4].__y : 0  [by b.b.dly.dly[4]._y:=1]
+	   1427643 b.b.dly.dly[4].___y : 1  [by b.b.dly.dly[4].__y:=0]
+	   1455970 b.b.dly.dly[4].y : 0  [by b.b.dly.dly[4].___y:=1]
+	   1456029 b.b.dly.dly[5]._y : 1  [by b.b.dly.dly[4].y:=0]
+	   1456059 b.b.dly.dly[5].__y : 0  [by b.b.dly.dly[5]._y:=1]
+	   1457526 b.b.dly.dly[5].___y : 1  [by b.b.dly.dly[5].__y:=0]
+	   1517030 b.b.dly.dly[5].y : 0  [by b.b.dly.dly[5].___y:=1]
+	   1536414 b.b.dly.dly[6]._y : 1  [by b.b.dly.dly[5].y:=0]
+	   1537099 b.b.dly.dly[6].__y : 0  [by b.b.dly.dly[6]._y:=1]
+	   1553814 b.b.dly.dly[6].___y : 1  [by b.b.dly.dly[6].__y:=0]
+	   1553941 b.b.dly.dly[6].y : 0  [by b.b.dly.dly[6].___y:=1]
+	   1554110 b.b.dly.mu2[2]._y : 1  [by b.b.dly.dly[6].y:=0]
+	   1554153 b.b.dly._a[3] : 0  [by b.b.dly.mu2[2]._y:=1]
+	   1554165 b.b.dly.and2[3]._y : 1  [by b.b.dly._a[3]:=0]
+	   1555444 b.b.dly.dly[7].a : 0  [by b.b.dly.and2[3]._y:=1]
+	   1555677 b.b.dly.dly[7]._y : 1  [by b.b.dly.dly[7].a:=0]
+	   1555680 b.b.dly.dly[7].__y : 0  [by b.b.dly.dly[7]._y:=1]
+	   1555718 b.b.dly.dly[7].___y : 1  [by b.b.dly.dly[7].__y:=0]
+	   1555719 b.b.dly.dly[7].y : 0  [by b.b.dly.dly[7].___y:=1]
+	   1568471 b.b.dly.dly[8]._y : 1  [by b.b.dly.dly[7].y:=0]
+	   1568563 b.b.dly.dly[8].__y : 0  [by b.b.dly.dly[8]._y:=1]
+	   1571290 b.b.dly.dly[8].___y : 1  [by b.b.dly.dly[8].__y:=0]
+	   1571292 b.b.dly.dly[8].y : 0  [by b.b.dly.dly[8].___y:=1]
+	   1571293 b.b.dly.dly[9]._y : 1  [by b.b.dly.dly[8].y:=0]
+	   1572794 b.b.dly.dly[9].__y : 0  [by b.b.dly.dly[9]._y:=1]
+	   1572796 b.b.dly.dly[9].___y : 1  [by b.b.dly.dly[9].__y:=0]
+	   1572814 b.b.dly.dly[9].y : 0  [by b.b.dly.dly[9].___y:=1]
+	   1572933 b.b.dly.dly[10]._y : 1  [by b.b.dly.dly[9].y:=0]
+	   1578653 b.b.dly.dly[10].__y : 0  [by b.b.dly.dly[10]._y:=1]
+	   1578661 b.b.dly.dly[10].___y : 1  [by b.b.dly.dly[10].__y:=0]
+	   1578715 b.b.dly.dly[10].y : 0  [by b.b.dly.dly[10].___y:=1]
+	   1629253 b.b.dly.dly[11]._y : 1  [by b.b.dly.dly[10].y:=0]
+	   1629258 b.b.dly.dly[11].__y : 0  [by b.b.dly.dly[11]._y:=1]
+	   1630325 b.b.dly.dly[11].___y : 1  [by b.b.dly.dly[11].__y:=0]
+	   1630326 b.b.dly.dly[11].y : 0  [by b.b.dly.dly[11].___y:=1]
+	   1630464 b.b.dly.dly[12]._y : 1  [by b.b.dly.dly[11].y:=0]
+	   1630465 b.b.dly.dly[12].__y : 0  [by b.b.dly.dly[12]._y:=1]
+	   1630529 b.b.dly.dly[12].___y : 1  [by b.b.dly.dly[12].__y:=0]
+	   1630652 b.b.dly.dly[12].y : 0  [by b.b.dly.dly[12].___y:=1]
+	   1630654 b.b.dly.dly[13]._y : 1  [by b.b.dly.dly[12].y:=0]
+	   1630691 b.b.dly.dly[13].__y : 0  [by b.b.dly.dly[13]._y:=1]
+	   1630834 b.b.dly.dly[13].___y : 1  [by b.b.dly.dly[13].__y:=0]
+	   1630885 b.b.dly.dly[13].y : 0  [by b.b.dly.dly[13].___y:=1]
+	   1631327 b.b.dly.dly[14]._y : 1  [by b.b.dly.dly[13].y:=0]
+	   1631338 b.b.dly.dly[14].__y : 0  [by b.b.dly.dly[14]._y:=1]
+	   1631339 b.b.dly.dly[14].___y : 1  [by b.b.dly.dly[14].__y:=0]
+	   1631348 b.b.dly.mu2[3].b : 0  [by b.b.dly.dly[14].___y:=1]
+	   1631373 b.b.dly.mu2[3]._y : 1  [by b.b.dly.mu2[3].b:=0]
+	   1641626 b.b._req : 0  [by b.b.dly.mu2[3]._y:=1]
+	   1645147 b.b.req_buf._y : 1  [by b.b._req:=0]
+	   1645292 b.b._reqX : 0  [by b.b.req_buf._y:=1]
+	   1661460 b.b.req_bufarray.buf2._y : 1  [by b.b._reqX:=0]
+	   1661690 b.b._reqXX[0] : 0  [by b.b.req_bufarray.buf2._y:=1]
+[] Receiving ack out
+	   1661690 b.out.a : 1
+	   1662381 b.b._out_a_B : 0  [by b.out.a:=1]
+	   1662395 b.b.out_a_B_buf_t.buf2._y : 1  [by b.b._out_a_B:=0]
+	   1663924 b.b.out_a_B_buf_f.buf2._y : 1  [by b.b._out_a_B:=0]
+	   1664006 b.b._out_a_BX_f[0] : 0  [by b.b.out_a_B_buf_t.buf2._y:=1]
+	   1664007 b.b.f_buf_func[3]._y : 1  [by b.b._out_a_BX_f[0]:=0]
+	   1664008 b.b.f_buf_func[3].y : 0  [by b.b.f_buf_func[3]._y:=1]
+	   1664017 b.b.f_buf_func[0]._y : 1  [by b.b._out_a_BX_f[0]:=0]
+	   1670518 b.b.f_buf_func[0].y : 0  [by b.b.f_buf_func[0]._y:=1]
+	   1681436 b.b._out_a_BX_t[0] : 0  [by b.b.out_a_B_buf_f.buf2._y:=1]
+	   1681568 b.b.t_buf_func[4]._y : 1  [by b.b._out_a_BX_t[0]:=0]
+	   1681569 b.b.t_buf_func[4].y : 0  [by b.b.t_buf_func[4]._y:=1]
+	   1682075 b.b.t_buf_func[1]._y : 1  [by b.b._out_a_BX_t[0]:=0]
+	   1682092 b.b.t_buf_func[1].y : 0  [by b.b.t_buf_func[1]._y:=1]
+	   1683229 b.b.t_buf_func[2]._y : 1  [by b.b._out_a_BX_t[0]:=0]
+	   1683381 b.b.t_buf_func[2].y : 0  [by b.b.t_buf_func[2]._y:=1]
+	   1683381 b.out.v : 0
+	   1686364 b.b.inack_ctl._y : 1  [by b.out.v:=0]
+	   1686367 b.in.a : 0  [by b.b.inack_ctl._y:=1]
+	   1686791 b.b._en : 1  [by b.in.a:=0]
+	   1686797 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	   1689258 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+	   1689379 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	   1690209 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+[] Set ack out 0
+	   1690209 b.out.a : 0
+	   1713141 b.b._out_a_B : 1  [by b.out.a:=0]
+	   1713143 b.b.out_a_B_buf_t.buf2._y : 0  [by b.b._out_a_B:=1]
+	   1713335 b.b.out_a_B_buf_f.buf2._y : 0  [by b.b._out_a_B:=1]
+	   1713473 b.b._out_a_BX_t[0] : 1  [by b.b.out_a_B_buf_f.buf2._y:=0]
+	   1713746 b.b._out_a_BX_f[0] : 1  [by b.b.out_a_B_buf_t.buf2._y:=0]
+[] Again!!! setting data
+	   1713746 b.in.d[0] : 0
+	   1713746 b.in.d[2] : 0
+	   1713746 b.in.d[1] : 0
+	   1713763 b.b._inB[2] : 1  [by b.in.d[2]:=0]
+	   1713763 b.b._inB[0] : 1  [by b.in.d[0]:=0]
+	   1714172 b.b._inB[1] : 1  [by b.in.d[1]:=0]
+[] Again!!! setting req 1
+	   1714172 b.in.r : 1
+	   1714173 b.b.dly.and2[0]._y : 0  [by b.in.r:=1]
+	   1714174 b.b.dly.dly[0].a : 1  [by b.b.dly.and2[0]._y:=0]
+	   1715200 b.b.dly.dly[0]._y : 0  [by b.b.dly.dly[0].a:=1]
+	   1715201 b.b.dly.dly[0].__y : 1  [by b.b.dly.dly[0]._y:=0]
+	   1715220 b.b.dly.dly[0].___y : 0  [by b.b.dly.dly[0].__y:=1]
+	   1715388 b.b.dly.dly[0].y : 1  [by b.b.dly.dly[0].___y:=0]
+	   1715927 b.b.dly.mu2[0]._y : 0  [by b.b.dly.dly[0].y:=1]
+	   1716088 b.b.dly._a[1] : 1  [by b.b.dly.mu2[0]._y:=0]
+	   1716261 b.b.dly.and2[1]._y : 0  [by b.b.dly._a[1]:=1]
+	   1718808 b.b.dly.dly[1].a : 1  [by b.b.dly.and2[1]._y:=0]
+	   1733869 b.b.dly.dly[1]._y : 0  [by b.b.dly.dly[1].a:=1]
+	   1733870 b.b.dly.dly[1].__y : 1  [by b.b.dly.dly[1]._y:=0]
+	   1733871 b.b.dly.dly[1].___y : 0  [by b.b.dly.dly[1].__y:=1]
+	   1734261 b.b.dly.dly[1].y : 1  [by b.b.dly.dly[1].___y:=0]
+	   1734468 b.b.dly.dly[2]._y : 0  [by b.b.dly.dly[1].y:=1]
+	   1735301 b.b.dly.dly[2].__y : 1  [by b.b.dly.dly[2]._y:=0]
+	   1735329 b.b.dly.dly[2].___y : 0  [by b.b.dly.dly[2].__y:=1]
+	   1735336 b.b.dly.dly[2].y : 1  [by b.b.dly.dly[2].___y:=0]
+	   1735750 b.b.dly.mu2[1]._y : 0  [by b.b.dly.dly[2].y:=1]
+	   1735754 b.b.dly._a[2] : 1  [by b.b.dly.mu2[1]._y:=0]
+	   1737533 b.b.dly.and2[2]._y : 0  [by b.b.dly._a[2]:=1]
+	   1760407 b.b.dly.dly[3].a : 1  [by b.b.dly.and2[2]._y:=0]
+	   1760573 b.b.dly.dly[3]._y : 0  [by b.b.dly.dly[3].a:=1]
+	   1800443 b.b.dly.dly[3].__y : 1  [by b.b.dly.dly[3]._y:=0]
+	   1809088 b.b.dly.dly[3].___y : 0  [by b.b.dly.dly[3].__y:=1]
+	   1810021 b.b.dly.dly[3].y : 1  [by b.b.dly.dly[3].___y:=0]
+	   1810877 b.b.dly.dly[4]._y : 0  [by b.b.dly.dly[3].y:=1]
+	   1811016 b.b.dly.dly[4].__y : 1  [by b.b.dly.dly[4]._y:=0]
+	   1837225 b.b.dly.dly[4].___y : 0  [by b.b.dly.dly[4].__y:=1]
+	   1837420 b.b.dly.dly[4].y : 1  [by b.b.dly.dly[4].___y:=0]
+	   1837422 b.b.dly.dly[5]._y : 0  [by b.b.dly.dly[4].y:=1]
+	   1890871 b.b.dly.dly[5].__y : 1  [by b.b.dly.dly[5]._y:=0]
+	   1890877 b.b.dly.dly[5].___y : 0  [by b.b.dly.dly[5].__y:=1]
+	   1891131 b.b.dly.dly[5].y : 1  [by b.b.dly.dly[5].___y:=0]
+	   1891139 b.b.dly.dly[6]._y : 0  [by b.b.dly.dly[5].y:=1]
+	   1891140 b.b.dly.dly[6].__y : 1  [by b.b.dly.dly[6]._y:=0]
+	   1891146 b.b.dly.dly[6].___y : 0  [by b.b.dly.dly[6].__y:=1]
+	   1942182 b.b.dly.dly[6].y : 1  [by b.b.dly.dly[6].___y:=0]
+	   1945272 b.b.dly.mu2[2]._y : 0  [by b.b.dly.dly[6].y:=1]
+	   1945498 b.b.dly._a[3] : 1  [by b.b.dly.mu2[2]._y:=0]
+	   1946317 b.b.dly.and2[3]._y : 0  [by b.b.dly._a[3]:=1]
+	   1946318 b.b.dly.dly[7].a : 1  [by b.b.dly.and2[3]._y:=0]
+	   1946324 b.b.dly.dly[7]._y : 0  [by b.b.dly.dly[7].a:=1]
+	   1946326 b.b.dly.dly[7].__y : 1  [by b.b.dly.dly[7]._y:=0]
+	   1949888 b.b.dly.dly[7].___y : 0  [by b.b.dly.dly[7].__y:=1]
+	   1949903 b.b.dly.dly[7].y : 1  [by b.b.dly.dly[7].___y:=0]
+	   1970704 b.b.dly.dly[8]._y : 0  [by b.b.dly.dly[7].y:=1]
+	   1970811 b.b.dly.dly[8].__y : 1  [by b.b.dly.dly[8]._y:=0]
+	   1970904 b.b.dly.dly[8].___y : 0  [by b.b.dly.dly[8].__y:=1]
+	   1972556 b.b.dly.dly[8].y : 1  [by b.b.dly.dly[8].___y:=0]
+	   1976495 b.b.dly.dly[9]._y : 0  [by b.b.dly.dly[8].y:=1]
+	   1977253 b.b.dly.dly[9].__y : 1  [by b.b.dly.dly[9]._y:=0]
+	   1979876 b.b.dly.dly[9].___y : 0  [by b.b.dly.dly[9].__y:=1]
+	   1980592 b.b.dly.dly[9].y : 1  [by b.b.dly.dly[9].___y:=0]
+	   1980593 b.b.dly.dly[10]._y : 0  [by b.b.dly.dly[9].y:=1]
+	   1982333 b.b.dly.dly[10].__y : 1  [by b.b.dly.dly[10]._y:=0]
+	   1982334 b.b.dly.dly[10].___y : 0  [by b.b.dly.dly[10].__y:=1]
+	   1994486 b.b.dly.dly[10].y : 1  [by b.b.dly.dly[10].___y:=0]
+	   2022685 b.b.dly.dly[11]._y : 0  [by b.b.dly.dly[10].y:=1]
+	   2022686 b.b.dly.dly[11].__y : 1  [by b.b.dly.dly[11]._y:=0]
+	   2022692 b.b.dly.dly[11].___y : 0  [by b.b.dly.dly[11].__y:=1]
+	   2022693 b.b.dly.dly[11].y : 1  [by b.b.dly.dly[11].___y:=0]
+	   2062182 b.b.dly.dly[12]._y : 0  [by b.b.dly.dly[11].y:=1]
+	   2083781 b.b.dly.dly[12].__y : 1  [by b.b.dly.dly[12]._y:=0]
+	   2083803 b.b.dly.dly[12].___y : 0  [by b.b.dly.dly[12].__y:=1]
+	   2106311 b.b.dly.dly[12].y : 1  [by b.b.dly.dly[12].___y:=0]
+	   2106318 b.b.dly.dly[13]._y : 0  [by b.b.dly.dly[12].y:=1]
+	   2106383 b.b.dly.dly[13].__y : 1  [by b.b.dly.dly[13]._y:=0]
+	   2106396 b.b.dly.dly[13].___y : 0  [by b.b.dly.dly[13].__y:=1]
+	   2107520 b.b.dly.dly[13].y : 1  [by b.b.dly.dly[13].___y:=0]
+	   2107624 b.b.dly.dly[14]._y : 0  [by b.b.dly.dly[13].y:=1]
+	   2107665 b.b.dly.dly[14].__y : 1  [by b.b.dly.dly[14]._y:=0]
+	   2107666 b.b.dly.dly[14].___y : 0  [by b.b.dly.dly[14].__y:=1]
+	   2107667 b.b.dly.mu2[3].b : 1  [by b.b.dly.dly[14].___y:=0]
+	   2172045 b.b.dly.mu2[3]._y : 0  [by b.b.dly.mu2[3].b:=1]
+	   2185217 b.b._req : 1  [by b.b.dly.mu2[3]._y:=0]
+	   2185218 b.b.req_buf._y : 0  [by b.b._req:=1]
+	   2205043 b.b._reqX : 1  [by b.b.req_buf._y:=0]
+	   2208179 b.b.req_bufarray.buf2._y : 0  [by b.b._reqX:=1]
+	   2209005 b.b._reqXX[0] : 1  [by b.b.req_bufarray.buf2._y:=0]
+	   2209063 b.b.f_buf_func[2]._y : 0  [by b.b._reqXX[0]:=1]
+	   2210838 b.b.f_buf_func[0]._y : 0  [by b.b._reqXX[0]:=1]
+	   2210852 b.b.f_buf_func[0].y : 1  [by b.b.f_buf_func[0]._y:=0]
+	   2211448 b.b.f_buf_func[3]._y : 0  [by b.b._reqXX[0]:=1]
+	   2211804 b.b.f_buf_func[3].y : 1  [by b.b.f_buf_func[3]._y:=0]
+	   2225553 b.b.f_buf_func[1]._y : 0  [by b.b._reqXX[0]:=1]
+	   2225778 b.b.f_buf_func[4]._y : 0  [by b.b._reqXX[0]:=1]
+	   2225883 b.b.f_buf_func[4].y : 1  [by b.b.f_buf_func[4]._y:=0]
+	   2246262 b.b.f_buf_func[2].y : 1  [by b.b.f_buf_func[2]._y:=0]
+	   2261391 b.b.f_buf_func[1].y : 1  [by b.b.f_buf_func[1]._y:=0]
+[] Receiving val out
+	   2261391 b.out.v : 1
+	   2261500 b.b.inack_ctl._y : 0  [by b.out.v:=1]
+	   2261501 b.in.a : 1  [by b.b.inack_ctl._y:=0]
+	   2261510 b.b._en : 0  [by b.in.a:=1]
+	   2261511 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	   2297905 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+	   2299463 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	   2299464 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+[] Changing some input data
+	   2299464 b.in.d[0] : 1
+	   2299464 b.in.d[2] : 1
+	   2299464 b.in.d[1] : 1
+	   2300214 b.b._inB[1] : 0  [by b.in.d[1]:=1]
+	   2302553 b.b._inB[0] : 0  [by b.in.d[0]:=1]
+	   2348190 b.b._inB[2] : 0  [by b.in.d[2]:=1]
+[] Removing req
+[] Changing more data
+	   2348190 b.in.r : 0
+	   2354945 b.b.dly.and2[0]._y : 1  [by b.in.r:=0]
+	   2354996 b.b.dly.dly[0].a : 0  [by b.b.dly.and2[0]._y:=1]
+	   2355006 b.b.dly.dly[0]._y : 1  [by b.b.dly.dly[0].a:=0]
+	   2355326 b.b.dly.dly[0].__y : 0  [by b.b.dly.dly[0]._y:=1]
+	   2362908 b.b.dly.dly[0].___y : 1  [by b.b.dly.dly[0].__y:=0]
+	   2362909 b.b.dly.dly[0].y : 0  [by b.b.dly.dly[0].___y:=1]
+	   2362910 b.b.dly.mu2[0]._y : 1  [by b.b.dly.dly[0].y:=0]
+	   2364640 b.b.dly._a[1] : 0  [by b.b.dly.mu2[0]._y:=1]
+	   2366327 b.b.dly.and2[1]._y : 1  [by b.b.dly._a[1]:=0]
+	   2366342 b.b.dly.dly[1].a : 0  [by b.b.dly.and2[1]._y:=1]
+	   2390616 b.b.dly.dly[1]._y : 1  [by b.b.dly.dly[1].a:=0]
+	   2391070 b.b.dly.dly[1].__y : 0  [by b.b.dly.dly[1]._y:=1]
+	   2391386 b.b.dly.dly[1].___y : 1  [by b.b.dly.dly[1].__y:=0]
+	   2391387 b.b.dly.dly[1].y : 0  [by b.b.dly.dly[1].___y:=1]
+	   2391770 b.b.dly.dly[2]._y : 1  [by b.b.dly.dly[1].y:=0]
+	   2399233 b.b.dly.dly[2].__y : 0  [by b.b.dly.dly[2]._y:=1]
+	   2399253 b.b.dly.dly[2].___y : 1  [by b.b.dly.dly[2].__y:=0]
+	   2400576 b.b.dly.dly[2].y : 0  [by b.b.dly.dly[2].___y:=1]
+	   2400663 b.b.dly.mu2[1]._y : 1  [by b.b.dly.dly[2].y:=0]
+	   2407385 b.b.dly._a[2] : 0  [by b.b.dly.mu2[1]._y:=1]
+	   2407397 b.b.dly.and2[2]._y : 1  [by b.b.dly._a[2]:=0]
+	   2407542 b.b.dly.dly[3].a : 0  [by b.b.dly.and2[2]._y:=1]
+	   2408443 b.b.dly.dly[3]._y : 1  [by b.b.dly.dly[3].a:=0]
+	   2409792 b.b.dly.dly[3].__y : 0  [by b.b.dly.dly[3]._y:=1]
+	   2410011 b.b.dly.dly[3].___y : 1  [by b.b.dly.dly[3].__y:=0]
+	   2418342 b.b.dly.dly[3].y : 0  [by b.b.dly.dly[3].___y:=1]
+	   2449923 b.b.dly.dly[4]._y : 1  [by b.b.dly.dly[3].y:=0]
+	   2449941 b.b.dly.dly[4].__y : 0  [by b.b.dly.dly[4]._y:=1]
+	   2452135 b.b.dly.dly[4].___y : 1  [by b.b.dly.dly[4].__y:=0]
+	   2490107 b.b.dly.dly[4].y : 0  [by b.b.dly.dly[4].___y:=1]
+	   2490227 b.b.dly.dly[5]._y : 1  [by b.b.dly.dly[4].y:=0]
+	   2496542 b.b.dly.dly[5].__y : 0  [by b.b.dly.dly[5]._y:=1]
+	   2498606 b.b.dly.dly[5].___y : 1  [by b.b.dly.dly[5].__y:=0]
+	   2499198 b.b.dly.dly[5].y : 0  [by b.b.dly.dly[5].___y:=1]
+	   2499205 b.b.dly.dly[6]._y : 1  [by b.b.dly.dly[5].y:=0]
+	   2499206 b.b.dly.dly[6].__y : 0  [by b.b.dly.dly[6]._y:=1]
+	   2499330 b.b.dly.dly[6].___y : 1  [by b.b.dly.dly[6].__y:=0]
+	   2505260 b.b.dly.dly[6].y : 0  [by b.b.dly.dly[6].___y:=1]
+	   2506312 b.b.dly.mu2[2]._y : 1  [by b.b.dly.dly[6].y:=0]
+	   2506672 b.b.dly._a[3] : 0  [by b.b.dly.mu2[2]._y:=1]
+	   2516866 b.b.dly.and2[3]._y : 1  [by b.b.dly._a[3]:=0]
+	   2517963 b.b.dly.dly[7].a : 0  [by b.b.dly.and2[3]._y:=1]
+	   2537855 b.b.dly.dly[7]._y : 1  [by b.b.dly.dly[7].a:=0]
+	   2537859 b.b.dly.dly[7].__y : 0  [by b.b.dly.dly[7]._y:=1]
+	   2549523 b.b.dly.dly[7].___y : 1  [by b.b.dly.dly[7].__y:=0]
+	   2587442 b.b.dly.dly[7].y : 0  [by b.b.dly.dly[7].___y:=1]
+	   2605103 b.b.dly.dly[8]._y : 1  [by b.b.dly.dly[7].y:=0]
+	   2608484 b.b.dly.dly[8].__y : 0  [by b.b.dly.dly[8]._y:=1]
+	   2608740 b.b.dly.dly[8].___y : 1  [by b.b.dly.dly[8].__y:=0]
+	   2623670 b.b.dly.dly[8].y : 0  [by b.b.dly.dly[8].___y:=1]
+	   2623707 b.b.dly.dly[9]._y : 1  [by b.b.dly.dly[8].y:=0]
+	   2623719 b.b.dly.dly[9].__y : 0  [by b.b.dly.dly[9]._y:=1]
+	   2623728 b.b.dly.dly[9].___y : 1  [by b.b.dly.dly[9].__y:=0]
+	   2624155 b.b.dly.dly[9].y : 0  [by b.b.dly.dly[9].___y:=1]
+	   2624397 b.b.dly.dly[10]._y : 1  [by b.b.dly.dly[9].y:=0]
+	   2625232 b.b.dly.dly[10].__y : 0  [by b.b.dly.dly[10]._y:=1]
+	   2671968 b.b.dly.dly[10].___y : 1  [by b.b.dly.dly[10].__y:=0]
+	   2673528 b.b.dly.dly[10].y : 0  [by b.b.dly.dly[10].___y:=1]
+	   2710621 b.b.dly.dly[11]._y : 1  [by b.b.dly.dly[10].y:=0]
+	   2710881 b.b.dly.dly[11].__y : 0  [by b.b.dly.dly[11]._y:=1]
+	   2719869 b.b.dly.dly[11].___y : 1  [by b.b.dly.dly[11].__y:=0]
+	   2719870 b.b.dly.dly[11].y : 0  [by b.b.dly.dly[11].___y:=1]
+	   2755920 b.b.dly.dly[12]._y : 1  [by b.b.dly.dly[11].y:=0]
+	   2756304 b.b.dly.dly[12].__y : 0  [by b.b.dly.dly[12]._y:=1]
+	   2756323 b.b.dly.dly[12].___y : 1  [by b.b.dly.dly[12].__y:=0]
+	   2756332 b.b.dly.dly[12].y : 0  [by b.b.dly.dly[12].___y:=1]
+	   2778286 b.b.dly.dly[13]._y : 1  [by b.b.dly.dly[12].y:=0]
+	   2778474 b.b.dly.dly[13].__y : 0  [by b.b.dly.dly[13]._y:=1]
+	   2824250 b.b.dly.dly[13].___y : 1  [by b.b.dly.dly[13].__y:=0]
+	   2827850 b.b.dly.dly[13].y : 0  [by b.b.dly.dly[13].___y:=1]
+	   2827998 b.b.dly.dly[14]._y : 1  [by b.b.dly.dly[13].y:=0]
+	   2846875 b.b.dly.dly[14].__y : 0  [by b.b.dly.dly[14]._y:=1]
+	   2846890 b.b.dly.dly[14].___y : 1  [by b.b.dly.dly[14].__y:=0]
+	   2857499 b.b.dly.mu2[3].b : 0  [by b.b.dly.dly[14].___y:=1]
+	   2858386 b.b.dly.mu2[3]._y : 1  [by b.b.dly.mu2[3].b:=0]
+	   2866368 b.b._req : 0  [by b.b.dly.mu2[3]._y:=1]
+	   2866369 b.b.req_buf._y : 1  [by b.b._req:=0]
+	   2873095 b.b._reqX : 0  [by b.b.req_buf._y:=1]
+	   2873460 b.b.req_bufarray.buf2._y : 1  [by b.b._reqX:=0]
+	   2882418 b.b._reqXX[0] : 0  [by b.b.req_bufarray.buf2._y:=1]
+[] Receiving ack out
+	   2882418 b.out.a : 1
+	   2883802 b.b._out_a_B : 0  [by b.out.a:=1]
+	   2883823 b.b.out_a_B_buf_t.buf2._y : 1  [by b.b._out_a_B:=0]
+	   2883826 b.b._out_a_BX_f[0] : 0  [by b.b.out_a_B_buf_t.buf2._y:=1]
+	   2883828 b.b.f_buf_func[3]._y : 1  [by b.b._out_a_BX_f[0]:=0]
+	   2883829 b.b.f_buf_func[4]._y : 1  [by b.b._out_a_BX_f[0]:=0]
+	   2883829 b.b.f_buf_func[3].y : 0  [by b.b.f_buf_func[3]._y:=1]
+	   2883843 b.b.out_a_B_buf_f.buf2._y : 1  [by b.b._out_a_B:=0]
+	   2884408 b.b.f_buf_func[2]._y : 1  [by b.b._out_a_BX_f[0]:=0]
+	   2885268 b.b.f_buf_func[2].y : 0  [by b.b.f_buf_func[2]._y:=1]
+	   2885703 b.b.f_buf_func[0]._y : 1  [by b.b._out_a_BX_f[0]:=0]
+	   2885704 b.b.f_buf_func[0].y : 0  [by b.b.f_buf_func[0]._y:=1]
+	   2887281 b.b.f_buf_func[4].y : 0  [by b.b.f_buf_func[4]._y:=1]
+	   2890976 b.b._out_a_BX_t[0] : 0  [by b.b.out_a_B_buf_f.buf2._y:=1]
+	   2893335 b.b.f_buf_func[1]._y : 1  [by b.b._out_a_BX_f[0]:=0]
+	   2893410 b.b.f_buf_func[1].y : 0  [by b.b.f_buf_func[1]._y:=1]
+	   2893410 b.out.v : 0
+	   2921361 b.b.inack_ctl._y : 1  [by b.out.v:=0]
+	   2921435 b.in.a : 0  [by b.b.inack_ctl._y:=1]
+	   2923705 b.b._en : 1  [by b.in.a:=0]
+	   2923803 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	   2929476 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	   2933329 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+	   2955531 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+[] Set ack out 0
+	   2955531 b.out.a : 0
+	   2961672 b.b._out_a_B : 1  [by b.out.a:=0]
+	   2961676 b.b.out_a_B_buf_f.buf2._y : 0  [by b.b._out_a_B:=1]
+	   2961681 b.b._out_a_BX_t[0] : 1  [by b.b.out_a_B_buf_f.buf2._y:=0]
+	   2964032 b.b.out_a_B_buf_t.buf2._y : 0  [by b.b._out_a_B:=1]
+	   2964323 b.b._out_a_BX_f[0] : 1  [by b.b.out_a_B_buf_t.buf2._y:=0]

test/unit_tests/bd2qdi_5/run/test.prs

@@ -0,0 +1,731 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"Reset"->"b._reset_B"-
+~("Reset")->"b._reset_B"+
+"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
+~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
+"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
+~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
+= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
+= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
+= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
+~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"&~"b.b.inack_ctl.c3"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl._y"+
+"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.c3"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl._y"-
+"b.b.inack_ctl._y"->"b.b.inack_ctl.y"-
+~("b.b.inack_ctl._y")->"b.b.inack_ctl.y"+
+"b.b.dly.and2[0].a"&"b.b.dly.and2[0].b"->"b.b.dly.and2[0]._y"-
+~("b.b.dly.and2[0].a"&"b.b.dly.and2[0].b")->"b.b.dly.and2[0]._y"+
+"b.b.dly.and2[0]._y"->"b.b.dly.and2[0].y"-
+~("b.b.dly.and2[0]._y")->"b.b.dly.and2[0].y"+
+"b.b.dly.and2[1].a"&"b.b.dly.and2[1].b"->"b.b.dly.and2[1]._y"-
+~("b.b.dly.and2[1].a"&"b.b.dly.and2[1].b")->"b.b.dly.and2[1]._y"+
+"b.b.dly.and2[1]._y"->"b.b.dly.and2[1].y"-
+~("b.b.dly.and2[1]._y")->"b.b.dly.and2[1].y"+
+"b.b.dly.and2[2].a"&"b.b.dly.and2[2].b"->"b.b.dly.and2[2]._y"-
+~("b.b.dly.and2[2].a"&"b.b.dly.and2[2].b")->"b.b.dly.and2[2]._y"+
+"b.b.dly.and2[2]._y"->"b.b.dly.and2[2].y"-
+~("b.b.dly.and2[2]._y")->"b.b.dly.and2[2].y"+
+"b.b.dly.and2[3].a"&"b.b.dly.and2[3].b"->"b.b.dly.and2[3]._y"-
+~("b.b.dly.and2[3].a"&"b.b.dly.and2[3].b")->"b.b.dly.and2[3]._y"+
+"b.b.dly.and2[3]._y"->"b.b.dly.and2[3].y"-
+~("b.b.dly.and2[3]._y")->"b.b.dly.and2[3].y"+
+= "b.b.dly.s[0]" "b.b.dly.mu2[0].s"
+= "b.b.dly.s[0]" "b.b.dly.and2[0].b"
+= "b.b.dly.s[1]" "b.b.dly.mu2[1].s"
+= "b.b.dly.s[1]" "b.b.dly.and2[1].b"
+= "b.b.dly.s[2]" "b.b.dly.mu2[2].s"
+= "b.b.dly.s[2]" "b.b.dly.and2[2].b"
+= "b.b.dly.s[3]" "b.b.dly.mu2[3].s"
+= "b.b.dly.s[3]" "b.b.dly.and2[3].b"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[14].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[13].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[12].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[11].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[10].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[9].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[8].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[7].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[6].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[5].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[4].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[3].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[2].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[1].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.dly[0].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.mu2[3].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.mu2[2].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.mu2[1].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.mu2[0].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.and2[3].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.and2[2].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.and2[1].vdd"
+= "b.b.dly.supply.vdd" "b.b.dly.and2[0].vdd"
+= "b.b.dly.supply.vss" "b.b.dly.dly[14].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[13].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[12].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[11].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[10].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[9].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[8].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[7].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[6].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[5].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[4].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[3].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[2].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[1].vss"
+= "b.b.dly.supply.vss" "b.b.dly.dly[0].vss"
+= "b.b.dly.supply.vss" "b.b.dly.mu2[3].vss"
+= "b.b.dly.supply.vss" "b.b.dly.mu2[2].vss"
+= "b.b.dly.supply.vss" "b.b.dly.mu2[1].vss"
+= "b.b.dly.supply.vss" "b.b.dly.mu2[0].vss"
+= "b.b.dly.supply.vss" "b.b.dly.and2[3].vss"
+= "b.b.dly.supply.vss" "b.b.dly.and2[2].vss"
+= "b.b.dly.supply.vss" "b.b.dly.and2[1].vss"
+= "b.b.dly.supply.vss" "b.b.dly.and2[0].vss"
+"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._s"-
+~("b.b.dly.mu2[0].s")->"b.b.dly.mu2[0]._s"+
+~"b.b.dly.mu2[0].a"&~"b.b.dly.mu2[0].s"|~"b.b.dly.mu2[0].b"&~"b.b.dly.mu2[0]._s"->"b.b.dly.mu2[0]._y"+
+"b.b.dly.mu2[0].a"&"b.b.dly.mu2[0]._s"|"b.b.dly.mu2[0].b"&"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._y"-
+"b.b.dly.mu2[0]._y"->"b.b.dly.mu2[0].y"-
+~("b.b.dly.mu2[0]._y")->"b.b.dly.mu2[0].y"+
+"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._s"-
+~("b.b.dly.mu2[1].s")->"b.b.dly.mu2[1]._s"+
+~"b.b.dly.mu2[1].a"&~"b.b.dly.mu2[1].s"|~"b.b.dly.mu2[1].b"&~"b.b.dly.mu2[1]._s"->"b.b.dly.mu2[1]._y"+
+"b.b.dly.mu2[1].a"&"b.b.dly.mu2[1]._s"|"b.b.dly.mu2[1].b"&"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._y"-
+"b.b.dly.mu2[1]._y"->"b.b.dly.mu2[1].y"-
+~("b.b.dly.mu2[1]._y")->"b.b.dly.mu2[1].y"+
+"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._s"-
+~("b.b.dly.mu2[2].s")->"b.b.dly.mu2[2]._s"+
+~"b.b.dly.mu2[2].a"&~"b.b.dly.mu2[2].s"|~"b.b.dly.mu2[2].b"&~"b.b.dly.mu2[2]._s"->"b.b.dly.mu2[2]._y"+
+"b.b.dly.mu2[2].a"&"b.b.dly.mu2[2]._s"|"b.b.dly.mu2[2].b"&"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._y"-
+"b.b.dly.mu2[2]._y"->"b.b.dly.mu2[2].y"-
+~("b.b.dly.mu2[2]._y")->"b.b.dly.mu2[2].y"+
+"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._s"-
+~("b.b.dly.mu2[3].s")->"b.b.dly.mu2[3]._s"+
+~"b.b.dly.mu2[3].a"&~"b.b.dly.mu2[3].s"|~"b.b.dly.mu2[3].b"&~"b.b.dly.mu2[3]._s"->"b.b.dly.mu2[3]._y"+
+"b.b.dly.mu2[3].a"&"b.b.dly.mu2[3]._s"|"b.b.dly.mu2[3].b"&"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._y"-
+"b.b.dly.mu2[3]._y"->"b.b.dly.mu2[3].y"-
+~("b.b.dly.mu2[3]._y")->"b.b.dly.mu2[3].y"+
+"b.b.dly.dly[0].a"->"b.b.dly.dly[0]._y"-
+~("b.b.dly.dly[0].a")->"b.b.dly.dly[0]._y"+
+"b.b.dly.dly[0]._y"->"b.b.dly.dly[0].__y"-
+~("b.b.dly.dly[0]._y")->"b.b.dly.dly[0].__y"+
+"b.b.dly.dly[0].__y"->"b.b.dly.dly[0].___y"-
+~("b.b.dly.dly[0].__y")->"b.b.dly.dly[0].___y"+
+"b.b.dly.dly[0].___y"->"b.b.dly.dly[0].y"-
+~("b.b.dly.dly[0].___y")->"b.b.dly.dly[0].y"+
+"b.b.dly.dly[1].a"->"b.b.dly.dly[1]._y"-
+~("b.b.dly.dly[1].a")->"b.b.dly.dly[1]._y"+
+"b.b.dly.dly[1]._y"->"b.b.dly.dly[1].__y"-
+~("b.b.dly.dly[1]._y")->"b.b.dly.dly[1].__y"+
+"b.b.dly.dly[1].__y"->"b.b.dly.dly[1].___y"-
+~("b.b.dly.dly[1].__y")->"b.b.dly.dly[1].___y"+
+"b.b.dly.dly[1].___y"->"b.b.dly.dly[1].y"-
+~("b.b.dly.dly[1].___y")->"b.b.dly.dly[1].y"+
+"b.b.dly.dly[2].a"->"b.b.dly.dly[2]._y"-
+~("b.b.dly.dly[2].a")->"b.b.dly.dly[2]._y"+
+"b.b.dly.dly[2]._y"->"b.b.dly.dly[2].__y"-
+~("b.b.dly.dly[2]._y")->"b.b.dly.dly[2].__y"+
+"b.b.dly.dly[2].__y"->"b.b.dly.dly[2].___y"-
+~("b.b.dly.dly[2].__y")->"b.b.dly.dly[2].___y"+
+"b.b.dly.dly[2].___y"->"b.b.dly.dly[2].y"-
+~("b.b.dly.dly[2].___y")->"b.b.dly.dly[2].y"+
+"b.b.dly.dly[3].a"->"b.b.dly.dly[3]._y"-
+~("b.b.dly.dly[3].a")->"b.b.dly.dly[3]._y"+
+"b.b.dly.dly[3]._y"->"b.b.dly.dly[3].__y"-
+~("b.b.dly.dly[3]._y")->"b.b.dly.dly[3].__y"+
+"b.b.dly.dly[3].__y"->"b.b.dly.dly[3].___y"-
+~("b.b.dly.dly[3].__y")->"b.b.dly.dly[3].___y"+
+"b.b.dly.dly[3].___y"->"b.b.dly.dly[3].y"-
+~("b.b.dly.dly[3].___y")->"b.b.dly.dly[3].y"+
+"b.b.dly.dly[4].a"->"b.b.dly.dly[4]._y"-
+~("b.b.dly.dly[4].a")->"b.b.dly.dly[4]._y"+
+"b.b.dly.dly[4]._y"->"b.b.dly.dly[4].__y"-
+~("b.b.dly.dly[4]._y")->"b.b.dly.dly[4].__y"+
+"b.b.dly.dly[4].__y"->"b.b.dly.dly[4].___y"-
+~("b.b.dly.dly[4].__y")->"b.b.dly.dly[4].___y"+
+"b.b.dly.dly[4].___y"->"b.b.dly.dly[4].y"-
+~("b.b.dly.dly[4].___y")->"b.b.dly.dly[4].y"+
+"b.b.dly.dly[5].a"->"b.b.dly.dly[5]._y"-
+~("b.b.dly.dly[5].a")->"b.b.dly.dly[5]._y"+
+"b.b.dly.dly[5]._y"->"b.b.dly.dly[5].__y"-
+~("b.b.dly.dly[5]._y")->"b.b.dly.dly[5].__y"+
+"b.b.dly.dly[5].__y"->"b.b.dly.dly[5].___y"-
+~("b.b.dly.dly[5].__y")->"b.b.dly.dly[5].___y"+
+"b.b.dly.dly[5].___y"->"b.b.dly.dly[5].y"-
+~("b.b.dly.dly[5].___y")->"b.b.dly.dly[5].y"+
+"b.b.dly.dly[6].a"->"b.b.dly.dly[6]._y"-
+~("b.b.dly.dly[6].a")->"b.b.dly.dly[6]._y"+
+"b.b.dly.dly[6]._y"->"b.b.dly.dly[6].__y"-
+~("b.b.dly.dly[6]._y")->"b.b.dly.dly[6].__y"+
+"b.b.dly.dly[6].__y"->"b.b.dly.dly[6].___y"-
+~("b.b.dly.dly[6].__y")->"b.b.dly.dly[6].___y"+
+"b.b.dly.dly[6].___y"->"b.b.dly.dly[6].y"-
+~("b.b.dly.dly[6].___y")->"b.b.dly.dly[6].y"+
+"b.b.dly.dly[7].a"->"b.b.dly.dly[7]._y"-
+~("b.b.dly.dly[7].a")->"b.b.dly.dly[7]._y"+
+"b.b.dly.dly[7]._y"->"b.b.dly.dly[7].__y"-
+~("b.b.dly.dly[7]._y")->"b.b.dly.dly[7].__y"+
+"b.b.dly.dly[7].__y"->"b.b.dly.dly[7].___y"-
+~("b.b.dly.dly[7].__y")->"b.b.dly.dly[7].___y"+
+"b.b.dly.dly[7].___y"->"b.b.dly.dly[7].y"-
+~("b.b.dly.dly[7].___y")->"b.b.dly.dly[7].y"+
+"b.b.dly.dly[8].a"->"b.b.dly.dly[8]._y"-
+~("b.b.dly.dly[8].a")->"b.b.dly.dly[8]._y"+
+"b.b.dly.dly[8]._y"->"b.b.dly.dly[8].__y"-
+~("b.b.dly.dly[8]._y")->"b.b.dly.dly[8].__y"+
+"b.b.dly.dly[8].__y"->"b.b.dly.dly[8].___y"-
+~("b.b.dly.dly[8].__y")->"b.b.dly.dly[8].___y"+
+"b.b.dly.dly[8].___y"->"b.b.dly.dly[8].y"-
+~("b.b.dly.dly[8].___y")->"b.b.dly.dly[8].y"+
+"b.b.dly.dly[9].a"->"b.b.dly.dly[9]._y"-
+~("b.b.dly.dly[9].a")->"b.b.dly.dly[9]._y"+
+"b.b.dly.dly[9]._y"->"b.b.dly.dly[9].__y"-
+~("b.b.dly.dly[9]._y")->"b.b.dly.dly[9].__y"+
+"b.b.dly.dly[9].__y"->"b.b.dly.dly[9].___y"-
+~("b.b.dly.dly[9].__y")->"b.b.dly.dly[9].___y"+
+"b.b.dly.dly[9].___y"->"b.b.dly.dly[9].y"-
+~("b.b.dly.dly[9].___y")->"b.b.dly.dly[9].y"+
+"b.b.dly.dly[10].a"->"b.b.dly.dly[10]._y"-
+~("b.b.dly.dly[10].a")->"b.b.dly.dly[10]._y"+
+"b.b.dly.dly[10]._y"->"b.b.dly.dly[10].__y"-
+~("b.b.dly.dly[10]._y")->"b.b.dly.dly[10].__y"+
+"b.b.dly.dly[10].__y"->"b.b.dly.dly[10].___y"-
+~("b.b.dly.dly[10].__y")->"b.b.dly.dly[10].___y"+
+"b.b.dly.dly[10].___y"->"b.b.dly.dly[10].y"-
+~("b.b.dly.dly[10].___y")->"b.b.dly.dly[10].y"+
+"b.b.dly.dly[11].a"->"b.b.dly.dly[11]._y"-
+~("b.b.dly.dly[11].a")->"b.b.dly.dly[11]._y"+
+"b.b.dly.dly[11]._y"->"b.b.dly.dly[11].__y"-
+~("b.b.dly.dly[11]._y")->"b.b.dly.dly[11].__y"+
+"b.b.dly.dly[11].__y"->"b.b.dly.dly[11].___y"-
+~("b.b.dly.dly[11].__y")->"b.b.dly.dly[11].___y"+
+"b.b.dly.dly[11].___y"->"b.b.dly.dly[11].y"-
+~("b.b.dly.dly[11].___y")->"b.b.dly.dly[11].y"+
+"b.b.dly.dly[12].a"->"b.b.dly.dly[12]._y"-
+~("b.b.dly.dly[12].a")->"b.b.dly.dly[12]._y"+
+"b.b.dly.dly[12]._y"->"b.b.dly.dly[12].__y"-
+~("b.b.dly.dly[12]._y")->"b.b.dly.dly[12].__y"+
+"b.b.dly.dly[12].__y"->"b.b.dly.dly[12].___y"-
+~("b.b.dly.dly[12].__y")->"b.b.dly.dly[12].___y"+
+"b.b.dly.dly[12].___y"->"b.b.dly.dly[12].y"-
+~("b.b.dly.dly[12].___y")->"b.b.dly.dly[12].y"+
+"b.b.dly.dly[13].a"->"b.b.dly.dly[13]._y"-
+~("b.b.dly.dly[13].a")->"b.b.dly.dly[13]._y"+
+"b.b.dly.dly[13]._y"->"b.b.dly.dly[13].__y"-
+~("b.b.dly.dly[13]._y")->"b.b.dly.dly[13].__y"+
+"b.b.dly.dly[13].__y"->"b.b.dly.dly[13].___y"-
+~("b.b.dly.dly[13].__y")->"b.b.dly.dly[13].___y"+
+"b.b.dly.dly[13].___y"->"b.b.dly.dly[13].y"-
+~("b.b.dly.dly[13].___y")->"b.b.dly.dly[13].y"+
+"b.b.dly.dly[14].a"->"b.b.dly.dly[14]._y"-
+~("b.b.dly.dly[14].a")->"b.b.dly.dly[14]._y"+
+"b.b.dly.dly[14]._y"->"b.b.dly.dly[14].__y"-
+~("b.b.dly.dly[14]._y")->"b.b.dly.dly[14].__y"+
+"b.b.dly.dly[14].__y"->"b.b.dly.dly[14].___y"-
+~("b.b.dly.dly[14].__y")->"b.b.dly.dly[14].___y"+
+"b.b.dly.dly[14].___y"->"b.b.dly.dly[14].y"-
+~("b.b.dly.dly[14].___y")->"b.b.dly.dly[14].y"+
+= "b.b.dly.dly[14].y" "b.b.dly.mu2[3].b"
+= "b.b.dly.dly[14].a" "b.b.dly.dly[13].y"
+= "b.b.dly.dly[13].a" "b.b.dly.dly[12].y"
+= "b.b.dly.dly[12].a" "b.b.dly.dly[11].y"
+= "b.b.dly.dly[11].a" "b.b.dly.dly[10].y"
+= "b.b.dly.dly[10].a" "b.b.dly.dly[9].y"
+= "b.b.dly.dly[9].a" "b.b.dly.dly[8].y"
+= "b.b.dly.dly[8].a" "b.b.dly.dly[7].y"
+= "b.b.dly.dly[7].a" "b.b.dly.and2[3].y"
+= "b.b.dly.dly[6].y" "b.b.dly.mu2[2].b"
+= "b.b.dly.dly[6].a" "b.b.dly.dly[5].y"
+= "b.b.dly.dly[5].a" "b.b.dly.dly[4].y"
+= "b.b.dly.dly[4].a" "b.b.dly.dly[3].y"
+= "b.b.dly.dly[3].a" "b.b.dly.and2[2].y"
+= "b.b.dly.dly[2].y" "b.b.dly.mu2[1].b"
+= "b.b.dly.dly[2].a" "b.b.dly.dly[1].y"
+= "b.b.dly.dly[1].a" "b.b.dly.and2[1].y"
+= "b.b.dly.dly[0].y" "b.b.dly.mu2[0].b"
+= "b.b.dly.dly[0].a" "b.b.dly.and2[0].y"
+= "b.b.dly._a[1]" "b.b.dly.mu2[1].a"
+= "b.b.dly._a[1]" "b.b.dly.and2[1].a"
+= "b.b.dly._a[1]" "b.b.dly.mu2[0].y"
+= "b.b.dly._a[2]" "b.b.dly.mu2[2].a"
+= "b.b.dly._a[2]" "b.b.dly.and2[2].a"
+= "b.b.dly._a[2]" "b.b.dly.mu2[1].y"
+= "b.b.dly._a[3]" "b.b.dly.mu2[3].a"
+= "b.b.dly._a[3]" "b.b.dly.and2[3].a"
+= "b.b.dly._a[3]" "b.b.dly.mu2[2].y"
+= "b.b.dly.out" "b.b.dly.mu2[3].y"
+= "b.b.dly.out" "b.b.dly._a[4]"
+= "b.b.dly.in" "b.b.dly.mu2[0].a"
+= "b.b.dly.in" "b.b.dly.and2[0].a"
+= "b.b.dly.in" "b.b.dly._a[0]"
+= "b.b._out_a_BX_f[0]" "b.b.out_a_B_buf_t.out[0]"
+= "b.b._out_a_BX_f[1]" "b.b.out_a_B_buf_t.out[1]"
+= "b.b._out_a_BX_f[2]" "b.b.out_a_B_buf_t.out[2]"
+= "b.b._out_a_BX_f[3]" "b.b.out_a_B_buf_t.out[3]"
+= "b.b._out_a_BX_f[4]" "b.b.out_a_B_buf_t.out[4]"
+= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[4].c2"
+= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[3].c2"
+= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[2].c2"
+= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[1].c2"
+= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[0].c2"
+= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[4]"
+= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[3]"
+= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[2]"
+= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[1]"
+"b.b.out_a_inv.a"->"b.b.out_a_inv.y"-
+~("b.b.out_a_inv.a")->"b.b.out_a_inv.y"+
+= "b.b._en" "b.b.en_buf_f.in"
+= "b.b._en" "b.b.en_buf_t.in"
+= "b.b._en" "b.b.en_ctl.y"
+= "b.b._en" "b.b.inack_ctl.c1"
+timing("b.b.in.a"-,"b.b.in.d[0]","b.b.in.r"+)
+timing("b.b.in.a"-,"b.b.in.d[1]","b.b.in.r"+)
+timing("b.b.in.a"-,"b.b.in.d[2]","b.b.in.r"+)
+timing("b.b.in.a"-,"b.b.in.d[3]","b.b.in.r"+)
+timing("b.b.in.a"-,"b.b.in.d[4]","b.b.in.r"+)
+= "b.b.in.r" "b.b.dly.in"
+= "b.b.in.a" "b.b.en_ctl.c1"
+= "b.b.in.a" "b.b.inack_ctl.y"
+= "b.b.in.d[0]" "b.b.t_buf_func[0].n1"
+= "b.b.in.d[0]" "b.b.input_invs[0].a"
+= "b.b.in.d[1]" "b.b.t_buf_func[1].n1"
+= "b.b.in.d[1]" "b.b.input_invs[1].a"
+= "b.b.in.d[2]" "b.b.t_buf_func[2].n1"
+= "b.b.in.d[2]" "b.b.input_invs[2].a"
+= "b.b.in.d[3]" "b.b.t_buf_func[3].n1"
+= "b.b.in.d[3]" "b.b.input_invs[3].a"
+= "b.b.in.d[4]" "b.b.t_buf_func[4].n1"
+= "b.b.in.d[4]" "b.b.input_invs[4].a"
+= "b.b._inB[0]" "b.b.f_buf_func[0].n1"
+= "b.b._inB[0]" "b.b.input_invs[0].y"
+= "b.b._inB[1]" "b.b.f_buf_func[1].n1"
+= "b.b._inB[1]" "b.b.input_invs[1].y"
+= "b.b._inB[2]" "b.b.f_buf_func[2].n1"
+= "b.b._inB[2]" "b.b.input_invs[2].y"
+= "b.b._inB[3]" "b.b.f_buf_func[3].n1"
+= "b.b._inB[3]" "b.b.input_invs[3].y"
+= "b.b._inB[4]" "b.b.f_buf_func[4].n1"
+= "b.b._inB[4]" "b.b.input_invs[4].y"
+"b.b.reset_buf.a"->"b.b.reset_buf._y"-
+~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
+"b.b.reset_buf._y"->"b.b.reset_buf.y"-
+~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
+= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
+= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
+= "b.b._reset_BX" "b.b.reset_bufarray.in"
+= "b.b._reset_BX" "b.b.reset_buf.y"
+= "b.b.reset_B" "b.b.reset_buf.a"
+= "b.b._out_a_BX_t[0]" "b.b.out_a_B_buf_f.out[0]"
+= "b.b._out_a_BX_t[1]" "b.b.out_a_B_buf_f.out[1]"
+= "b.b._out_a_BX_t[2]" "b.b.out_a_B_buf_f.out[2]"
+= "b.b._out_a_BX_t[3]" "b.b.out_a_B_buf_f.out[3]"
+= "b.b._out_a_BX_t[4]" "b.b.out_a_B_buf_f.out[4]"
+= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[4].c2"
+= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[3].c2"
+= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[2].c2"
+= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[1].c2"
+= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[0].c2"
+= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[4]"
+= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[3]"
+= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[2]"
+= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[1]"
+= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
+= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
+= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
+= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
+= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].sr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].sr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].sr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].sr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].sr_B"
+= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].pr_B"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
+"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
+~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
+"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
+~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
+= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
+= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
+= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
+"b.b.input_invs[0].a"->"b.b.input_invs[0].y"-
+~("b.b.input_invs[0].a")->"b.b.input_invs[0].y"+
+"b.b.input_invs[1].a"->"b.b.input_invs[1].y"-
+~("b.b.input_invs[1].a")->"b.b.input_invs[1].y"+
+"b.b.input_invs[2].a"->"b.b.input_invs[2].y"-
+~("b.b.input_invs[2].a")->"b.b.input_invs[2].y"+
+"b.b.input_invs[3].a"->"b.b.input_invs[3].y"-
+~("b.b.input_invs[3].a")->"b.b.input_invs[3].y"+
+"b.b.input_invs[4].a"->"b.b.input_invs[4].y"-
+~("b.b.input_invs[4].a")->"b.b.input_invs[4].y"+
+"b.b.out_a_B_buf_t.buf2.a"->"b.b.out_a_B_buf_t.buf2._y"-
+~("b.b.out_a_B_buf_t.buf2.a")->"b.b.out_a_B_buf_t.buf2._y"+
+"b.b.out_a_B_buf_t.buf2._y"->"b.b.out_a_B_buf_t.buf2.y"-
+~("b.b.out_a_B_buf_t.buf2._y")->"b.b.out_a_B_buf_t.buf2.y"+
+= "b.b.out_a_B_buf_t.supply.vdd" "b.b.out_a_B_buf_t.buf2.vdd"
+= "b.b.out_a_B_buf_t.supply.vss" "b.b.out_a_B_buf_t.buf2.vss"
+= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[4]"
+= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[3]"
+= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[2]"
+= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[1]"
+= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.buf2.y"
+= "b.b.out_a_B_buf_t.in" "b.b.out_a_B_buf_t.buf2.a"
+= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
+= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
+= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
+= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
+= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[4].c1"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[3].c1"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[2].c1"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[1].c1"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[0].c1"
+= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
+= "b.b.dly_cfg[0]" "b.b.dly.s[0]"
+= "b.b.dly_cfg[1]" "b.b.dly.s[1]"
+= "b.b.dly_cfg[2]" "b.b.dly.s[2]"
+= "b.b.dly_cfg[3]" "b.b.dly.s[3]"
+= "b.b.supply.vss" "b.b.out_a_B_buf_t.supply.vss"
+= "b.b.supply.vdd" "b.b.out_a_B_buf_t.supply.vdd"
+= "b.b.supply.vss" "b.b.out_a_B_buf_f.supply.vss"
+= "b.b.supply.vdd" "b.b.out_a_B_buf_f.supply.vdd"
+= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
+= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
+= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
+= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
+= "b.b.supply.vss" "b.b.req_bufarray.supply.vss"
+= "b.b.supply.vdd" "b.b.req_bufarray.supply.vdd"
+= "b.b.supply.vss" "b.b.reset_bufarray.supply.vss"
+= "b.b.supply.vdd" "b.b.reset_bufarray.supply.vdd"
+= "b.b.supply.vss" "b.b.dly.supply.vss"
+= "b.b.supply.vdd" "b.b.dly.supply.vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
+= "b.b.supply.vdd" "b.b.out_a_inv.vdd"
+= "b.b.supply.vdd" "b.b.en_ctl.vdd"
+= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
+= "b.b.supply.vdd" "b.b.input_invs[4].vdd"
+= "b.b.supply.vdd" "b.b.input_invs[3].vdd"
+= "b.b.supply.vdd" "b.b.input_invs[2].vdd"
+= "b.b.supply.vdd" "b.b.input_invs[1].vdd"
+= "b.b.supply.vdd" "b.b.input_invs[0].vdd"
+= "b.b.supply.vdd" "b.b.req_buf.vdd"
+= "b.b.supply.vdd" "b.b.reset_buf.vdd"
+= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
+= "b.b.supply.vss" "b.b.out_a_inv.vss"
+= "b.b.supply.vss" "b.b.en_ctl.vss"
+= "b.b.supply.vss" "b.b.inack_ctl.vss"
+= "b.b.supply.vss" "b.b.input_invs[4].vss"
+= "b.b.supply.vss" "b.b.input_invs[3].vss"
+= "b.b.supply.vss" "b.b.input_invs[2].vss"
+= "b.b.supply.vss" "b.b.input_invs[1].vss"
+= "b.b.supply.vss" "b.b.input_invs[0].vss"
+= "b.b.supply.vss" "b.b.req_buf.vss"
+= "b.b.supply.vss" "b.b.reset_buf.vss"
+~"b.b.en_ctl.p1"&~"b.b.en_ctl.c1"->"b.b.en_ctl.y"+
+"b.b.en_ctl.c1"->"b.b.en_ctl.y"-
+"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
+~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
+"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
+~("b.b.out_a_B_buf_f.buf2._y")->"b.b.out_a_B_buf_f.buf2.y"+
+= "b.b.out_a_B_buf_f.supply.vdd" "b.b.out_a_B_buf_f.buf2.vdd"
+= "b.b.out_a_B_buf_f.supply.vss" "b.b.out_a_B_buf_f.buf2.vss"
+= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[4]"
+= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[3]"
+= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[2]"
+= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[1]"
+= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.buf2.y"
+= "b.b.out_a_B_buf_f.in" "b.b.out_a_B_buf_f.buf2.a"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.a" "b.b.out_a_inv.a"
+= "b.b.out.v" "b.b.en_ctl.p1"
+= "b.b.out.v" "b.b.inack_ctl.c3"
+= "b.b.out.d.d[4].d[0]" "b.b.f_buf_func[4].y"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.t_buf_func[4].y"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.f_buf_func[3].y"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.t_buf_func[3].y"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.f_buf_func[2].y"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.t_buf_func[2].y"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.f_buf_func[1].y"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.t_buf_func[1].y"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.f_buf_func[0].y"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.t_buf_func[0].y"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b._reqXX[0]" "b.b.req_bufarray.out[0]"
+= "b.b._reqXX[1]" "b.b.req_bufarray.out[1]"
+= "b.b._reqXX[2]" "b.b.req_bufarray.out[2]"
+= "b.b._reqXX[3]" "b.b.req_bufarray.out[3]"
+= "b.b._reqXX[4]" "b.b.req_bufarray.out[4]"
+= "b.b._reqXX[0]" "b.b.t_buf_func[4].n2"
+= "b.b._reqXX[0]" "b.b.f_buf_func[4].n2"
+= "b.b._reqXX[0]" "b.b.t_buf_func[3].n2"
+= "b.b._reqXX[0]" "b.b.f_buf_func[3].n2"
+= "b.b._reqXX[0]" "b.b.t_buf_func[2].n2"
+= "b.b._reqXX[0]" "b.b.f_buf_func[2].n2"
+= "b.b._reqXX[0]" "b.b.t_buf_func[1].n2"
+= "b.b._reqXX[0]" "b.b.f_buf_func[1].n2"
+= "b.b._reqXX[0]" "b.b.t_buf_func[0].n2"
+= "b.b._reqXX[0]" "b.b.f_buf_func[0].n2"
+= "b.b._reqXX[0]" "b.b._reqXX[4]"
+= "b.b._reqXX[0]" "b.b._reqXX[3]"
+= "b.b._reqXX[0]" "b.b._reqXX[2]"
+= "b.b._reqXX[0]" "b.b._reqXX[1]"
+= "b.b._req" "b.b.req_buf.a"
+= "b.b._req" "b.b.dly.out"
+"b.b.req_bufarray.buf2.a"->"b.b.req_bufarray.buf2._y"-
+~("b.b.req_bufarray.buf2.a")->"b.b.req_bufarray.buf2._y"+
+"b.b.req_bufarray.buf2._y"->"b.b.req_bufarray.buf2.y"-
+~("b.b.req_bufarray.buf2._y")->"b.b.req_bufarray.buf2.y"+
+= "b.b.req_bufarray.supply.vdd" "b.b.req_bufarray.buf2.vdd"
+= "b.b.req_bufarray.supply.vss" "b.b.req_bufarray.buf2.vss"
+= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[4]"
+= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[3]"
+= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[2]"
+= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[1]"
+= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.buf2.y"
+= "b.b.req_bufarray.in" "b.b.req_bufarray.buf2.a"
+= "b.b._reqX" "b.b.inack_ctl.c2"
+= "b.b._reqX" "b.b.req_bufarray.in"
+= "b.b._reqX" "b.b.req_buf.y"
+= "b.b._out_a_B" "b.b.out_a_B_buf_t.in"
+= "b.b._out_a_B" "b.b.out_a_B_buf_f.in"
+= "b.b._out_a_B" "b.b.out_a_inv.y"
+"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
+~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
+"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
+~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
+= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
+= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
+= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
+"b.b.req_buf.a"->"b.b.req_buf._y"-
+~("b.b.req_buf.a")->"b.b.req_buf._y"+
+"b.b.req_buf._y"->"b.b.req_buf.y"-
+~("b.b.req_buf._y")->"b.b.req_buf.y"+
+= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
+= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
+= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
+= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
+= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[4].c1"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[3].c1"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[2].c1"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[1].c1"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[0].c1"
+= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
+~"b.b.f_buf_func[0].c1"&~"b.b.f_buf_func[0].c2"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
+"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].c2"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
+"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
+~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
+~"b.b.f_buf_func[1].c1"&~"b.b.f_buf_func[1].c2"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
+"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].c2"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
+"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
+~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
+~"b.b.f_buf_func[2].c1"&~"b.b.f_buf_func[2].c2"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
+"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].c2"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
+"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
+~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
+~"b.b.f_buf_func[3].c1"&~"b.b.f_buf_func[3].c2"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
+"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].c2"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
+"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
+~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
+~"b.b.f_buf_func[4].c1"&~"b.b.f_buf_func[4].c2"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
+"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].c2"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
+"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
+~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
+~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].c2"|~"b.b.t_buf_func[0].pr_B"->"b.b.t_buf_func[0]._y"+
+"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].c2"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"&"b.b.t_buf_func[0].sr_B"->"b.b.t_buf_func[0]._y"-
+"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
+~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
+~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].c2"|~"b.b.t_buf_func[1].pr_B"->"b.b.t_buf_func[1]._y"+
+"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].c2"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"&"b.b.t_buf_func[1].sr_B"->"b.b.t_buf_func[1]._y"-
+"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
+~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
+~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].c2"|~"b.b.t_buf_func[2].pr_B"->"b.b.t_buf_func[2]._y"+
+"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].c2"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"&"b.b.t_buf_func[2].sr_B"->"b.b.t_buf_func[2]._y"-
+"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
+~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
+~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].c2"|~"b.b.t_buf_func[3].pr_B"->"b.b.t_buf_func[3]._y"+
+"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].c2"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"&"b.b.t_buf_func[3].sr_B"->"b.b.t_buf_func[3]._y"-
+"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
+~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
+~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].c2"|~"b.b.t_buf_func[4].pr_B"->"b.b.t_buf_func[4]._y"+
+"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].c2"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"&"b.b.t_buf_func[4].sr_B"->"b.b.t_buf_func[4]._y"-
+"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
+~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
+= "Vdd" "b.b.supply.vdd"
+= "GND" "b.b.supply.vss"
+= "b._reset_B" "b.b.reset_B"
+= "b.dly_cfg[0]" "b.b.dly_cfg[0]"
+= "b.dly_cfg[1]" "b.b.dly_cfg[1]"
+= "b.dly_cfg[2]" "b.b.dly_cfg[2]"
+= "b.dly_cfg[3]" "b.b.dly_cfg[3]"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.v" "b.b.out.v"
+= "b.out.a" "b.b.out.a"
+= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
+= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
+= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
+= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
+= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
+= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
+= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
+= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
+= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
+= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
+= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
+= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
+= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
+= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
+= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
+= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
+= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
+= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
+= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
+= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+timing("b.in.a"-,"b.in.d[0]","b.in.r"+)
+timing("b.in.a"-,"b.in.d[1]","b.in.r"+)
+timing("b.in.a"-,"b.in.d[2]","b.in.r"+)
+timing("b.in.a"-,"b.in.d[3]","b.in.r"+)
+timing("b.in.a"-,"b.in.d[4]","b.in.r"+)
+= "b.in.a" "b.b.in.a"
+= "b.in.r" "b.b.in.r"
+= "b.in.d[0]" "b.b.in.d[0]"
+= "b.in.d[1]" "b.b.in.d[1]"
+= "b.in.d[2]" "b.b.in.d[2]"
+= "b.in.d[3]" "b.b.in.d[3]"
+= "b.in.d[4]" "b.b.in.d[4]"

test/unit_tests/bd2qdi_5/test.act

@@ -0,0 +1,45 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ *  It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/interfaces.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc bd2qdi_5(bd<5> in; avMx1of2<5> out; bool? dly_cfg[4])
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+  bd2qdi<5,4> b(.in = in, .out = out, .reset_B = _reset_B, .dly_cfg = dly_cfg);
+  b.supply.vdd = Vdd;
+  b.supply.vss = GND; 
+}
+
+bd2qdi_5 b;

test/unit_tests/bd2qdi_5/test.prsim

@@ -0,0 +1,137 @@
+watchall
+
+set b.out.a 0
+set b.out.v 0
+set b.in.r 0
+
+set b.dly_cfg[0] 1
+set b.dly_cfg[1] 1
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
+
+set b.in.d[0] 1
+set b.in.d[1] 0
+set b.in.d[2] 0
+set b.in.d[3] 1
+set b.in.d[4] 0
+
+set Reset 0
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+status X
+assert-qdi-channel-neutral "b.out" 5
+assert b.in.a 0
+
+
+system "echo '[] Reset finished, setting data'"
+set b.in.d[0] 0
+set b.in.d[1] 1
+set b.in.d[2] 1
+set b.in.d[3] 0
+set b.in.d[4] 1
+cycle
+
+system "echo '[] Reset finished, setting req 1'"
+set b.in.r 1
+cycle
+assert-qdi-channel-valid "b.out" 5 22
+
+system "echo '[] Receiving val out'"
+set b.out.v 1
+# set b.out.a 1
+cycle
+assert-qdi-channel-valid "b.out" 5 22
+assert b.in.a 1
+
+system "echo '[] Changing some input data'"
+set b.in.d[0] 1
+set b.in.d[1] 1
+set b.in.d[2] 1
+cycle
+system "echo '[] Removing req'"
+set b.in.r 0
+system "echo '[] Changing more data'"
+set b.in.d[3] 0
+set b.in.d[4] 0
+cycle
+assert-qdi-channel-valid "b.out" 5 22
+
+system "echo '[] Receiving ack out'"
+set b.out.a 1
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+set b.out.v 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Set ack out 0'"
+set b.out.a 0
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+assert b.in.a 0
+
+
+
+
+
+
+
+
+
+
+system "echo '[] Again!!! setting data'"
+
+
+set b.in.d[0] 0
+set b.in.d[1] 0
+set b.in.d[2] 0
+set b.in.d[3] 0
+set b.in.d[4] 0
+cycle
+
+system "echo '[] Again!!! setting req 1'"
+set b.in.r 1
+cycle
+assert-qdi-channel-valid "b.out" 5 0
+
+system "echo '[] Receiving val out'"
+set b.out.v 1
+# set b.out.a 1
+cycle
+assert-qdi-channel-valid "b.out" 5 0
+assert b.in.a 1
+
+system "echo '[] Changing some input data'"
+set b.in.d[0] 1
+set b.in.d[1] 1
+set b.in.d[2] 1
+cycle
+system "echo '[] Removing req'"
+set b.in.r 0
+system "echo '[] Changing more data'"
+set b.in.d[3] 0
+set b.in.d[4] 0
+cycle
+assert-qdi-channel-valid "b.out" 5 0
+
+system "echo '[] Receiving ack out'"
+set b.out.a 1
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+set b.out.v 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Set ack out 0'"
+set b.out.a 0
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+assert b.in.a 0

test/unit_tests/buf_s_5/run/prsim.out

@@ -1,4 +1,4 @@
-b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.vc.tmp[0] b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.tmp[2] b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.OR2_tf[2]._y b.b.en_buf_f.buf2._y b.b.vc.tmp[5] b.b.en_buf_t.buf2._y b.b._en b.b.vc.tmp[4] b.b.vc.C3Els[0]._y b.b.vc.OR2_tf[4]._y b.out.a b.b._in_v b.b.vc.tmp[6] b.b.vc.tmp[3] b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.vc.C2Els[0]._y b.b.out_a_B_buf_f.buf2._y b.b.vc.OR2_tf[3]._y 
+b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[0].y b.b.vc.OR2_tf[1]._y b.b.vc.OR2_tf[1].y b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.vc.OR2_tf[4].y b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.myctree.tmp[5] b.b.vc.OR2_tf[3].y b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.myctree.C3Els[0]._y b.b.vc.OR2_tf[2]._y b.b.vc.myctree.tmp[6] b.b.en_buf_f.buf2._y b.b._in_v b.b.vc.myctree.C2Els[0]._y b.b.en_buf_t.buf2._y b.b._en b.b.vc.OR2_tf[4]._y b.out.a b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.out_a_B_buf_f.buf2._y b.b.vc.myctree.C2Els[1]._y b.b.vc.OR2_tf[3]._y 
 	     84120 b.b.f_buf_func[0].n1 : 0
 	     84120 b.b.f_buf_func[4].y : 1
 	     84120 b.b.t_buf_func[4].y : 1
@@ -25,7 +25,7 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	     84121 b.b.f_buf_func[2].y : 0
 	     84121 b.b._en : 1  [by b.out.v:=0]
 	     84123 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
-	     84141 b.b.vc.tmp[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	     84141 b.b.vc.OR2_tf[1].y : 0  [by b.b.vc.OR2_tf[1]._y:=1]
 	     84402 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
 	     84542 b.b.t_buf_func[0].y : 0
 	     84671 b.b.t_buf_func[2].y : 0
@@ -34,16 +34,16 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	     85103 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
 	     85191 b.b.vc.OR2_tf[3]._y : 1  [by b.b.t_buf_func[3].n1:=0]
 	     85201 b.b.t_buf_func[1].y : 0
-	     88415 b.b.vc.tmp[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	     88415 b.b.vc.OR2_tf[2].y : 0  [by b.b.vc.OR2_tf[2]._y:=1]
 	     88891 b.b.out_a_B_buf_t.buf2._y : 0  [by b.b._out_a_B:=1]
 	     89393 b.b._out_a_BX_f[0] : 1  [by b.b.out_a_B_buf_t.buf2._y:=0]
-	     89951 b.b.vc.tmp[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	     89951 b.b.vc.OR2_tf[3].y : 0  [by b.b.vc.OR2_tf[3]._y:=1]
 	     97969 b.b.f_buf_func[3].y : 0
 	     98463 b.b.f_buf_func[0].y : 0
 	    104325 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
-	    104528 b.b.vc.tmp[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
-	    106382 b.b.vc.C2Els[0]._y : 1  [by b.b.vc.tmp[0]:=0]
-	    106521 b.b.vc.tmp[5] : 0  [by b.b.vc.C2Els[0]._y:=1]
+	    104528 b.b.vc.OR2_tf[0].y : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    106382 b.b.vc.myctree.C2Els[0]._y : 1  [by b.b.vc.OR2_tf[0].y:=0]
+	    106521 b.b.vc.myctree.tmp[5] : 0  [by b.b.vc.myctree.C2Els[0]._y:=1]
 	    106561 b.b.vc.OR2_tf[4]._y : 1  [by b.b.f_buf_func[4].n1:=0]
 	    106687 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
 	    108932 b.b.t_buf_func[3].y : 0
@@ -55,11 +55,11 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	    135773 b.b.f_buf_func[4].y : 0
 	    138591 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
 	    138795 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
-	    142907 b.b.vc.tmp[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
-	    142922 b.b.vc.C3Els[0]._y : 1  [by b.b.vc.tmp[4]:=0]
-	    142923 b.b.vc.tmp[6] : 0  [by b.b.vc.C3Els[0]._y:=1]
-	    142960 b.b.vc.C2Els[1]._y : 1  [by b.b.vc.tmp[6]:=0]
-	    143699 b.b._in_v : 0  [by b.b.vc.C2Els[1]._y:=1]
+	    142907 b.b.vc.OR2_tf[4].y : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    142922 b.b.vc.myctree.C3Els[0]._y : 1  [by b.b.vc.OR2_tf[4].y:=0]
+	    142923 b.b.vc.myctree.tmp[6] : 0  [by b.b.vc.myctree.C3Els[0]._y:=1]
+	    142960 b.b.vc.myctree.C2Els[1]._y : 1  [by b.b.vc.myctree.tmp[6]:=0]
+	    143699 b.b._in_v : 0  [by b.b.vc.myctree.C2Els[1]._y:=1]
 	    143811 b.b.in_v_buf4._y : 1  [by b.b._in_v:=0]
 	    184631 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
 	    184671 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
@@ -88,23 +88,23 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	    200679 b.b.f_buf_func[2].n1 : 1
 	    200679 b.b.t_buf_func[1].n1 : 1
 	    200812 b.b.vc.OR2_tf[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
-	    201171 b.b.vc.tmp[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    201171 b.b.vc.OR2_tf[2].y : 1  [by b.b.vc.OR2_tf[2]._y:=0]
 	    201526 b.b.vc.OR2_tf[0]._y : 0  [by b.b.t_buf_func[0].n1:=1]
-	    215642 b.b.vc.tmp[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    215642 b.b.vc.OR2_tf[0].y : 1  [by b.b.vc.OR2_tf[0]._y:=0]
 	    216341 b.b.vc.OR2_tf[1]._y : 0  [by b.b.t_buf_func[1].n1:=1]
-	    216562 b.b.vc.tmp[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
-	    216569 b.b.vc.C2Els[0]._y : 0  [by b.b.vc.tmp[1]:=1]
-	    216599 b.b.vc.tmp[5] : 1  [by b.b.vc.C2Els[0]._y:=0]
+	    216562 b.b.vc.OR2_tf[1].y : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    216569 b.b.vc.myctree.C2Els[0]._y : 0  [by b.b.vc.OR2_tf[1].y:=1]
+	    216599 b.b.vc.myctree.tmp[5] : 1  [by b.b.vc.myctree.C2Els[0]._y:=0]
 	    230807 b.b.vc.OR2_tf[3]._y : 0  [by b.b.f_buf_func[3].n1:=1]
-	    237520 b.b.vc.tmp[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    237520 b.b.vc.OR2_tf[3].y : 1  [by b.b.vc.OR2_tf[3]._y:=0]
 [] Setting final input
 	    237520 b.b.t_buf_func[4].n1 : 1
 	    294981 b.b.vc.OR2_tf[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
-	    295072 b.b.vc.tmp[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
-	    297261 b.b.vc.C3Els[0]._y : 0  [by b.b.vc.tmp[4]:=1]
-	    297268 b.b.vc.tmp[6] : 1  [by b.b.vc.C3Els[0]._y:=0]
-	    300055 b.b.vc.C2Els[1]._y : 0  [by b.b.vc.tmp[6]:=1]
-	    300161 b.b._in_v : 1  [by b.b.vc.C2Els[1]._y:=0]
+	    295072 b.b.vc.OR2_tf[4].y : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    297261 b.b.vc.myctree.C3Els[0]._y : 0  [by b.b.vc.OR2_tf[4].y:=1]
+	    297268 b.b.vc.myctree.tmp[6] : 1  [by b.b.vc.myctree.C3Els[0]._y:=0]
+	    300055 b.b.vc.myctree.C2Els[1]._y : 0  [by b.b.vc.myctree.tmp[6]:=1]
+	    300161 b.b._in_v : 1  [by b.b.vc.myctree.C2Els[1]._y:=0]
 	    300239 b.b.in_v_buf4._y : 0  [by b.b._in_v:=1]
 	    300514 b.in.v : 1  [by b.b.in_v_buf4._y:=0]
 	    319510 b.b.in_v_bufN.buf2._y : 0  [by b.in.v:=1]
@@ -136,20 +136,20 @@ b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_b
 	    337917 b.b.f_buf_func[3].n1 : 0
 	    337918 b.b.vc.OR2_tf[4]._y : 1  [by b.b.t_buf_func[4].n1:=0]
 	    337928 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
-	    337985 b.b.vc.tmp[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    337985 b.b.vc.OR2_tf[4].y : 0  [by b.b.vc.OR2_tf[4]._y:=1]
 	    338287 b.b.vc.OR2_tf[3]._y : 1  [by b.b.f_buf_func[3].n1:=0]
-	    338303 b.b.vc.tmp[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    338303 b.b.vc.OR2_tf[3].y : 0  [by b.b.vc.OR2_tf[3]._y:=1]
 	    338465 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
-	    340569 b.b.vc.tmp[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
-	    343027 b.b.vc.tmp[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
-	    343555 b.b.vc.C3Els[0]._y : 1  [by b.b.vc.tmp[2]:=0]
-	    345990 b.b.vc.tmp[6] : 0  [by b.b.vc.C3Els[0]._y:=1]
+	    340569 b.b.vc.OR2_tf[1].y : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    343027 b.b.vc.OR2_tf[2].y : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    343555 b.b.vc.myctree.C3Els[0]._y : 1  [by b.b.vc.OR2_tf[2].y:=0]
+	    345990 b.b.vc.myctree.tmp[6] : 0  [by b.b.vc.myctree.C3Els[0]._y:=1]
 	    381834 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
-	    408714 b.b.vc.tmp[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
-	    432639 b.b.vc.C2Els[0]._y : 1  [by b.b.vc.tmp[0]:=0]
-	    445680 b.b.vc.tmp[5] : 0  [by b.b.vc.C2Els[0]._y:=1]
-	    445682 b.b.vc.C2Els[1]._y : 1  [by b.b.vc.tmp[5]:=0]
-	    506640 b.b._in_v : 0  [by b.b.vc.C2Els[1]._y:=1]
+	    408714 b.b.vc.OR2_tf[0].y : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    432639 b.b.vc.myctree.C2Els[0]._y : 1  [by b.b.vc.OR2_tf[0].y:=0]
+	    445680 b.b.vc.myctree.tmp[5] : 0  [by b.b.vc.myctree.C2Els[0]._y:=1]
+	    445682 b.b.vc.myctree.C2Els[1]._y : 1  [by b.b.vc.myctree.tmp[5]:=0]
+	    506640 b.b._in_v : 0  [by b.b.vc.myctree.C2Els[1]._y:=1]
 	    506643 b.b.in_v_buf4._y : 1  [by b.b._in_v:=0]
 	    506672 b.in.v : 0  [by b.b.in_v_buf4._y:=1]
 	    506989 b.b.in_v_bufN.buf2._y : 1  [by b.in.v:=0]

test/unit_tests/buf_s_5/run/test.prs

@@ -101,18 +101,40 @@
 = "b.b.supply.vss" "b.b.reset_buf.vss"
 = "b.b.supply.vss" "b.b.en_ctl.vss"
 = "b.b.supply.vss" "b.b.inack_ctl.vss"
-~"b.b.vc.C2Els[0].c1"&~"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"+
-"b.b.vc.C2Els[0].c1"&"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"-
-"b.b.vc.C2Els[0]._y"->"b.b.vc.C2Els[0].y"-
-~("b.b.vc.C2Els[0]._y")->"b.b.vc.C2Els[0].y"+
-~"b.b.vc.C2Els[1].c1"&~"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"+
-"b.b.vc.C2Els[1].c1"&"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"-
-"b.b.vc.C2Els[1]._y"->"b.b.vc.C2Els[1].y"-
-~("b.b.vc.C2Els[1]._y")->"b.b.vc.C2Els[1].y"+
-~"b.b.vc.C3Els[0].c1"&~"b.b.vc.C3Els[0].c2"&~"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"+
-"b.b.vc.C3Els[0].c1"&"b.b.vc.C3Els[0].c2"&"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"-
-"b.b.vc.C3Els[0]._y"->"b.b.vc.C3Els[0].y"-
-~("b.b.vc.C3Els[0]._y")->"b.b.vc.C3Els[0].y"+
+~"b.b.vc.myctree.C2Els[0].c1"&~"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"+
+"b.b.vc.myctree.C2Els[0].c1"&"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"-
+"b.b.vc.myctree.C2Els[0]._y"->"b.b.vc.myctree.C2Els[0].y"-
+~("b.b.vc.myctree.C2Els[0]._y")->"b.b.vc.myctree.C2Els[0].y"+
+~"b.b.vc.myctree.C2Els[1].c1"&~"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"+
+"b.b.vc.myctree.C2Els[1].c1"&"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"-
+"b.b.vc.myctree.C2Els[1]._y"->"b.b.vc.myctree.C2Els[1].y"-
+~("b.b.vc.myctree.C2Els[1]._y")->"b.b.vc.myctree.C2Els[1].y"+
+~"b.b.vc.myctree.C3Els[0].c1"&~"b.b.vc.myctree.C3Els[0].c2"&~"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"+
+"b.b.vc.myctree.C3Els[0].c1"&"b.b.vc.myctree.C3Els[0].c2"&"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"-
+"b.b.vc.myctree.C3Els[0]._y"->"b.b.vc.myctree.C3Els[0].y"-
+~("b.b.vc.myctree.C3Els[0]._y")->"b.b.vc.myctree.C3Els[0].y"+
+= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[1].c1"
+= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[0].y"
+= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C2Els[1].c2"
+= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C3Els[0].y"
+= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C3Els[0].vdd"
+= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[1].vdd"
+= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[0].vdd"
+= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C3Els[0].vss"
+= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[1].vss"
+= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[0].vss"
+= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.C2Els[0].c1"
+= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.tmp[0]"
+= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.C2Els[0].c2"
+= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.tmp[1]"
+= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.C3Els[0].c1"
+= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.tmp[2]"
+= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.C3Els[0].c2"
+= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.tmp[3]"
+= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.C3Els[0].c3"
+= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.tmp[4]"
+= "b.b.vc.myctree.out" "b.b.vc.myctree.C2Els[1].y"
+= "b.b.vc.myctree.out" "b.b.vc.myctree.tmp[7]"
 "b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
 ~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
 "b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
@@ -133,36 +155,24 @@
 ~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
 "b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
 ~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
-= "b.b.vc.tmp[0]" "b.b.vc.C2Els[0].c1"
-= "b.b.vc.tmp[0]" "b.b.vc.OR2_tf[0].y"
-= "b.b.vc.tmp[1]" "b.b.vc.C2Els[0].c2"
-= "b.b.vc.tmp[1]" "b.b.vc.OR2_tf[1].y"
-= "b.b.vc.tmp[2]" "b.b.vc.C3Els[0].c1"
-= "b.b.vc.tmp[2]" "b.b.vc.OR2_tf[2].y"
-= "b.b.vc.tmp[3]" "b.b.vc.C3Els[0].c2"
-= "b.b.vc.tmp[3]" "b.b.vc.OR2_tf[3].y"
-= "b.b.vc.tmp[4]" "b.b.vc.C3Els[0].c3"
-= "b.b.vc.tmp[4]" "b.b.vc.OR2_tf[4].y"
-= "b.b.vc.tmp[5]" "b.b.vc.C2Els[1].c1"
-= "b.b.vc.tmp[5]" "b.b.vc.C2Els[0].y"
-= "b.b.vc.tmp[6]" "b.b.vc.C2Els[1].c2"
-= "b.b.vc.tmp[6]" "b.b.vc.C3Els[0].y"
-= "b.b.vc.supply.vdd" "b.b.vc.C3Els[0].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.C2Els[1].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.C2Els[0].vdd"
+= "b.b.vc.OR2_tf[4].y" "b.b.vc.myctree.in[4]"
+= "b.b.vc.OR2_tf[3].y" "b.b.vc.myctree.in[3]"
+= "b.b.vc.OR2_tf[2].y" "b.b.vc.myctree.in[2]"
+= "b.b.vc.OR2_tf[1].y" "b.b.vc.myctree.in[1]"
+= "b.b.vc.OR2_tf[0].y" "b.b.vc.myctree.in[0]"
+= "b.b.vc.supply.vss" "b.b.vc.myctree.supply.vss"
+= "b.b.vc.supply.vdd" "b.b.vc.myctree.supply.vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
 = "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
-= "b.b.vc.supply.vss" "b.b.vc.C3Els[0].vss"
-= "b.b.vc.supply.vss" "b.b.vc.C2Els[1].vss"
-= "b.b.vc.supply.vss" "b.b.vc.C2Els[0].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
 = "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
+= "b.b.vc.out" "b.b.vc.myctree.out"
 = "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
 = "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
 = "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
@@ -203,8 +213,6 @@
 = "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
 = "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
 = "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
-= "b.b.vc.out" "b.b.vc.C2Els[1].y"
-= "b.b.vc.out" "b.b.vc.tmp[7]"
 "b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
 ~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
 "b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-

test/unit_tests/buff.v

@@ -0,0 +1,685 @@
+//
+// Verilog module for: BUF_X6<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   wire a;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: sigbuf<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
+   input in;
+   output \out[0] ;
+
+// -- signals ---
+   reg \out[0] ;
+   wire in;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6  (.y(\out[0] ), .a(in));
+endmodule
+
+//
+// Verilog module for: A_3C_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   wire pr_B;
+   wire c3;
+   wire c1;
+   wire sr_B;
+   wire c2;
+   reg _y;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: INV_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
+   output y;
+   input c1;
+   input c2;
+
+// -- signals ---
+   wire c2;
+   wire c1;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_3C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+
+// -- signals ---
+   wire c1;
+   reg y;
+   reg _y;
+   wire c3;
+   wire c2;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: ctree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
+   input \in[0] ;
+   input \in[1] ;
+   input \in[2] ;
+   input \in[3] ;
+   input \in[4] ;
+   input \in[5] ;
+   input \in[6] ;
+   input \in[7] ;
+   input \in[8] ;
+   input \in[9] ;
+   input \in[10] ;
+   input \in[11] ;
+   input \in[12] ;
+   input \in[13] ;
+   input \in[14] ;
+   output out;
+
+// -- signals ---
+   wire \in[9] ;
+   wire \in[11] ;
+   reg \tmp[18] ;
+   reg \tmp[16] ;
+   reg \tmp[24] ;
+   wire \in[0] ;
+   reg \tmp[22] ;
+   reg out;
+   wire \in[7] ;
+   reg \tmp[23] ;
+   wire \in[4] ;
+   wire \in[3] ;
+   wire \in[12] ;
+   reg \tmp[20] ;
+   wire \in[2] ;
+   reg \tmp[19] ;
+   wire \in[14] ;
+   wire \in[6] ;
+   wire \in[10] ;
+   wire \in[5] ;
+   wire \in[8] ;
+   wire \in[13] ;
+   wire \in[1] ;
+   reg \tmp[21] ;
+   reg \tmp[17] ;
+   reg \tmp[15] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0]  (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1]  (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2]  (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3]  (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4]  (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5]  (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6]  (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7]  (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0]  (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1]  (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2]  (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
+endmodule
+
+//
+// Verilog module for: OR2_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
+   output y;
+   input a;
+   input b;
+
+// -- signals ---
+   wire a;
+   wire b;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: vtree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
+   input \in.d[0].d[0] ;
+   input \in.d[0].d[1] ;
+   input \in.d[1].d[0] ;
+   input \in.d[1].d[1] ;
+   input \in.d[2].d[0] ;
+   input \in.d[2].d[1] ;
+   input \in.d[3].d[0] ;
+   input \in.d[3].d[1] ;
+   input \in.d[4].d[0] ;
+   input \in.d[4].d[1] ;
+   input \in.d[5].d[0] ;
+   input \in.d[5].d[1] ;
+   input \in.d[6].d[0] ;
+   input \in.d[6].d[1] ;
+   input \in.d[7].d[0] ;
+   input \in.d[7].d[1] ;
+   input \in.d[8].d[0] ;
+   input \in.d[8].d[1] ;
+   input \in.d[9].d[0] ;
+   input \in.d[9].d[1] ;
+   input \in.d[10].d[0] ;
+   input \in.d[10].d[1] ;
+   input \in.d[11].d[0] ;
+   input \in.d[11].d[1] ;
+   input \in.d[12].d[0] ;
+   input \in.d[12].d[1] ;
+   input \in.d[13].d[0] ;
+   input \in.d[13].d[1] ;
+   input \in.d[14].d[0] ;
+   input \in.d[14].d[1] ;
+   output out;
+
+// -- signals ---
+   wire \in.d[2].d[1] ;
+   wire \in.d[14].d[1] ;
+   reg \ct.in[8] ;
+   wire \in.d[10].d[1] ;
+   wire \in.d[7].d[1] ;
+   reg \ct.in[14] ;
+   wire \in.d[3].d[0] ;
+   reg \ct.in[0] ;
+   wire \in.d[8].d[1] ;
+   wire \in.d[6].d[1] ;
+   reg out;
+   wire \in.d[14].d[0] ;
+   wire \in.d[6].d[0] ;
+   wire \in.d[10].d[0] ;
+   wire \in.d[5].d[1] ;
+   wire \in.d[7].d[0] ;
+   wire \in.d[3].d[1] ;
+   wire \in.d[2].d[0] ;
+   reg \ct.in[6] ;
+   reg \ct.in[4] ;
+   wire \in.d[5].d[0] ;
+   wire \in.d[1].d[1] ;
+   wire \in.d[0].d[1] ;
+   reg \ct.in[5] ;
+   reg \ct.in[1] ;
+   wire \in.d[9].d[0] ;
+   wire \in.d[0].d[0] ;
+   wire \in.d[4].d[1] ;
+   reg \ct.in[12] ;
+   wire \in.d[12].d[1] ;
+   wire \in.d[8].d[0] ;
+   reg \ct.in[2] ;
+   wire \in.d[13].d[0] ;
+   wire \in.d[4].d[0] ;
+   wire \in.d[12].d[0] ;
+   wire \in.d[11].d[0] ;
+   wire \in.d[13].d[1] ;
+   reg \ct.in[9] ;
+   reg \ct.in[3] ;
+   reg \ct.in[11] ;
+   wire \in.d[1].d[0] ;
+   reg \ct.in[7] ;
+   wire \in.d[11].d[1] ;
+   wire \in.d[9].d[1] ;
+   reg \ct.in[10] ;
+   reg \ct.in[13] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct  (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0]  (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1]  (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2]  (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3]  (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4]  (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5]  (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6]  (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7]  (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8]  (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9]  (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10]  (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11]  (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12]  (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13]  (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14]  (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
+endmodule
+
+//
+// Verilog module for: A_1C1P_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
+   output y;
+   input c1;
+   input p1;
+
+// -- signals ---
+   wire c1;
+   wire p1;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C1N_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input n1;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   reg y;
+   wire n1;
+   wire sr_B;
+   wire pr_B;
+   wire c2;
+   wire c1;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: buffer<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+   input reset_B;
+
+// -- signals ---
+   wire \in.d.d[9].d[0] ;
+   reg _out_a_B;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   wire \in.d.d[14].d[0] ;
+   wire \in.d.d[10].d[1] ;
+   reg \out.d.d[14].d[1] ;
+   wire \in.d.d[8].d[1] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[3].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[5].d[0] ;
+   wire \out.v ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[1].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[4].d[1] ;
+   reg _reset_BX;
+   reg \in.v ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   reg \out.d.d[5].d[0] ;
+   reg \out.d.d[10].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   reg \out.d.d[7].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[5].d[1] ;
+   reg _en;
+   reg \_out_a_BX_f[0] ;
+   reg \out.d.d[9].d[0] ;
+   wire \in.d.d[13].d[1] ;
+   reg \out.d.d[11].d[0] ;
+   wire \in.d.d[12].d[0] ;
+   wire \in.d.d[11].d[0] ;
+   wire \in.d.d[1].d[1] ;
+   wire \in.d.d[1].d[0] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[4].d[1] ;
+   reg _in_v;
+   reg \out.d.d[13].d[0] ;
+   reg \out.d.d[2].d[0] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[2].d[1] ;
+   reg \in.a ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[3].d[1] ;
+   reg \_out_a_BX_t[0] ;
+   wire \in.d.d[2].d[0] ;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[0].d[0] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \_en_X_t[0] ;
+   wire \in.d.d[10].d[0] ;
+   wire \out.a ;
+   reg \out.d.d[12].d[1] ;
+   wire reset_B;
+   wire \in.d.d[7].d[1] ;
+   wire \in.d.d[6].d[1] ;
+   wire \in.d.d[12].d[1] ;
+   wire \in.d.d[0].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   reg \_reset_BXX[0] ;
+   reg \out.d.d[4].d[0] ;
+   reg \out.d.d[13].d[1] ;
+   reg \_en_X_f[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t  (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl  (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray  (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf  (.y(\in.v ), .a(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv  (.y(_out_a_B), .a(\out.a ));
+_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc  (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f  (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl  (.y(_en), .c1(\in.a ), .p1(\out.v ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf  (.y(_reset_BX), .a(reset_B));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f  (.in(_en), .\out[0] (\_en_X_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t  (.in(_en), .\out[0] (\_en_X_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0]  (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1]  (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2]  (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3]  (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4]  (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5]  (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6]  (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7]  (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8]  (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9]  (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10]  (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11]  (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12]  (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13]  (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14]  (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0]  (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1]  (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2]  (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3]  (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4]  (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5]  (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6]  (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7]  (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8]  (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9]  (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10]  (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11]  (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12]  (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13]  (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14]  (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+endmodule
+
+//
+// Verilog module for: buffer_15<>
+//
+module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+
+// -- signals ---
+   reg \out.d.d[2].d[0] ;
+   reg \out.d.d[14].d[1] ;
+   reg \out.d.d[4].d[0] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[8].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   wire \in.d.d[1].d[0] ;
+   reg _reset_B;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[5].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   wire \in.d.d[2].d[1] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[5].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[10].d[0] ;
+   wire \in.d.d[3].d[1] ;
+   wire \in.d.d[11].d[0] ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[9].d[0] ;
+   wire \in.d.d[2].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[4].d[1] ;
+   wire \in.d.d[1].d[1] ;
+   reg \out.d.d[13].d[1] ;
+   reg \out.d.d[1].d[1] ;
+   reg \out.d.d[10].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   wire \in.d.d[5].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[0].d[1] ;
+   wire \out.v ;
+   wire \in.d.d[12].d[0] ;
+   reg \out.d.d[3].d[1] ;
+   reg \out.d.d[7].d[1] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[11].d[0] ;
+   reg \out.d.d[4].d[1] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[7].d[1] ;
+   wire \out.a ;
+   reg \in.a ;
+   wire \in.d.d[13].d[1] ;
+   wire \in.d.d[10].d[1] ;
+   reg \out.d.d[12].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[6].d[1] ;
+   reg \in.v ;
+   wire \in.d.d[14].d[0] ;
+   reg \out.d.d[13].d[0] ;
+   wire \in.d.d[12].d[1] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[9].d[0] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[0].d[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test  (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
+endmodule
+

test/unit_tests/buffer_register_7/run/prsim.out

@@ -0,0 +1,417 @@
+b.b.f_buf_func[3].n1 b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.f_buf_func[5].n1 b.b.vc.ct.in[6] b.in.v b.b._flushB b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b.f_buf_func[6].n1 b.b.vc.OR2_tf[6]._y b.b.vc.ct.in[1] b.out_v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b.vc.ct.C3Els[1]._y b.b.t_buf_func[2].n1 b.b.t_buf_func[6].n1 b.b.vc.OR2_tf[0]._y b.b.vc.ct.in[3] b.b.t_buf_func[0].n1 b.flush b.b._in_v b.b.vc.ct.in[4] b.b.f_buf_func[4].n1 b.b.vc.ct.in[5] b.b.vc.OR2_tf[2]._y b.b.vc.ct.tmp[8] b.b.vc.ct.tmp[9] b.b.vc.ct.C2Els[0]._y b.b.t_buf_func[5].n1 b.b.vc.OR2_tf[4]._y b.b.vc.ct.in[2] b.b.vc.ct.tmp[7] b.b.vc.OR2_tf[5]._y b.b.vc.ct.in[0] b.b.vc.OR2_tf[3]._y b.b.in_v_buf._y b.b.vc.ct.C3Els[0]._y b.b.vc.ct.C2Els[1]._y 
+	     74426 b.out_v : 0
+	     74426 b.b.t_buf_func[6].n1 : 0
+	     74426 b.b.f_buf_func[6].n1 : 0
+	     74426 b.b.t_buf_func[5].n1 : 0
+	     74426 b.b.f_buf_func[0].n1 : 0
+	     74426 b.b.f_buf_func[5].n1 : 0
+	     74426 b.b.t_buf_func[4].n1 : 0
+	     74426 b.b.f_buf_func[2].n1 : 0
+	     74426 b.b.f_buf_func[4].n1 : 0
+	     74426 b.b.t_buf_func[3].n1 : 0
+	     74426 b.b.t_buf_func[1].n1 : 0
+	     74426 b.b.f_buf_func[3].n1 : 0
+	     74426 b.b.t_buf_func[2].n1 : 0
+	     74426 b.flush : 0
+	     74426 b.b.f_buf_func[1].n1 : 0
+	     74426 b.b.t_buf_func[0].n1 : 0
+	     74444 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
+	     74977 b.b.vc.OR2_tf[5]._y : 1  [by b.b.f_buf_func[5].n1:=0]
+	     75380 b.b.vc.OR2_tf[3]._y : 1  [by b.b.f_buf_func[3].n1:=0]
+	     75408 b.b.vc.OR2_tf[1]._y : 1  [by b.b.f_buf_func[1].n1:=0]
+	     75497 b.b.vc.OR2_tf[4]._y : 1  [by b.b.f_buf_func[4].n1:=0]
+	     75507 b.b.vc.OR2_tf[2]._y : 1  [by b.b.t_buf_func[2].n1:=0]
+	     76009 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	     78457 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	     78980 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	     80257 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	     96867 b.b.vc.OR2_tf[6]._y : 1  [by b.b.f_buf_func[6].n1:=0]
+	     96992 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	     97070 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	     97209 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[6]:=0]
+	     98846 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[1]:=0]
+	     98915 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    120281 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    120292 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[3]:=0]
+	    128896 b.b._flushB : 1  [by b.flush:=0]
+	    133555 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    172078 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    172282 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[8]:=0]
+	    172297 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    172298 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    172335 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+[] Set reset 0
+
+	    172335 Reset : 0
+	    173074 b._reset_B : 1  [by Reset:=0]
+	    173186 b.b.reset_buf._y : 0  [by b._reset_B:=1]
+	    173226 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
+	    173483 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
+	    173570 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]
+	    220586 b.b._reset : 0  [by b._reset_B:=1]
+[] Flushing data
+	    220586 b.flush : 1
+	    220880 b.b._flushB : 0  [by b.flush:=1]
+	    220881 b.b.t_buf_func[0]._y : 1  [by b.b._flushB:=0]
+	    221045 b.out.d[0].t : 0  [by b.b.t_buf_func[0]._y:=1]
+	    221058 b.b.t_buf_func[5]._y : 1  [by b.b._flushB:=0]
+	    221470 b.b.t_buf_func[4]._y : 1  [by b.b._flushB:=0]
+	    221492 b.out.d[4].t : 0  [by b.b.t_buf_func[4]._y:=1]
+	    221683 b.b.t_buf_func[6]._y : 1  [by b.b._flushB:=0]
+	    222089 b.b.t_buf_func[3]._y : 1  [by b.b._flushB:=0]
+	    222530 b.out.d[6].t : 0  [by b.b.t_buf_func[6]._y:=1]
+	    222686 b.b.t_buf_func[1]._y : 1  [by b.b._flushB:=0]
+	    222819 b.out.d[1].t : 0  [by b.b.t_buf_func[1]._y:=1]
+	    222887 b.b.t_buf_func[2]._y : 1  [by b.b._flushB:=0]
+	    223253 b.out.d[5].t : 0  [by b.b.t_buf_func[5]._y:=1]
+	    238549 b.out.d[2].t : 0  [by b.b.t_buf_func[2]._y:=1]
+	    252217 b.out.d[3].t : 0  [by b.b.t_buf_func[3]._y:=1]
+	    252217 b.flush : 0
+	    252576 b.b._flushB : 1  [by b.flush:=0]
+[] Sending in a 0
+	    252576 b.b.f_buf_func[0].n1 : 1
+	    252576 b.b.f_buf_func[6].n1 : 1
+	    252576 b.b.f_buf_func[2].n1 : 1
+	    252576 b.b.f_buf_func[5].n1 : 1
+	    252576 b.b.f_buf_func[1].n1 : 1
+	    252576 b.b.f_buf_func[4].n1 : 1
+	    252576 b.b.f_buf_func[3].n1 : 1
+	    252583 b.b.vc.OR2_tf[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    252583 b.b.vc.OR2_tf[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    252595 b.b.vc.ct.in[6] : 1  [by b.b.vc.OR2_tf[6]._y:=0]
+	    252606 b.b.f_buf_func[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    252654 b.b.f_buf_func[4]._y : 0  [by b.b.f_buf_func[4].n1:=1]
+	    252666 b.out.d[4].f : 1  [by b.b.f_buf_func[4]._y:=0]
+	    252667 b.b.vc.OR2_tf[5]._y : 0  [by b.b.f_buf_func[5].n1:=1]
+	    252682 b.b.vc.OR2_tf[4]._y : 0  [by b.b.f_buf_func[4].n1:=1]
+	    252797 b.b.f_buf_func[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    252851 b.b.vc.OR2_tf[3]._y : 0  [by b.b.f_buf_func[3].n1:=1]
+	    253010 b.out.d[6].f : 1  [by b.b.f_buf_func[6]._y:=0]
+	    253038 b.b.vc.ct.in[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    254765 b.b.f_buf_func[5]._y : 0  [by b.b.f_buf_func[5].n1:=1]
+	    254767 b.out.d[5].f : 1  [by b.b.f_buf_func[5]._y:=0]
+	    255363 b.b.f_buf_func[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    255696 b.out.d[0].f : 1  [by b.b.f_buf_func[0]._y:=0]
+	    256958 b.b.vc.ct.in[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    257146 b.b.vc.ct.in[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    258583 b.b.vc.ct.in[5] : 1  [by b.b.vc.OR2_tf[5]._y:=0]
+	    259289 b.b.vc.OR2_tf[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    259832 b.b.vc.ct.C3Els[0]._y : 0  [by b.b.vc.ct.in[5]:=1]
+	    259898 b.out.d[1].f : 1  [by b.b.f_buf_func[1]._y:=0]
+	    259998 b.b.vc.ct.tmp[9] : 1  [by b.b.vc.ct.C3Els[0]._y:=0]
+	    262788 b.b.vc.ct.in[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    262863 b.b.vc.ct.C2Els[1]._y : 0  [by b.b.vc.ct.in[2]:=1]
+	    263208 b.b.vc.ct.tmp[8] : 1  [by b.b.vc.ct.C2Els[1]._y:=0]
+	    266692 b.b.vc.OR2_tf[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    266830 b.b.vc.ct.in[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    271572 b.b.f_buf_func[3]._y : 0  [by b.b.f_buf_func[3].n1:=1]
+	    271574 b.out.d[3].f : 1  [by b.b.f_buf_func[3]._y:=0]
+	    272093 b.b.vc.ct.C2Els[0]._y : 0  [by b.b.vc.ct.in[0]:=1]
+	    310037 b.b.f_buf_func[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    310038 b.out.d[2].f : 1  [by b.b.f_buf_func[2]._y:=0]
+	    316010 b.b.vc.ct.tmp[7] : 1  [by b.b.vc.ct.C2Els[0]._y:=0]
+	    316558 b.b.vc.ct.C3Els[1]._y : 0  [by b.b.vc.ct.tmp[7]:=1]
+	    316569 b.b._in_v : 1  [by b.b.vc.ct.C3Els[1]._y:=0]
+	    316939 b.b.in_v_buf._y : 0  [by b.b._in_v:=1]
+	    317006 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+[] Sending in output valid
+	    317006 b.out_v : 1
+	    319647 b.b._en : 0  [by b.out_v:=1]
+	    319663 b.in.a : 1  [by b.b._en:=0]
+	    320175 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	    322610 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+	    324209 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	    351089 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+[] Removing input
+	    351089 b.b.f_buf_func[0].n1 : 0
+	    351089 b.b.f_buf_func[6].n1 : 0
+	    351089 b.b.f_buf_func[2].n1 : 0
+	    351089 b.b.f_buf_func[5].n1 : 0
+	    351089 b.b.f_buf_func[1].n1 : 0
+	    351089 b.b.f_buf_func[4].n1 : 0
+	    351089 b.b.f_buf_func[3].n1 : 0
+	    351091 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
+	    351092 b.b.vc.OR2_tf[1]._y : 1  [by b.b.f_buf_func[1].n1:=0]
+	    351118 b.b.vc.OR2_tf[4]._y : 1  [by b.b.f_buf_func[4].n1:=0]
+	    351162 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    351245 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    351406 b.b.vc.OR2_tf[3]._y : 1  [by b.b.f_buf_func[3].n1:=0]
+	    352692 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    354167 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    364130 b.b.vc.OR2_tf[6]._y : 1  [by b.b.f_buf_func[6].n1:=0]
+	    364131 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	    367850 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[3]:=0]
+	    368067 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    375014 b.b.vc.OR2_tf[0]._y : 1  [by b.b.f_buf_func[0].n1:=0]
+	    375036 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    375037 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[0]:=0]
+	    376618 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    412047 b.b.vc.OR2_tf[5]._y : 1  [by b.b.f_buf_func[5].n1:=0]
+	    421392 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	    421551 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[5]:=0]
+	    441227 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    442514 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[9]:=0]
+	    444746 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    444891 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    447723 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    454077 b.b._en : 1  [by b.in.v:=0]
+	    454078 b.in.a : 0  [by b.b._en:=1]
+	    454239 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	    461608 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+	    493361 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	    493375 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+[] Flushing data
+	    493375 b.flush : 1
+	    493382 b.b._flushB : 0  [by b.flush:=1]
+	    493383 b.b.f_buf_func[2]._y : 1  [by b.b._flushB:=0]
+	    493383 b.b.f_buf_func[3]._y : 1  [by b.b._flushB:=0]
+	    493383 b.b.f_buf_func[4]._y : 1  [by b.b._flushB:=0]
+	    493384 b.out.d[2].f : 0  [by b.b.f_buf_func[2]._y:=1]
+	    493542 b.b.f_buf_func[0]._y : 1  [by b.b._flushB:=0]
+	    493543 b.out.d[0].f : 0  [by b.b.f_buf_func[0]._y:=1]
+	    493569 b.b.f_buf_func[6]._y : 1  [by b.b._flushB:=0]
+	    494422 b.out.d[6].f : 0  [by b.b.f_buf_func[6]._y:=1]
+	    495625 b.b.f_buf_func[5]._y : 1  [by b.b._flushB:=0]
+	    495630 b.out.d[5].f : 0  [by b.b.f_buf_func[5]._y:=1]
+	    497565 b.out.d[3].f : 0  [by b.b.f_buf_func[3]._y:=1]
+	    514939 b.b.f_buf_func[1]._y : 1  [by b.b._flushB:=0]
+	    515830 b.out.d[1].f : 0  [by b.b.f_buf_func[1]._y:=1]
+	    528165 b.out.d[4].f : 0  [by b.b.f_buf_func[4]._y:=1]
+	    528165 b.out_v : 0
+	    528165 b.flush : 0
+	    528166 b.b._flushB : 1  [by b.flush:=0]
+[] Sending in a 127
+	    528166 b.b.t_buf_func[0].n1 : 1
+	    528166 b.b.t_buf_func[6].n1 : 1
+	    528166 b.b.t_buf_func[2].n1 : 1
+	    528166 b.b.t_buf_func[5].n1 : 1
+	    528166 b.b.t_buf_func[1].n1 : 1
+	    528166 b.b.t_buf_func[4].n1 : 1
+	    528166 b.b.t_buf_func[3].n1 : 1
+	    528167 b.b.vc.OR2_tf[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    528169 b.b.t_buf_func[6]._y : 0  [by b.b.t_buf_func[6].n1:=1]
+	    528174 b.b.vc.OR2_tf[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    528178 b.b.vc.ct.in[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    528183 b.b.vc.OR2_tf[0]._y : 0  [by b.b.t_buf_func[0].n1:=1]
+	    528200 b.b.t_buf_func[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    528208 b.b.t_buf_func[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    528261 b.b.vc.OR2_tf[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    528501 b.b.t_buf_func[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    528549 b.out.d[4].t : 1  [by b.b.t_buf_func[4]._y:=0]
+	    529087 b.out.d[6].t : 1  [by b.b.t_buf_func[6]._y:=0]
+	    529107 b.b.vc.OR2_tf[2]._y : 0  [by b.b.t_buf_func[2].n1:=1]
+	    529110 b.b.vc.ct.in[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    529288 b.b.vc.ct.C2Els[1]._y : 0  [by b.b.vc.ct.in[2]:=1]
+	    530598 b.out.d[3].t : 1  [by b.b.t_buf_func[3]._y:=0]
+	    530739 b.b.t_buf_func[0]._y : 0  [by b.b.t_buf_func[0].n1:=1]
+	    530983 b.b.vc.OR2_tf[1]._y : 0  [by b.b.t_buf_func[1].n1:=1]
+	    531423 b.out.d[5].t : 1  [by b.b.t_buf_func[5]._y:=0]
+	    536527 b.b.vc.OR2_tf[6]._y : 0  [by b.b.t_buf_func[6].n1:=1]
+	    536934 b.b.vc.ct.in[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    541899 b.b.t_buf_func[1]._y : 0  [by b.b.t_buf_func[1].n1:=1]
+	    542054 b.b.vc.ct.in[5] : 1  [by b.b.vc.OR2_tf[5]._y:=0]
+	    542638 b.out.d[0].t : 1  [by b.b.t_buf_func[0]._y:=0]
+	    542726 b.out.d[1].t : 1  [by b.b.t_buf_func[1]._y:=0]
+	    550265 b.b.vc.ct.tmp[8] : 1  [by b.b.vc.ct.C2Els[1]._y:=0]
+	    574561 b.b.vc.ct.in[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    574734 b.b.vc.ct.C2Els[0]._y : 0  [by b.b.vc.ct.in[0]:=1]
+	    574918 b.b.vc.ct.tmp[7] : 1  [by b.b.vc.ct.C2Els[0]._y:=0]
+	    575380 b.b.vc.ct.in[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    576012 b.b.vc.ct.in[6] : 1  [by b.b.vc.OR2_tf[6]._y:=0]
+	    576013 b.b.vc.ct.C3Els[0]._y : 0  [by b.b.vc.ct.in[6]:=1]
+	    576086 b.b.vc.ct.tmp[9] : 1  [by b.b.vc.ct.C3Els[0]._y:=0]
+	    576090 b.b.vc.ct.C3Els[1]._y : 0  [by b.b.vc.ct.tmp[9]:=1]
+	    587128 b.b.t_buf_func[2]._y : 0  [by b.b.t_buf_func[2].n1:=1]
+	    587224 b.out.d[2].t : 1  [by b.b.t_buf_func[2]._y:=0]
+	    613378 b.b._in_v : 1  [by b.b.vc.ct.C3Els[1]._y:=0]
+	    613514 b.b.in_v_buf._y : 0  [by b.b._in_v:=1]
+	    613515 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+[] Sending in output valid
+	    613515 b.out_v : 1
+	    632561 b.b._en : 0  [by b.out_v:=1]
+	    632573 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	    632802 b.in.a : 1  [by b.b._en:=0]
+	    636473 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+	    636520 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	    637549 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+[] Removing input
+	    637549 b.b.t_buf_func[0].n1 : 0
+	    637549 b.b.t_buf_func[6].n1 : 0
+	    637549 b.b.t_buf_func[2].n1 : 0
+	    637549 b.b.t_buf_func[5].n1 : 0
+	    637549 b.b.t_buf_func[1].n1 : 0
+	    637549 b.b.t_buf_func[4].n1 : 0
+	    637549 b.b.t_buf_func[3].n1 : 0
+	    637550 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
+	    637550 b.b.vc.OR2_tf[3]._y : 1  [by b.b.t_buf_func[3].n1:=0]
+	    637550 b.b.vc.OR2_tf[5]._y : 1  [by b.b.t_buf_func[5].n1:=0]
+	    637563 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	    637586 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
+	    637605 b.b.vc.OR2_tf[6]._y : 1  [by b.b.t_buf_func[6].n1:=0]
+	    637962 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	    639242 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    641114 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    654570 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    654595 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[1]:=0]
+	    654616 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    660924 b.b.vc.OR2_tf[4]._y : 1  [by b.b.t_buf_func[4].n1:=0]
+	    660925 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    670573 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[4]:=0]
+	    670574 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    682555 b.b.vc.OR2_tf[2]._y : 1  [by b.b.t_buf_func[2].n1:=0]
+	    682556 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    682717 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[2]:=0]
+	    683754 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    683759 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[8]:=0]
+	    684340 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    684748 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    684759 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    685806 b.b._en : 1  [by b.in.v:=0]
+	    685810 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	    685820 b.in.a : 0  [by b.b._en:=1]
+	    685824 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	    685914 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+	    717268 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+[] Flushing data
+	    717268 b.flush : 1
+	    718472 b.b._flushB : 0  [by b.flush:=1]
+	    718483 b.b.t_buf_func[6]._y : 1  [by b.b._flushB:=0]
+	    718486 b.out.d[6].t : 0  [by b.b.t_buf_func[6]._y:=1]
+	    718542 b.b.t_buf_func[4]._y : 1  [by b.b._flushB:=0]
+	    718596 b.out.d[4].t : 0  [by b.b.t_buf_func[4]._y:=1]
+	    718700 b.b.t_buf_func[1]._y : 1  [by b.b._flushB:=0]
+	    719315 b.b.t_buf_func[2]._y : 1  [by b.b._flushB:=0]
+	    719848 b.out.d[1].t : 0  [by b.b.t_buf_func[1]._y:=1]
+	    719931 b.b.t_buf_func[3]._y : 1  [by b.b._flushB:=0]
+	    720476 b.out.d[2].t : 0  [by b.b.t_buf_func[2]._y:=1]
+	    726927 b.b.t_buf_func[0]._y : 1  [by b.b._flushB:=0]
+	    727008 b.out.d[0].t : 0  [by b.b.t_buf_func[0]._y:=1]
+	    728583 b.out.d[3].t : 0  [by b.b.t_buf_func[3]._y:=1]
+	    768894 b.b.t_buf_func[5]._y : 1  [by b.b._flushB:=0]
+	    779971 b.out.d[5].t : 0  [by b.b.t_buf_func[5]._y:=1]
+	    779971 b.out_v : 0
+	    779971 b.flush : 0
+	    797954 b.b._flushB : 1  [by b.flush:=0]
+[] Sending in a 56
+	    797954 b.b.f_buf_func[0].n1 : 1
+	    797954 b.b.f_buf_func[6].n1 : 1
+	    797954 b.b.f_buf_func[2].n1 : 1
+	    797954 b.b.t_buf_func[5].n1 : 1
+	    797954 b.b.f_buf_func[1].n1 : 1
+	    797954 b.b.t_buf_func[4].n1 : 1
+	    797954 b.b.t_buf_func[3].n1 : 1
+	    797961 b.b.t_buf_func[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    797963 b.out.d[4].t : 1  [by b.b.t_buf_func[4]._y:=0]
+	    797999 b.b.f_buf_func[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    798006 b.b.vc.OR2_tf[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
+	    798046 b.b.vc.OR2_tf[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    798047 b.b.vc.ct.in[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
+	    798139 b.b.vc.ct.in[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
+	    798353 b.out.d[2].f : 1  [by b.b.f_buf_func[2]._y:=0]
+	    798479 b.b.vc.OR2_tf[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    798483 b.b.vc.ct.in[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
+	    798567 b.b.f_buf_func[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    798854 b.b.f_buf_func[1]._y : 0  [by b.b.f_buf_func[1].n1:=1]
+	    798855 b.out.d[1].f : 1  [by b.b.f_buf_func[1]._y:=0]
+	    798951 b.b.vc.OR2_tf[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    799029 b.b.vc.ct.C2Els[0]._y : 0  [by b.b.vc.ct.in[1]:=1]
+	    799108 b.b.vc.ct.tmp[7] : 1  [by b.b.vc.ct.C2Els[0]._y:=0]
+	    799603 b.b.t_buf_func[5]._y : 0  [by b.b.t_buf_func[5].n1:=1]
+	    799698 b.b.vc.OR2_tf[6]._y : 0  [by b.b.f_buf_func[6].n1:=1]
+	    799786 b.b.vc.ct.in[6] : 1  [by b.b.vc.OR2_tf[6]._y:=0]
+	    802036 b.out.d[5].t : 1  [by b.b.t_buf_func[5]._y:=0]
+	    804421 b.b.t_buf_func[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    806265 b.b.f_buf_func[0]._y : 0  [by b.b.f_buf_func[0].n1:=1]
+	    811329 b.b.vc.ct.in[5] : 1  [by b.b.vc.OR2_tf[5]._y:=0]
+	    811388 b.b.vc.ct.C3Els[0]._y : 0  [by b.b.vc.ct.in[5]:=1]
+	    811418 b.b.vc.ct.tmp[9] : 1  [by b.b.vc.ct.C3Els[0]._y:=0]
+	    811976 b.b.vc.OR2_tf[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
+	    812203 b.out.d[3].t : 1  [by b.b.t_buf_func[3]._y:=0]
+	    813443 b.b.vc.ct.in[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
+	    813566 b.b.vc.OR2_tf[3]._y : 0  [by b.b.t_buf_func[3].n1:=1]
+	    834592 b.out.d[0].f : 1  [by b.b.f_buf_func[0]._y:=0]
+	    844130 b.out.d[6].f : 1  [by b.b.f_buf_func[6]._y:=0]
+	    873070 b.b.vc.ct.in[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
+	    892454 b.b.vc.ct.C2Els[1]._y : 0  [by b.b.vc.ct.in[3]:=1]
+	    893139 b.b.vc.ct.tmp[8] : 1  [by b.b.vc.ct.C2Els[1]._y:=0]
+	    909854 b.b.vc.ct.C3Els[1]._y : 0  [by b.b.vc.ct.tmp[8]:=1]
+	    909981 b.b._in_v : 1  [by b.b.vc.ct.C3Els[1]._y:=0]
+	    910150 b.b.in_v_buf._y : 0  [by b.b._in_v:=1]
+	    910193 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+[] Sending in output valid
+	    910193 b.out_v : 1
+	    910205 b.b._en : 0  [by b.out_v:=1]
+	    910208 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
+	    910246 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
+	    910438 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
+	    910439 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
+	    911484 b.in.a : 1  [by b.b._en:=0]
+[] Removing input
+	    911484 b.b.f_buf_func[0].n1 : 0
+	    911484 b.b.f_buf_func[6].n1 : 0
+	    911484 b.b.f_buf_func[2].n1 : 0
+	    911484 b.b.t_buf_func[5].n1 : 0
+	    911484 b.b.f_buf_func[1].n1 : 0
+	    911484 b.b.t_buf_func[4].n1 : 0
+	    911484 b.b.t_buf_func[3].n1 : 0
+	    911485 b.b.vc.OR2_tf[1]._y : 1  [by b.b.f_buf_func[1].n1:=0]
+	    911486 b.b.vc.OR2_tf[3]._y : 1  [by b.b.t_buf_func[3].n1:=0]
+	    911486 b.b.vc.OR2_tf[5]._y : 1  [by b.b.t_buf_func[5].n1:=0]
+	    911503 b.b.vc.ct.in[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
+	    911576 b.b.vc.OR2_tf[6]._y : 1  [by b.b.f_buf_func[6].n1:=0]
+	    911584 b.b.vc.ct.in[6] : 0  [by b.b.vc.OR2_tf[6]._y:=1]
+	    911605 b.b.vc.ct.in[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
+	    912985 b.b.vc.OR2_tf[4]._y : 1  [by b.b.t_buf_func[4].n1:=0]
+	    913039 b.b.vc.ct.in[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
+	    914211 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
+	    917206 b.b.vc.ct.in[5] : 0  [by b.b.vc.OR2_tf[5]._y:=1]
+	    917211 b.b.vc.ct.C3Els[0]._y : 1  [by b.b.vc.ct.in[5]:=0]
+	    918278 b.b.vc.ct.tmp[9] : 0  [by b.b.vc.ct.C3Els[0]._y:=1]
+	    924236 b.b.vc.OR2_tf[0]._y : 1  [by b.b.f_buf_func[0].n1:=0]
+	    924237 b.b.vc.ct.in[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
+	    924375 b.b.vc.ct.C2Els[0]._y : 1  [by b.b.vc.ct.in[0]:=0]
+	    924376 b.b.vc.ct.tmp[7] : 0  [by b.b.vc.ct.C2Els[0]._y:=1]
+	    964749 b.b.vc.ct.in[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
+	    964813 b.b.vc.ct.C2Els[1]._y : 1  [by b.b.vc.ct.in[2]:=0]
+	    964936 b.b.vc.ct.tmp[8] : 0  [by b.b.vc.ct.C2Els[1]._y:=1]
+	    964938 b.b.vc.ct.C3Els[1]._y : 1  [by b.b.vc.ct.tmp[8]:=0]
+	    964975 b.b._in_v : 0  [by b.b.vc.ct.C3Els[1]._y:=1]
+	    965118 b.b.in_v_buf._y : 1  [by b.b._in_v:=0]
+	    965169 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    965611 b.b._en : 1  [by b.in.v:=0]
+	    965612 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
+	    965620 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
+	    965622 b.in.a : 0  [by b.b._en:=1]
+	    965637 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
+	    975873 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
+[] Resetting
+	    975873 Reset : 1
+	    979394 b._reset_B : 0  [by Reset:=1]
+	    979539 b.b.reset_buf._y : 1  [by b._reset_B:=0]
+	    979769 b.b._reset_BX : 0  [by b.b.reset_buf._y:=1]
+	    980460 b.b.reset_bufarray.buf2._y : 1  [by b.b._reset_BX:=0]
+	    980474 b.b._reset_BXX[0] : 0  [by b.b.reset_bufarray.buf2._y:=1]
+	    980485 b.b.f_buf_func[6]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    980486 b.out.d[6].f : 0  [by b.b.f_buf_func[6]._y:=1]
+	    982017 b.b.f_buf_func[0]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    982018 b.out.d[0].f : 0  [by b.b.f_buf_func[0]._y:=1]
+	    982085 b.b.f_buf_func[1]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    988586 b.out.d[1].f : 0  [by b.b.f_buf_func[1]._y:=1]
+	    995562 b.b._reset : 1  [by b._reset_B:=0]
+	    995563 b.b.t_buf_func[6]._y : 0  [by b.b._reset:=1]
+	    995580 b.out.d[6].t : 1  [by b.b.t_buf_func[6]._y:=0]
+	    995694 b.b.t_buf_func[2]._y : 0  [by b.b._reset:=1]
+	    995846 b.out.d[2].t : 1  [by b.b.t_buf_func[2]._y:=0]
+	    996201 b.b.t_buf_func[0]._y : 0  [by b.b._reset:=1]
+	    997355 b.b.t_buf_func[1]._y : 0  [by b.b._reset:=1]
+	    997358 b.out.d[1].t : 1  [by b.b.t_buf_func[1]._y:=0]
+	    997986 b.b.f_buf_func[2]._y : 1  [by b.b._reset_BXX[0]:=0]
+	    998410 b.out.d[2].f : 0  [by b.b.f_buf_func[2]._y:=1]
+	    999184 b.out.d[0].t : 1  [by b.b.t_buf_func[0]._y:=0]
+	    999184 Reset : 0
+	    999190 b._reset_B : 1  [by Reset:=0]
+	   1001651 b.b._reset : 0  [by b._reset_B:=1]
+	   1001778 b.b.reset_buf._y : 0  [by b._reset_B:=1]
+	   1002608 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
+	   1025540 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
+	   1025542 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]

test/unit_tests/buffer_register_7/run/test.prs

@@ -0,0 +1,746 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"Reset"->"b._reset_B"-
+~("Reset")->"b._reset_B"+
+= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
+= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
+= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
+= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
+= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
+= "b.b._en_X_f[5]" "b.b.en_buf_f.out[5]"
+= "b.b._en_X_f[6]" "b.b.en_buf_f.out[6]"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[6].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[5].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[4].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[3].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[2].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[1].n2"
+= "b.b._en_X_f[0]" "b.b.f_buf_func[0].n2"
+= "b.b._en_X_f[0]" "b.b._en_X_f[6]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[5]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
+= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
+"b.b.in_v_buf.a"->"b.b.in_v_buf._y"-
+~("b.b.in_v_buf.a")->"b.b.in_v_buf._y"+
+"b.b.in_v_buf._y"->"b.b.in_v_buf.y"-
+~("b.b.in_v_buf._y")->"b.b.in_v_buf.y"+
+"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
+~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
+"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
+~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
+= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
+= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[6]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[5]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
+= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
+= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
+= "b.b.flush" "b.b.flush_inv.a"
+~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl.y"+
+"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.n1"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl.y"-
+~"b.b.vc.ct.C2Els[0].c1"&~"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"+
+"b.b.vc.ct.C2Els[0].c1"&"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"-
+"b.b.vc.ct.C2Els[0]._y"->"b.b.vc.ct.C2Els[0].y"-
+~("b.b.vc.ct.C2Els[0]._y")->"b.b.vc.ct.C2Els[0].y"+
+~"b.b.vc.ct.C2Els[1].c1"&~"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"+
+"b.b.vc.ct.C2Els[1].c1"&"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"-
+"b.b.vc.ct.C2Els[1]._y"->"b.b.vc.ct.C2Els[1].y"-
+~("b.b.vc.ct.C2Els[1]._y")->"b.b.vc.ct.C2Els[1].y"+
+~"b.b.vc.ct.C3Els[0].c1"&~"b.b.vc.ct.C3Els[0].c2"&~"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"+
+"b.b.vc.ct.C3Els[0].c1"&"b.b.vc.ct.C3Els[0].c2"&"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"-
+"b.b.vc.ct.C3Els[0]._y"->"b.b.vc.ct.C3Els[0].y"-
+~("b.b.vc.ct.C3Els[0]._y")->"b.b.vc.ct.C3Els[0].y"+
+~"b.b.vc.ct.C3Els[1].c1"&~"b.b.vc.ct.C3Els[1].c2"&~"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"+
+"b.b.vc.ct.C3Els[1].c1"&"b.b.vc.ct.C3Els[1].c2"&"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"-
+"b.b.vc.ct.C3Els[1]._y"->"b.b.vc.ct.C3Els[1].y"-
+~("b.b.vc.ct.C3Els[1]._y")->"b.b.vc.ct.C3Els[1].y"+
+= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C3Els[1].c1"
+= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C2Els[0].y"
+= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C3Els[1].c2"
+= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C2Els[1].y"
+= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[1].c3"
+= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[0].y"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[1].vdd"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[0].vdd"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[1].vdd"
+= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[0].vdd"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[1].vss"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[0].vss"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[1].vss"
+= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[0].vss"
+= "b.b.vc.ct.in[0]" "b.b.vc.ct.C2Els[0].c1"
+= "b.b.vc.ct.in[0]" "b.b.vc.ct.tmp[0]"
+= "b.b.vc.ct.in[1]" "b.b.vc.ct.C2Els[0].c2"
+= "b.b.vc.ct.in[1]" "b.b.vc.ct.tmp[1]"
+= "b.b.vc.ct.in[2]" "b.b.vc.ct.C2Els[1].c1"
+= "b.b.vc.ct.in[2]" "b.b.vc.ct.tmp[2]"
+= "b.b.vc.ct.in[3]" "b.b.vc.ct.C2Els[1].c2"
+= "b.b.vc.ct.in[3]" "b.b.vc.ct.tmp[3]"
+= "b.b.vc.ct.in[4]" "b.b.vc.ct.C3Els[0].c1"
+= "b.b.vc.ct.in[4]" "b.b.vc.ct.tmp[4]"
+= "b.b.vc.ct.in[5]" "b.b.vc.ct.C3Els[0].c2"
+= "b.b.vc.ct.in[5]" "b.b.vc.ct.tmp[5]"
+= "b.b.vc.ct.in[6]" "b.b.vc.ct.C3Els[0].c3"
+= "b.b.vc.ct.in[6]" "b.b.vc.ct.tmp[6]"
+= "b.b.vc.ct.out" "b.b.vc.ct.C3Els[1].y"
+= "b.b.vc.ct.out" "b.b.vc.ct.tmp[10]"
+= "b.b.vc.ct.in[0]" "b.b.vc.OR2_tf[0].y"
+= "b.b.vc.ct.in[1]" "b.b.vc.OR2_tf[1].y"
+= "b.b.vc.ct.in[2]" "b.b.vc.OR2_tf[2].y"
+= "b.b.vc.ct.in[3]" "b.b.vc.OR2_tf[3].y"
+= "b.b.vc.ct.in[4]" "b.b.vc.OR2_tf[4].y"
+= "b.b.vc.ct.in[5]" "b.b.vc.OR2_tf[5].y"
+= "b.b.vc.ct.in[6]" "b.b.vc.OR2_tf[6].y"
+"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
+~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
+"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
+~("b.b.vc.OR2_tf[0]._y")->"b.b.vc.OR2_tf[0].y"+
+"b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b"->"b.b.vc.OR2_tf[1]._y"-
+~("b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b")->"b.b.vc.OR2_tf[1]._y"+
+"b.b.vc.OR2_tf[1]._y"->"b.b.vc.OR2_tf[1].y"-
+~("b.b.vc.OR2_tf[1]._y")->"b.b.vc.OR2_tf[1].y"+
+"b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b"->"b.b.vc.OR2_tf[2]._y"-
+~("b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b")->"b.b.vc.OR2_tf[2]._y"+
+"b.b.vc.OR2_tf[2]._y"->"b.b.vc.OR2_tf[2].y"-
+~("b.b.vc.OR2_tf[2]._y")->"b.b.vc.OR2_tf[2].y"+
+"b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b"->"b.b.vc.OR2_tf[3]._y"-
+~("b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b")->"b.b.vc.OR2_tf[3]._y"+
+"b.b.vc.OR2_tf[3]._y"->"b.b.vc.OR2_tf[3].y"-
+~("b.b.vc.OR2_tf[3]._y")->"b.b.vc.OR2_tf[3].y"+
+"b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b"->"b.b.vc.OR2_tf[4]._y"-
+~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
+"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
+~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
+"b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b"->"b.b.vc.OR2_tf[5]._y"-
+~("b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b")->"b.b.vc.OR2_tf[5]._y"+
+"b.b.vc.OR2_tf[5]._y"->"b.b.vc.OR2_tf[5].y"-
+~("b.b.vc.OR2_tf[5]._y")->"b.b.vc.OR2_tf[5].y"+
+"b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b"->"b.b.vc.OR2_tf[6]._y"-
+~("b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b")->"b.b.vc.OR2_tf[6]._y"+
+"b.b.vc.OR2_tf[6]._y"->"b.b.vc.OR2_tf[6].y"-
+~("b.b.vc.OR2_tf[6]._y")->"b.b.vc.OR2_tf[6].y"+
+= "b.b.vc.supply.vss" "b.b.vc.ct.supply.vss"
+= "b.b.vc.supply.vdd" "b.b.vc.ct.supply.vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[6].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[5].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
+= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[6].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[5].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
+= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
+= "b.b.vc.out" "b.b.vc.ct.out"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.OR2_tf[6].b"
+= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.OR2_tf[6].a"
+= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.OR2_tf[5].b"
+= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.OR2_tf[5].a"
+= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.OR2_tf[4].b"
+= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.OR2_tf[4].a"
+= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.OR2_tf[3].b"
+= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.OR2_tf[3].a"
+= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.OR2_tf[2].b"
+= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.OR2_tf[2].a"
+= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.OR2_tf[1].b"
+= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.OR2_tf[1].a"
+= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.OR2_tf[0].b"
+= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
+= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
+= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
+= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
+= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
+= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
+= "b.b.supply.vss" "b.b.vc.supply.vss"
+= "b.b.supply.vdd" "b.b.vc.supply.vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[6].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[6].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[5].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[5].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
+= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
+= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
+= "b.b.supply.vdd" "b.b.in_v_buf.vdd"
+= "b.b.supply.vdd" "b.b.reset_buf.vdd"
+= "b.b.supply.vdd" "b.b.inack_inv.vdd"
+= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
+= "b.b.supply.vss" "b.b.t_buf_func[6].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[6].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[5].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[5].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
+= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
+= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
+= "b.b.supply.vss" "b.b.in_v_buf.vss"
+= "b.b.supply.vss" "b.b.reset_buf.vss"
+= "b.b.supply.vss" "b.b.inack_inv.vss"
+= "b.b.supply.vss" "b.b.inack_ctl.vss"
+= "b.b._en" "b.b.en_buf_f.in"
+= "b.b._en" "b.b.en_buf_t.in"
+= "b.b._en" "b.b.inack_inv.a"
+= "b.b._en" "b.b.inack_ctl.y"
+= "b.b._en" "b.b.inack_ctl.c1"
+= "b.b._en" "b.b._in_aB"
+"b.b.reset_inv.a"->"b.b.reset_inv.y"-
+~("b.b.reset_inv.a")->"b.b.reset_inv.y"+
+= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
+= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
+= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
+= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
+= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
+= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
+= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
+= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
+= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
+= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
+= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
+= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
+= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
+= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
+= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
+= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
+= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
+= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
+= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
+= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
+= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
+= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
+= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
+= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
+= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
+= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
+= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
+= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
+= "b.b.out.d[6].d[0]" "b.b.f_buf_func[6].y"
+= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
+= "b.b.out.d[6].d[1]" "b.b.t_buf_func[6].y"
+= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
+= "b.b.out.d[5].d[0]" "b.b.f_buf_func[5].y"
+= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
+= "b.b.out.d[5].d[1]" "b.b.t_buf_func[5].y"
+= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
+= "b.b.out.d[4].d[0]" "b.b.f_buf_func[4].y"
+= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
+= "b.b.out.d[4].d[1]" "b.b.t_buf_func[4].y"
+= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
+= "b.b.out.d[3].d[0]" "b.b.f_buf_func[3].y"
+= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
+= "b.b.out.d[3].d[1]" "b.b.t_buf_func[3].y"
+= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
+= "b.b.out.d[2].d[0]" "b.b.f_buf_func[2].y"
+= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
+= "b.b.out.d[2].d[1]" "b.b.t_buf_func[2].y"
+= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
+= "b.b.out.d[1].d[0]" "b.b.f_buf_func[1].y"
+= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
+= "b.b.out.d[1].d[1]" "b.b.t_buf_func[1].y"
+= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
+= "b.b.out.d[0].d[0]" "b.b.f_buf_func[0].y"
+= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
+= "b.b.out.d[0].d[1]" "b.b.t_buf_func[0].y"
+= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[0].f" "b.b.vc.in.d[0].f"
+= "b.b.in.d.d[0].t" "b.b.vc.in.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.vc.in.d[0].d[0]"
+= "b.b.in.d.d[0].d[1]" "b.b.vc.in.d[0].d[1]"
+= "b.b.in.d.d[1].f" "b.b.vc.in.d[1].f"
+= "b.b.in.d.d[1].t" "b.b.vc.in.d[1].t"
+= "b.b.in.d.d[1].d[0]" "b.b.vc.in.d[1].d[0]"
+= "b.b.in.d.d[1].d[1]" "b.b.vc.in.d[1].d[1]"
+= "b.b.in.d.d[2].f" "b.b.vc.in.d[2].f"
+= "b.b.in.d.d[2].t" "b.b.vc.in.d[2].t"
+= "b.b.in.d.d[2].d[0]" "b.b.vc.in.d[2].d[0]"
+= "b.b.in.d.d[2].d[1]" "b.b.vc.in.d[2].d[1]"
+= "b.b.in.d.d[3].f" "b.b.vc.in.d[3].f"
+= "b.b.in.d.d[3].t" "b.b.vc.in.d[3].t"
+= "b.b.in.d.d[3].d[0]" "b.b.vc.in.d[3].d[0]"
+= "b.b.in.d.d[3].d[1]" "b.b.vc.in.d[3].d[1]"
+= "b.b.in.d.d[4].f" "b.b.vc.in.d[4].f"
+= "b.b.in.d.d[4].t" "b.b.vc.in.d[4].t"
+= "b.b.in.d.d[4].d[0]" "b.b.vc.in.d[4].d[0]"
+= "b.b.in.d.d[4].d[1]" "b.b.vc.in.d[4].d[1]"
+= "b.b.in.d.d[5].f" "b.b.vc.in.d[5].f"
+= "b.b.in.d.d[5].t" "b.b.vc.in.d[5].t"
+= "b.b.in.d.d[5].d[0]" "b.b.vc.in.d[5].d[0]"
+= "b.b.in.d.d[5].d[1]" "b.b.vc.in.d[5].d[1]"
+= "b.b.in.d.d[6].f" "b.b.vc.in.d[6].f"
+= "b.b.in.d.d[6].t" "b.b.vc.in.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.vc.in.d[6].d[0]"
+= "b.b.in.d.d[6].d[1]" "b.b.vc.in.d[6].d[1]"
+= "b.b.in.a" "b.b.inack_inv.y"
+= "b.b.in.v" "b.b.in_v_buf.y"
+= "b.b.in.v" "b.b.inack_ctl.c2"
+= "b.b.in.d.d[6].d[0]" "b.b.f_buf_func[6].n1"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.t_buf_func[6].n1"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.f_buf_func[5].n1"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.t_buf_func[5].n1"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.f_buf_func[4].n1"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.t_buf_func[4].n1"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.f_buf_func[3].n1"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.t_buf_func[3].n1"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.f_buf_func[2].n1"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.t_buf_func[2].n1"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.f_buf_func[1].n1"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.t_buf_func[1].n1"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.f_buf_func[0].n1"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.t_buf_func[0].n1"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+"b.b.inack_inv.a"->"b.b.inack_inv.y"-
+~("b.b.inack_inv.a")->"b.b.inack_inv.y"+
+= "b.b._in_v" "b.b.in_v_buf.a"
+= "b.b._in_v" "b.b.vc.out"
+"b.b.reset_buf.a"->"b.b.reset_buf._y"-
+~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
+"b.b.reset_buf._y"->"b.b.reset_buf.y"-
+~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
+"b.b.flush_inv.a"->"b.b.flush_inv.y"-
+~("b.b.flush_inv.a")->"b.b.flush_inv.y"+
+= "b.b._reset_BX" "b.b.reset_bufarray.in"
+= "b.b._reset_BX" "b.b.reset_buf.y"
+= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
+= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
+= "b.b.reset_B" "b.b.reset_buf.a"
+= "b.b.reset_B" "b.b.reset_inv.a"
+= "b.b._reset" "b.b.t_buf_func[6].sr"
+= "b.b._reset" "b.b.t_buf_func[6].pr"
+= "b.b._reset" "b.b.t_buf_func[5].sr"
+= "b.b._reset" "b.b.t_buf_func[5].pr"
+= "b.b._reset" "b.b.t_buf_func[4].sr"
+= "b.b._reset" "b.b.t_buf_func[4].pr"
+= "b.b._reset" "b.b.t_buf_func[3].sr"
+= "b.b._reset" "b.b.t_buf_func[3].pr"
+= "b.b._reset" "b.b.t_buf_func[2].sr"
+= "b.b._reset" "b.b.t_buf_func[2].pr"
+= "b.b._reset" "b.b.t_buf_func[1].sr"
+= "b.b._reset" "b.b.t_buf_func[1].pr"
+= "b.b._reset" "b.b.t_buf_func[0].sr"
+= "b.b._reset" "b.b.t_buf_func[0].pr"
+= "b.b._reset" "b.b.reset_inv.y"
+= "b.b._flushB" "b.b.t_buf_func[6].c1"
+= "b.b._flushB" "b.b.f_buf_func[6].c1"
+= "b.b._flushB" "b.b.t_buf_func[5].c1"
+= "b.b._flushB" "b.b.f_buf_func[5].c1"
+= "b.b._flushB" "b.b.t_buf_func[4].c1"
+= "b.b._flushB" "b.b.f_buf_func[4].c1"
+= "b.b._flushB" "b.b.t_buf_func[3].c1"
+= "b.b._flushB" "b.b.f_buf_func[3].c1"
+= "b.b._flushB" "b.b.t_buf_func[2].c1"
+= "b.b._flushB" "b.b.f_buf_func[2].c1"
+= "b.b._flushB" "b.b.t_buf_func[1].c1"
+= "b.b._flushB" "b.b.f_buf_func[1].c1"
+= "b.b._flushB" "b.b.t_buf_func[0].c1"
+= "b.b._flushB" "b.b.f_buf_func[0].c1"
+= "b.b._flushB" "b.b.flush_inv.y"
+"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
+~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
+"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
+~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
+= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
+= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[6]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[5]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
+= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
+= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
+"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
+~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
+"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
+~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
+= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
+= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[6]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[5]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
+= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
+= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
+= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
+= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
+= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
+= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
+= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
+= "b.b._reset_BXX[5]" "b.b.reset_bufarray.out[5]"
+= "b.b._reset_BXX[6]" "b.b.reset_bufarray.out[6]"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
+= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[6]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[5]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
+= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
+~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].sr"->"b.b.t_buf_func[0]._y"+
+"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"|"b.b.t_buf_func[0].pr"->"b.b.t_buf_func[0]._y"-
+"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
+~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
+~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].sr"->"b.b.t_buf_func[1]._y"+
+"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"|"b.b.t_buf_func[1].pr"->"b.b.t_buf_func[1]._y"-
+"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
+~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
+~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].sr"->"b.b.t_buf_func[2]._y"+
+"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"|"b.b.t_buf_func[2].pr"->"b.b.t_buf_func[2]._y"-
+"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
+~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
+~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].sr"->"b.b.t_buf_func[3]._y"+
+"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"|"b.b.t_buf_func[3].pr"->"b.b.t_buf_func[3]._y"-
+"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
+~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
+~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].sr"->"b.b.t_buf_func[4]._y"+
+"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"|"b.b.t_buf_func[4].pr"->"b.b.t_buf_func[4]._y"-
+"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
+~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
+~"b.b.t_buf_func[5].c1"&~"b.b.t_buf_func[5].sr"->"b.b.t_buf_func[5]._y"+
+"b.b.t_buf_func[5].c1"&"b.b.t_buf_func[5].n1"&"b.b.t_buf_func[5].n2"|"b.b.t_buf_func[5].pr"->"b.b.t_buf_func[5]._y"-
+"b.b.t_buf_func[5]._y"->"b.b.t_buf_func[5].y"-
+~("b.b.t_buf_func[5]._y")->"b.b.t_buf_func[5].y"+
+~"b.b.t_buf_func[6].c1"&~"b.b.t_buf_func[6].sr"->"b.b.t_buf_func[6]._y"+
+"b.b.t_buf_func[6].c1"&"b.b.t_buf_func[6].n1"&"b.b.t_buf_func[6].n2"|"b.b.t_buf_func[6].pr"->"b.b.t_buf_func[6]._y"-
+"b.b.t_buf_func[6]._y"->"b.b.t_buf_func[6].y"-
+~("b.b.t_buf_func[6]._y")->"b.b.t_buf_func[6].y"+
+~"b.b.f_buf_func[0].c1"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
+"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
+"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
+~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
+~"b.b.f_buf_func[1].c1"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
+"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
+"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
+~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
+~"b.b.f_buf_func[2].c1"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
+"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
+"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
+~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
+~"b.b.f_buf_func[3].c1"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
+"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
+"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
+~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
+~"b.b.f_buf_func[4].c1"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
+"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
+"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
+~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
+~"b.b.f_buf_func[5].c1"|~"b.b.f_buf_func[5].pr_B"->"b.b.f_buf_func[5]._y"+
+"b.b.f_buf_func[5].c1"&"b.b.f_buf_func[5].n1"&"b.b.f_buf_func[5].n2"&"b.b.f_buf_func[5].sr_B"->"b.b.f_buf_func[5]._y"-
+"b.b.f_buf_func[5]._y"->"b.b.f_buf_func[5].y"-
+~("b.b.f_buf_func[5]._y")->"b.b.f_buf_func[5].y"+
+~"b.b.f_buf_func[6].c1"|~"b.b.f_buf_func[6].pr_B"->"b.b.f_buf_func[6]._y"+
+"b.b.f_buf_func[6].c1"&"b.b.f_buf_func[6].n1"&"b.b.f_buf_func[6].n2"&"b.b.f_buf_func[6].sr_B"->"b.b.f_buf_func[6]._y"-
+"b.b.f_buf_func[6]._y"->"b.b.f_buf_func[6].y"-
+~("b.b.f_buf_func[6]._y")->"b.b.f_buf_func[6].y"+
+= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
+= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
+= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
+= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
+= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
+= "b.b._en_X_t[5]" "b.b.en_buf_t.out[5]"
+= "b.b._en_X_t[6]" "b.b.en_buf_t.out[6]"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[6].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[5].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[4].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[3].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[2].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[1].n2"
+= "b.b._en_X_t[0]" "b.b.t_buf_func[0].n2"
+= "b.b._en_X_t[0]" "b.b._en_X_t[6]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[5]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
+= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
+= "b.b.out_v" "b.b.inack_ctl.n1"
+= "b._reset_B" "b.b.reset_B"
+= "b.flush" "b.b.flush"
+= "Vdd" "b.supply.vdd"
+= "GND" "b.supply.vss"
+= "b.out_v" "b.b.out_v"
+= "b.out.d[0].d[0]" "b.out.d[0].f"
+= "b.out.d[0].d[1]" "b.out.d[0].t"
+= "b.out.d[1].d[0]" "b.out.d[1].f"
+= "b.out.d[1].d[1]" "b.out.d[1].t"
+= "b.out.d[2].d[0]" "b.out.d[2].f"
+= "b.out.d[2].d[1]" "b.out.d[2].t"
+= "b.out.d[3].d[0]" "b.out.d[3].f"
+= "b.out.d[3].d[1]" "b.out.d[3].t"
+= "b.out.d[4].d[0]" "b.out.d[4].f"
+= "b.out.d[4].d[1]" "b.out.d[4].t"
+= "b.out.d[5].d[0]" "b.out.d[5].f"
+= "b.out.d[5].d[1]" "b.out.d[5].t"
+= "b.out.d[6].d[0]" "b.out.d[6].f"
+= "b.out.d[6].d[1]" "b.out.d[6].t"
+= "b.out.d[6].d[0]" "b.out.d[6].f"
+= "b.out.d[6].d[1]" "b.out.d[6].t"
+= "b.out.d[5].d[0]" "b.out.d[5].f"
+= "b.out.d[5].d[1]" "b.out.d[5].t"
+= "b.out.d[4].d[0]" "b.out.d[4].f"
+= "b.out.d[4].d[1]" "b.out.d[4].t"
+= "b.out.d[3].d[0]" "b.out.d[3].f"
+= "b.out.d[3].d[1]" "b.out.d[3].t"
+= "b.out.d[2].d[0]" "b.out.d[2].f"
+= "b.out.d[2].d[1]" "b.out.d[2].t"
+= "b.out.d[1].d[0]" "b.out.d[1].f"
+= "b.out.d[1].d[1]" "b.out.d[1].t"
+= "b.out.d[0].d[0]" "b.out.d[0].f"
+= "b.out.d[0].d[1]" "b.out.d[0].t"
+= "b.out.d[0].f" "b.b.out.d[0].f"
+= "b.out.d[0].t" "b.b.out.d[0].t"
+= "b.out.d[0].d[0]" "b.b.out.d[0].d[0]"
+= "b.out.d[0].d[1]" "b.b.out.d[0].d[1]"
+= "b.out.d[1].f" "b.b.out.d[1].f"
+= "b.out.d[1].t" "b.b.out.d[1].t"
+= "b.out.d[1].d[0]" "b.b.out.d[1].d[0]"
+= "b.out.d[1].d[1]" "b.b.out.d[1].d[1]"
+= "b.out.d[2].f" "b.b.out.d[2].f"
+= "b.out.d[2].t" "b.b.out.d[2].t"
+= "b.out.d[2].d[0]" "b.b.out.d[2].d[0]"
+= "b.out.d[2].d[1]" "b.b.out.d[2].d[1]"
+= "b.out.d[3].f" "b.b.out.d[3].f"
+= "b.out.d[3].t" "b.b.out.d[3].t"
+= "b.out.d[3].d[0]" "b.b.out.d[3].d[0]"
+= "b.out.d[3].d[1]" "b.b.out.d[3].d[1]"
+= "b.out.d[4].f" "b.b.out.d[4].f"
+= "b.out.d[4].t" "b.b.out.d[4].t"
+= "b.out.d[4].d[0]" "b.b.out.d[4].d[0]"
+= "b.out.d[4].d[1]" "b.b.out.d[4].d[1]"
+= "b.out.d[5].f" "b.b.out.d[5].f"
+= "b.out.d[5].t" "b.b.out.d[5].t"
+= "b.out.d[5].d[0]" "b.b.out.d[5].d[0]"
+= "b.out.d[5].d[1]" "b.b.out.d[5].d[1]"
+= "b.out.d[6].f" "b.b.out.d[6].f"
+= "b.out.d[6].t" "b.b.out.d[6].t"
+= "b.out.d[6].d[0]" "b.b.out.d[6].d[0]"
+= "b.out.d[6].d[1]" "b.b.out.d[6].d[1]"
+= "b.out.d[6].d[0]" "b.out.d[6].f"
+= "b.out.d[6].d[1]" "b.out.d[6].t"
+= "b.out.d[5].d[0]" "b.out.d[5].f"
+= "b.out.d[5].d[1]" "b.out.d[5].t"
+= "b.out.d[4].d[0]" "b.out.d[4].f"
+= "b.out.d[4].d[1]" "b.out.d[4].t"
+= "b.out.d[3].d[0]" "b.out.d[3].f"
+= "b.out.d[3].d[1]" "b.out.d[3].t"
+= "b.out.d[2].d[0]" "b.out.d[2].f"
+= "b.out.d[2].d[1]" "b.out.d[2].t"
+= "b.out.d[1].d[0]" "b.out.d[1].f"
+= "b.out.d[1].d[1]" "b.out.d[1].t"
+= "b.out.d[0].d[0]" "b.out.d[0].f"
+= "b.out.d[0].d[1]" "b.out.d[0].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.v" "b.b.in.v"
+= "b.in.a" "b.b.in.a"
+= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
+= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
+= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
+= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
+= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
+= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
+= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
+= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
+= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
+= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
+= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
+= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
+= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
+= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
+= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
+= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
+= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
+= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
+= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
+= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
+= "b.in.d.d[5].f" "b.b.in.d.d[5].f"
+= "b.in.d.d[5].t" "b.b.in.d.d[5].t"
+= "b.in.d.d[5].d[0]" "b.b.in.d.d[5].d[0]"
+= "b.in.d.d[5].d[1]" "b.b.in.d.d[5].d[1]"
+= "b.in.d.d[6].f" "b.b.in.d.d[6].f"
+= "b.in.d.d[6].t" "b.b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.b.in.d.d[6].d[0]"
+= "b.in.d.d[6].d[1]" "b.b.in.d.d[6].d[1]"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

test/unit_tests/buffer_register_7/test.act

@@ -0,0 +1,52 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc buffer_register_7 (avMx1of2<7> in; Mx1of2<7> out; bool? out_v, flush){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    buffer_register<7> b(.in = in, .out = out, .out_v = out_v, .flush = flush, .reset_B = _reset_B);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+buffer_register_7 b;

test/unit_tests/buffer_register_7/test.prsim

@@ -0,0 +1,163 @@
+watchall
+
+set b.out_v 0
+set b.flush 0
+set-qdi-channel-neutral "b.in" 7
+
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+
+system "echo '[] Flushing data'"
+set b.flush 1
+cycle
+assert b.out.d[0].t 0
+assert b.out.d[1].t 0
+assert b.out.d[2].t 0
+assert b.out.d[3].t 0
+assert b.out.d[4].t 0
+assert b.out.d[5].t 0
+assert b.out.d[6].t 0
+assert b.out.d[0].f 0
+assert b.out.d[1].f 0
+assert b.out.d[2].f 0
+assert b.out.d[3].f 0
+assert b.out.d[4].f 0
+assert b.out.d[5].f 0
+assert b.out.d[6].f 0
+set b.out_v 0
+set b.flush 0
+cycle
+
+system "echo '[] Sending in a 0'"
+set-qdi-channel-valid "b.in" 7 0
+cycle
+# assert-qdi-channel-valid 'b.out' 7 127
+assert b.in.a 0
+assert b.in.v 1
+assert-var-int "b.out" 7 0
+
+system "echo '[] Sending in output valid'"
+set b.out_v 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 0
+
+
+system "echo '[] Flushing data'"
+set b.flush 1
+cycle
+assert b.out.d[0].t 0
+assert b.out.d[1].t 0
+assert b.out.d[2].t 0
+assert b.out.d[3].t 0
+assert b.out.d[4].t 0
+assert b.out.d[5].t 0
+assert b.out.d[6].t 0
+assert b.out.d[0].f 0
+assert b.out.d[1].f 0
+assert b.out.d[2].f 0
+assert b.out.d[3].f 0
+assert b.out.d[4].f 0
+assert b.out.d[5].f 0
+assert b.out.d[6].f 0
+set b.out_v 0
+cycle
+set b.flush 0
+cycle
+
+
+system "echo '[] Sending in a 127'"
+set-qdi-channel-valid "b.in" 7 127
+cycle
+# assert-qdi-channel-valid 'b.out' 7 127
+assert b.in.a 0
+assert b.in.v 1
+assert-var-int "b.out" 7 127
+
+system "echo '[] Sending in output valid'"
+set b.out_v 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 127
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 127
+
+
+
+
+system "echo '[] Flushing data'"
+set b.flush 1
+cycle
+assert b.out.d[0].t 0
+assert b.out.d[1].t 0
+assert b.out.d[2].t 0
+assert b.out.d[3].t 0
+assert b.out.d[4].t 0
+assert b.out.d[5].t 0
+assert b.out.d[6].t 0
+assert b.out.d[0].f 0
+assert b.out.d[1].f 0
+assert b.out.d[2].f 0
+assert b.out.d[3].f 0
+assert b.out.d[4].f 0
+assert b.out.d[5].f 0
+assert b.out.d[6].f 0
+set b.out_v 0
+cycle
+set b.flush 0
+cycle
+
+
+
+
+system "echo '[] Sending in a 56'"
+set-qdi-channel-valid "b.in" 7 56
+cycle
+assert b.in.a 0
+assert b.in.v 1
+assert-var-int "b.out" 7 56
+
+system "echo '[] Sending in output valid'"
+set b.out_v 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.out" 7 56
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.out" 7 56
+
+system "echo '[] Resetting'"
+set Reset 1
+cycle
+assert-var-int "b.out" 7 127
+set Reset 0
+cycle
+assert-var-int "b.out" 7 127

test/unit_tests/decoder_2d_dly_8_16/test.prsim

@@ -7,8 +7,8 @@ set Reset 0
 # Set delay config lines
 set b.dly_cfg[0] 1
 set b.dly_cfg[1] 1
-set b.dly_cfg[2] 0
-set b.dly_cfg[3] 0
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
 
 cycle
 

test/unit_tests/decoder_2d_dly_and_2_4/run/prsim.out

@@ -1,351 +0,0 @@
-t.de.dly.dly[2].y t.de.dly.dly[4].y t.de.addr_buf._in_v t.de.dly._a[2] t.in.d.d[1].f t.de.dly.mu2[3].b t.de.dly.dly[3].y t.de.dly.dly[7].y t.de.dly.dly[3].___y t.in.d.d[0].t t.dly_cfg[1] t.de.dly.dly[13].__y t.de.dly.dly[1]._y t.de.dly.dly[13]._y t.de.addr_buf._out_a_BX_t[0] t.de.dly.dly[7].a t.de.dly.mu2[3]._y t.de.dly.dly[3].a t.in.d.d[0].f t.de.dly.dly[5]._y t.de.dly.dly[7].__y t.de.addr_buf._out_a_B t.de.dly.dly[3].__y t.dly_cfg[2] t.de.dly.dly[2].__y t.de.dly.dly[8].___y t.de.addr_buf._out_a_BX_f[0] t.de.addr_buf.vc.ct.in[0] t.de.dly.dly[13].___y t.de.dly.dly[1].a t.in.d.d[1].t t.in.v t.de.dly.dly[5].__y t.in.d.d[2].t t.de.addr_buf.in_v_buf._y t.de.dly.dly[9].y t.dly_cfg[0] t.in.d.d[2].f t.de.dly.out t.de.dly.mu2[2]._y t.dly_cfg[3] t.de.dly.dly[10]._y t.de.dly.dly[9].__y t.de.dly.and2[3]._y t.de.dly._a[3] t.de.addr_buf.vc.OR2_tf[1]._y t.de.addr_buf.vc.ct.in[2] t.de.dly.dly[5].y t.de.dly.dly[11].___y t.de.dly.dly[4].__y t.de.dly.and2[1]._y t.de.dly.dly[6].___y t.de.dly.dly[10].y t.de.dly.dly[11]._y t.de.dly.dly[10].__y t.de.dly.dly[12].__y t.de.dly.dly[1].__y t.de.addr_buf.vc.ct.in[1] t.de.addr_buf.out_a_B_buf_f.buf1._y t.de.dly._a[1] t.de.dly.dly[14].__y t.de.dly.dly[6].y t.de.dly.dly[11].y t.de.dly.dly[7]._y t.de.addr_buf.vc.ct.C3Els[0]._y t.de.dly.mu2[1]._y t.de.dly.dly[9]._y t.de.dly.dly[5].___y t.de.dly.dly[14]._y t.de.dly.and2[2]._y t.de.dly.dly[8].y t.de.dly.dly[9].___y t.de.dly.mu2[0]._s t.de.dly.mu2[1]._s t.de.dly.dly[2]._y t.de.dly.dly[8].__y t.de.dly.dly[12].___y t.de.dly.dly[13].y t.de.dly.dly[10].___y t.de.dly.dly[1].y t.de.dly.dly[1].___y t.de.dly.dly[2].___y t.de.addr_buf.out_a_B_buf_t.buf1._y t.de.dly.dly[4]._y t.de.dly.dly[8]._y t.de.dly.dly[4].___y t.de.dly.dly[12].y t.de.dly.dly[6].__y t.de.dly.dly[7].___y t.de.addr_buf.vc.OR2_tf[2]._y t.de.dly.dly[3]._y t.de.dly.dly[14].___y t.de.dly.mu2[3]._s t.de.dly.dly[11].__y t.de.dly.dly[6]._y t.de.addr_buf.vc.OR2_tf[0]._y t.de.dly.mu2[2]._s t.de.dly.mu2[0]._y t.de.dly.dly[12]._y 
-	    244317 t.in.d.d[0].f : 0
-	    244317 t.dly_cfg[3] : 1
-	    244317 t.dly_cfg[2] : 1
-	    244317 t.in.d.d[1].f : 0
-	    244317 Reset : 0
-	    244317 t.dly_cfg[1] : 1
-	    244317 t.in.d.d[2].t : 0
-	    244317 t.in.d.d[0].t : 0
-	    244317 t.dly_cfg[0] : 1
-	    244317 t.in.d.d[2].f : 0
-	    244317 t.in.d.d[1].t : 0
-	    244318 t._reset_B : 1  [by Reset:=0]
-	    244404 t.de.dly.mu2[3]._s : 0  [by t.dly_cfg[3]:=1]
-	    244495 t.de.addr_buf.vc.OR2_tf[1]._y : 1  [by t.in.d.d[1].t:=0]
-	    244611 t.de.dly.mu2[2]._s : 0  [by t.dly_cfg[2]:=1]
-	    244659 t.de.addr_buf.vc.ct.in[1] : 0  [by t.de.addr_buf.vc.OR2_tf[1]._y:=1]
-	    244907 t.de.addr_buf.vc.OR2_tf[2]._y : 1  [by t.in.d.d[2].f:=0]
-	    245121 t.de.addr_buf.reset_buf._y : 0  [by t._reset_B:=1]
-	    245143 t.de.addr_buf._reset_BX : 1  [by t.de.addr_buf.reset_buf._y:=0]
-	    245526 t.de.dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
-	    245990 t.de.addr_buf.reset_bufarray.buf1._y : 0  [by t.de.addr_buf._reset_BX:=1]
-	    246123 t.de.dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
-	    246123 t.de.addr_buf._reset_BXX[0] : 1  [by t.de.addr_buf.reset_bufarray.buf1._y:=0]
-	    246324 t.de.addr_buf.vc.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
-	    247102 t.de.addr_buf.vc.ct.in[2] : 0  [by t.de.addr_buf.vc.OR2_tf[2]._y:=1]
-	    261986 t.de.addr_buf.vc.ct.in[0] : 0  [by t.de.addr_buf.vc.OR2_tf[0]._y:=1]
-	    262345 t.de.addr_buf.vc.ct.C3Els[0]._y : 1  [by t.de.addr_buf.vc.ct.in[0]:=0]
-	    275654 t.de.dly.mu2[0]._y : 1  [by t.de.dly.mu2[0]._s:=0]
-	    275875 t.de.dly._a[1] : 0  [by t.de.dly.mu2[0]._y:=1]
-	    275882 t.de.dly.and2[1]._y : 1  [by t.de.dly._a[1]:=0]
-	    275912 t.de.dly.dly[1].a : 0  [by t.de.dly.and2[1]._y:=1]
-	    276461 t.de.addr_buf._in_v : 0  [by t.de.addr_buf.vc.ct.C3Els[0]._y:=1]
-	    282625 t.de.dly.dly[1]._y : 1  [by t.de.dly.dly[1].a:=0]
-	    282716 t.de.dly.dly[1].__y : 0  [by t.de.dly.dly[1]._y:=1]
-	    284905 t.de.dly.dly[1].___y : 1  [by t.de.dly.dly[1].__y:=0]
-	    284912 t.de.dly.dly[1].y : 0  [by t.de.dly.dly[1].___y:=1]
-	    287699 t.de.dly.dly[2]._y : 1  [by t.de.dly.dly[1].y:=0]
-	    287805 t.de.dly.dly[2].__y : 0  [by t.de.dly.dly[2]._y:=1]
-	    287883 t.de.dly.dly[2].___y : 1  [by t.de.dly.dly[2].__y:=0]
-	    288158 t.de.dly.dly[2].y : 0  [by t.de.dly.dly[2].___y:=1]
-	    307154 t.de.dly.mu2[1]._y : 1  [by t.de.dly.dly[2].y:=0]
-	    307609 t.de.dly._a[2] : 0  [by t.de.dly.mu2[1]._y:=1]
-	    307621 t.de.dly.and2[2]._y : 1  [by t.de.dly._a[2]:=0]
-	    308025 t.de.dly.dly[3].a : 0  [by t.de.dly.and2[2]._y:=1]
-	    308037 t.de.dly.dly[3]._y : 1  [by t.de.dly.dly[3].a:=0]
-	    313953 t.de.dly.dly[3].__y : 0  [by t.de.dly.dly[3]._y:=1]
-	    318229 t.de.dly.dly[3].___y : 1  [by t.de.dly.dly[3].__y:=0]
-	    321128 t.de.dly.dly[3].y : 0  [by t.de.dly.dly[3].___y:=1]
-	    325423 t.de.dly.dly[4]._y : 1  [by t.de.dly.dly[3].y:=0]
-	    325425 t.de.dly.dly[4].__y : 0  [by t.de.dly.dly[4]._y:=1]
-	    329960 t.de.dly.dly[4].___y : 1  [by t.de.dly.dly[4].__y:=0]
-	    331209 t.de.dly.dly[4].y : 0  [by t.de.dly.dly[4].___y:=1]
-	    333922 t.de.addr_buf.in_v_buf._y : 1  [by t.de.addr_buf._in_v:=0]
-	    334088 t.in.v : 0  [by t.de.addr_buf.in_v_buf._y:=1]
-	    334708 t.de.dly.dly[5]._y : 1  [by t.de.dly.dly[4].y:=0]
-	    334783 t.de.dly.dly[5].__y : 0  [by t.de.dly.dly[5]._y:=1]
-	    335128 t.de.dly.dly[5].___y : 1  [by t.de.dly.dly[5].__y:=0]
-	    335266 t.de.dly.dly[5].y : 0  [by t.de.dly.dly[5].___y:=1]
-	    340529 t.de.dly.dly[6]._y : 1  [by t.de.dly.dly[5].y:=0]
-	    340531 t.de.dly.dly[6].__y : 0  [by t.de.dly.dly[6]._y:=1]
-	    384448 t.de.dly.dly[6].___y : 1  [by t.de.dly.dly[6].__y:=0]
-	    384449 t.de.dly.dly[6].y : 0  [by t.de.dly.dly[6].___y:=1]
-	    384997 t.de.dly.mu2[2]._y : 1  [by t.de.dly.dly[6].y:=0]
-	    385008 t.de.dly._a[3] : 0  [by t.de.dly.mu2[2]._y:=1]
-	    385378 t.de.dly.and2[3]._y : 1  [by t.de.dly._a[3]:=0]
-	    385445 t.de.dly.dly[7].a : 0  [by t.de.dly.and2[3]._y:=1]
-	    388086 t.de.dly.dly[7]._y : 1  [by t.de.dly.dly[7].a:=0]
-	    388102 t.de.dly.dly[7].__y : 0  [by t.de.dly.dly[7]._y:=1]
-	    392664 t.de.dly.dly[7].___y : 1  [by t.de.dly.dly[7].__y:=0]
-	    393192 t.de.dly.dly[7].y : 0  [by t.de.dly.dly[7].___y:=1]
-	    395627 t.de.dly.dly[8]._y : 1  [by t.de.dly.dly[7].y:=0]
-	    422507 t.de.dly.dly[8].__y : 0  [by t.de.dly.dly[8]._y:=1]
-	    446432 t.de.dly.dly[8].___y : 1  [by t.de.dly.dly[8].__y:=0]
-	    459473 t.de.dly.dly[8].y : 0  [by t.de.dly.dly[8].___y:=1]
-	    459475 t.de.dly.dly[9]._y : 1  [by t.de.dly.dly[8].y:=0]
-	    520433 t.de.dly.dly[9].__y : 0  [by t.de.dly.dly[9]._y:=1]
-	    520436 t.de.dly.dly[9].___y : 1  [by t.de.dly.dly[9].__y:=0]
-	    520465 t.de.dly.dly[9].y : 0  [by t.de.dly.dly[9].___y:=1]
-	    520782 t.de.dly.dly[10]._y : 1  [by t.de.dly.dly[9].y:=0]
-	    522383 t.de.dly.dly[10].__y : 0  [by t.de.dly.dly[10]._y:=1]
-	    522536 t.de.dly.dly[10].___y : 1  [by t.de.dly.dly[10].__y:=0]
-	    522580 t.de.dly.dly[10].y : 0  [by t.de.dly.dly[10].___y:=1]
-	    525341 t.de.dly.dly[11]._y : 1  [by t.de.dly.dly[10].y:=0]
-	    539024 t.de.dly.dly[11].__y : 0  [by t.de.dly.dly[11]._y:=1]
-	    539025 t.de.dly.dly[11].___y : 1  [by t.de.dly.dly[11].__y:=0]
-	    539242 t.de.dly.dly[11].y : 0  [by t.de.dly.dly[11].___y:=1]
-	    539264 t.de.dly.dly[12]._y : 1  [by t.de.dly.dly[11].y:=0]
-	    539265 t.de.dly.dly[12].__y : 0  [by t.de.dly.dly[12]._y:=1]
-	    540846 t.de.dly.dly[12].___y : 1  [by t.de.dly.dly[12].__y:=0]
-	    550191 t.de.dly.dly[12].y : 0  [by t.de.dly.dly[12].___y:=1]
-	    550350 t.de.dly.dly[13]._y : 1  [by t.de.dly.dly[12].y:=0]
-	    570026 t.de.dly.dly[13].__y : 0  [by t.de.dly.dly[13]._y:=1]
-	    571313 t.de.dly.dly[13].___y : 1  [by t.de.dly.dly[13].__y:=0]
-	    573545 t.de.dly.dly[13].y : 0  [by t.de.dly.dly[13].___y:=1]
-	    573690 t.de.dly.dly[14]._y : 1  [by t.de.dly.dly[13].y:=0]
-	    576522 t.de.dly.dly[14].__y : 0  [by t.de.dly.dly[14]._y:=1]
-	    582876 t.de.dly.dly[14].___y : 1  [by t.de.dly.dly[14].__y:=0]
-	    582877 t.de.dly.mu2[3].b : 0  [by t.de.dly.dly[14].___y:=1]
-	    622161 t.de.dly.mu2[3]._y : 1  [by t.de.dly.mu2[3].b:=0]
-	    622323 t.de.dly.out : 0  [by t.de.dly.mu2[3]._y:=1]
-	    629692 t.de.addr_buf._out_a_B : 1  [by t.de.dly.out:=0]
-	    629699 t.de.addr_buf.out_a_B_buf_f.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	    629706 t.de.addr_buf.out_a_B_buf_t.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	    629859 t.de.addr_buf._out_a_BX_t[0] : 1  [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=0]
-	    651263 t.de.addr_buf._out_a_BX_f[0] : 1  [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=0]
-[] set Reset 1
-	    651263 Reset : 1
-	    651264 t._reset_B : 0  [by Reset:=1]
-	    651265 t.de.addr_buf.reset_buf._y : 1  [by t._reset_B:=0]
-	    651266 t.de.addr_buf._reset_BX : 0  [by t.de.addr_buf.reset_buf._y:=1]
-	    653509 t.de.addr_buf.reset_bufarray.buf1._y : 1  [by t.de.addr_buf._reset_BX:=0]
-	    653696 t.de.addr_buf._reset_BXX[0] : 0  [by t.de.addr_buf.reset_bufarray.buf1._y:=1]
-[] set Reset 0
-	    653696 Reset : 0
-	    653697 t._reset_B : 1  [by Reset:=0]
-	    657879 t.de.addr_buf.reset_buf._y : 0  [by t._reset_B:=1]
-	    692661 t.de.addr_buf._reset_BX : 1  [by t.de.addr_buf.reset_buf._y:=0]
-	    692662 t.de.addr_buf.reset_bufarray.buf1._y : 0  [by t.de.addr_buf._reset_BX:=1]
-	    693515 t.de.addr_buf._reset_BXX[0] : 1  [by t.de.addr_buf.reset_bufarray.buf1._y:=0]
-[] Sending packet in
-	    693515 t.in.d.d[0].t : 1
-	    693515 t.in.d.d[2].t : 1
-	    693515 t.in.d.d[1].t : 1
-	    693516 t.de.addr_buf.vc.OR2_tf[2]._y : 0  [by t.in.d.d[2].t:=1]
-	    693519 t.de.addr_buf.vc.ct.in[2] : 1  [by t.de.addr_buf.vc.OR2_tf[2]._y:=0]
-	    693520 t.de.addr_buf.vc.OR2_tf[0]._y : 0  [by t.in.d.d[0].t:=1]
-	    693532 t.de.addr_buf.t_buf_func[2]._y : 0  [by t.in.d.d[2].t:=1]
-	    694406 t.de.addr_buf.t_buf_func[0]._y : 0  [by t.in.d.d[0].t:=1]
-	    694407 t.de.atree_x[1].in[0] : 1  [by t.de.addr_buf.t_buf_func[0]._y:=0]
-	    694449 t.de.atree_x[1].b._y : 0  [by t.de.atree_x[1].in[0]:=1]
-	    694461 t.de.addr_buf.vc.ct.in[0] : 1  [by t.de.addr_buf.vc.OR2_tf[0]._y:=0]
-	    696088 t.de.addr_buf.vc.OR2_tf[1]._y : 0  [by t.in.d.d[1].t:=1]
-	    696183 t.de.addr_buf.vc.ct.in[1] : 1  [by t.de.addr_buf.vc.OR2_tf[1]._y:=0]
-	    696518 t.de.addr_buf.vc.ct.C3Els[0]._y : 0  [by t.de.addr_buf.vc.ct.in[1]:=1]
-	    696526 t.de.addr_buf._in_v : 1  [by t.de.addr_buf.vc.ct.C3Els[0]._y:=0]
-	    696560 t.de.addr_buf.in_v_buf._y : 0  [by t.de.addr_buf._in_v:=1]
-	    697224 t.de.vtree_x.OR2_tf[0]._y : 0  [by t.de.atree_x[1].in[0]:=1]
-	    698142 t.de.vtree_x.ct.in[0] : 1  [by t.de.vtree_x.OR2_tf[0]._y:=0]
-	    698146 t.de.vtree_x.ct.b._y : 0  [by t.de.vtree_x.ct.in[0]:=1]
-	    701876 t.de.addr_buf.t_buf_func[1]._y : 0  [by t.in.d.d[1].t:=1]
-	    704274 t.de.atree_y[1].in[0] : 1  [by t.de.addr_buf.t_buf_func[1]._y:=0]
-	    707489 t.de.vtree_y.OR2_tf[0]._y : 0  [by t.de.atree_y[1].in[0]:=1]
-	    708182 t.ag.inx[1] : 1  [by t.de.atree_x[1].b._y:=0]
-	    710447 t.in.v : 1  [by t.de.addr_buf.in_v_buf._y:=0]
-	    744524 t.de.C2el.c1 : 1  [by t.de.vtree_x.ct.b._y:=0]
-	    752494 t.de.atree_y[2].in[1] : 1  [by t.de.addr_buf.t_buf_func[2]._y:=0]
-	    752497 t.de.vtree_y.OR2_tf[1]._y : 0  [by t.de.atree_y[2].in[1]:=1]
-	    752542 t.de.atree_y[3].and2s[0]._y : 0  [by t.de.atree_y[2].in[1]:=1]
-	    752675 t.de.vtree_y.ct.in[1] : 1  [by t.de.vtree_y.OR2_tf[1]._y:=0]
-	    754608 t.de.vtree_y.ct.in[0] : 1  [by t.de.vtree_y.OR2_tf[0]._y:=0]
-	    766507 t.de.vtree_y.ct.C2Els[0]._y : 0  [by t.de.vtree_y.ct.in[0]:=1]
-	    772458 t.de.C2el.c2 : 1  [by t.de.vtree_y.ct.C2Els[0]._y:=0]
-	    773519 t.ag.iny[3] : 1  [by t.de.atree_y[3].and2s[0]._y:=0]
-	    774346 t.ag.ands[7]._y : 0  [by t.ag.iny[3]:=1]
-	    774519 t.out[7] : 1  [by t.ag.ands[7]._y:=0]
-	    811943 t.de.C2el._y : 0  [by t.de.C2el.c2:=1]
-	    812127 t.de.C2el.y : 1  [by t.de.C2el._y:=0]
-	    812128 t.de.dly.and2[0]._y : 0  [by t.de.C2el.y:=1]
-	    812132 t.de.dly.dly[0].a : 1  [by t.de.dly.and2[0]._y:=0]
-	    812200 t.de.addr_buf.inack_ctl._y : 0  [by t.de.C2el.y:=1]
-	    812296 t.in.a : 1  [by t.de.addr_buf.inack_ctl._y:=0]
-	    812432 t.de.addr_buf._en : 0  [by t.in.a:=1]
-	    812433 t.de.addr_buf.en_buf_f.buf1._y : 1  [by t.de.addr_buf._en:=0]
-	    812674 t.de.addr_buf._en_X_f[0] : 0  [by t.de.addr_buf.en_buf_f.buf1._y:=1]
-	    831478 t.de.addr_buf.en_buf_t.buf1._y : 1  [by t.de.addr_buf._en:=0]
-	    835437 t.de.addr_buf._en_X_t[0] : 0  [by t.de.addr_buf.en_buf_t.buf1._y:=1]
-	    849420 t.de.dly.dly[0]._y : 0  [by t.de.dly.dly[0].a:=1]
-	    849432 t.de.dly.dly[0].__y : 1  [by t.de.dly.dly[0]._y:=0]
-	    853332 t.de.dly.dly[0].___y : 0  [by t.de.dly.dly[0].__y:=1]
-	    854361 t.de.dly.dly[0].y : 1  [by t.de.dly.dly[0].___y:=0]
-	    854362 t.de.dly.mu2[0]._y : 0  [by t.de.dly.dly[0].y:=1]
-	    854418 t.de.dly._a[1] : 1  [by t.de.dly.mu2[0]._y:=0]
-	    899424 t.de.dly.and2[1]._y : 0  [by t.de.dly._a[1]:=1]
-	    899425 t.de.dly.dly[1].a : 1  [by t.de.dly.and2[1]._y:=0]
-	    899462 t.de.dly.dly[1]._y : 0  [by t.de.dly.dly[1].a:=1]
-	    922837 t.de.dly.dly[1].__y : 1  [by t.de.dly.dly[1]._y:=0]
-	    922838 t.de.dly.dly[1].___y : 0  [by t.de.dly.dly[1].__y:=1]
-	    926402 t.de.dly.dly[1].y : 1  [by t.de.dly.dly[1].___y:=0]
-	    928094 t.de.dly.dly[2]._y : 0  [by t.de.dly.dly[1].y:=1]
-	    928107 t.de.dly.dly[2].__y : 1  [by t.de.dly.dly[2]._y:=0]
-	    945091 t.de.dly.dly[2].___y : 0  [by t.de.dly.dly[2].__y:=1]
-	    945448 t.de.dly.dly[2].y : 1  [by t.de.dly.dly[2].___y:=0]
-	    945473 t.de.dly.mu2[1]._y : 0  [by t.de.dly.dly[2].y:=1]
-	    945494 t.de.dly._a[2] : 1  [by t.de.dly.mu2[1]._y:=0]
-	    945495 t.de.dly.and2[2]._y : 0  [by t.de.dly._a[2]:=1]
-	    955143 t.de.dly.dly[3].a : 1  [by t.de.dly.and2[2]._y:=0]
-	    955144 t.de.dly.dly[3]._y : 0  [by t.de.dly.dly[3].a:=1]
-	    955145 t.de.dly.dly[3].__y : 1  [by t.de.dly.dly[3]._y:=0]
-	    955306 t.de.dly.dly[3].___y : 0  [by t.de.dly.dly[3].__y:=1]
-	    956343 t.de.dly.dly[3].y : 1  [by t.de.dly.dly[3].___y:=0]
-	    956348 t.de.dly.dly[4]._y : 0  [by t.de.dly.dly[3].y:=1]
-	    956929 t.de.dly.dly[4].__y : 1  [by t.de.dly.dly[4]._y:=0]
-	    957337 t.de.dly.dly[4].___y : 0  [by t.de.dly.dly[4].__y:=1]
-	    957348 t.de.dly.dly[4].y : 1  [by t.de.dly.dly[4].___y:=0]
-	    958395 t.de.dly.dly[5]._y : 0  [by t.de.dly.dly[4].y:=1]
-	    958409 t.de.dly.dly[5].__y : 1  [by t.de.dly.dly[5]._y:=0]
-	    958427 t.de.dly.dly[5].___y : 0  [by t.de.dly.dly[5].__y:=1]
-	    958431 t.de.dly.dly[5].y : 1  [by t.de.dly.dly[5].___y:=0]
-	    958535 t.de.dly.dly[6]._y : 0  [by t.de.dly.dly[5].y:=1]
-	    989979 t.de.dly.dly[6].__y : 1  [by t.de.dly.dly[6]._y:=0]
-	    991183 t.de.dly.dly[6].___y : 0  [by t.de.dly.dly[6].__y:=1]
-	    999638 t.de.dly.dly[6].y : 1  [by t.de.dly.dly[6].___y:=0]
-	    999866 t.de.dly.mu2[2]._y : 0  [by t.de.dly.dly[6].y:=1]
-	   1000709 t.de.dly._a[3] : 1  [by t.de.dly.mu2[2]._y:=0]
-	   1002168 t.de.dly.and2[3]._y : 0  [by t.de.dly._a[3]:=1]
-	   1002238 t.de.dly.dly[7].a : 1  [by t.de.dly.and2[3]._y:=0]
-	   1052660 t.de.dly.dly[7]._y : 0  [by t.de.dly.dly[7].a:=1]
-	   1052671 t.de.dly.dly[7].__y : 1  [by t.de.dly.dly[7]._y:=0]
-	   1052674 t.de.dly.dly[7].___y : 0  [by t.de.dly.dly[7].__y:=1]
-	   1052728 t.de.dly.dly[7].y : 1  [by t.de.dly.dly[7].___y:=0]
-	   1053876 t.de.dly.dly[8]._y : 0  [by t.de.dly.dly[7].y:=1]
-	   1055037 t.de.dly.dly[8].__y : 1  [by t.de.dly.dly[8]._y:=0]
-	   1063689 t.de.dly.dly[8].___y : 0  [by t.de.dly.dly[8].__y:=1]
-	   1063770 t.de.dly.dly[8].y : 1  [by t.de.dly.dly[8].___y:=0]
-	   1074847 t.de.dly.dly[9]._y : 0  [by t.de.dly.dly[8].y:=1]
-	   1092830 t.de.dly.dly[9].__y : 1  [by t.de.dly.dly[9]._y:=0]
-	   1092922 t.de.dly.dly[9].___y : 0  [by t.de.dly.dly[9].__y:=1]
-	   1101233 t.de.dly.dly[9].y : 1  [by t.de.dly.dly[9].___y:=0]
-	   1102977 t.de.dly.dly[10]._y : 0  [by t.de.dly.dly[9].y:=1]
-	   1103590 t.de.dly.dly[10].__y : 1  [by t.de.dly.dly[10]._y:=0]
-	   1117612 t.de.dly.dly[10].___y : 0  [by t.de.dly.dly[10].__y:=1]
-	   1117657 t.de.dly.dly[10].y : 1  [by t.de.dly.dly[10].___y:=0]
-	   1118654 t.de.dly.dly[11]._y : 0  [by t.de.dly.dly[10].y:=1]
-	   1120303 t.de.dly.dly[11].__y : 1  [by t.de.dly.dly[11]._y:=0]
-	   1120828 t.de.dly.dly[11].___y : 0  [by t.de.dly.dly[11].__y:=1]
-	   1121728 t.de.dly.dly[11].y : 1  [by t.de.dly.dly[11].___y:=0]
-	   1121780 t.de.dly.dly[12]._y : 0  [by t.de.dly.dly[11].y:=1]
-	   1121787 t.de.dly.dly[12].__y : 1  [by t.de.dly.dly[12]._y:=0]
-	   1137399 t.de.dly.dly[12].___y : 0  [by t.de.dly.dly[12].__y:=1]
-	   1143866 t.de.dly.dly[12].y : 1  [by t.de.dly.dly[12].___y:=0]
-	   1143868 t.de.dly.dly[13]._y : 0  [by t.de.dly.dly[12].y:=1]
-	   1144222 t.de.dly.dly[13].__y : 1  [by t.de.dly.dly[13]._y:=0]
-	   1144355 t.de.dly.dly[13].___y : 0  [by t.de.dly.dly[13].__y:=1]
-	   1144356 t.de.dly.dly[13].y : 1  [by t.de.dly.dly[13].___y:=0]
-	   1144360 t.de.dly.dly[14]._y : 0  [by t.de.dly.dly[13].y:=1]
-	   1144906 t.de.dly.dly[14].__y : 1  [by t.de.dly.dly[14]._y:=0]
-	   1190469 t.de.dly.dly[14].___y : 0  [by t.de.dly.dly[14].__y:=1]
-	   1190470 t.de.dly.mu2[3].b : 1  [by t.de.dly.dly[14].___y:=0]
-	   1202848 t.de.dly.mu2[3]._y : 0  [by t.de.dly.mu2[3].b:=1]
-	   1202927 t.de.dly.out : 1  [by t.de.dly.mu2[3]._y:=0]
-	   1205360 t.de.addr_buf._out_a_B : 0  [by t.de.dly.out:=1]
-	   1205448 t.de.addr_buf.out_a_B_buf_t.buf1._y : 1  [by t.de.addr_buf._out_a_B:=0]
-	   1213142 t.de.addr_buf.out_a_B_buf_f.buf1._y : 1  [by t.de.addr_buf._out_a_B:=0]
-	   1213201 t.de.addr_buf._out_a_BX_t[0] : 0  [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=1]
-	   1213231 t.de.addr_buf.t_buf_func[0]._y : 1  [by t.de.addr_buf._out_a_BX_t[0]:=0]
-	   1214668 t.de.addr_buf.t_buf_func[1]._y : 1  [by t.de.addr_buf._out_a_BX_t[0]:=0]
-	   1215353 t.de.atree_y[1].in[0] : 0  [by t.de.addr_buf.t_buf_func[1]._y:=1]
-	   1215480 t.de.vtree_y.OR2_tf[0]._y : 1  [by t.de.atree_y[1].in[0]:=0]
-	   1215649 t.de.vtree_y.ct.in[0] : 0  [by t.de.vtree_y.OR2_tf[0]._y:=1]
-	   1232068 t.de.atree_y[3].and2s[0]._y : 1  [by t.de.atree_y[1].in[0]:=0]
-	   1232111 t.ag.iny[3] : 0  [by t.de.atree_y[3].and2s[0]._y:=1]
-	   1232123 t.ag.ands[7]._y : 1  [by t.ag.iny[3]:=0]
-	   1232615 t.de.atree_x[1].in[0] : 0  [by t.de.addr_buf.t_buf_func[0]._y:=1]
-	   1232618 t.de.vtree_x.OR2_tf[0]._y : 1  [by t.de.atree_x[1].in[0]:=0]
-	   1232656 t.de.vtree_x.ct.in[0] : 0  [by t.de.vtree_x.OR2_tf[0]._y:=1]
-	   1232657 t.de.vtree_x.ct.b._y : 1  [by t.de.vtree_x.ct.in[0]:=0]
-	   1232848 t.de.atree_x[1].b._y : 1  [by t.de.atree_x[1].in[0]:=0]
-	   1232940 t.ag.inx[1] : 0  [by t.de.atree_x[1].b._y:=1]
-	   1233402 t.out[7] : 0  [by t.ag.ands[7]._y:=1]
-	   1233775 t.de.addr_buf._out_a_BX_f[0] : 0  [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=1]
-	   1245409 t.de.C2el.c1 : 0  [by t.de.vtree_x.ct.b._y:=1]
-	   1272705 t.de.addr_buf.t_buf_func[2]._y : 1  [by t.de.addr_buf._out_a_BX_t[0]:=0]
-	   1275432 t.de.atree_y[2].in[1] : 0  [by t.de.addr_buf.t_buf_func[2]._y:=1]
-	   1275434 t.de.vtree_y.OR2_tf[1]._y : 1  [by t.de.atree_y[2].in[1]:=0]
-	   1275435 t.de.vtree_y.ct.in[1] : 0  [by t.de.vtree_y.OR2_tf[1]._y:=1]
-	   1276936 t.de.vtree_y.ct.C2Els[0]._y : 1  [by t.de.vtree_y.ct.in[1]:=0]
-	   1276938 t.de.C2el.c2 : 0  [by t.de.vtree_y.ct.C2Els[0]._y:=1]
-	   1276956 t.de.C2el._y : 1  [by t.de.C2el.c2:=0]
-	   1277075 t.de.C2el.y : 0  [by t.de.C2el._y:=1]
-	   1282795 t.de.dly.and2[0]._y : 1  [by t.de.C2el.y:=0]
-	   1282803 t.de.dly.dly[0].a : 0  [by t.de.dly.and2[0]._y:=1]
-	   1282857 t.de.dly.dly[0]._y : 1  [by t.de.dly.dly[0].a:=0]
-	   1333395 t.de.dly.dly[0].__y : 0  [by t.de.dly.dly[0]._y:=1]
-	   1333400 t.de.dly.dly[0].___y : 1  [by t.de.dly.dly[0].__y:=0]
-	   1334467 t.de.dly.dly[0].y : 0  [by t.de.dly.dly[0].___y:=1]
-	   1334468 t.de.dly.mu2[0]._y : 1  [by t.de.dly.dly[0].y:=0]
-	   1334606 t.de.dly._a[1] : 0  [by t.de.dly.mu2[0]._y:=1]
-	   1334607 t.de.dly.and2[1]._y : 1  [by t.de.dly._a[1]:=0]
-	   1334671 t.de.dly.dly[1].a : 0  [by t.de.dly.and2[1]._y:=1]
-	   1334794 t.de.dly.dly[1]._y : 1  [by t.de.dly.dly[1].a:=0]
-	   1334796 t.de.dly.dly[1].__y : 0  [by t.de.dly.dly[1]._y:=1]
-	   1334833 t.de.dly.dly[1].___y : 1  [by t.de.dly.dly[1].__y:=0]
-	   1334976 t.de.dly.dly[1].y : 0  [by t.de.dly.dly[1].___y:=1]
-	   1335027 t.de.dly.dly[2]._y : 1  [by t.de.dly.dly[1].y:=0]
-	   1335469 t.de.dly.dly[2].__y : 0  [by t.de.dly.dly[2]._y:=1]
-	   1335480 t.de.dly.dly[2].___y : 1  [by t.de.dly.dly[2].__y:=0]
-	   1335481 t.de.dly.dly[2].y : 0  [by t.de.dly.dly[2].___y:=1]
-	   1335490 t.de.dly.mu2[1]._y : 1  [by t.de.dly.dly[2].y:=0]
-	   1335515 t.de.dly._a[2] : 0  [by t.de.dly.mu2[1]._y:=1]
-	   1345768 t.de.dly.and2[2]._y : 1  [by t.de.dly._a[2]:=0]
-	   1349289 t.de.dly.dly[3].a : 0  [by t.de.dly.and2[2]._y:=1]
-	   1349434 t.de.dly.dly[3]._y : 1  [by t.de.dly.dly[3].a:=0]
-	   1365602 t.de.dly.dly[3].__y : 0  [by t.de.dly.dly[3]._y:=1]
-	   1365832 t.de.dly.dly[3].___y : 1  [by t.de.dly.dly[3].__y:=0]
-	   1366523 t.de.dly.dly[3].y : 0  [by t.de.dly.dly[3].___y:=1]
-	   1366537 t.de.dly.dly[4]._y : 1  [by t.de.dly.dly[3].y:=0]
-	   1368080 t.de.dly.dly[4].__y : 0  [by t.de.dly.dly[4]._y:=1]
-	   1369691 t.de.dly.dly[4].___y : 1  [by t.de.dly.dly[4].__y:=0]
-	   1387203 t.de.dly.dly[4].y : 0  [by t.de.dly.dly[4].___y:=1]
-	   1387214 t.de.dly.dly[5]._y : 1  [by t.de.dly.dly[4].y:=0]
-	   1387215 t.de.dly.dly[5].__y : 0  [by t.de.dly.dly[5]._y:=1]
-	   1387216 t.de.dly.dly[5].___y : 1  [by t.de.dly.dly[5].__y:=0]
-	   1393717 t.de.dly.dly[5].y : 0  [by t.de.dly.dly[5].___y:=1]
-	   1394356 t.de.dly.dly[6]._y : 1  [by t.de.dly.dly[5].y:=0]
-	   1396149 t.de.dly.dly[6].__y : 0  [by t.de.dly.dly[6]._y:=1]
-	   1396281 t.de.dly.dly[6].___y : 1  [by t.de.dly.dly[6].__y:=0]
-	   1396282 t.de.dly.dly[6].y : 0  [by t.de.dly.dly[6].___y:=1]
-	   1396299 t.de.dly.mu2[2]._y : 1  [by t.de.dly.dly[6].y:=0]
-	   1396451 t.de.dly._a[3] : 0  [by t.de.dly.mu2[2]._y:=1]
-	   1399434 t.de.dly.and2[3]._y : 1  [by t.de.dly._a[3]:=0]
-	   1399437 t.de.dly.dly[7].a : 0  [by t.de.dly.and2[3]._y:=1]
-	   1399861 t.de.dly.dly[7]._y : 1  [by t.de.dly.dly[7].a:=0]
-	   1399867 t.de.dly.dly[7].__y : 0  [by t.de.dly.dly[7]._y:=1]
-	   1402455 t.de.dly.dly[7].___y : 1  [by t.de.dly.dly[7].__y:=0]
-	   1404916 t.de.dly.dly[7].y : 0  [by t.de.dly.dly[7].___y:=1]
-	   1405746 t.de.dly.dly[8]._y : 1  [by t.de.dly.dly[7].y:=0]
-	   1428678 t.de.dly.dly[8].__y : 0  [by t.de.dly.dly[8]._y:=1]
-	   1428680 t.de.dly.dly[8].___y : 1  [by t.de.dly.dly[8].__y:=0]
-	   1428874 t.de.dly.dly[8].y : 0  [by t.de.dly.dly[8].___y:=1]
-	   1429477 t.de.dly.dly[9]._y : 1  [by t.de.dly.dly[8].y:=0]
-	   1429615 t.de.dly.dly[9].__y : 0  [by t.de.dly.dly[9]._y:=1]
-	   1429632 t.de.dly.dly[9].___y : 1  [by t.de.dly.dly[9].__y:=0]
-	   1429649 t.de.dly.dly[9].y : 0  [by t.de.dly.dly[9].___y:=1]
-	   1430075 t.de.dly.dly[10]._y : 1  [by t.de.dly.dly[9].y:=0]
-	   1430076 t.de.dly.dly[10].__y : 0  [by t.de.dly.dly[10]._y:=1]
-	   1430077 t.de.dly.dly[10].___y : 1  [by t.de.dly.dly[10].__y:=0]
-	   1431103 t.de.dly.dly[10].y : 0  [by t.de.dly.dly[10].___y:=1]
-	   1431104 t.de.dly.dly[11]._y : 1  [by t.de.dly.dly[10].y:=0]
-	   1431123 t.de.dly.dly[11].__y : 0  [by t.de.dly.dly[11]._y:=1]
-	   1431291 t.de.dly.dly[11].___y : 1  [by t.de.dly.dly[11].__y:=0]
-	   1431830 t.de.dly.dly[11].y : 0  [by t.de.dly.dly[11].___y:=1]
-	   1431991 t.de.dly.dly[12]._y : 1  [by t.de.dly.dly[11].y:=0]
-	   1432164 t.de.dly.dly[12].__y : 0  [by t.de.dly.dly[12]._y:=1]
-	   1434711 t.de.dly.dly[12].___y : 1  [by t.de.dly.dly[12].__y:=0]
-	   1449772 t.de.dly.dly[12].y : 0  [by t.de.dly.dly[12].___y:=1]
-	   1449773 t.de.dly.dly[13]._y : 1  [by t.de.dly.dly[12].y:=0]
-	   1449774 t.de.dly.dly[13].__y : 0  [by t.de.dly.dly[13]._y:=1]
-	   1450164 t.de.dly.dly[13].___y : 1  [by t.de.dly.dly[13].__y:=0]
-	   1450371 t.de.dly.dly[13].y : 0  [by t.de.dly.dly[13].___y:=1]
-	   1451204 t.de.dly.dly[14]._y : 1  [by t.de.dly.dly[13].y:=0]
-	   1451232 t.de.dly.dly[14].__y : 0  [by t.de.dly.dly[14]._y:=1]
-	   1451239 t.de.dly.dly[14].___y : 1  [by t.de.dly.dly[14].__y:=0]
-	   1451653 t.de.dly.mu2[3].b : 0  [by t.de.dly.dly[14].___y:=1]
-	   1451657 t.de.dly.mu2[3]._y : 1  [by t.de.dly.mu2[3].b:=0]
-	   1453436 t.de.dly.out : 0  [by t.de.dly.mu2[3]._y:=1]
-	   1476310 t.de.addr_buf._out_a_B : 1  [by t.de.dly.out:=0]
-	   1476476 t.de.addr_buf.out_a_B_buf_t.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	   1485121 t.de.addr_buf._out_a_BX_f[0] : 1  [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=0]
-	   1516180 t.de.addr_buf.out_a_B_buf_f.buf1._y : 0  [by t.de.addr_buf._out_a_B:=1]
-	   1517113 t.de.addr_buf._out_a_BX_t[0] : 1  [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=0]

test/unit_tests/decoder_2d_dly_and_2_4/run/test.prs

@@ -1,948 +1,3 @@
 = "GND" "GND"
 = "Vdd" "Vdd"
 = "Reset" "Reset"
-"Reset"->"t._reset_B"-
-~("Reset")->"t._reset_B"+
-= "t._reset_B" "t.de.reset_B"
-= "t.ag.iny[0]" "t.ag.ands[1].b"
-= "t.ag.iny[0]" "t.ag.ands[0].b"
-= "t.ag.iny[1]" "t.ag.ands[3].b"
-= "t.ag.iny[1]" "t.ag.ands[2].b"
-= "t.ag.iny[2]" "t.ag.ands[5].b"
-= "t.ag.iny[2]" "t.ag.ands[4].b"
-= "t.ag.iny[3]" "t.ag.ands[7].b"
-= "t.ag.iny[3]" "t.ag.ands[6].b"
-= "t.ag.inx[0]" "t.ag.ands[6].a"
-= "t.ag.inx[0]" "t.ag.ands[4].a"
-= "t.ag.inx[0]" "t.ag.ands[2].a"
-= "t.ag.inx[0]" "t.ag.ands[0].a"
-= "t.ag.inx[1]" "t.ag.ands[7].a"
-= "t.ag.inx[1]" "t.ag.ands[5].a"
-= "t.ag.inx[1]" "t.ag.ands[3].a"
-= "t.ag.inx[1]" "t.ag.ands[1].a"
-"t.ag.ands[0].a"&"t.ag.ands[0].b"->"t.ag.ands[0]._y"-
-~("t.ag.ands[0].a"&"t.ag.ands[0].b")->"t.ag.ands[0]._y"+
-"t.ag.ands[0]._y"->"t.ag.ands[0].y"-
-~("t.ag.ands[0]._y")->"t.ag.ands[0].y"+
-"t.ag.ands[1].a"&"t.ag.ands[1].b"->"t.ag.ands[1]._y"-
-~("t.ag.ands[1].a"&"t.ag.ands[1].b")->"t.ag.ands[1]._y"+
-"t.ag.ands[1]._y"->"t.ag.ands[1].y"-
-~("t.ag.ands[1]._y")->"t.ag.ands[1].y"+
-"t.ag.ands[2].a"&"t.ag.ands[2].b"->"t.ag.ands[2]._y"-
-~("t.ag.ands[2].a"&"t.ag.ands[2].b")->"t.ag.ands[2]._y"+
-"t.ag.ands[2]._y"->"t.ag.ands[2].y"-
-~("t.ag.ands[2]._y")->"t.ag.ands[2].y"+
-"t.ag.ands[3].a"&"t.ag.ands[3].b"->"t.ag.ands[3]._y"-
-~("t.ag.ands[3].a"&"t.ag.ands[3].b")->"t.ag.ands[3]._y"+
-"t.ag.ands[3]._y"->"t.ag.ands[3].y"-
-~("t.ag.ands[3]._y")->"t.ag.ands[3].y"+
-"t.ag.ands[4].a"&"t.ag.ands[4].b"->"t.ag.ands[4]._y"-
-~("t.ag.ands[4].a"&"t.ag.ands[4].b")->"t.ag.ands[4]._y"+
-"t.ag.ands[4]._y"->"t.ag.ands[4].y"-
-~("t.ag.ands[4]._y")->"t.ag.ands[4].y"+
-"t.ag.ands[5].a"&"t.ag.ands[5].b"->"t.ag.ands[5]._y"-
-~("t.ag.ands[5].a"&"t.ag.ands[5].b")->"t.ag.ands[5]._y"+
-"t.ag.ands[5]._y"->"t.ag.ands[5].y"-
-~("t.ag.ands[5]._y")->"t.ag.ands[5].y"+
-"t.ag.ands[6].a"&"t.ag.ands[6].b"->"t.ag.ands[6]._y"-
-~("t.ag.ands[6].a"&"t.ag.ands[6].b")->"t.ag.ands[6]._y"+
-"t.ag.ands[6]._y"->"t.ag.ands[6].y"-
-~("t.ag.ands[6]._y")->"t.ag.ands[6].y"+
-"t.ag.ands[7].a"&"t.ag.ands[7].b"->"t.ag.ands[7]._y"-
-~("t.ag.ands[7].a"&"t.ag.ands[7].b")->"t.ag.ands[7]._y"+
-"t.ag.ands[7]._y"->"t.ag.ands[7].y"-
-~("t.ag.ands[7]._y")->"t.ag.ands[7].y"+
-= "t.ag.supply.vdd" "t.ag.ands[7].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[6].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[5].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[4].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[3].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[2].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[1].vdd"
-= "t.ag.supply.vdd" "t.ag.ands[0].vdd"
-= "t.ag.supply.vss" "t.ag.ands[7].vss"
-= "t.ag.supply.vss" "t.ag.ands[6].vss"
-= "t.ag.supply.vss" "t.ag.ands[5].vss"
-= "t.ag.supply.vss" "t.ag.ands[4].vss"
-= "t.ag.supply.vss" "t.ag.ands[3].vss"
-= "t.ag.supply.vss" "t.ag.ands[2].vss"
-= "t.ag.supply.vss" "t.ag.ands[1].vss"
-= "t.ag.supply.vss" "t.ag.ands[0].vss"
-= "t.ag.out[0]" "t.ag.ands[0].y"
-= "t.ag.out[1]" "t.ag.ands[1].y"
-= "t.ag.out[2]" "t.ag.ands[2].y"
-= "t.ag.out[3]" "t.ag.ands[3].y"
-= "t.ag.out[4]" "t.ag.ands[4].y"
-= "t.ag.out[5]" "t.ag.ands[5].y"
-= "t.ag.out[6]" "t.ag.ands[6].y"
-= "t.ag.out[7]" "t.ag.ands[7].y"
-= "t.ag.inx[0]" "t.de.outx[0]"
-= "t.ag.inx[1]" "t.de.outx[1]"
-= "t.ag.iny[0]" "t.de.outy[0]"
-= "t.ag.iny[1]" "t.de.outy[1]"
-= "t.ag.iny[2]" "t.de.outy[2]"
-= "t.ag.iny[3]" "t.de.outy[3]"
-= "Vdd" "t.ag.supply.vdd"
-= "GND" "t.ag.supply.vss"
-"t.de.atree_x[0].b.a"->"t.de.atree_x[0].b._y"-
-~("t.de.atree_x[0].b.a")->"t.de.atree_x[0].b._y"+
-"t.de.atree_x[0].b._y"->"t.de.atree_x[0].b.y"-
-~("t.de.atree_x[0].b._y")->"t.de.atree_x[0].b.y"+
-= "t.de.atree_x[0].supply.vdd" "t.de.atree_x[0].b.vdd"
-= "t.de.atree_x[0].supply.vss" "t.de.atree_x[0].b.vss"
-= "t.de.atree_x[0].out" "t.de.atree_x[0].b.y"
-= "t.de.atree_x[0].in[0]" "t.de.atree_x[0].b.a"
-"t.de.atree_x[1].b.a"->"t.de.atree_x[1].b._y"-
-~("t.de.atree_x[1].b.a")->"t.de.atree_x[1].b._y"+
-"t.de.atree_x[1].b._y"->"t.de.atree_x[1].b.y"-
-~("t.de.atree_x[1].b._y")->"t.de.atree_x[1].b.y"+
-= "t.de.atree_x[1].supply.vdd" "t.de.atree_x[1].b.vdd"
-= "t.de.atree_x[1].supply.vss" "t.de.atree_x[1].b.vss"
-= "t.de.atree_x[1].out" "t.de.atree_x[1].b.y"
-= "t.de.atree_x[1].in[0]" "t.de.atree_x[1].b.a"
-= "t.de.atree_x[1].in[0]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.atree_x[1].in[0]" "t.de.addr_buf.out.d.d[0].d[1]"
-= "t.de.atree_x[1].in[0]" "t.de.vtree_x.in.d[0].t"
-= "t.de.atree_x[1].in[0]" "t.de.vtree_x.in.d[0].d[1]"
-= "t.de.atree_x[0].in[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.atree_x[0].in[0]" "t.de.addr_buf.out.d.d[0].d[0]"
-= "t.de.atree_x[0].in[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.atree_x[0].in[0]" "t.de.vtree_x.in.d[0].d[0]"
-= "t.de.dly_cfg[0]" "t.de.dly.s[0]"
-= "t.de.dly_cfg[1]" "t.de.dly.s[1]"
-= "t.de.dly_cfg[2]" "t.de.dly.s[2]"
-= "t.de.dly_cfg[3]" "t.de.dly.s[3]"
-= "t.de.supply.vss" "t.de.atree_y[3].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[3].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_y[2].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[2].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_y[1].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[1].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_y[0].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_y[0].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_x[1].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_x[1].supply.vdd"
-= "t.de.supply.vss" "t.de.atree_x[0].supply.vss"
-= "t.de.supply.vdd" "t.de.atree_x[0].supply.vdd"
-= "t.de.supply.vss" "t.de.dly.supply.vss"
-= "t.de.supply.vdd" "t.de.dly.supply.vdd"
-= "t.de.supply.vss" "t.de.vtree_y.supply.vss"
-= "t.de.supply.vdd" "t.de.vtree_y.supply.vdd"
-= "t.de.supply.vss" "t.de.vtree_x.supply.vss"
-= "t.de.supply.vdd" "t.de.vtree_x.supply.vdd"
-= "t.de.supply.vss" "t.de.addr_buf.supply.vss"
-= "t.de.supply.vdd" "t.de.addr_buf.supply.vdd"
-= "t.de.supply.vdd" "t.de.C2el.vdd"
-= "t.de.supply.vss" "t.de.C2el.vss"
-~"t.de.C2el.c1"&~"t.de.C2el.c2"->"t.de.C2el._y"+
-"t.de.C2el.c1"&"t.de.C2el.c2"->"t.de.C2el._y"-
-"t.de.C2el._y"->"t.de.C2el.y"-
-~("t.de.C2el._y")->"t.de.C2el.y"+
-= "t.de.C2el.c1" "t.de.vtree_x.out"
-= "t.de.C2el.c2" "t.de.vtree_y.out"
-"t.de.dly.and2[0].a"&"t.de.dly.and2[0].b"->"t.de.dly.and2[0]._y"-
-~("t.de.dly.and2[0].a"&"t.de.dly.and2[0].b")->"t.de.dly.and2[0]._y"+
-"t.de.dly.and2[0]._y"->"t.de.dly.and2[0].y"-
-~("t.de.dly.and2[0]._y")->"t.de.dly.and2[0].y"+
-"t.de.dly.and2[1].a"&"t.de.dly.and2[1].b"->"t.de.dly.and2[1]._y"-
-~("t.de.dly.and2[1].a"&"t.de.dly.and2[1].b")->"t.de.dly.and2[1]._y"+
-"t.de.dly.and2[1]._y"->"t.de.dly.and2[1].y"-
-~("t.de.dly.and2[1]._y")->"t.de.dly.and2[1].y"+
-"t.de.dly.and2[2].a"&"t.de.dly.and2[2].b"->"t.de.dly.and2[2]._y"-
-~("t.de.dly.and2[2].a"&"t.de.dly.and2[2].b")->"t.de.dly.and2[2]._y"+
-"t.de.dly.and2[2]._y"->"t.de.dly.and2[2].y"-
-~("t.de.dly.and2[2]._y")->"t.de.dly.and2[2].y"+
-"t.de.dly.and2[3].a"&"t.de.dly.and2[3].b"->"t.de.dly.and2[3]._y"-
-~("t.de.dly.and2[3].a"&"t.de.dly.and2[3].b")->"t.de.dly.and2[3]._y"+
-"t.de.dly.and2[3]._y"->"t.de.dly.and2[3].y"-
-~("t.de.dly.and2[3]._y")->"t.de.dly.and2[3].y"+
-= "t.de.dly.s[0]" "t.de.dly.mu2[0].s"
-= "t.de.dly.s[0]" "t.de.dly.and2[0].b"
-= "t.de.dly.s[1]" "t.de.dly.mu2[1].s"
-= "t.de.dly.s[1]" "t.de.dly.and2[1].b"
-= "t.de.dly.s[2]" "t.de.dly.mu2[2].s"
-= "t.de.dly.s[2]" "t.de.dly.and2[2].b"
-= "t.de.dly.s[3]" "t.de.dly.mu2[3].s"
-= "t.de.dly.s[3]" "t.de.dly.and2[3].b"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[14].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[13].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[12].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[11].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[10].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[9].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[8].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[7].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[6].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[5].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[4].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[3].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[2].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[1].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.dly[0].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[3].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[2].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[1].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.mu2[0].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[3].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[2].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[1].vdd"
-= "t.de.dly.supply.vdd" "t.de.dly.and2[0].vdd"
-= "t.de.dly.supply.vss" "t.de.dly.dly[14].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[13].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[12].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[11].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[10].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[9].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[8].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[7].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[6].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[5].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[4].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[3].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[2].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[1].vss"
-= "t.de.dly.supply.vss" "t.de.dly.dly[0].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[3].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[2].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[1].vss"
-= "t.de.dly.supply.vss" "t.de.dly.mu2[0].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[3].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[2].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[1].vss"
-= "t.de.dly.supply.vss" "t.de.dly.and2[0].vss"
-"t.de.dly.mu2[0].s"->"t.de.dly.mu2[0]._s"-
-~("t.de.dly.mu2[0].s")->"t.de.dly.mu2[0]._s"+
-~"t.de.dly.mu2[0].a"&~"t.de.dly.mu2[0].s"|~"t.de.dly.mu2[0].b"&~"t.de.dly.mu2[0]._s"->"t.de.dly.mu2[0]._y"+
-"t.de.dly.mu2[0].a"&"t.de.dly.mu2[0]._s"|"t.de.dly.mu2[0].b"&"t.de.dly.mu2[0].s"->"t.de.dly.mu2[0]._y"-
-"t.de.dly.mu2[0]._y"->"t.de.dly.mu2[0].y"-
-~("t.de.dly.mu2[0]._y")->"t.de.dly.mu2[0].y"+
-"t.de.dly.mu2[1].s"->"t.de.dly.mu2[1]._s"-
-~("t.de.dly.mu2[1].s")->"t.de.dly.mu2[1]._s"+
-~"t.de.dly.mu2[1].a"&~"t.de.dly.mu2[1].s"|~"t.de.dly.mu2[1].b"&~"t.de.dly.mu2[1]._s"->"t.de.dly.mu2[1]._y"+
-"t.de.dly.mu2[1].a"&"t.de.dly.mu2[1]._s"|"t.de.dly.mu2[1].b"&"t.de.dly.mu2[1].s"->"t.de.dly.mu2[1]._y"-
-"t.de.dly.mu2[1]._y"->"t.de.dly.mu2[1].y"-
-~("t.de.dly.mu2[1]._y")->"t.de.dly.mu2[1].y"+
-"t.de.dly.mu2[2].s"->"t.de.dly.mu2[2]._s"-
-~("t.de.dly.mu2[2].s")->"t.de.dly.mu2[2]._s"+
-~"t.de.dly.mu2[2].a"&~"t.de.dly.mu2[2].s"|~"t.de.dly.mu2[2].b"&~"t.de.dly.mu2[2]._s"->"t.de.dly.mu2[2]._y"+
-"t.de.dly.mu2[2].a"&"t.de.dly.mu2[2]._s"|"t.de.dly.mu2[2].b"&"t.de.dly.mu2[2].s"->"t.de.dly.mu2[2]._y"-
-"t.de.dly.mu2[2]._y"->"t.de.dly.mu2[2].y"-
-~("t.de.dly.mu2[2]._y")->"t.de.dly.mu2[2].y"+
-"t.de.dly.mu2[3].s"->"t.de.dly.mu2[3]._s"-
-~("t.de.dly.mu2[3].s")->"t.de.dly.mu2[3]._s"+
-~"t.de.dly.mu2[3].a"&~"t.de.dly.mu2[3].s"|~"t.de.dly.mu2[3].b"&~"t.de.dly.mu2[3]._s"->"t.de.dly.mu2[3]._y"+
-"t.de.dly.mu2[3].a"&"t.de.dly.mu2[3]._s"|"t.de.dly.mu2[3].b"&"t.de.dly.mu2[3].s"->"t.de.dly.mu2[3]._y"-
-"t.de.dly.mu2[3]._y"->"t.de.dly.mu2[3].y"-
-~("t.de.dly.mu2[3]._y")->"t.de.dly.mu2[3].y"+
-"t.de.dly.dly[0].a"->"t.de.dly.dly[0]._y"-
-~("t.de.dly.dly[0].a")->"t.de.dly.dly[0]._y"+
-"t.de.dly.dly[0]._y"->"t.de.dly.dly[0].__y"-
-~("t.de.dly.dly[0]._y")->"t.de.dly.dly[0].__y"+
-"t.de.dly.dly[0].__y"->"t.de.dly.dly[0].___y"-
-~("t.de.dly.dly[0].__y")->"t.de.dly.dly[0].___y"+
-"t.de.dly.dly[0].___y"->"t.de.dly.dly[0].y"-
-~("t.de.dly.dly[0].___y")->"t.de.dly.dly[0].y"+
-"t.de.dly.dly[1].a"->"t.de.dly.dly[1]._y"-
-~("t.de.dly.dly[1].a")->"t.de.dly.dly[1]._y"+
-"t.de.dly.dly[1]._y"->"t.de.dly.dly[1].__y"-
-~("t.de.dly.dly[1]._y")->"t.de.dly.dly[1].__y"+
-"t.de.dly.dly[1].__y"->"t.de.dly.dly[1].___y"-
-~("t.de.dly.dly[1].__y")->"t.de.dly.dly[1].___y"+
-"t.de.dly.dly[1].___y"->"t.de.dly.dly[1].y"-
-~("t.de.dly.dly[1].___y")->"t.de.dly.dly[1].y"+
-"t.de.dly.dly[2].a"->"t.de.dly.dly[2]._y"-
-~("t.de.dly.dly[2].a")->"t.de.dly.dly[2]._y"+
-"t.de.dly.dly[2]._y"->"t.de.dly.dly[2].__y"-
-~("t.de.dly.dly[2]._y")->"t.de.dly.dly[2].__y"+
-"t.de.dly.dly[2].__y"->"t.de.dly.dly[2].___y"-
-~("t.de.dly.dly[2].__y")->"t.de.dly.dly[2].___y"+
-"t.de.dly.dly[2].___y"->"t.de.dly.dly[2].y"-
-~("t.de.dly.dly[2].___y")->"t.de.dly.dly[2].y"+
-"t.de.dly.dly[3].a"->"t.de.dly.dly[3]._y"-
-~("t.de.dly.dly[3].a")->"t.de.dly.dly[3]._y"+
-"t.de.dly.dly[3]._y"->"t.de.dly.dly[3].__y"-
-~("t.de.dly.dly[3]._y")->"t.de.dly.dly[3].__y"+
-"t.de.dly.dly[3].__y"->"t.de.dly.dly[3].___y"-
-~("t.de.dly.dly[3].__y")->"t.de.dly.dly[3].___y"+
-"t.de.dly.dly[3].___y"->"t.de.dly.dly[3].y"-
-~("t.de.dly.dly[3].___y")->"t.de.dly.dly[3].y"+
-"t.de.dly.dly[4].a"->"t.de.dly.dly[4]._y"-
-~("t.de.dly.dly[4].a")->"t.de.dly.dly[4]._y"+
-"t.de.dly.dly[4]._y"->"t.de.dly.dly[4].__y"-
-~("t.de.dly.dly[4]._y")->"t.de.dly.dly[4].__y"+
-"t.de.dly.dly[4].__y"->"t.de.dly.dly[4].___y"-
-~("t.de.dly.dly[4].__y")->"t.de.dly.dly[4].___y"+
-"t.de.dly.dly[4].___y"->"t.de.dly.dly[4].y"-
-~("t.de.dly.dly[4].___y")->"t.de.dly.dly[4].y"+
-"t.de.dly.dly[5].a"->"t.de.dly.dly[5]._y"-
-~("t.de.dly.dly[5].a")->"t.de.dly.dly[5]._y"+
-"t.de.dly.dly[5]._y"->"t.de.dly.dly[5].__y"-
-~("t.de.dly.dly[5]._y")->"t.de.dly.dly[5].__y"+
-"t.de.dly.dly[5].__y"->"t.de.dly.dly[5].___y"-
-~("t.de.dly.dly[5].__y")->"t.de.dly.dly[5].___y"+
-"t.de.dly.dly[5].___y"->"t.de.dly.dly[5].y"-
-~("t.de.dly.dly[5].___y")->"t.de.dly.dly[5].y"+
-"t.de.dly.dly[6].a"->"t.de.dly.dly[6]._y"-
-~("t.de.dly.dly[6].a")->"t.de.dly.dly[6]._y"+
-"t.de.dly.dly[6]._y"->"t.de.dly.dly[6].__y"-
-~("t.de.dly.dly[6]._y")->"t.de.dly.dly[6].__y"+
-"t.de.dly.dly[6].__y"->"t.de.dly.dly[6].___y"-
-~("t.de.dly.dly[6].__y")->"t.de.dly.dly[6].___y"+
-"t.de.dly.dly[6].___y"->"t.de.dly.dly[6].y"-
-~("t.de.dly.dly[6].___y")->"t.de.dly.dly[6].y"+
-"t.de.dly.dly[7].a"->"t.de.dly.dly[7]._y"-
-~("t.de.dly.dly[7].a")->"t.de.dly.dly[7]._y"+
-"t.de.dly.dly[7]._y"->"t.de.dly.dly[7].__y"-
-~("t.de.dly.dly[7]._y")->"t.de.dly.dly[7].__y"+
-"t.de.dly.dly[7].__y"->"t.de.dly.dly[7].___y"-
-~("t.de.dly.dly[7].__y")->"t.de.dly.dly[7].___y"+
-"t.de.dly.dly[7].___y"->"t.de.dly.dly[7].y"-
-~("t.de.dly.dly[7].___y")->"t.de.dly.dly[7].y"+
-"t.de.dly.dly[8].a"->"t.de.dly.dly[8]._y"-
-~("t.de.dly.dly[8].a")->"t.de.dly.dly[8]._y"+
-"t.de.dly.dly[8]._y"->"t.de.dly.dly[8].__y"-
-~("t.de.dly.dly[8]._y")->"t.de.dly.dly[8].__y"+
-"t.de.dly.dly[8].__y"->"t.de.dly.dly[8].___y"-
-~("t.de.dly.dly[8].__y")->"t.de.dly.dly[8].___y"+
-"t.de.dly.dly[8].___y"->"t.de.dly.dly[8].y"-
-~("t.de.dly.dly[8].___y")->"t.de.dly.dly[8].y"+
-"t.de.dly.dly[9].a"->"t.de.dly.dly[9]._y"-
-~("t.de.dly.dly[9].a")->"t.de.dly.dly[9]._y"+
-"t.de.dly.dly[9]._y"->"t.de.dly.dly[9].__y"-
-~("t.de.dly.dly[9]._y")->"t.de.dly.dly[9].__y"+
-"t.de.dly.dly[9].__y"->"t.de.dly.dly[9].___y"-
-~("t.de.dly.dly[9].__y")->"t.de.dly.dly[9].___y"+
-"t.de.dly.dly[9].___y"->"t.de.dly.dly[9].y"-
-~("t.de.dly.dly[9].___y")->"t.de.dly.dly[9].y"+
-"t.de.dly.dly[10].a"->"t.de.dly.dly[10]._y"-
-~("t.de.dly.dly[10].a")->"t.de.dly.dly[10]._y"+
-"t.de.dly.dly[10]._y"->"t.de.dly.dly[10].__y"-
-~("t.de.dly.dly[10]._y")->"t.de.dly.dly[10].__y"+
-"t.de.dly.dly[10].__y"->"t.de.dly.dly[10].___y"-
-~("t.de.dly.dly[10].__y")->"t.de.dly.dly[10].___y"+
-"t.de.dly.dly[10].___y"->"t.de.dly.dly[10].y"-
-~("t.de.dly.dly[10].___y")->"t.de.dly.dly[10].y"+
-"t.de.dly.dly[11].a"->"t.de.dly.dly[11]._y"-
-~("t.de.dly.dly[11].a")->"t.de.dly.dly[11]._y"+
-"t.de.dly.dly[11]._y"->"t.de.dly.dly[11].__y"-
-~("t.de.dly.dly[11]._y")->"t.de.dly.dly[11].__y"+
-"t.de.dly.dly[11].__y"->"t.de.dly.dly[11].___y"-
-~("t.de.dly.dly[11].__y")->"t.de.dly.dly[11].___y"+
-"t.de.dly.dly[11].___y"->"t.de.dly.dly[11].y"-
-~("t.de.dly.dly[11].___y")->"t.de.dly.dly[11].y"+
-"t.de.dly.dly[12].a"->"t.de.dly.dly[12]._y"-
-~("t.de.dly.dly[12].a")->"t.de.dly.dly[12]._y"+
-"t.de.dly.dly[12]._y"->"t.de.dly.dly[12].__y"-
-~("t.de.dly.dly[12]._y")->"t.de.dly.dly[12].__y"+
-"t.de.dly.dly[12].__y"->"t.de.dly.dly[12].___y"-
-~("t.de.dly.dly[12].__y")->"t.de.dly.dly[12].___y"+
-"t.de.dly.dly[12].___y"->"t.de.dly.dly[12].y"-
-~("t.de.dly.dly[12].___y")->"t.de.dly.dly[12].y"+
-"t.de.dly.dly[13].a"->"t.de.dly.dly[13]._y"-
-~("t.de.dly.dly[13].a")->"t.de.dly.dly[13]._y"+
-"t.de.dly.dly[13]._y"->"t.de.dly.dly[13].__y"-
-~("t.de.dly.dly[13]._y")->"t.de.dly.dly[13].__y"+
-"t.de.dly.dly[13].__y"->"t.de.dly.dly[13].___y"-
-~("t.de.dly.dly[13].__y")->"t.de.dly.dly[13].___y"+
-"t.de.dly.dly[13].___y"->"t.de.dly.dly[13].y"-
-~("t.de.dly.dly[13].___y")->"t.de.dly.dly[13].y"+
-"t.de.dly.dly[14].a"->"t.de.dly.dly[14]._y"-
-~("t.de.dly.dly[14].a")->"t.de.dly.dly[14]._y"+
-"t.de.dly.dly[14]._y"->"t.de.dly.dly[14].__y"-
-~("t.de.dly.dly[14]._y")->"t.de.dly.dly[14].__y"+
-"t.de.dly.dly[14].__y"->"t.de.dly.dly[14].___y"-
-~("t.de.dly.dly[14].__y")->"t.de.dly.dly[14].___y"+
-"t.de.dly.dly[14].___y"->"t.de.dly.dly[14].y"-
-~("t.de.dly.dly[14].___y")->"t.de.dly.dly[14].y"+
-= "t.de.dly.dly[14].y" "t.de.dly.mu2[3].b"
-= "t.de.dly.dly[14].a" "t.de.dly.dly[13].y"
-= "t.de.dly.dly[13].a" "t.de.dly.dly[12].y"
-= "t.de.dly.dly[12].a" "t.de.dly.dly[11].y"
-= "t.de.dly.dly[11].a" "t.de.dly.dly[10].y"
-= "t.de.dly.dly[10].a" "t.de.dly.dly[9].y"
-= "t.de.dly.dly[9].a" "t.de.dly.dly[8].y"
-= "t.de.dly.dly[8].a" "t.de.dly.dly[7].y"
-= "t.de.dly.dly[7].a" "t.de.dly.and2[3].y"
-= "t.de.dly.dly[6].y" "t.de.dly.mu2[2].b"
-= "t.de.dly.dly[6].a" "t.de.dly.dly[5].y"
-= "t.de.dly.dly[5].a" "t.de.dly.dly[4].y"
-= "t.de.dly.dly[4].a" "t.de.dly.dly[3].y"
-= "t.de.dly.dly[3].a" "t.de.dly.and2[2].y"
-= "t.de.dly.dly[2].y" "t.de.dly.mu2[1].b"
-= "t.de.dly.dly[2].a" "t.de.dly.dly[1].y"
-= "t.de.dly.dly[1].a" "t.de.dly.and2[1].y"
-= "t.de.dly.dly[0].y" "t.de.dly.mu2[0].b"
-= "t.de.dly.dly[0].a" "t.de.dly.and2[0].y"
-= "t.de.dly._a[1]" "t.de.dly.mu2[1].a"
-= "t.de.dly._a[1]" "t.de.dly.and2[1].a"
-= "t.de.dly._a[1]" "t.de.dly.mu2[0].y"
-= "t.de.dly._a[2]" "t.de.dly.mu2[2].a"
-= "t.de.dly._a[2]" "t.de.dly.and2[2].a"
-= "t.de.dly._a[2]" "t.de.dly.mu2[1].y"
-= "t.de.dly._a[3]" "t.de.dly.mu2[3].a"
-= "t.de.dly._a[3]" "t.de.dly.and2[3].a"
-= "t.de.dly._a[3]" "t.de.dly.mu2[2].y"
-= "t.de.dly.out" "t.de.dly.mu2[3].y"
-= "t.de.dly.out" "t.de.dly._a[4]"
-= "t.de.dly.in" "t.de.dly.mu2[0].a"
-= "t.de.dly.in" "t.de.dly.and2[0].a"
-= "t.de.dly.in" "t.de.dly._a[0]"
-= "t.de.dly.out" "t.de.addr_buf.out.a"
-= "t.de.dly.in" "t.de.addr_buf.out.v"
-= "t.de.dly.in" "t.de.C2el.y"
-= "t.de.atree_y[0].supply.vdd" "t.de.atree_y[0].and2s[0].vdd"
-= "t.de.atree_y[0].supply.vss" "t.de.atree_y[0].and2s[0].vss"
-"t.de.atree_y[0].and2s[0].a"&"t.de.atree_y[0].and2s[0].b"->"t.de.atree_y[0].and2s[0]._y"-
-~("t.de.atree_y[0].and2s[0].a"&"t.de.atree_y[0].and2s[0].b")->"t.de.atree_y[0].and2s[0]._y"+
-"t.de.atree_y[0].and2s[0]._y"->"t.de.atree_y[0].and2s[0].y"-
-~("t.de.atree_y[0].and2s[0]._y")->"t.de.atree_y[0].and2s[0].y"+
-= "t.de.atree_y[0].in[0]" "t.de.atree_y[0].and2s[0].a"
-= "t.de.atree_y[0].in[0]" "t.de.atree_y[0].tmp[0]"
-= "t.de.atree_y[0].in[1]" "t.de.atree_y[0].and2s[0].b"
-= "t.de.atree_y[0].in[1]" "t.de.atree_y[0].tmp[1]"
-= "t.de.atree_y[0].out" "t.de.atree_y[0].and2s[0].y"
-= "t.de.atree_y[0].out" "t.de.atree_y[0].tmp[2]"
-= "t.de.atree_y[1].supply.vdd" "t.de.atree_y[1].and2s[0].vdd"
-= "t.de.atree_y[1].supply.vss" "t.de.atree_y[1].and2s[0].vss"
-"t.de.atree_y[1].and2s[0].a"&"t.de.atree_y[1].and2s[0].b"->"t.de.atree_y[1].and2s[0]._y"-
-~("t.de.atree_y[1].and2s[0].a"&"t.de.atree_y[1].and2s[0].b")->"t.de.atree_y[1].and2s[0]._y"+
-"t.de.atree_y[1].and2s[0]._y"->"t.de.atree_y[1].and2s[0].y"-
-~("t.de.atree_y[1].and2s[0]._y")->"t.de.atree_y[1].and2s[0].y"+
-= "t.de.atree_y[1].in[0]" "t.de.atree_y[1].and2s[0].a"
-= "t.de.atree_y[1].in[0]" "t.de.atree_y[1].tmp[0]"
-= "t.de.atree_y[1].in[1]" "t.de.atree_y[1].and2s[0].b"
-= "t.de.atree_y[1].in[1]" "t.de.atree_y[1].tmp[1]"
-= "t.de.atree_y[1].out" "t.de.atree_y[1].and2s[0].y"
-= "t.de.atree_y[1].out" "t.de.atree_y[1].tmp[2]"
-= "t.de.atree_y[2].supply.vdd" "t.de.atree_y[2].and2s[0].vdd"
-= "t.de.atree_y[2].supply.vss" "t.de.atree_y[2].and2s[0].vss"
-"t.de.atree_y[2].and2s[0].a"&"t.de.atree_y[2].and2s[0].b"->"t.de.atree_y[2].and2s[0]._y"-
-~("t.de.atree_y[2].and2s[0].a"&"t.de.atree_y[2].and2s[0].b")->"t.de.atree_y[2].and2s[0]._y"+
-"t.de.atree_y[2].and2s[0]._y"->"t.de.atree_y[2].and2s[0].y"-
-~("t.de.atree_y[2].and2s[0]._y")->"t.de.atree_y[2].and2s[0].y"+
-= "t.de.atree_y[2].in[0]" "t.de.atree_y[2].and2s[0].a"
-= "t.de.atree_y[2].in[0]" "t.de.atree_y[2].tmp[0]"
-= "t.de.atree_y[2].in[1]" "t.de.atree_y[2].and2s[0].b"
-= "t.de.atree_y[2].in[1]" "t.de.atree_y[2].tmp[1]"
-= "t.de.atree_y[2].out" "t.de.atree_y[2].and2s[0].y"
-= "t.de.atree_y[2].out" "t.de.atree_y[2].tmp[2]"
-= "t.de.atree_y[3].supply.vdd" "t.de.atree_y[3].and2s[0].vdd"
-= "t.de.atree_y[3].supply.vss" "t.de.atree_y[3].and2s[0].vss"
-"t.de.atree_y[3].and2s[0].a"&"t.de.atree_y[3].and2s[0].b"->"t.de.atree_y[3].and2s[0]._y"-
-~("t.de.atree_y[3].and2s[0].a"&"t.de.atree_y[3].and2s[0].b")->"t.de.atree_y[3].and2s[0]._y"+
-"t.de.atree_y[3].and2s[0]._y"->"t.de.atree_y[3].and2s[0].y"-
-~("t.de.atree_y[3].and2s[0]._y")->"t.de.atree_y[3].and2s[0].y"+
-= "t.de.atree_y[3].in[0]" "t.de.atree_y[3].and2s[0].a"
-= "t.de.atree_y[3].in[0]" "t.de.atree_y[3].tmp[0]"
-= "t.de.atree_y[3].in[1]" "t.de.atree_y[3].and2s[0].b"
-= "t.de.atree_y[3].in[1]" "t.de.atree_y[3].tmp[1]"
-= "t.de.atree_y[3].out" "t.de.atree_y[3].and2s[0].y"
-= "t.de.atree_y[3].out" "t.de.atree_y[3].tmp[2]"
-= "t.de.atree_y[3].in[0]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.atree_y[3].in[0]" "t.de.addr_buf.out.d.d[1].d[1]"
-= "t.de.atree_y[3].in[0]" "t.de.vtree_y.in.d[0].t"
-= "t.de.atree_y[3].in[0]" "t.de.vtree_y.in.d[0].d[1]"
-= "t.de.atree_y[3].in[0]" "t.de.atree_y[1].in[0]"
-= "t.de.atree_y[3].in[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.atree_y[3].in[1]" "t.de.addr_buf.out.d.d[2].d[1]"
-= "t.de.atree_y[3].in[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.atree_y[3].in[1]" "t.de.vtree_y.in.d[1].d[1]"
-= "t.de.atree_y[3].in[1]" "t.de.atree_y[2].in[1]"
-= "t.de.atree_y[2].in[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.atree_y[2].in[0]" "t.de.addr_buf.out.d.d[1].d[0]"
-= "t.de.atree_y[2].in[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.atree_y[2].in[0]" "t.de.vtree_y.in.d[0].d[0]"
-= "t.de.atree_y[2].in[0]" "t.de.atree_y[0].in[0]"
-= "t.de.atree_y[1].in[1]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.atree_y[1].in[1]" "t.de.addr_buf.out.d.d[2].d[0]"
-= "t.de.atree_y[1].in[1]" "t.de.vtree_y.in.d[1].f"
-= "t.de.atree_y[1].in[1]" "t.de.vtree_y.in.d[1].d[0]"
-= "t.de.atree_y[1].in[1]" "t.de.atree_y[0].in[1]"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-= "t.de.in.v" "t.de.addr_buf.in.v"
-= "t.de.in.a" "t.de.addr_buf.in.a"
-= "t.de.in.d.d[0].f" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.in.d.d[0].t" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].d[0]"
-= "t.de.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].d[1]"
-= "t.de.in.d.d[1].f" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.in.d.d[1].t" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].d[0]"
-= "t.de.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].d[1]"
-= "t.de.in.d.d[2].f" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.in.d.d[2].t" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].d[0]"
-= "t.de.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].d[1]"
-= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
-= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
-= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
-= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
-= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
-= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
-~"t.de.vtree_y.ct.C2Els[0].c1"&~"t.de.vtree_y.ct.C2Els[0].c2"->"t.de.vtree_y.ct.C2Els[0]._y"+
-"t.de.vtree_y.ct.C2Els[0].c1"&"t.de.vtree_y.ct.C2Els[0].c2"->"t.de.vtree_y.ct.C2Els[0]._y"-
-"t.de.vtree_y.ct.C2Els[0]._y"->"t.de.vtree_y.ct.C2Els[0].y"-
-~("t.de.vtree_y.ct.C2Els[0]._y")->"t.de.vtree_y.ct.C2Els[0].y"+
-= "t.de.vtree_y.ct.supply.vdd" "t.de.vtree_y.ct.C2Els[0].vdd"
-= "t.de.vtree_y.ct.supply.vss" "t.de.vtree_y.ct.C2Els[0].vss"
-= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.ct.C2Els[0].c1"
-= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.ct.tmp[0]"
-= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.ct.C2Els[0].c2"
-= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.ct.tmp[1]"
-= "t.de.vtree_y.ct.out" "t.de.vtree_y.ct.C2Els[0].y"
-= "t.de.vtree_y.ct.out" "t.de.vtree_y.ct.tmp[2]"
-= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.OR2_tf[0].y"
-= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.OR2_tf[1].y"
-"t.de.vtree_y.OR2_tf[0].a"|"t.de.vtree_y.OR2_tf[0].b"->"t.de.vtree_y.OR2_tf[0]._y"-
-~("t.de.vtree_y.OR2_tf[0].a"|"t.de.vtree_y.OR2_tf[0].b")->"t.de.vtree_y.OR2_tf[0]._y"+
-"t.de.vtree_y.OR2_tf[0]._y"->"t.de.vtree_y.OR2_tf[0].y"-
-~("t.de.vtree_y.OR2_tf[0]._y")->"t.de.vtree_y.OR2_tf[0].y"+
-"t.de.vtree_y.OR2_tf[1].a"|"t.de.vtree_y.OR2_tf[1].b"->"t.de.vtree_y.OR2_tf[1]._y"-
-~("t.de.vtree_y.OR2_tf[1].a"|"t.de.vtree_y.OR2_tf[1].b")->"t.de.vtree_y.OR2_tf[1]._y"+
-"t.de.vtree_y.OR2_tf[1]._y"->"t.de.vtree_y.OR2_tf[1].y"-
-~("t.de.vtree_y.OR2_tf[1]._y")->"t.de.vtree_y.OR2_tf[1].y"+
-= "t.de.vtree_y.supply.vss" "t.de.vtree_y.ct.supply.vss"
-= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.ct.supply.vdd"
-= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.OR2_tf[1].vdd"
-= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.OR2_tf[0].vdd"
-= "t.de.vtree_y.supply.vss" "t.de.vtree_y.OR2_tf[1].vss"
-= "t.de.vtree_y.supply.vss" "t.de.vtree_y.OR2_tf[0].vss"
-= "t.de.vtree_y.out" "t.de.vtree_y.ct.out"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.OR2_tf[1].b"
-= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.OR2_tf[1].a"
-= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.OR2_tf[0].b"
-= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.OR2_tf[0].a"
-= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
-= "t.de.outy[0]" "t.de.atree_y[0].out"
-= "t.de.outy[1]" "t.de.atree_y[1].out"
-= "t.de.outy[2]" "t.de.atree_y[2].out"
-= "t.de.outy[3]" "t.de.atree_y[3].out"
-= "t.de.outx[0]" "t.de.atree_x[0].out"
-= "t.de.outx[1]" "t.de.atree_x[1].out"
-= "t.de.reset_B" "t.de.addr_buf.reset_B"
-"t.de.addr_buf.out_a_B_buf_t.buf1.a"->"t.de.addr_buf.out_a_B_buf_t.buf1._y"-
-~("t.de.addr_buf.out_a_B_buf_t.buf1.a")->"t.de.addr_buf.out_a_B_buf_t.buf1._y"+
-"t.de.addr_buf.out_a_B_buf_t.buf1._y"->"t.de.addr_buf.out_a_B_buf_t.buf1.y"-
-~("t.de.addr_buf.out_a_B_buf_t.buf1._y")->"t.de.addr_buf.out_a_B_buf_t.buf1.y"+
-= "t.de.addr_buf.out_a_B_buf_t.supply.vdd" "t.de.addr_buf.out_a_B_buf_t.buf1.vdd"
-= "t.de.addr_buf.out_a_B_buf_t.supply.vss" "t.de.addr_buf.out_a_B_buf_t.buf1.vss"
-= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.out[2]"
-= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.out[1]"
-= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.buf1.y"
-= "t.de.addr_buf.out_a_B_buf_t.in" "t.de.addr_buf.out_a_B_buf_t.buf1.a"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.en_buf_f.out[0]"
-= "t.de.addr_buf._en_X_f[1]" "t.de.addr_buf.en_buf_f.out[1]"
-= "t.de.addr_buf._en_X_f[2]" "t.de.addr_buf.en_buf_f.out[2]"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[2].c1"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[1].c1"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[0].c1"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf._en_X_f[2]"
-= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf._en_X_f[1]"
-~"t.de.addr_buf.inack_ctl.c1"&~"t.de.addr_buf.inack_ctl.c2"&~"t.de.addr_buf.inack_ctl.c3"|~"t.de.addr_buf.inack_ctl.pr_B"->"t.de.addr_buf.inack_ctl._y"+
-"t.de.addr_buf.inack_ctl.c1"&"t.de.addr_buf.inack_ctl.c2"&"t.de.addr_buf.inack_ctl.c3"&"t.de.addr_buf.inack_ctl.sr_B"->"t.de.addr_buf.inack_ctl._y"-
-"t.de.addr_buf.inack_ctl._y"->"t.de.addr_buf.inack_ctl.y"-
-~("t.de.addr_buf.inack_ctl._y")->"t.de.addr_buf.inack_ctl.y"+
-"t.de.addr_buf.reset_bufarray.buf1.a"->"t.de.addr_buf.reset_bufarray.buf1._y"-
-~("t.de.addr_buf.reset_bufarray.buf1.a")->"t.de.addr_buf.reset_bufarray.buf1._y"+
-"t.de.addr_buf.reset_bufarray.buf1._y"->"t.de.addr_buf.reset_bufarray.buf1.y"-
-~("t.de.addr_buf.reset_bufarray.buf1._y")->"t.de.addr_buf.reset_bufarray.buf1.y"+
-= "t.de.addr_buf.reset_bufarray.supply.vdd" "t.de.addr_buf.reset_bufarray.buf1.vdd"
-= "t.de.addr_buf.reset_bufarray.supply.vss" "t.de.addr_buf.reset_bufarray.buf1.vss"
-= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.out[2]"
-= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.out[1]"
-= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.buf1.y"
-= "t.de.addr_buf.reset_bufarray.in" "t.de.addr_buf.reset_bufarray.buf1.a"
-"t.de.addr_buf.in_v_buf.a"->"t.de.addr_buf.in_v_buf._y"-
-~("t.de.addr_buf.in_v_buf.a")->"t.de.addr_buf.in_v_buf._y"+
-"t.de.addr_buf.in_v_buf._y"->"t.de.addr_buf.in_v_buf.y"-
-~("t.de.addr_buf.in_v_buf._y")->"t.de.addr_buf.in_v_buf.y"+
-"t.de.addr_buf.out_a_inv.a"->"t.de.addr_buf.out_a_inv.y"-
-~("t.de.addr_buf.out_a_inv.a")->"t.de.addr_buf.out_a_inv.y"+
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_buf_f.supply.vss"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_buf_f.supply.vdd"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_buf_t.supply.vss"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_buf_t.supply.vdd"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.vc.supply.vss"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.vc.supply.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[2].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[2].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[1].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[1].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[0].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[0].vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.in_v_buf.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.reset_buf.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_ctl.vdd"
-= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.inack_ctl.vdd"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[2].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[2].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[1].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[1].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[0].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[0].vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.in_v_buf.vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.reset_buf.vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_ctl.vss"
-= "t.de.addr_buf.supply.vss" "t.de.addr_buf.inack_ctl.vss"
-~"t.de.addr_buf.vc.ct.C3Els[0].c1"&~"t.de.addr_buf.vc.ct.C3Els[0].c2"&~"t.de.addr_buf.vc.ct.C3Els[0].c3"->"t.de.addr_buf.vc.ct.C3Els[0]._y"+
-"t.de.addr_buf.vc.ct.C3Els[0].c1"&"t.de.addr_buf.vc.ct.C3Els[0].c2"&"t.de.addr_buf.vc.ct.C3Els[0].c3"->"t.de.addr_buf.vc.ct.C3Els[0]._y"-
-"t.de.addr_buf.vc.ct.C3Els[0]._y"->"t.de.addr_buf.vc.ct.C3Els[0].y"-
-~("t.de.addr_buf.vc.ct.C3Els[0]._y")->"t.de.addr_buf.vc.ct.C3Els[0].y"+
-= "t.de.addr_buf.vc.ct.supply.vdd" "t.de.addr_buf.vc.ct.C3Els[0].vdd"
-= "t.de.addr_buf.vc.ct.supply.vss" "t.de.addr_buf.vc.ct.C3Els[0].vss"
-= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.ct.C3Els[0].c1"
-= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.ct.tmp[0]"
-= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.ct.C3Els[0].c2"
-= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.ct.tmp[1]"
-= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.ct.C3Els[0].c3"
-= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.ct.tmp[2]"
-= "t.de.addr_buf.vc.ct.out" "t.de.addr_buf.vc.ct.C3Els[0].y"
-= "t.de.addr_buf.vc.ct.out" "t.de.addr_buf.vc.ct.tmp[3]"
-= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.OR2_tf[0].y"
-= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.OR2_tf[1].y"
-= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.OR2_tf[2].y"
-"t.de.addr_buf.vc.OR2_tf[0].a"|"t.de.addr_buf.vc.OR2_tf[0].b"->"t.de.addr_buf.vc.OR2_tf[0]._y"-
-~("t.de.addr_buf.vc.OR2_tf[0].a"|"t.de.addr_buf.vc.OR2_tf[0].b")->"t.de.addr_buf.vc.OR2_tf[0]._y"+
-"t.de.addr_buf.vc.OR2_tf[0]._y"->"t.de.addr_buf.vc.OR2_tf[0].y"-
-~("t.de.addr_buf.vc.OR2_tf[0]._y")->"t.de.addr_buf.vc.OR2_tf[0].y"+
-"t.de.addr_buf.vc.OR2_tf[1].a"|"t.de.addr_buf.vc.OR2_tf[1].b"->"t.de.addr_buf.vc.OR2_tf[1]._y"-
-~("t.de.addr_buf.vc.OR2_tf[1].a"|"t.de.addr_buf.vc.OR2_tf[1].b")->"t.de.addr_buf.vc.OR2_tf[1]._y"+
-"t.de.addr_buf.vc.OR2_tf[1]._y"->"t.de.addr_buf.vc.OR2_tf[1].y"-
-~("t.de.addr_buf.vc.OR2_tf[1]._y")->"t.de.addr_buf.vc.OR2_tf[1].y"+
-"t.de.addr_buf.vc.OR2_tf[2].a"|"t.de.addr_buf.vc.OR2_tf[2].b"->"t.de.addr_buf.vc.OR2_tf[2]._y"-
-~("t.de.addr_buf.vc.OR2_tf[2].a"|"t.de.addr_buf.vc.OR2_tf[2].b")->"t.de.addr_buf.vc.OR2_tf[2]._y"+
-"t.de.addr_buf.vc.OR2_tf[2]._y"->"t.de.addr_buf.vc.OR2_tf[2].y"-
-~("t.de.addr_buf.vc.OR2_tf[2]._y")->"t.de.addr_buf.vc.OR2_tf[2].y"+
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.ct.supply.vss"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.ct.supply.vdd"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[2].vdd"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[1].vdd"
-= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[0].vdd"
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[2].vss"
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[1].vss"
-= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[0].vss"
-= "t.de.addr_buf.vc.out" "t.de.addr_buf.vc.ct.out"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.OR2_tf[2].b"
-= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.OR2_tf[2].a"
-= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.OR2_tf[1].b"
-= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.OR2_tf[1].a"
-= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.OR2_tf[0].b"
-= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.OR2_tf[0].a"
-= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.out_a_B_buf_t.out[0]"
-= "t.de.addr_buf._out_a_BX_f[1]" "t.de.addr_buf.out_a_B_buf_t.out[1]"
-= "t.de.addr_buf._out_a_BX_f[2]" "t.de.addr_buf.out_a_B_buf_t.out[2]"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[2].c2"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[1].c2"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[0].c2"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf._out_a_BX_f[2]"
-= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf._out_a_BX_f[1]"
-"t.de.addr_buf.out_a_B_buf_f.buf1.a"->"t.de.addr_buf.out_a_B_buf_f.buf1._y"-
-~("t.de.addr_buf.out_a_B_buf_f.buf1.a")->"t.de.addr_buf.out_a_B_buf_f.buf1._y"+
-"t.de.addr_buf.out_a_B_buf_f.buf1._y"->"t.de.addr_buf.out_a_B_buf_f.buf1.y"-
-~("t.de.addr_buf.out_a_B_buf_f.buf1._y")->"t.de.addr_buf.out_a_B_buf_f.buf1.y"+
-= "t.de.addr_buf.out_a_B_buf_f.supply.vdd" "t.de.addr_buf.out_a_B_buf_f.buf1.vdd"
-= "t.de.addr_buf.out_a_B_buf_f.supply.vss" "t.de.addr_buf.out_a_B_buf_f.buf1.vss"
-= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.out[2]"
-= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.out[1]"
-= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.buf1.y"
-= "t.de.addr_buf.out_a_B_buf_f.in" "t.de.addr_buf.out_a_B_buf_f.buf1.a"
-= "t.de.addr_buf._en" "t.de.addr_buf.en_buf_f.in"
-= "t.de.addr_buf._en" "t.de.addr_buf.en_buf_t.in"
-= "t.de.addr_buf._en" "t.de.addr_buf.en_ctl.y"
-= "t.de.addr_buf._en" "t.de.addr_buf.inack_ctl.c1"
-~"t.de.addr_buf.en_ctl.p1"&~"t.de.addr_buf.en_ctl.c1"->"t.de.addr_buf.en_ctl.y"+
-"t.de.addr_buf.en_ctl.c1"->"t.de.addr_buf.en_ctl.y"-
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.out.a" "t.de.addr_buf.out_a_inv.a"
-= "t.de.addr_buf.out.v" "t.de.addr_buf.en_ctl.p1"
-= "t.de.addr_buf.out.v" "t.de.addr_buf.inack_ctl.c3"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.f_buf_func[2].y"
-= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.t_buf_func[2].y"
-= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.f_buf_func[1].y"
-= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.t_buf_func[1].y"
-= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.f_buf_func[0].y"
-= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.t_buf_func[0].y"
-= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-= "t.de.addr_buf.in.d.d[0].f" "t.de.addr_buf.vc.in.d[0].f"
-= "t.de.addr_buf.in.d.d[0].t" "t.de.addr_buf.vc.in.d[0].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].d[0]"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].d[1]"
-= "t.de.addr_buf.in.d.d[1].f" "t.de.addr_buf.vc.in.d[1].f"
-= "t.de.addr_buf.in.d.d[1].t" "t.de.addr_buf.vc.in.d[1].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].d[0]"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].d[1]"
-= "t.de.addr_buf.in.d.d[2].f" "t.de.addr_buf.vc.in.d[2].f"
-= "t.de.addr_buf.in.d.d[2].t" "t.de.addr_buf.vc.in.d[2].t"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].d[0]"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].d[1]"
-= "t.de.addr_buf.in.a" "t.de.addr_buf.en_ctl.c1"
-= "t.de.addr_buf.in.a" "t.de.addr_buf.inack_ctl.y"
-= "t.de.addr_buf.in.v" "t.de.addr_buf.in_v_buf.y"
-= "t.de.addr_buf.in.v" "t.de.addr_buf.inack_ctl.c2"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.f_buf_func[2].n1"
-= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.t_buf_func[2].n1"
-= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.f_buf_func[1].n1"
-= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.t_buf_func[1].n1"
-= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.f_buf_func[0].n1"
-= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.t_buf_func[0].n1"
-= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
-"t.de.addr_buf.reset_buf.a"->"t.de.addr_buf.reset_buf._y"-
-~("t.de.addr_buf.reset_buf.a")->"t.de.addr_buf.reset_buf._y"+
-"t.de.addr_buf.reset_buf._y"->"t.de.addr_buf.reset_buf.y"-
-~("t.de.addr_buf.reset_buf._y")->"t.de.addr_buf.reset_buf.y"+
-= "t.de.addr_buf._in_v" "t.de.addr_buf.in_v_buf.a"
-= "t.de.addr_buf._in_v" "t.de.addr_buf.vc.out"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.reset_bufarray.in"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.reset_buf.y"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.inack_ctl.sr_B"
-= "t.de.addr_buf._reset_BX" "t.de.addr_buf.inack_ctl.pr_B"
-= "t.de.addr_buf.reset_B" "t.de.addr_buf.reset_buf.a"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.out_a_B_buf_f.out[0]"
-= "t.de.addr_buf._out_a_BX_t[1]" "t.de.addr_buf.out_a_B_buf_f.out[1]"
-= "t.de.addr_buf._out_a_BX_t[2]" "t.de.addr_buf.out_a_B_buf_f.out[2]"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[2].c2"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[1].c2"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[0].c2"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf._out_a_BX_t[2]"
-= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf._out_a_BX_t[1]"
-"t.de.addr_buf.en_buf_f.buf1.a"->"t.de.addr_buf.en_buf_f.buf1._y"-
-~("t.de.addr_buf.en_buf_f.buf1.a")->"t.de.addr_buf.en_buf_f.buf1._y"+
-"t.de.addr_buf.en_buf_f.buf1._y"->"t.de.addr_buf.en_buf_f.buf1.y"-
-~("t.de.addr_buf.en_buf_f.buf1._y")->"t.de.addr_buf.en_buf_f.buf1.y"+
-= "t.de.addr_buf.en_buf_f.supply.vdd" "t.de.addr_buf.en_buf_f.buf1.vdd"
-= "t.de.addr_buf.en_buf_f.supply.vss" "t.de.addr_buf.en_buf_f.buf1.vss"
-= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.out[2]"
-= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.out[1]"
-= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.buf1.y"
-= "t.de.addr_buf.en_buf_f.in" "t.de.addr_buf.en_buf_f.buf1.a"
-"t.de.addr_buf.en_buf_t.buf1.a"->"t.de.addr_buf.en_buf_t.buf1._y"-
-~("t.de.addr_buf.en_buf_t.buf1.a")->"t.de.addr_buf.en_buf_t.buf1._y"+
-"t.de.addr_buf.en_buf_t.buf1._y"->"t.de.addr_buf.en_buf_t.buf1.y"-
-~("t.de.addr_buf.en_buf_t.buf1._y")->"t.de.addr_buf.en_buf_t.buf1.y"+
-= "t.de.addr_buf.en_buf_t.supply.vdd" "t.de.addr_buf.en_buf_t.buf1.vdd"
-= "t.de.addr_buf.en_buf_t.supply.vss" "t.de.addr_buf.en_buf_t.buf1.vss"
-= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.out[2]"
-= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.out[1]"
-= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.buf1.y"
-= "t.de.addr_buf.en_buf_t.in" "t.de.addr_buf.en_buf_t.buf1.a"
-= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_B_buf_t.in"
-= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_B_buf_f.in"
-= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_inv.y"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.reset_bufarray.out[0]"
-= "t.de.addr_buf._reset_BXX[1]" "t.de.addr_buf.reset_bufarray.out[1]"
-= "t.de.addr_buf._reset_BXX[2]" "t.de.addr_buf.reset_bufarray.out[2]"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[2].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[2].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[2].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[2].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[1].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[1].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[1].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[1].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[0].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[0].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[0].sr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[0].pr_B"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf._reset_BXX[2]"
-= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf._reset_BXX[1]"
-~"t.de.addr_buf.t_buf_func[0].c1"&~"t.de.addr_buf.t_buf_func[0].c2"|~"t.de.addr_buf.t_buf_func[0].pr_B"->"t.de.addr_buf.t_buf_func[0]._y"+
-"t.de.addr_buf.t_buf_func[0].c1"&"t.de.addr_buf.t_buf_func[0].c2"&"t.de.addr_buf.t_buf_func[0].n1"&"t.de.addr_buf.t_buf_func[0].sr_B"->"t.de.addr_buf.t_buf_func[0]._y"-
-"t.de.addr_buf.t_buf_func[0]._y"->"t.de.addr_buf.t_buf_func[0].y"-
-~("t.de.addr_buf.t_buf_func[0]._y")->"t.de.addr_buf.t_buf_func[0].y"+
-~"t.de.addr_buf.t_buf_func[1].c1"&~"t.de.addr_buf.t_buf_func[1].c2"|~"t.de.addr_buf.t_buf_func[1].pr_B"->"t.de.addr_buf.t_buf_func[1]._y"+
-"t.de.addr_buf.t_buf_func[1].c1"&"t.de.addr_buf.t_buf_func[1].c2"&"t.de.addr_buf.t_buf_func[1].n1"&"t.de.addr_buf.t_buf_func[1].sr_B"->"t.de.addr_buf.t_buf_func[1]._y"-
-"t.de.addr_buf.t_buf_func[1]._y"->"t.de.addr_buf.t_buf_func[1].y"-
-~("t.de.addr_buf.t_buf_func[1]._y")->"t.de.addr_buf.t_buf_func[1].y"+
-~"t.de.addr_buf.t_buf_func[2].c1"&~"t.de.addr_buf.t_buf_func[2].c2"|~"t.de.addr_buf.t_buf_func[2].pr_B"->"t.de.addr_buf.t_buf_func[2]._y"+
-"t.de.addr_buf.t_buf_func[2].c1"&"t.de.addr_buf.t_buf_func[2].c2"&"t.de.addr_buf.t_buf_func[2].n1"&"t.de.addr_buf.t_buf_func[2].sr_B"->"t.de.addr_buf.t_buf_func[2]._y"-
-"t.de.addr_buf.t_buf_func[2]._y"->"t.de.addr_buf.t_buf_func[2].y"-
-~("t.de.addr_buf.t_buf_func[2]._y")->"t.de.addr_buf.t_buf_func[2].y"+
-~"t.de.addr_buf.f_buf_func[0].c1"&~"t.de.addr_buf.f_buf_func[0].c2"|~"t.de.addr_buf.f_buf_func[0].pr_B"->"t.de.addr_buf.f_buf_func[0]._y"+
-"t.de.addr_buf.f_buf_func[0].c1"&"t.de.addr_buf.f_buf_func[0].c2"&"t.de.addr_buf.f_buf_func[0].n1"&"t.de.addr_buf.f_buf_func[0].sr_B"->"t.de.addr_buf.f_buf_func[0]._y"-
-"t.de.addr_buf.f_buf_func[0]._y"->"t.de.addr_buf.f_buf_func[0].y"-
-~("t.de.addr_buf.f_buf_func[0]._y")->"t.de.addr_buf.f_buf_func[0].y"+
-~"t.de.addr_buf.f_buf_func[1].c1"&~"t.de.addr_buf.f_buf_func[1].c2"|~"t.de.addr_buf.f_buf_func[1].pr_B"->"t.de.addr_buf.f_buf_func[1]._y"+
-"t.de.addr_buf.f_buf_func[1].c1"&"t.de.addr_buf.f_buf_func[1].c2"&"t.de.addr_buf.f_buf_func[1].n1"&"t.de.addr_buf.f_buf_func[1].sr_B"->"t.de.addr_buf.f_buf_func[1]._y"-
-"t.de.addr_buf.f_buf_func[1]._y"->"t.de.addr_buf.f_buf_func[1].y"-
-~("t.de.addr_buf.f_buf_func[1]._y")->"t.de.addr_buf.f_buf_func[1].y"+
-~"t.de.addr_buf.f_buf_func[2].c1"&~"t.de.addr_buf.f_buf_func[2].c2"|~"t.de.addr_buf.f_buf_func[2].pr_B"->"t.de.addr_buf.f_buf_func[2]._y"+
-"t.de.addr_buf.f_buf_func[2].c1"&"t.de.addr_buf.f_buf_func[2].c2"&"t.de.addr_buf.f_buf_func[2].n1"&"t.de.addr_buf.f_buf_func[2].sr_B"->"t.de.addr_buf.f_buf_func[2]._y"-
-"t.de.addr_buf.f_buf_func[2]._y"->"t.de.addr_buf.f_buf_func[2].y"-
-~("t.de.addr_buf.f_buf_func[2]._y")->"t.de.addr_buf.f_buf_func[2].y"+
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.en_buf_t.out[0]"
-= "t.de.addr_buf._en_X_t[1]" "t.de.addr_buf.en_buf_t.out[1]"
-= "t.de.addr_buf._en_X_t[2]" "t.de.addr_buf.en_buf_t.out[2]"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[2].c1"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[1].c1"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[0].c1"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf._en_X_t[2]"
-= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf._en_X_t[1]"
-"t.de.vtree_x.ct.b.a"->"t.de.vtree_x.ct.b._y"-
-~("t.de.vtree_x.ct.b.a")->"t.de.vtree_x.ct.b._y"+
-"t.de.vtree_x.ct.b._y"->"t.de.vtree_x.ct.b.y"-
-~("t.de.vtree_x.ct.b._y")->"t.de.vtree_x.ct.b.y"+
-= "t.de.vtree_x.ct.supply.vdd" "t.de.vtree_x.ct.b.vdd"
-= "t.de.vtree_x.ct.supply.vss" "t.de.vtree_x.ct.b.vss"
-= "t.de.vtree_x.ct.out" "t.de.vtree_x.ct.b.y"
-= "t.de.vtree_x.ct.in[0]" "t.de.vtree_x.ct.b.a"
-= "t.de.vtree_x.ct.in[0]" "t.de.vtree_x.OR2_tf[0].y"
-"t.de.vtree_x.OR2_tf[0].a"|"t.de.vtree_x.OR2_tf[0].b"->"t.de.vtree_x.OR2_tf[0]._y"-
-~("t.de.vtree_x.OR2_tf[0].a"|"t.de.vtree_x.OR2_tf[0].b")->"t.de.vtree_x.OR2_tf[0]._y"+
-"t.de.vtree_x.OR2_tf[0]._y"->"t.de.vtree_x.OR2_tf[0].y"-
-~("t.de.vtree_x.OR2_tf[0]._y")->"t.de.vtree_x.OR2_tf[0].y"+
-= "t.de.vtree_x.supply.vss" "t.de.vtree_x.ct.supply.vss"
-= "t.de.vtree_x.supply.vdd" "t.de.vtree_x.ct.supply.vdd"
-= "t.de.vtree_x.supply.vdd" "t.de.vtree_x.OR2_tf[0].vdd"
-= "t.de.vtree_x.supply.vss" "t.de.vtree_x.OR2_tf[0].vss"
-= "t.de.vtree_x.out" "t.de.vtree_x.ct.out"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.OR2_tf[0].b"
-= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.OR2_tf[0].a"
-= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
-= "Vdd" "t.de.supply.vdd"
-= "GND" "t.de.supply.vss"
-= "t.dly_cfg[0]" "t.de.dly_cfg[0]"
-= "t.dly_cfg[1]" "t.de.dly_cfg[1]"
-= "t.dly_cfg[2]" "t.de.dly_cfg[2]"
-= "t.dly_cfg[3]" "t.de.dly_cfg[3]"
-= "t.out[0]" "t.ag.out[0]"
-= "t.out[1]" "t.ag.out[1]"
-= "t.out[2]" "t.ag.out[2]"
-= "t.out[3]" "t.ag.out[3]"
-= "t.out[4]" "t.ag.out[4]"
-= "t.out[5]" "t.ag.out[5]"
-= "t.out[6]" "t.ag.out[6]"
-= "t.out[7]" "t.ag.out[7]"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
-= "t.in.v" "t.de.in.v"
-= "t.in.a" "t.de.in.a"
-= "t.in.d.d[0].f" "t.de.in.d.d[0].f"
-= "t.in.d.d[0].t" "t.de.in.d.d[0].t"
-= "t.in.d.d[0].d[0]" "t.de.in.d.d[0].d[0]"
-= "t.in.d.d[0].d[1]" "t.de.in.d.d[0].d[1]"
-= "t.in.d.d[1].f" "t.de.in.d.d[1].f"
-= "t.in.d.d[1].t" "t.de.in.d.d[1].t"
-= "t.in.d.d[1].d[0]" "t.de.in.d.d[1].d[0]"
-= "t.in.d.d[1].d[1]" "t.de.in.d.d[1].d[1]"
-= "t.in.d.d[2].f" "t.de.in.d.d[2].f"
-= "t.in.d.d[2].t" "t.de.in.d.d[2].t"
-= "t.in.d.d[2].d[0]" "t.de.in.d.d[2].d[0]"
-= "t.in.d.d[2].d[1]" "t.de.in.d.d[2].d[1]"
-= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
-= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
-= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
-= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
-= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
-= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"

test/unit_tests/decoder_2d_hs/run/prsim.out

@@ -0,0 +1,460 @@
+e.in.d.d[2].t e.in.d.d[1].f e.in.d.d[0].f e.in.d.d[2].f e.decoder.addr_buf._in_v e.in.d.d[1].t e.decoder.addr_buf.vc.ct.in[0] e.decoder.addr_buf.vc.ct.in[1] e.in.d.d[0].t e.decoder.addr_buf.vc.ct.C3Els[0]._y e.decoder.addr_buf.vc.OR2_tf[0]._y e.in.v e.decoder.addr_buf.in_v_buf._y e.decoder.addr_buf.vc.ct.in[2] e.decoder.addr_buf.vc.OR2_tf[2]._y e.decoder.addr_buf.vc.OR2_tf[1]._y 
+	    162088 e.in.d.d[0].f : 0
+	    162088 e.in.d.d[2].t : 0
+	    162088 e.in.d.d[2].f : 0
+	    162088 e.in.d.d[1].t : 0
+	    162088 e.in.d.d[1].f : 0
+	    162088 e.in.d.d[0].t : 0
+	    162104 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1  [by e.in.d.d[1].f:=0]
+	    162632 e.decoder.addr_buf.vc.ct.in[1] : 0  [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
+	    164729 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1  [by e.in.d.d[2].f:=0]
+	    166650 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1  [by e.in.d.d[0].t:=0]
+	    167164 e.decoder.addr_buf.vc.ct.in[2] : 0  [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
+	    193530 e.decoder.addr_buf.vc.ct.in[0] : 0  [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
+	    217455 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1  [by e.decoder.addr_buf.vc.ct.in[0]:=0]
+	    230496 e.decoder.addr_buf._in_v : 0  [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
+	    230498 e.decoder.addr_buf.in_v_buf._y : 1  [by e.decoder.addr_buf._in_v:=0]
+	    291456 e.in.v : 0  [by e.decoder.addr_buf.in_v_buf._y:=1]
+[] Set reset 0
+
+	    291456 Reset : 0
+	    291459 e._reset_B : 1  [by Reset:=0]
+	    291488 e.decoder.addr_buf.reset_buf._y : 0  [by e._reset_B:=1]
+	    291805 e.decoder.addr_buf._reset_BX : 1  [by e.decoder.addr_buf.reset_buf._y:=0]
+	    293406 e.decoder.addr_buf.reset_bufarray.buf1._y : 0  [by e.decoder.addr_buf._reset_BX:=1]
+	    293559 e.decoder.addr_buf._reset_BXX[0] : 1  [by e.decoder.addr_buf.reset_bufarray.buf1._y:=0]
+[] Sending in a 7 packet
+	    293559 e.in.d.d[0].t : 1
+	    293559 e.in.d.d[2].t : 1
+	    293559 e.in.d.d[1].t : 1
+	    293560 e.decoder.addr_buf.t_buf_func[2]._y : 0  [by e.in.d.d[2].t:=1]
+	    293561 e.decoder.d_dr_y.in_tX[1].in : 1  [by e.decoder.addr_buf.t_buf_func[2]._y:=0]
+	    293581 e.decoder.addr_buf.t_buf_func[1]._y : 0  [by e.in.d.d[1].t:=1]
+	    293603 e.decoder.addr_buf.vc.OR2_tf[0]._y : 0  [by e.in.d.d[0].t:=1]
+	    293740 e.decoder.d_dr_y.in_tX[0].in : 1  [by e.decoder.addr_buf.t_buf_func[1]._y:=0]
+	    293776 e.decoder.addr_buf.vc.OR2_tf[1]._y : 0  [by e.in.d.d[1].t:=1]
+	    293921 e.decoder.addr_buf.vc.ct.in[1] : 1  [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=0]
+	    295027 e.decoder.d_dr_y.in_tX[0].buf1._y : 0  [by e.decoder.d_dr_y.in_tX[0].in:=1]
+	    295142 e.decoder.d_dr_y.in_tX[1].buf1._y : 0  [by e.decoder.d_dr_y.in_tX[1].in:=1]
+	    295972 e.decoder.vtree_y.OR2_tf[0]._y : 0  [by e.decoder.d_dr_y.in_tX[0].in:=1]
+	    295973 e.decoder.vtree_y.ct.in[0] : 1  [by e.decoder.vtree_y.OR2_tf[0]._y:=0]
+	    296320 e.decoder.addr_buf.t_buf_func[0]._y : 0  [by e.in.d.d[0].t:=1]
+	    297859 e.decoder.d_dr_y.atree[1].in[0] : 1  [by e.decoder.d_dr_y.in_tX[0].buf1._y:=0]
+	    301496 e.decoder.d_dr_y.atree[2].in[1] : 1  [by e.decoder.d_dr_y.in_tX[1].buf1._y:=0]
+	    301658 e.decoder.d_dr_y.atree[3].and2s[0]._y : 0  [by e.decoder.d_dr_y.atree[2].in[1]:=1]
+	    302906 e.decoder.vtree_y.OR2_tf[1]._y : 0  [by e.decoder.d_dr_y.in_tX[1].in:=1]
+	    302920 e.decoder.vtree_y.ct.in[1] : 1  [by e.decoder.vtree_y.OR2_tf[1]._y:=0]
+	    302927 e.decoder.vtree_y.ct.C2Els[0]._y : 0  [by e.decoder.vtree_y.ct.in[1]:=1]
+	    303087 e.decoder.vtree_y.out : 1  [by e.decoder.vtree_y.ct.C2Els[0]._y:=0]
+	    307242 e.decoder.addr_buf.vc.OR2_tf[2]._y : 0  [by e.in.d.d[2].t:=1]
+	    309027 e.decoder.d_dr_y.out[3] : 1  [by e.decoder.d_dr_y.atree[3].and2s[0]._y:=0]
+	    309028 e.decoder._and_grid.ybuf[3].buf1._y : 0  [by e.decoder.d_dr_y.out[3]:=1]
+	    309029 e.decoder._and_grid.ands[6].b : 1  [by e.decoder._and_grid.ybuf[3].buf1._y:=0]
+	    313279 e.decoder.addr_buf.vc.ct.in[0] : 1  [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=0]
+	    328799 e.decoder.addr_buf.vc.ct.in[2] : 1  [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=0]
+	    328800 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 0  [by e.decoder.addr_buf.vc.ct.in[2]:=1]
+	    331043 e.decoder.addr_buf._in_v : 1  [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=0]
+	    331230 e.decoder.addr_buf.in_v_buf._y : 0  [by e.decoder.addr_buf._in_v:=1]
+	    331231 e.in.v : 1  [by e.decoder.addr_buf.in_v_buf._y:=0]
+	    335604 e.decoder.d_dr_x.in_tX[0].in : 1  [by e.decoder.addr_buf.t_buf_func[0]._y:=0]
+	    339786 e.decoder.d_dr_x.in_tX[0].buf1._y : 0  [by e.decoder.d_dr_x.in_tX[0].in:=1]
+	    339787 e.decoder.d_dr_x.atree[1].in[0] : 1  [by e.decoder.d_dr_x.in_tX[0].buf1._y:=0]
+	    340640 e.decoder.d_dr_x.atree[1].b._y : 0  [by e.decoder.d_dr_x.atree[1].in[0]:=1]
+	    340645 e.decoder.d_dr_x.out[1] : 1  [by e.decoder.d_dr_x.atree[1].b._y:=0]
+	    340646 e.decoder.d_dr_xX[1].buf2._y : 0  [by e.decoder.d_dr_x.out[1]:=1]
+	    340663 e.decoder.pu_ANDs[1].a : 1  [by e.decoder.d_dr_xX[1].buf2._y:=0]
+	    341536 e.decoder._and_grid.xbuf[1].buf1._y : 0  [by e.decoder.d_dr_x.out[1]:=1]
+	    343236 e.decoder.pu_ANDs[1]._y : 0  [by e.decoder.pu_ANDs[1].a:=1]
+	    343239 e.decoder.pu[1].a : 1  [by e.decoder.pu_ANDs[1]._y:=0]
+	    349897 e.decoder._and_grid.ands[1].a : 1  [by e.decoder._and_grid.xbuf[1].buf1._y:=0]
+	    350838 e.decoder._and_grid.ands[7]._y : 0  [by e.decoder._and_grid.ands[1].a:=1]
+	    370386 e.decoder.vtree_x.OR2_tf[0]._y : 0  [by e.decoder.d_dr_x.in_tX[0].in:=1]
+	    370387 e.decoder.vtree_x.ct.in[0] : 1  [by e.decoder.vtree_x.OR2_tf[0]._y:=0]
+	    370429 e.decoder.vtree_x.ct.b._y : 0  [by e.decoder.vtree_x.ct.in[0]:=1]
+	    373246 e.decoder.vtree_x.out : 1  [by e.decoder.vtree_x.ct.b._y:=0]
+	    386979 e.decoder.valid_Cel._y : 0  [by e.decoder.vtree_x.out:=1]
+	    387074 e.decoder.valid_Cel.y : 1  [by e.decoder.valid_Cel._y:=0]
+	    387409 e.decoder.addr_buf.inack_ctl._y : 0  [by e.decoder.valid_Cel.y:=1]
+	    387417 e.in.a : 1  [by e.decoder.addr_buf.inack_ctl._y:=0]
+	    387451 e.decoder.addr_buf._en : 0  [by e.in.a:=1]
+	    388369 e.decoder.addr_buf.en_buf_t.buf1._y : 1  [by e.decoder.addr_buf._en:=0]
+	    388373 e.decoder.addr_buf._en_X_t[0] : 0  [by e.decoder.addr_buf.en_buf_t.buf1._y:=1]
+	    401338 e.decoder.addr_buf.en_buf_f.buf1._y : 1  [by e.decoder.addr_buf._en:=0]
+	    409800 e.out[7].r : 1  [by e.decoder._and_grid.ands[7]._y:=0]
+	    412198 e.synapses[7].y : 0  [by e.out[7].r:=1]
+	    447716 e.decoder.addr_buf._en_X_f[0] : 0  [by e.decoder.addr_buf.en_buf_f.buf1._y:=1]
+[] Removing input
+[] Synapse [7] gives ack
+	    447716 e.in.d.d[0].t : 0
+	    447716 e.out[7].a : 1
+	    447716 e.in.d.d[2].t : 0
+	    447716 e.in.d.d[1].t : 0
+	    447719 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1  [by e.in.d.d[1].t:=0]
+	    447764 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1  [by e.in.d.d[2].t:=0]
+	    447897 e.decoder.addr_buf.vc.ct.in[1] : 0  [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
+	    450931 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1  [by e.in.d.d[0].t:=0]
+	    462830 e.decoder.addr_buf.vc.ct.in[0] : 0  [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
+	    468741 e.decoder.addr_buf.vc.ct.in[2] : 0  [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
+	    474692 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1  [by e.decoder.addr_buf.vc.ct.in[2]:=0]
+	    494835 e.decoder._out_acksB[1] : 0  [by e.out[7].a:=1]
+	    495662 e.decoder._ortree.in[1] : 1  [by e.decoder._out_acksB[1]:=0]
+	    495835 e.decoder._ortree.or2s[0]._y : 0  [by e.decoder._ortree.in[1]:=1]
+	    496019 e.decoder._ortree.out : 1  [by e.decoder._ortree.or2s[0]._y:=0]
+	    496020 e.decoder.buf_ack_Cel._y : 0  [by e.decoder._ortree.out:=1]
+	    496093 e.decoder.buf_ack_Cel.y : 1  [by e.decoder.buf_ack_Cel._y:=0]
+	    496097 e.decoder.addr_buf._out_a_B : 0  [by e.decoder.buf_ack_Cel.y:=1]
+	    496193 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 1  [by e.decoder.addr_buf._out_a_B:=0]
+	    496329 e.decoder.addr_buf._out_a_BX_t[0] : 0  [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=1]
+	    496330 e.decoder.addr_buf.t_buf_func[0]._y : 1  [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
+	    496570 e.decoder.addr_buf.t_buf_func[2]._y : 1  [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
+	    496582 e.decoder.d_dr_y.in_tX[1].in : 0  [by e.decoder.addr_buf.t_buf_func[2]._y:=1]
+	    497611 e.decoder.vtree_y.OR2_tf[1]._y : 1  [by e.decoder.d_dr_y.in_tX[1].in:=0]
+	    497612 e.decoder.vtree_y.ct.in[1] : 0  [by e.decoder.vtree_y.OR2_tf[1]._y:=1]
+	    500289 e.decoder.d_dr_x.in_tX[0].in : 0  [by e.decoder.addr_buf.t_buf_func[0]._y:=1]
+	    500345 e.decoder.d_dr_x.in_tX[0].buf1._y : 1  [by e.decoder.d_dr_x.in_tX[0].in:=0]
+	    500346 e.decoder.d_dr_x.atree[1].in[0] : 0  [by e.decoder.d_dr_x.in_tX[0].buf1._y:=1]
+	    500383 e.decoder.d_dr_x.atree[1].b._y : 1  [by e.decoder.d_dr_x.atree[1].in[0]:=0]
+	    500482 e.decoder.d_dr_y.in_tX[1].buf1._y : 1  [by e.decoder.d_dr_y.in_tX[1].in:=0]
+	    500483 e.decoder.d_dr_y.atree[2].in[1] : 0  [by e.decoder.d_dr_y.in_tX[1].buf1._y:=1]
+	    504047 e.decoder.d_dr_y.atree[3].and2s[0]._y : 1  [by e.decoder.d_dr_y.atree[2].in[1]:=0]
+	    505739 e.decoder.d_dr_y.out[3] : 0  [by e.decoder.d_dr_y.atree[3].and2s[0]._y:=1]
+	    505752 e.decoder._and_grid.ybuf[3].buf1._y : 1  [by e.decoder.d_dr_y.out[3]:=0]
+	    514177 e.decoder.addr_buf._in_v : 0  [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
+	    514534 e.decoder.addr_buf.in_v_buf._y : 1  [by e.decoder.addr_buf._in_v:=0]
+	    514559 e.in.v : 0  [by e.decoder.addr_buf.in_v_buf._y:=1]
+	    515375 e.decoder.addr_buf.t_buf_func[1]._y : 1  [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
+	    515396 e.decoder.d_dr_y.in_tX[0].in : 0  [by e.decoder.addr_buf.t_buf_func[1]._y:=1]
+	    515397 e.decoder.d_dr_y.in_tX[0].buf1._y : 1  [by e.decoder.d_dr_y.in_tX[0].in:=0]
+	    515398 e.decoder.d_dr_y.atree[1].in[0] : 0  [by e.decoder.d_dr_y.in_tX[0].buf1._y:=1]
+	    522736 e.decoder._and_grid.ands[6].b : 0  [by e.decoder._and_grid.ybuf[3].buf1._y:=1]
+	    522737 e.decoder._and_grid.ands[7]._y : 1  [by e.decoder._and_grid.ands[6].b:=0]
+	    522898 e.out[7].r : 0  [by e.decoder._and_grid.ands[7]._y:=1]
+	    523758 e.decoder.d_dr_x.out[1] : 0  [by e.decoder.d_dr_x.atree[1].b._y:=1]
+	    523763 e.decoder._and_grid.xbuf[1].buf1._y : 1  [by e.decoder.d_dr_x.out[1]:=0]
+	    523935 e.synapses[7].y : 1  [by e.out[7].r:=0]
+	    523946 e.out[7].a : 0  [by e.synapses[7].y:=1]
+	    524171 e.decoder._and_grid.ands[1].a : 0  [by e.decoder._and_grid.xbuf[1].buf1._y:=1]
+	    524339 e.decoder.d_dr_xX[1].buf2._y : 1  [by e.decoder.d_dr_x.out[1]:=0]
+	    525044 e.decoder.vtree_y.OR2_tf[0]._y : 1  [by e.decoder.d_dr_y.in_tX[0].in:=0]
+	    525058 e.decoder.vtree_y.ct.in[0] : 0  [by e.decoder.vtree_y.OR2_tf[0]._y:=1]
+	    525076 e.decoder.vtree_y.ct.C2Els[0]._y : 1  [by e.decoder.vtree_y.ct.in[0]:=0]
+	    525080 e.decoder.vtree_y.out : 0  [by e.decoder.vtree_y.ct.C2Els[0]._y:=1]
+	    525386 e.decoder.pu_ANDs[1].a : 0  [by e.decoder.d_dr_xX[1].buf2._y:=1]
+	    525490 e.decoder.pu_ANDs[1]._y : 1  [by e.decoder.pu_ANDs[1].a:=0]
+	    533385 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 1  [by e.decoder.addr_buf._out_a_B:=0]
+	    534589 e.decoder.addr_buf._out_a_BX_f[0] : 0  [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=1]
+	    545295 e.decoder.vtree_x.OR2_tf[0]._y : 1  [by e.decoder.d_dr_x.in_tX[0].in:=0]
+	    553750 e.decoder.vtree_x.ct.in[0] : 0  [by e.decoder.vtree_x.OR2_tf[0]._y:=1]
+	    553978 e.decoder.vtree_x.ct.b._y : 1  [by e.decoder.vtree_x.ct.in[0]:=0]
+	    554821 e.decoder.vtree_x.out : 0  [by e.decoder.vtree_x.ct.b._y:=1]
+	    556280 e.decoder.valid_Cel._y : 1  [by e.decoder.vtree_x.out:=0]
+	    556350 e.decoder.valid_Cel.y : 0  [by e.decoder.valid_Cel._y:=1]
+	    556934 e.decoder.pu[1].a : 0  [by e.decoder.pu_ANDs[1]._y:=1]
+	    556945 e.decoder._out_acksB[1] : 1  [by e.decoder.pu[1].a:=0]
+	    556948 e.decoder._ortree.in[1] : 0  [by e.decoder._out_acksB[1]:=1]
+	    557002 e.decoder._ortree.or2s[0]._y : 1  [by e.decoder._ortree.in[1]:=0]
+	    558150 e.decoder._ortree.out : 0  [by e.decoder._ortree.or2s[0]._y:=1]
+	    559311 e.decoder.buf_ack_Cel._y : 1  [by e.decoder._ortree.out:=0]
+	    567963 e.decoder.buf_ack_Cel.y : 0  [by e.decoder.buf_ack_Cel._y:=1]
+	    568044 e.decoder.addr_buf._out_a_B : 1  [by e.decoder.buf_ack_Cel.y:=0]
+	    579121 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 0  [by e.decoder.addr_buf._out_a_B:=1]
+	    579213 e.decoder.addr_buf._out_a_BX_f[0] : 1  [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=0]
+	    586027 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 0  [by e.decoder.addr_buf._out_a_B:=1]
+	    594338 e.decoder.addr_buf._out_a_BX_t[0] : 1  [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=0]
+	    606772 e.decoder.addr_buf.inack_ctl._y : 1  [by e.decoder.valid_Cel.y:=0]
+	    608516 e.in.a : 0  [by e.decoder.addr_buf.inack_ctl._y:=1]
+	    609129 e.decoder.addr_buf._en : 1  [by e.in.a:=0]
+	    609174 e.decoder.addr_buf.en_buf_t.buf1._y : 0  [by e.decoder.addr_buf._en:=1]
+	    610171 e.decoder.addr_buf._en_X_t[0] : 1  [by e.decoder.addr_buf.en_buf_t.buf1._y:=0]
+	    623151 e.decoder.addr_buf.en_buf_f.buf1._y : 0  [by e.decoder.addr_buf._en:=1]
+	    624800 e.decoder.addr_buf._en_X_f[0] : 1  [by e.decoder.addr_buf.en_buf_f.buf1._y:=0]
+[] Sending in a 5 packet
+	    624800 e.in.d.d[0].t : 1
+	    624800 e.in.d.d[2].t : 1
+	    624800 e.in.d.d[1].f : 1
+	    624807 e.decoder.addr_buf.t_buf_func[2]._y : 0  [by e.in.d.d[2].t:=1]
+	    624809 e.decoder.d_dr_y.in_tX[1].in : 1  [by e.decoder.addr_buf.t_buf_func[2]._y:=0]
+	    624852 e.decoder.addr_buf.vc.OR2_tf[2]._y : 0  [by e.in.d.d[2].t:=1]
+	    624853 e.decoder.addr_buf.vc.ct.in[2] : 1  [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=0]
+	    624942 e.decoder.vtree_y.OR2_tf[1]._y : 0  [by e.decoder.d_dr_y.in_tX[1].in:=1]
+	    624946 e.decoder.vtree_y.ct.in[1] : 1  [by e.decoder.vtree_y.OR2_tf[1]._y:=0]
+	    625163 e.decoder.d_dr_y.in_tX[1].buf1._y : 0  [by e.decoder.d_dr_y.in_tX[1].in:=1]
+	    625325 e.decoder.addr_buf.vc.OR2_tf[0]._y : 0  [by e.in.d.d[0].t:=1]
+	    625700 e.decoder.addr_buf.t_buf_func[0]._y : 0  [by e.in.d.d[0].t:=1]
+	    625701 e.decoder.d_dr_x.in_tX[0].in : 1  [by e.decoder.addr_buf.t_buf_func[0]._y:=0]
+	    625709 e.decoder.d_dr_y.atree[2].in[1] : 1  [by e.decoder.d_dr_y.in_tX[1].buf1._y:=0]
+	    625780 e.decoder.vtree_x.OR2_tf[0]._y : 0  [by e.decoder.d_dr_x.in_tX[0].in:=1]
+	    628213 e.decoder.vtree_x.ct.in[0] : 1  [by e.decoder.vtree_x.OR2_tf[0]._y:=0]
+	    628301 e.decoder.vtree_x.ct.b._y : 0  [by e.decoder.vtree_x.ct.in[0]:=1]
+	    631267 e.decoder.addr_buf.f_buf_func[1]._y : 0  [by e.in.d.d[1].f:=1]
+	    636083 e.decoder.vtree_x.out : 1  [by e.decoder.vtree_x.ct.b._y:=0]
+	    638079 e.decoder.d_dr_x.in_tX[0].buf1._y : 0  [by e.decoder.d_dr_x.in_tX[0].in:=1]
+	    638138 e.decoder.d_dr_x.atree[1].in[0] : 1  [by e.decoder.d_dr_x.in_tX[0].buf1._y:=0]
+	    638168 e.decoder.d_dr_x.atree[1].b._y : 0  [by e.decoder.d_dr_x.atree[1].in[0]:=1]
+	    639635 e.decoder.d_dr_x.out[1] : 1  [by e.decoder.d_dr_x.atree[1].b._y:=0]
+	    640412 e.decoder.addr_buf.vc.OR2_tf[1]._y : 0  [by e.in.d.d[1].f:=1]
+	    641097 e.decoder.addr_buf.vc.ct.in[1] : 1  [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=0]
+	    659019 e.decoder.d_dr_xX[1].buf2._y : 0  [by e.decoder.d_dr_x.out[1]:=1]
+	    659594 e.decoder.d_dr_y.in_fX[0].in : 1  [by e.decoder.addr_buf.f_buf_func[1]._y:=0]
+	    659721 e.decoder.d_dr_y.in_fX[0].buf1._y : 0  [by e.decoder.d_dr_y.in_fX[0].in:=1]
+	    659763 e.decoder.vtree_y.OR2_tf[0]._y : 0  [by e.decoder.d_dr_y.in_fX[0].in:=1]
+	    659764 e.decoder.d_dr_y.atree[0].in[0] : 1  [by e.decoder.d_dr_y.in_fX[0].buf1._y:=0]
+	    659775 e.decoder.vtree_y.ct.in[0] : 1  [by e.decoder.vtree_y.OR2_tf[0]._y:=0]
+	    660008 e.decoder.vtree_y.ct.C2Els[0]._y : 0  [by e.decoder.vtree_y.ct.in[0]:=1]
+	    660011 e.decoder.vtree_y.out : 1  [by e.decoder.vtree_y.ct.C2Els[0]._y:=0]
+	    660049 e.decoder.valid_Cel._y : 0  [by e.decoder.vtree_y.out:=1]
+	    660050 e.decoder.valid_Cel.y : 1  [by e.decoder.valid_Cel._y:=0]
+	    661043 e.decoder.d_dr_y.atree[2].and2s[0]._y : 0  [by e.decoder.d_dr_y.atree[0].in[0]:=1]
+	    670888 e.decoder.addr_buf.vc.ct.in[0] : 1  [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=0]
+	    670980 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 0  [by e.decoder.addr_buf.vc.ct.in[0]:=1]
+	    673707 e.decoder.addr_buf._in_v : 1  [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=0]
+	    673709 e.decoder.addr_buf.in_v_buf._y : 0  [by e.decoder.addr_buf._in_v:=1]
+	    673710 e.in.v : 1  [by e.decoder.addr_buf.in_v_buf._y:=0]
+	    673795 e.decoder.d_dr_y.out[2] : 1  [by e.decoder.d_dr_y.atree[2].and2s[0]._y:=0]
+	    673797 e.decoder._and_grid.ybuf[2].buf1._y : 0  [by e.decoder.d_dr_y.out[2]:=1]
+	    673815 e.decoder._and_grid.ands[4].b : 1  [by e.decoder._and_grid.ybuf[2].buf1._y:=0]
+	    675211 e.decoder.addr_buf.inack_ctl._y : 0  [by e.in.v:=1]
+	    675330 e.in.a : 1  [by e.decoder.addr_buf.inack_ctl._y:=0]
+	    675734 e.decoder.pu_ANDs[1].a : 1  [by e.decoder.d_dr_xX[1].buf2._y:=0]
+	    675742 e.decoder.pu_ANDs[1]._y : 0  [by e.decoder.pu_ANDs[1].a:=1]
+	    675796 e.decoder.pu[1].a : 1  [by e.decoder.pu_ANDs[1]._y:=0]
+	    681050 e.decoder.addr_buf._en : 0  [by e.in.a:=1]
+	    681055 e.decoder.addr_buf.en_buf_t.buf1._y : 1  [by e.decoder.addr_buf._en:=0]
+	    682122 e.decoder.addr_buf._en_X_t[0] : 0  [by e.decoder.addr_buf.en_buf_t.buf1._y:=1]
+	    699139 e.decoder._and_grid.xbuf[1].buf1._y : 0  [by e.decoder.d_dr_x.out[1]:=1]
+	    699140 e.decoder._and_grid.ands[1].a : 1  [by e.decoder._and_grid.xbuf[1].buf1._y:=0]
+	    699278 e.decoder._and_grid.ands[5]._y : 0  [by e.decoder._and_grid.ands[1].a:=1]
+	    699279 e.out[5].r : 1  [by e.decoder._and_grid.ands[5]._y:=0]
+	    699343 e.synapses[5].y : 0  [by e.out[5].r:=1]
+	    731588 e.decoder.addr_buf.en_buf_f.buf1._y : 1  [by e.decoder.addr_buf._en:=0]
+	    731711 e.decoder.addr_buf._en_X_f[0] : 0  [by e.decoder.addr_buf.en_buf_f.buf1._y:=1]
+[] Removing input
+[] Synapse [5] gives ack
+	    731711 e.in.d.d[0].t : 0
+	    731711 e.out[5].a : 1
+	    731711 e.in.d.d[2].t : 0
+	    731711 e.in.d.d[1].f : 0
+	    731713 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1  [by e.in.d.d[0].t:=0]
+	    731748 e.decoder._out_acksB[1] : 0  [by e.out[5].a:=1]
+	    731759 e.decoder._ortree.in[1] : 1  [by e.decoder._out_acksB[1]:=0]
+	    731760 e.decoder._ortree.or2s[0]._y : 0  [by e.decoder._ortree.in[1]:=1]
+	    731762 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1  [by e.in.d.d[1].f:=0]
+	    731769 e.decoder._ortree.out : 1  [by e.decoder._ortree.or2s[0]._y:=0]
+	    731787 e.decoder.addr_buf.vc.ct.in[1] : 0  [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
+	    731854 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1  [by e.in.d.d[2].t:=0]
+	    732155 e.decoder.addr_buf.vc.ct.in[0] : 0  [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
+	    735375 e.decoder.addr_buf.vc.ct.in[2] : 0  [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
+	    735520 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1  [by e.decoder.addr_buf.vc.ct.in[2]:=0]
+	    742022 e.decoder.buf_ack_Cel._y : 0  [by e.decoder._ortree.out:=1]
+	    742252 e.decoder.buf_ack_Cel.y : 1  [by e.decoder.buf_ack_Cel._y:=0]
+	    742943 e.decoder.addr_buf._out_a_B : 0  [by e.decoder.buf_ack_Cel.y:=1]
+	    742957 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 1  [by e.decoder.addr_buf._out_a_B:=0]
+	    744486 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 1  [by e.decoder.addr_buf._out_a_B:=0]
+	    744568 e.decoder.addr_buf._out_a_BX_f[0] : 0  [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=1]
+	    744579 e.decoder.addr_buf.f_buf_func[1]._y : 1  [by e.decoder.addr_buf._out_a_BX_f[0]:=0]
+	    744580 e.decoder.d_dr_y.in_fX[0].in : 0  [by e.decoder.addr_buf.f_buf_func[1]._y:=1]
+	    744581 e.decoder.d_dr_y.in_fX[0].buf1._y : 1  [by e.decoder.d_dr_y.in_fX[0].in:=0]
+	    745220 e.decoder.d_dr_y.atree[0].in[0] : 0  [by e.decoder.d_dr_y.in_fX[0].buf1._y:=1]
+	    747013 e.decoder.d_dr_y.atree[2].and2s[0]._y : 1  [by e.decoder.d_dr_y.atree[0].in[0]:=0]
+	    747145 e.decoder.d_dr_y.out[2] : 0  [by e.decoder.d_dr_y.atree[2].and2s[0]._y:=1]
+	    747146 e.decoder._and_grid.ybuf[2].buf1._y : 1  [by e.decoder.d_dr_y.out[2]:=0]
+	    747163 e.decoder._and_grid.ands[4].b : 0  [by e.decoder._and_grid.ybuf[2].buf1._y:=1]
+	    747315 e.decoder._and_grid.ands[5]._y : 1  [by e.decoder._and_grid.ands[4].b:=0]
+	    750298 e.out[5].r : 0  [by e.decoder._and_grid.ands[5]._y:=1]
+	    750301 e.synapses[5].y : 1  [by e.out[5].r:=0]
+	    750725 e.out[5].a : 0  [by e.synapses[5].y:=1]
+	    751081 e.decoder.vtree_y.OR2_tf[0]._y : 1  [by e.decoder.d_dr_y.in_fX[0].in:=0]
+	    751087 e.decoder.vtree_y.ct.in[0] : 0  [by e.decoder.vtree_y.OR2_tf[0]._y:=1]
+	    751688 e.decoder.addr_buf._in_v : 0  [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
+	    754276 e.decoder.addr_buf.in_v_buf._y : 1  [by e.decoder.addr_buf._in_v:=0]
+	    756737 e.in.v : 0  [by e.decoder.addr_buf.in_v_buf._y:=1]
+	    761998 e.decoder.addr_buf._out_a_BX_t[0] : 0  [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=1]
+	    762828 e.decoder.addr_buf.t_buf_func[0]._y : 1  [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
+	    762830 e.decoder.d_dr_x.in_tX[0].in : 0  [by e.decoder.addr_buf.t_buf_func[0]._y:=1]
+	    763024 e.decoder.d_dr_x.in_tX[0].buf1._y : 1  [by e.decoder.d_dr_x.in_tX[0].in:=0]
+	    763162 e.decoder.d_dr_x.atree[1].in[0] : 0  [by e.decoder.d_dr_x.in_tX[0].buf1._y:=1]
+	    763179 e.decoder.d_dr_x.atree[1].b._y : 1  [by e.decoder.d_dr_x.atree[1].in[0]:=0]
+	    763196 e.decoder.d_dr_x.out[1] : 0  [by e.decoder.d_dr_x.atree[1].b._y:=1]
+	    763197 e.decoder.d_dr_xX[1].buf2._y : 1  [by e.decoder.d_dr_x.out[1]:=0]
+	    763198 e.decoder.pu_ANDs[1].a : 0  [by e.decoder.d_dr_xX[1].buf2._y:=1]
+	    763433 e.decoder.vtree_x.OR2_tf[0]._y : 1  [by e.decoder.d_dr_x.in_tX[0].in:=0]
+	    763434 e.decoder.vtree_x.ct.in[0] : 0  [by e.decoder.vtree_x.OR2_tf[0]._y:=1]
+	    763453 e.decoder.vtree_x.ct.b._y : 1  [by e.decoder.vtree_x.ct.in[0]:=0]
+	    763621 e.decoder.vtree_x.out : 0  [by e.decoder.vtree_x.ct.b._y:=1]
+	    763622 e.decoder._and_grid.xbuf[1].buf1._y : 1  [by e.decoder.d_dr_x.out[1]:=0]
+	    764161 e.decoder._and_grid.ands[1].a : 0  [by e.decoder._and_grid.xbuf[1].buf1._y:=1]
+	    764224 e.decoder.pu_ANDs[1]._y : 1  [by e.decoder.pu_ANDs[1].a:=0]
+	    764385 e.decoder.pu[1].a : 0  [by e.decoder.pu_ANDs[1]._y:=1]
+	    764558 e.decoder._out_acksB[1] : 1  [by e.decoder.pu[1].a:=0]
+	    767105 e.decoder._ortree.in[1] : 0  [by e.decoder._out_acksB[1]:=1]
+	    782166 e.decoder._ortree.or2s[0]._y : 1  [by e.decoder._ortree.in[1]:=0]
+	    782167 e.decoder._ortree.out : 0  [by e.decoder._ortree.or2s[0]._y:=1]
+	    784930 e.decoder.addr_buf.t_buf_func[2]._y : 1  [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
+	    784931 e.decoder.d_dr_y.in_tX[1].in : 0  [by e.decoder.addr_buf.t_buf_func[2]._y:=1]
+	    785138 e.decoder.vtree_y.OR2_tf[1]._y : 1  [by e.decoder.d_dr_y.in_tX[1].in:=0]
+	    785321 e.decoder.d_dr_y.in_tX[1].buf1._y : 1  [by e.decoder.d_dr_y.in_tX[1].in:=0]
+	    785349 e.decoder.d_dr_y.atree[2].in[1] : 0  [by e.decoder.d_dr_y.in_tX[1].buf1._y:=1]
+	    785971 e.decoder.vtree_y.ct.in[1] : 0  [by e.decoder.vtree_y.OR2_tf[1]._y:=1]
+	    785978 e.decoder.vtree_y.ct.C2Els[0]._y : 1  [by e.decoder.vtree_y.ct.in[1]:=0]
+	    786392 e.decoder.vtree_y.out : 0  [by e.decoder.vtree_y.ct.C2Els[0]._y:=1]
+	    786396 e.decoder.valid_Cel._y : 1  [by e.decoder.vtree_y.out:=0]
+	    788175 e.decoder.valid_Cel.y : 0  [by e.decoder.valid_Cel._y:=1]
+	    788341 e.decoder.addr_buf.inack_ctl._y : 1  [by e.decoder.valid_Cel.y:=0]
+	    811049 e.decoder.buf_ack_Cel._y : 1  [by e.decoder.valid_Cel.y:=0]
+	    819694 e.decoder.buf_ack_Cel.y : 0  [by e.decoder.buf_ack_Cel._y:=1]
+	    820627 e.decoder.addr_buf._out_a_B : 1  [by e.decoder.buf_ack_Cel.y:=0]
+	    820766 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 0  [by e.decoder.addr_buf._out_a_B:=1]
+	    821483 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 0  [by e.decoder.addr_buf._out_a_B:=1]
+	    821678 e.decoder.addr_buf._out_a_BX_f[0] : 1  [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=0]
+	    828211 e.in.a : 0  [by e.decoder.addr_buf.inack_ctl._y:=1]
+	    828213 e.decoder.addr_buf._en : 1  [by e.in.a:=0]
+	    828219 e.decoder.addr_buf.en_buf_t.buf1._y : 0  [by e.decoder.addr_buf._en:=1]
+	    828473 e.decoder.addr_buf._en_X_t[0] : 1  [by e.decoder.addr_buf.en_buf_t.buf1._y:=0]
+	    846975 e.decoder.addr_buf._out_a_BX_t[0] : 1  [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=0]
+	    881662 e.decoder.addr_buf.en_buf_f.buf1._y : 0  [by e.decoder.addr_buf._en:=1]
+	    881670 e.decoder.addr_buf._en_X_f[0] : 1  [by e.decoder.addr_buf.en_buf_f.buf1._y:=0]
+[] Sending in a 1 packet
+	    881670 e.in.d.d[0].t : 1
+	    881670 e.in.d.d[2].f : 1
+	    881670 e.in.d.d[1].f : 1
+	    881671 e.decoder.addr_buf.vc.OR2_tf[0]._y : 0  [by e.in.d.d[0].t:=1]
+	    881672 e.decoder.addr_buf.vc.ct.in[0] : 1  [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=0]
+	    881676 e.decoder.addr_buf.t_buf_func[0]._y : 0  [by e.in.d.d[0].t:=1]
+	    881682 e.decoder.d_dr_x.in_tX[0].in : 1  [by e.decoder.addr_buf.t_buf_func[0]._y:=0]
+	    881684 e.decoder.d_dr_x.in_tX[0].buf1._y : 0  [by e.decoder.d_dr_x.in_tX[0].in:=1]
+	    881699 e.decoder.d_dr_x.atree[1].in[0] : 1  [by e.decoder.d_dr_x.in_tX[0].buf1._y:=0]
+	    881896 e.decoder.addr_buf.vc.OR2_tf[1]._y : 0  [by e.in.d.d[1].f:=1]
+	    882003 e.decoder.addr_buf.vc.ct.in[1] : 1  [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=0]
+	    882489 e.decoder.addr_buf.f_buf_func[1]._y : 0  [by e.in.d.d[1].f:=1]
+	    882582 e.decoder.d_dr_y.in_fX[0].in : 1  [by e.decoder.addr_buf.f_buf_func[1]._y:=0]
+	    884234 e.decoder.d_dr_y.in_fX[0].buf1._y : 0  [by e.decoder.d_dr_y.in_fX[0].in:=1]
+	    884760 e.decoder.addr_buf.f_buf_func[2]._y : 0  [by e.in.d.d[2].f:=1]
+	    884992 e.decoder.d_dr_y.atree[0].in[0] : 1  [by e.decoder.d_dr_y.in_fX[0].buf1._y:=0]
+	    885244 e.decoder.vtree_x.OR2_tf[0]._y : 0  [by e.decoder.d_dr_x.in_tX[0].in:=1]
+	    885960 e.decoder.vtree_x.ct.in[0] : 1  [by e.decoder.vtree_x.OR2_tf[0]._y:=0]
+	    885961 e.decoder.vtree_x.ct.b._y : 0  [by e.decoder.vtree_x.ct.in[0]:=1]
+	    886521 e.decoder.vtree_y.OR2_tf[0]._y : 0  [by e.decoder.d_dr_y.in_fX[0].in:=1]
+	    886522 e.decoder.vtree_y.ct.in[0] : 1  [by e.decoder.vtree_y.OR2_tf[0]._y:=0]
+	    887383 e.decoder.d_dr_y.in_fX[1].in : 1  [by e.decoder.addr_buf.f_buf_func[2]._y:=0]
+	    887701 e.decoder.vtree_x.out : 1  [by e.decoder.vtree_x.ct.b._y:=0]
+	    899535 e.decoder.d_dr_y.in_fX[1].buf1._y : 0  [by e.decoder.d_dr_y.in_fX[1].in:=1]
+	    899536 e.decoder.d_dr_y.atree[0].in[1] : 1  [by e.decoder.d_dr_y.in_fX[1].buf1._y:=0]
+	    899542 e.decoder.d_dr_y.atree[0].and2s[0]._y : 0  [by e.decoder.d_dr_y.atree[0].in[1]:=1]
+	    899543 e.decoder.d_dr_y.out[0] : 1  [by e.decoder.d_dr_y.atree[0].and2s[0]._y:=0]
+	    902500 e.decoder.d_dr_x.atree[1].b._y : 0  [by e.decoder.d_dr_x.atree[1].in[0]:=1]
+	    915582 e.decoder.vtree_y.OR2_tf[1]._y : 0  [by e.decoder.d_dr_y.in_fX[1].in:=1]
+	    915604 e.decoder.vtree_y.ct.in[1] : 1  [by e.decoder.vtree_y.OR2_tf[1]._y:=0]
+	    924099 e.decoder.d_dr_x.out[1] : 1  [by e.decoder.d_dr_x.atree[1].b._y:=0]
+	    924106 e.decoder._and_grid.xbuf[1].buf1._y : 0  [by e.decoder.d_dr_x.out[1]:=1]
+	    924119 e.decoder._and_grid.ands[1].a : 1  [by e.decoder._and_grid.xbuf[1].buf1._y:=0]
+	    924164 e.decoder.d_dr_xX[1].buf2._y : 0  [by e.decoder.d_dr_x.out[1]:=1]
+	    925288 e.decoder.pu_ANDs[1].a : 1  [by e.decoder.d_dr_xX[1].buf2._y:=0]
+	    925392 e.decoder.pu_ANDs[1]._y : 0  [by e.decoder.pu_ANDs[1].a:=1]
+	    925433 e.decoder.pu[1].a : 1  [by e.decoder.pu_ANDs[1]._y:=0]
+	    932706 e.decoder.addr_buf.vc.OR2_tf[2]._y : 0  [by e.in.d.d[2].f:=1]
+	    932707 e.decoder.addr_buf.vc.ct.in[2] : 1  [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=0]
+	    932708 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 0  [by e.decoder.addr_buf.vc.ct.in[2]:=1]
+	    938112 e.decoder.vtree_y.ct.C2Els[0]._y : 0  [by e.decoder.vtree_y.ct.in[1]:=1]
+	    939032 e.decoder._and_grid.ybuf[0].buf1._y : 0  [by e.decoder.d_dr_y.out[0]:=1]
+	    939033 e.decoder._and_grid.ands[0].b : 1  [by e.decoder._and_grid.ybuf[0].buf1._y:=0]
+	    951284 e.decoder.vtree_y.out : 1  [by e.decoder.vtree_y.ct.C2Els[0]._y:=0]
+	    954420 e.decoder.valid_Cel._y : 0  [by e.decoder.vtree_y.out:=1]
+	    955246 e.decoder.valid_Cel.y : 1  [by e.decoder.valid_Cel._y:=0]
+	    958858 e.decoder._and_grid.ands[1]._y : 0  [by e.decoder._and_grid.ands[0].b:=1]
+	    960691 e.out[1].r : 1  [by e.decoder._and_grid.ands[1]._y:=0]
+	    977239 e.synapses[1].y : 0  [by e.out[1].r:=1]
+	    997086 e.decoder.addr_buf._in_v : 1  [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=0]
+	    997144 e.decoder.addr_buf.in_v_buf._y : 0  [by e.decoder.addr_buf._in_v:=1]
+	    999587 e.in.v : 1  [by e.decoder.addr_buf.in_v_buf._y:=0]
+	   1016360 e.decoder.addr_buf.inack_ctl._y : 0  [by e.in.v:=1]
+	   1053559 e.in.a : 1  [by e.decoder.addr_buf.inack_ctl._y:=0]
+	   1053573 e.decoder.addr_buf._en : 0  [by e.in.a:=1]
+	   1053929 e.decoder.addr_buf.en_buf_f.buf1._y : 1  [by e.decoder.addr_buf._en:=0]
+	   1054034 e.decoder.addr_buf._en_X_f[0] : 0  [by e.decoder.addr_buf.en_buf_f.buf1._y:=1]
+	   1089411 e.decoder.addr_buf.en_buf_t.buf1._y : 1  [by e.decoder.addr_buf._en:=0]
+	   1089520 e.decoder.addr_buf._en_X_t[0] : 0  [by e.decoder.addr_buf.en_buf_t.buf1._y:=1]
+[] Synapse [5] gives ack
+	   1089520 e.out[1].a : 1
+	   1089521 e.decoder._out_acksB[1] : 0  [by e.out[1].a:=1]
+	   1089530 e.decoder._ortree.in[1] : 1  [by e.decoder._out_acksB[1]:=0]
+	   1127483 e.decoder._ortree.or2s[0]._y : 0  [by e.decoder._ortree.in[1]:=1]
+	   1127484 e.decoder._ortree.out : 1  [by e.decoder._ortree.or2s[0]._y:=0]
+	   1163878 e.decoder.buf_ack_Cel._y : 0  [by e.decoder._ortree.out:=1]
+	   1163879 e.decoder.buf_ack_Cel.y : 1  [by e.decoder.buf_ack_Cel._y:=0]
+	   1166968 e.decoder.addr_buf._out_a_B : 0  [by e.decoder.buf_ack_Cel.y:=1]
+	   1167718 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 1  [by e.decoder.addr_buf._out_a_B:=0]
+	   1174473 e.decoder.addr_buf._out_a_BX_t[0] : 0  [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=1]
+	   1174524 e.decoder.addr_buf.t_buf_func[0]._y : 1  [by e.decoder.addr_buf._out_a_BX_t[0]:=0]
+	   1174534 e.decoder.d_dr_x.in_tX[0].in : 0  [by e.decoder.addr_buf.t_buf_func[0]._y:=1]
+	   1174854 e.decoder.d_dr_x.in_tX[0].buf1._y : 1  [by e.decoder.d_dr_x.in_tX[0].in:=0]
+	   1174855 e.decoder.d_dr_x.atree[1].in[0] : 0  [by e.decoder.d_dr_x.in_tX[0].buf1._y:=1]
+	   1174856 e.decoder.d_dr_x.atree[1].b._y : 1  [by e.decoder.d_dr_x.atree[1].in[0]:=0]
+	   1176586 e.decoder.d_dr_x.out[1] : 0  [by e.decoder.d_dr_x.atree[1].b._y:=1]
+	   1176601 e.decoder.d_dr_xX[1].buf2._y : 1  [by e.decoder.d_dr_x.out[1]:=0]
+	   1178273 e.decoder._and_grid.xbuf[1].buf1._y : 1  [by e.decoder.d_dr_x.out[1]:=0]
+	   1178727 e.decoder._and_grid.ands[1].a : 0  [by e.decoder._and_grid.xbuf[1].buf1._y:=1]
+	   1179043 e.decoder._and_grid.ands[1]._y : 1  [by e.decoder._and_grid.ands[1].a:=0]
+	   1179044 e.out[1].r : 0  [by e.decoder._and_grid.ands[1]._y:=1]
+	   1179427 e.synapses[1].y : 1  [by e.out[1].r:=0]
+	   1182116 e.decoder.vtree_x.OR2_tf[0]._y : 1  [by e.decoder.d_dr_x.in_tX[0].in:=0]
+	   1182136 e.decoder.vtree_x.ct.in[0] : 0  [by e.decoder.vtree_x.OR2_tf[0]._y:=1]
+	   1183459 e.decoder.vtree_x.ct.b._y : 1  [by e.decoder.vtree_x.ct.in[0]:=0]
+	   1183546 e.decoder.vtree_x.out : 0  [by e.decoder.vtree_x.ct.b._y:=1]
+	   1186890 e.out[1].a : 0  [by e.synapses[1].y:=1]
+	   1200875 e.decoder.pu_ANDs[1].a : 0  [by e.decoder.d_dr_xX[1].buf2._y:=1]
+	   1207597 e.decoder.pu_ANDs[1]._y : 1  [by e.decoder.pu_ANDs[1].a:=0]
+	   1207609 e.decoder.pu[1].a : 0  [by e.decoder.pu_ANDs[1]._y:=1]
+	   1207754 e.decoder._out_acksB[1] : 1  [by e.decoder.pu[1].a:=0]
+	   1208655 e.decoder._ortree.in[1] : 0  [by e.decoder._out_acksB[1]:=1]
+	   1210004 e.decoder._ortree.or2s[0]._y : 1  [by e.decoder._ortree.in[1]:=0]
+	   1210223 e.decoder._ortree.out : 0  [by e.decoder._ortree.or2s[0]._y:=1]
+	   1215694 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 1  [by e.decoder.addr_buf._out_a_B:=0]
+	   1224025 e.decoder.addr_buf._out_a_BX_f[0] : 0  [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=1]
+	   1224043 e.decoder.addr_buf.f_buf_func[2]._y : 1  [by e.decoder.addr_buf._out_a_BX_f[0]:=0]
+	   1226237 e.decoder.d_dr_y.in_fX[1].in : 0  [by e.decoder.addr_buf.f_buf_func[2]._y:=1]
+	   1226357 e.decoder.vtree_y.OR2_tf[1]._y : 1  [by e.decoder.d_dr_y.in_fX[1].in:=0]
+	   1232672 e.decoder.vtree_y.ct.in[1] : 0  [by e.decoder.vtree_y.OR2_tf[1]._y:=1]
+	   1255606 e.decoder.addr_buf.f_buf_func[1]._y : 1  [by e.decoder.addr_buf._out_a_BX_f[0]:=0]
+	   1257670 e.decoder.d_dr_y.in_fX[0].in : 0  [by e.decoder.addr_buf.f_buf_func[1]._y:=1]
+	   1257677 e.decoder.vtree_y.OR2_tf[0]._y : 1  [by e.decoder.d_dr_y.in_fX[0].in:=0]
+	   1257678 e.decoder.vtree_y.ct.in[0] : 0  [by e.decoder.vtree_y.OR2_tf[0]._y:=1]
+	   1257802 e.decoder.vtree_y.ct.C2Els[0]._y : 1  [by e.decoder.vtree_y.ct.in[0]:=0]
+	   1258262 e.decoder.d_dr_y.in_fX[0].buf1._y : 1  [by e.decoder.d_dr_y.in_fX[0].in:=0]
+	   1259314 e.decoder.d_dr_y.atree[0].in[0] : 0  [by e.decoder.d_dr_y.in_fX[0].buf1._y:=1]
+	   1259674 e.decoder.d_dr_y.atree[0].and2s[0]._y : 1  [by e.decoder.d_dr_y.atree[0].in[0]:=0]
+	   1263732 e.decoder.vtree_y.out : 0  [by e.decoder.vtree_y.ct.C2Els[0]._y:=1]
+	   1264209 e.decoder.d_dr_y.in_fX[1].buf1._y : 1  [by e.decoder.d_dr_y.in_fX[1].in:=0]
+	   1264829 e.decoder.valid_Cel._y : 1  [by e.decoder.vtree_y.out:=0]
+	   1264833 e.decoder.valid_Cel.y : 0  [by e.decoder.valid_Cel._y:=1]
+	   1269868 e.decoder.d_dr_y.out[0] : 0  [by e.decoder.d_dr_y.atree[0].and2s[0]._y:=1]
+	   1276497 e.decoder.buf_ack_Cel._y : 1  [by e.decoder.valid_Cel.y:=0]
+	   1284101 e.decoder.d_dr_y.atree[0].in[1] : 0  [by e.decoder.d_dr_y.in_fX[1].buf1._y:=1]
+	   1294158 e.decoder.buf_ack_Cel.y : 0  [by e.decoder.buf_ack_Cel._y:=1]
+	   1297539 e.decoder.addr_buf._out_a_B : 1  [by e.decoder.buf_ack_Cel.y:=0]
+	   1297795 e.decoder.addr_buf.out_a_B_buf_t.buf1._y : 0  [by e.decoder.addr_buf._out_a_B:=1]
+	   1297832 e.decoder.addr_buf._out_a_BX_f[0] : 1  [by e.decoder.addr_buf.out_a_B_buf_t.buf1._y:=0]
+	   1307787 e.decoder._and_grid.ybuf[0].buf1._y : 1  [by e.decoder.d_dr_y.out[0]:=0]
+	   1307799 e.decoder._and_grid.ands[0].b : 0  [by e.decoder._and_grid.ybuf[0].buf1._y:=1]
+	   1312469 e.decoder.addr_buf.out_a_B_buf_f.buf1._y : 0  [by e.decoder.addr_buf._out_a_B:=1]
+	   1312478 e.decoder.addr_buf._out_a_BX_t[0] : 1  [by e.decoder.addr_buf.out_a_B_buf_f.buf1._y:=0]
+[] Removing input
+	   1312478 e.in.d.d[0].t : 0
+	   1312478 e.in.d.d[2].f : 0
+	   1312478 e.in.d.d[1].f : 0
+	   1312720 e.decoder.addr_buf.vc.OR2_tf[2]._y : 1  [by e.in.d.d[2].f:=0]
+	   1312905 e.decoder.addr_buf.vc.OR2_tf[0]._y : 1  [by e.in.d.d[0].t:=0]
+	   1313313 e.decoder.addr_buf.vc.OR2_tf[1]._y : 1  [by e.in.d.d[1].f:=0]
+	   1314465 e.decoder.addr_buf.vc.ct.in[0] : 0  [by e.decoder.addr_buf.vc.OR2_tf[0]._y:=1]
+	   1350406 e.decoder.addr_buf.vc.ct.in[1] : 0  [by e.decoder.addr_buf.vc.OR2_tf[1]._y:=1]
+	   1359456 e.decoder.addr_buf.vc.ct.in[2] : 0  [by e.decoder.addr_buf.vc.OR2_tf[2]._y:=1]
+	   1359716 e.decoder.addr_buf.vc.ct.C3Els[0]._y : 1  [by e.decoder.addr_buf.vc.ct.in[2]:=0]
+	   1368704 e.decoder.addr_buf._in_v : 0  [by e.decoder.addr_buf.vc.ct.C3Els[0]._y:=1]
+	   1368705 e.decoder.addr_buf.in_v_buf._y : 1  [by e.decoder.addr_buf._in_v:=0]
+	   1404755 e.in.v : 0  [by e.decoder.addr_buf.in_v_buf._y:=1]
+	   1405139 e.decoder.addr_buf.inack_ctl._y : 1  [by e.in.v:=0]
+	   1405158 e.in.a : 0  [by e.decoder.addr_buf.inack_ctl._y:=1]
+	   1405167 e.decoder.addr_buf._en : 1  [by e.in.a:=0]
+	   1405355 e.decoder.addr_buf.en_buf_t.buf1._y : 0  [by e.decoder.addr_buf._en:=1]
+	   1427121 e.decoder.addr_buf.en_buf_f.buf1._y : 0  [by e.decoder.addr_buf._en:=1]
+	   1430721 e.decoder.addr_buf._en_X_f[0] : 1  [by e.decoder.addr_buf.en_buf_f.buf1._y:=0]
+	   1451131 e.decoder.addr_buf._en_X_t[0] : 1  [by e.decoder.addr_buf.en_buf_t.buf1._y:=0]

test/unit_tests/decoder_2d_hs/test.act

@@ -0,0 +1,73 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc decoder_2d_hs_2x4 (avMx1of2<3> in; a1of1 out[8]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    decoder_2d_hs<1,2,2,4> decoder(.in = in, .out = out,
+        .reset_B = _reset_B, .supply = supply);
+
+    // model the synapse as having automatic pulldown of ack.
+    INV_X1 synapses[8];
+    PULLDOWN_X4 synapses2[8];
+    (i:8:
+        synapses[i].a = decoder.out[i].r;
+        synapses2[i].a = synapses[i].y; 
+        synapses2[i].y = decoder.out[i].a;
+
+        synapses[i].vss = supply.vss;
+        synapses[i].vdd = supply.vdd;
+        synapses2[i].vss = supply.vss;
+        synapses2[i].vdd = supply.vdd;
+
+    )
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+decoder_2d_hs_2x4 e; 

test/unit_tests/decoder_2d_hs/test.prsim

@@ -0,0 +1,153 @@
+watchall
+
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+
+set-qdi-channel-neutral "e.in" 3
+set Reset 1
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+system "echo '[] Sending in a 7 packet'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+

test/unit_tests/decoder_2d_hybrid/test.act

@@ -0,0 +1,74 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .out = out, .dly_cfg = dly_cfg, .hs_en = hs_en,
+        .reset_B = _reset_B, .supply = supply);
+
+    // model the synapse as having automatic pulldown of ack.
+    INV_X1 synapses[8];
+    
+    PULLDOWN_X4 synapses2[8];
+    (i:8:
+        synapses[i].a = decoder.out[i].r;
+        synapses2[i].a = synapses[i].y; 
+        synapses2[i].y = decoder.out[i].a;
+
+        synapses[i].vss = supply.vss;
+        synapses[i].vdd = supply.vdd;
+        synapses2[i].vss = supply.vss;
+        synapses2[i].vdd = supply.vdd;
+
+    )
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+decoder_2d_hybrid_2x4 e; 

test/unit_tests/decoder_2d_hybrid/test.prsim

@@ -0,0 +1,341 @@
+watchall
+
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+
+set e.dly_cfg[0] 0
+set e.dly_cfg[1] 0
+set e.dly_cfg[2] 0
+set e.dly_cfg[3] 0
+
+set e.hs_en 1
+
+set-qdi-channel-neutral "e.in" 3
+set Reset 1
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+system "echo '[] Sending in a 7 packet'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [1] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input, enabling delays'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+system "echo '[] Enabling delays'"
+cycle
+set e.dly_cfg[0] 1
+set e.dly_cfg[1] 1
+set e.dly_cfg[2] 1
+set e.dly_cfg[3] 1
+
+system "echo '[] Sending in a 7 packet, with delays'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [1] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input, disabling handshaking'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+set e.hs_en 0
+cycle
+
+system "echo '[] Sending in a 0, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 0
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in a 7, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+system "echo '[] Sending in a 5, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+

test/unit_tests/delayprog_4/run/prsim.out

@@ -1,134 +1,272 @@
-t.s[2] t.dp.dly[2].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.a t.s[0] t.dp.and2[2]._y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[11].y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[9].a t.dp.dly[1].y t.dp.dly[1].a t.dp.dly[4].a t.y t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[10].a t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[8].a t.dp.dly[0].a t.dp.dly[7].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.mu2[1]._s t.dp.dly[11].a t.dp.dly[14].a t.dp.dly[13].a t.dp.dly[13]._y t.dp.dly[7].y t.dp.dly[8]._y t.dp.mu2[2]._y t.dp.dly[3].y t.dp.dly[14].y t.dp.dly[0].y t.dp.dly[3]._y t.dp.dly[13].y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[10].y t.dp.dly[9].y t.dp.dly[4]._y t.dp.dly[12].y t.dp.dly[8].y t.dp.mu2[1]._y t.dp.dly[12].a t.dp.dly[10]._y 
+t.s[2] t.dp.dly[4].__y t.dp.dly[3].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.dp.dly[9].___y t.dp.dly[0].___y t.s[0] t.dp.dly[6].___y t.dp.dly[4].___y t.dp.and2[2]._y t.dp.dly[3].__y t.dp.dly[11].__y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp.dly[8].___y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[10].___y t.dp.dly[11].y t.dp.dly[8].__y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[11].___y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[12].___y t.dp.dly[8].y t.dp.dly[1].y t.dp.dly[5].__y t.dp.dly[1].a t.in t.dp.dly[7].a t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[9].y t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[7].y t.dp.dly[6].__y t.dp.dly[0].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.dly[13].___y t.out t.dp.mu2[3].b t.dp.mu2[1]._s t.dp.dly[10].y t.dp.dly[1].__y t.dp.dly[13].y t.dp.dly[12].y t.dp.dly[13]._y t.dp.dly[12].__y t.dp.dly[8]._y t.dp.dly[14].__y t.dp.dly[10].__y t.dp.mu2[2]._y t.dp.dly[5].___y t.dp.dly[9].__y t.dp.dly[3].y t.dp.dly[14].___y t.dp.dly[7].__y t.dp.dly[0].y t.dp.dly[2].__y t.dp.dly[3]._y t.dp.dly[3].___y t.dp.dly[2].___y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[13].__y t.dp.dly[1].___y t.dp.dly[4]._y t.dp.dly[7].___y t.dp.mu2[1]._y t.dp.dly[0].__y t.dp.dly[10]._y 
 0
-	         0 t.a : 0
+	         0 t.in : 0
 	         0 t.s[3] : 1
 	         0 t.s[1] : 1
 	         0 t.s[0] : 1
 	         0 t.s[2] : 1
-	         1 t.dp.and2[0]._y : 1  [by t.a:=0]
+	         1 t.dp.and2[0]._y : 1  [by t.in:=0]
 	         2 t.dp.mu2[0]._s : 0  [by t.s[0]:=1]
 	      1138 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
 	      1252 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
 	      4753 t.dp.mu2[2]._s : 0  [by t.s[2]:=1]
 	      7092 t.dp.mu2[3]._s : 0  [by t.s[3]:=1]
 	     10467 t.dp.mu2[1]._s : 0  [by t.s[1]:=1]
-	     66618 t.dp.dly[0].y : 0  [by t.dp.dly[0]._y:=1]
-	     68344 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
-	     68383 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	     68398 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
-	     68889 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
-	     68902 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
-	     68942 t.dp.dly[1].y : 0  [by t.dp.dly[1]._y:=1]
-	     69357 t.dp.mu2[1]._y : 1  [by t.dp.dly[1].y:=0]
-	     69377 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	     75438 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
-	     75485 t.dp.dly[2].a : 0  [by t.dp.and2[2]._y:=1]
-	     75501 t.dp.dly[2]._y : 1  [by t.dp.dly[2].a:=0]
-	    119599 t.dp.dly[2].y : 0  [by t.dp.dly[2]._y:=1]
-	    133323 t.dp.dly[3]._y : 1  [by t.dp.dly[2].y:=0]
-	    133327 t.dp.dly[3].y : 0  [by t.dp.dly[3]._y:=1]
-	    142456 t.dp.mu2[2]._y : 1  [by t.dp.dly[3].y:=0]
-	    142471 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    185719 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
-	    222650 t.dp.dly[4].a : 0  [by t.dp.and2[3]._y:=1]
-	    222705 t.dp.dly[4]._y : 1  [by t.dp.dly[4].a:=0]
-	    274358 t.dp.dly[4].y : 0  [by t.dp.dly[4]._y:=1]
-	    304138 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
-	    317987 t.dp.dly[5].y : 0  [by t.dp.dly[5]._y:=1]
-	    342799 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
-	    357142 t.dp.dly[6].y : 0  [by t.dp.dly[6]._y:=1]
-	    357564 t.dp.mu2[3]._y : 1  [by t.dp.dly[6].y:=0]
-	    406278 t.y : 0  [by t.dp.mu2[3]._y:=1]
+	     66618 t.dp.dly[0].__y : 0  [by t.dp.dly[0]._y:=1]
+	     68344 t.dp.dly[0].___y : 1  [by t.dp.dly[0].__y:=0]
+	     68383 t.dp.dly[0].y : 0  [by t.dp.dly[0].___y:=1]
+	     68398 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
+	     68889 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
+	     68902 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
+	     68942 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
+	     69357 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
+	     69377 t.dp.dly[1].__y : 0  [by t.dp.dly[1]._y:=1]
+	     75438 t.dp.dly[1].___y : 1  [by t.dp.dly[1].__y:=0]
+	     75485 t.dp.dly[1].y : 0  [by t.dp.dly[1].___y:=1]
+	     75501 t.dp.dly[2]._y : 1  [by t.dp.dly[1].y:=0]
+	    119599 t.dp.dly[2].__y : 0  [by t.dp.dly[2]._y:=1]
+	    133323 t.dp.dly[2].___y : 1  [by t.dp.dly[2].__y:=0]
+	    133327 t.dp.dly[2].y : 0  [by t.dp.dly[2].___y:=1]
+	    142456 t.dp.mu2[1]._y : 1  [by t.dp.dly[2].y:=0]
+	    142471 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
+	    185719 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
+	    222650 t.dp.dly[3].a : 0  [by t.dp.and2[2]._y:=1]
+	    222705 t.dp.dly[3]._y : 1  [by t.dp.dly[3].a:=0]
+	    274358 t.dp.dly[3].__y : 0  [by t.dp.dly[3]._y:=1]
+	    304138 t.dp.dly[3].___y : 1  [by t.dp.dly[3].__y:=0]
+	    317987 t.dp.dly[3].y : 0  [by t.dp.dly[3].___y:=1]
+	    342799 t.dp.dly[4]._y : 1  [by t.dp.dly[3].y:=0]
+	    357142 t.dp.dly[4].__y : 0  [by t.dp.dly[4]._y:=1]
+	    357564 t.dp.dly[4].___y : 1  [by t.dp.dly[4].__y:=0]
+	    406278 t.dp.dly[4].y : 0  [by t.dp.dly[4].___y:=1]
+	    406279 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
+	    406280 t.dp.dly[5].__y : 0  [by t.dp.dly[5]._y:=1]
+	    426485 t.dp.dly[5].___y : 1  [by t.dp.dly[5].__y:=0]
+	    426767 t.dp.dly[5].y : 0  [by t.dp.dly[5].___y:=1]
+	    427535 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
+	    427538 t.dp.dly[6].__y : 0  [by t.dp.dly[6]._y:=1]
+	    449979 t.dp.dly[6].___y : 1  [by t.dp.dly[6].__y:=0]
+	    450530 t.dp.dly[6].y : 0  [by t.dp.dly[6].___y:=1]
+	    451601 t.dp.mu2[2]._y : 1  [by t.dp.dly[6].y:=0]
+	    452555 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
+	    453636 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
+	    508106 t.dp.dly[7].a : 0  [by t.dp.and2[3]._y:=1]
+	    509088 t.dp.dly[7]._y : 1  [by t.dp.dly[7].a:=0]
+	    509106 t.dp.dly[7].__y : 0  [by t.dp.dly[7]._y:=1]
+	    513119 t.dp.dly[7].___y : 1  [by t.dp.dly[7].__y:=0]
+	    517122 t.dp.dly[7].y : 0  [by t.dp.dly[7].___y:=1]
+	    562023 t.dp.dly[8]._y : 1  [by t.dp.dly[7].y:=0]
+	    583607 t.dp.dly[8].__y : 0  [by t.dp.dly[8]._y:=1]
+	    588367 t.dp.dly[8].___y : 1  [by t.dp.dly[8].__y:=0]
+	    588869 t.dp.dly[8].y : 0  [by t.dp.dly[8].___y:=1]
+	    589072 t.dp.dly[9]._y : 1  [by t.dp.dly[8].y:=0]
+	    590926 t.dp.dly[9].__y : 0  [by t.dp.dly[9]._y:=1]
+	    591065 t.dp.dly[9].___y : 1  [by t.dp.dly[9].__y:=0]
+	    627411 t.dp.dly[9].y : 0  [by t.dp.dly[9].___y:=1]
+	    627480 t.dp.dly[10]._y : 1  [by t.dp.dly[9].y:=0]
+	    627491 t.dp.dly[10].__y : 0  [by t.dp.dly[10]._y:=1]
+	    679277 t.dp.dly[10].___y : 1  [by t.dp.dly[10].__y:=0]
+	    679481 t.dp.dly[10].y : 0  [by t.dp.dly[10].___y:=1]
+	    679496 t.dp.dly[11]._y : 1  [by t.dp.dly[10].y:=0]
+	    679497 t.dp.dly[11].__y : 0  [by t.dp.dly[11]._y:=1]
+	    679534 t.dp.dly[11].___y : 1  [by t.dp.dly[11].__y:=0]
+	    680273 t.dp.dly[11].y : 0  [by t.dp.dly[11].___y:=1]
+	    680385 t.dp.dly[12]._y : 1  [by t.dp.dly[11].y:=0]
+	    727897 t.dp.dly[12].__y : 0  [by t.dp.dly[12]._y:=1]
+	    727937 t.dp.dly[12].___y : 1  [by t.dp.dly[12].__y:=0]
+	    728194 t.dp.dly[12].y : 0  [by t.dp.dly[12].___y:=1]
+	    728281 t.dp.dly[13]._y : 1  [by t.dp.dly[12].y:=0]
+	    728575 t.dp.dly[13].__y : 0  [by t.dp.dly[13]._y:=1]
+	    728576 t.dp.dly[13].___y : 1  [by t.dp.dly[13].__y:=0]
+	    730382 t.dp.dly[13].y : 0  [by t.dp.dly[13].___y:=1]
+	    732389 t.dp.dly[14]._y : 1  [by t.dp.dly[13].y:=0]
+	    733598 t.dp.dly[14].__y : 0  [by t.dp.dly[14]._y:=1]
+	    734188 t.dp.dly[14].___y : 1  [by t.dp.dly[14].__y:=0]
+	    734366 t.dp.mu2[3].b : 0  [by t.dp.dly[14].___y:=1]
+	    735169 t.dp.mu2[3]._y : 1  [by t.dp.mu2[3].b:=0]
+	    735333 t.out : 0  [by t.dp.mu2[3]._y:=1]
 [] setting high
-	    406278 t.a : 1
-	    406279 t.dp.and2[0]._y : 0  [by t.a:=1]
-	    406280 t.dp.dly[0].a : 1  [by t.dp.and2[0]._y:=0]
-	    426485 t.dp.dly[0]._y : 0  [by t.dp.dly[0].a:=1]
-	    426767 t.dp.dly[0].y : 1  [by t.dp.dly[0]._y:=0]
-	    427535 t.dp.mu2[0]._y : 0  [by t.dp.dly[0].y:=1]
-	    427538 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
-	    449979 t.dp.and2[1]._y : 0  [by t.dp._a[1]:=1]
-	    450530 t.dp.dly[1].a : 1  [by t.dp.and2[1]._y:=0]
-	    451601 t.dp.dly[1]._y : 0  [by t.dp.dly[1].a:=1]
-	    452555 t.dp.dly[1].y : 1  [by t.dp.dly[1]._y:=0]
-	    453636 t.dp.mu2[1]._y : 0  [by t.dp.dly[1].y:=1]
-	    508106 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
-	    509088 t.dp.and2[2]._y : 0  [by t.dp._a[2]:=1]
-	    509106 t.dp.dly[2].a : 1  [by t.dp.and2[2]._y:=0]
-	    513119 t.dp.dly[2]._y : 0  [by t.dp.dly[2].a:=1]
-	    517122 t.dp.dly[2].y : 1  [by t.dp.dly[2]._y:=0]
-	    562023 t.dp.dly[3]._y : 0  [by t.dp.dly[2].y:=1]
-	    583607 t.dp.dly[3].y : 1  [by t.dp.dly[3]._y:=0]
-	    588367 t.dp.mu2[2]._y : 0  [by t.dp.dly[3].y:=1]
-	    588869 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
-	    589072 t.dp.and2[3]._y : 0  [by t.dp._a[3]:=1]
-	    590926 t.dp.dly[4].a : 1  [by t.dp.and2[3]._y:=0]
-	    591065 t.dp.dly[4]._y : 0  [by t.dp.dly[4].a:=1]
-	    627411 t.dp.dly[4].y : 1  [by t.dp.dly[4]._y:=0]
-	    627480 t.dp.dly[5]._y : 0  [by t.dp.dly[4].y:=1]
-	    627491 t.dp.dly[5].y : 1  [by t.dp.dly[5]._y:=0]
-	    679277 t.dp.dly[6]._y : 0  [by t.dp.dly[5].y:=1]
-	    679481 t.dp.dly[6].y : 1  [by t.dp.dly[6]._y:=0]
-	    679496 t.dp.mu2[3]._y : 0  [by t.dp.dly[6].y:=1]
-	    679497 t.y : 1  [by t.dp.mu2[3]._y:=0]
+	    735333 t.in : 1
+	    737528 t.dp.and2[0]._y : 0  [by t.in:=1]
+	    737550 t.dp.dly[0].a : 1  [by t.dp.and2[0]._y:=0]
+	    738397 t.dp.dly[0]._y : 0  [by t.dp.dly[0].a:=1]
+	    768525 t.dp.dly[0].__y : 1  [by t.dp.dly[0]._y:=0]
+	    768658 t.dp.dly[0].___y : 0  [by t.dp.dly[0].__y:=1]
+	    784320 t.dp.dly[0].y : 1  [by t.dp.dly[0].___y:=0]
+	    784679 t.dp.mu2[0]._y : 0  [by t.dp.dly[0].y:=1]
+	    798795 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
+	    799016 t.dp.and2[1]._y : 0  [by t.dp._a[1]:=1]
+	    799023 t.dp.dly[1].a : 1  [by t.dp.and2[1]._y:=0]
+	    799053 t.dp.dly[1]._y : 0  [by t.dp.dly[1].a:=1]
+	    805766 t.dp.dly[1].__y : 1  [by t.dp.dly[1]._y:=0]
+	    863227 t.dp.dly[1].___y : 0  [by t.dp.dly[1].__y:=1]
+	    863318 t.dp.dly[1].y : 1  [by t.dp.dly[1].___y:=0]
+	    865507 t.dp.dly[2]._y : 0  [by t.dp.dly[1].y:=1]
+	    865514 t.dp.dly[2].__y : 1  [by t.dp.dly[2]._y:=0]
+	    868301 t.dp.dly[2].___y : 0  [by t.dp.dly[2].__y:=1]
+	    868407 t.dp.dly[2].y : 1  [by t.dp.dly[2].___y:=0]
+	    868485 t.dp.mu2[1]._y : 0  [by t.dp.dly[2].y:=1]
+	    868760 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
+	    887756 t.dp.and2[2]._y : 0  [by t.dp._a[2]:=1]
+	    888211 t.dp.dly[3].a : 1  [by t.dp.and2[2]._y:=0]
+	    888223 t.dp.dly[3]._y : 0  [by t.dp.dly[3].a:=1]
+	    888627 t.dp.dly[3].__y : 1  [by t.dp.dly[3]._y:=0]
+	    888639 t.dp.dly[3].___y : 0  [by t.dp.dly[3].__y:=1]
+	    894555 t.dp.dly[3].y : 1  [by t.dp.dly[3].___y:=0]
+	    898831 t.dp.dly[4]._y : 0  [by t.dp.dly[3].y:=1]
+	    901730 t.dp.dly[4].__y : 1  [by t.dp.dly[4]._y:=0]
+	    906025 t.dp.dly[4].___y : 0  [by t.dp.dly[4].__y:=1]
+	    906027 t.dp.dly[4].y : 1  [by t.dp.dly[4].___y:=0]
+	    910562 t.dp.dly[5]._y : 0  [by t.dp.dly[4].y:=1]
+	    911811 t.dp.dly[5].__y : 1  [by t.dp.dly[5]._y:=0]
+	    915310 t.dp.dly[5].___y : 0  [by t.dp.dly[5].__y:=1]
+	    915476 t.dp.dly[5].y : 1  [by t.dp.dly[5].___y:=0]
+	    915551 t.dp.dly[6]._y : 0  [by t.dp.dly[5].y:=1]
+	    915896 t.dp.dly[6].__y : 1  [by t.dp.dly[6]._y:=0]
+	    916034 t.dp.dly[6].___y : 0  [by t.dp.dly[6].__y:=1]
+	    921297 t.dp.dly[6].y : 1  [by t.dp.dly[6].___y:=0]
+	    921299 t.dp.mu2[2]._y : 0  [by t.dp.dly[6].y:=1]
+	    965216 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
+	    965217 t.dp.and2[3]._y : 0  [by t.dp._a[3]:=1]
+	    965765 t.dp.dly[7].a : 1  [by t.dp.and2[3]._y:=0]
+	    965776 t.dp.dly[7]._y : 0  [by t.dp.dly[7].a:=1]
+	    966146 t.dp.dly[7].__y : 1  [by t.dp.dly[7]._y:=0]
+	    966213 t.dp.dly[7].___y : 0  [by t.dp.dly[7].__y:=1]
+	    968854 t.dp.dly[7].y : 1  [by t.dp.dly[7].___y:=0]
+	    968870 t.dp.dly[8]._y : 0  [by t.dp.dly[7].y:=1]
+	    973432 t.dp.dly[8].__y : 1  [by t.dp.dly[8]._y:=0]
+	    973960 t.dp.dly[8].___y : 0  [by t.dp.dly[8].__y:=1]
+	    976395 t.dp.dly[8].y : 1  [by t.dp.dly[8].___y:=0]
+	   1003275 t.dp.dly[9]._y : 0  [by t.dp.dly[8].y:=1]
+	   1027200 t.dp.dly[9].__y : 1  [by t.dp.dly[9]._y:=0]
+	   1040241 t.dp.dly[9].___y : 0  [by t.dp.dly[9].__y:=1]
+	   1040243 t.dp.dly[9].y : 1  [by t.dp.dly[9].___y:=0]
+	   1101201 t.dp.dly[10]._y : 0  [by t.dp.dly[9].y:=1]
+	   1101204 t.dp.dly[10].__y : 1  [by t.dp.dly[10]._y:=0]
+	   1101233 t.dp.dly[10].___y : 0  [by t.dp.dly[10].__y:=1]
+	   1101550 t.dp.dly[10].y : 1  [by t.dp.dly[10].___y:=0]
+	   1103151 t.dp.dly[11]._y : 0  [by t.dp.dly[10].y:=1]
+	   1103304 t.dp.dly[11].__y : 1  [by t.dp.dly[11]._y:=0]
+	   1103348 t.dp.dly[11].___y : 0  [by t.dp.dly[11].__y:=1]
+	   1106109 t.dp.dly[11].y : 1  [by t.dp.dly[11].___y:=0]
+	   1119792 t.dp.dly[12]._y : 0  [by t.dp.dly[11].y:=1]
+	   1119793 t.dp.dly[12].__y : 1  [by t.dp.dly[12]._y:=0]
+	   1120010 t.dp.dly[12].___y : 0  [by t.dp.dly[12].__y:=1]
+	   1120032 t.dp.dly[12].y : 1  [by t.dp.dly[12].___y:=0]
+	   1120033 t.dp.dly[13]._y : 0  [by t.dp.dly[12].y:=1]
+	   1121614 t.dp.dly[13].__y : 1  [by t.dp.dly[13]._y:=0]
+	   1130959 t.dp.dly[13].___y : 0  [by t.dp.dly[13].__y:=1]
+	   1131118 t.dp.dly[13].y : 1  [by t.dp.dly[13].___y:=0]
+	   1150794 t.dp.dly[14]._y : 0  [by t.dp.dly[13].y:=1]
+	   1152081 t.dp.dly[14].__y : 1  [by t.dp.dly[14]._y:=0]
+	   1154313 t.dp.dly[14].___y : 0  [by t.dp.dly[14].__y:=1]
+	   1154458 t.dp.mu2[3].b : 1  [by t.dp.dly[14].___y:=0]
+	   1157290 t.dp.mu2[3]._y : 0  [by t.dp.mu2[3].b:=1]
+	   1163644 t.out : 1  [by t.dp.mu2[3]._y:=0]
 [] setting low
-	    679497 t.a : 0
-	    679534 t.dp.and2[0]._y : 1  [by t.a:=0]
-	    680273 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
-	    680385 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
-	    727897 t.dp.dly[0].y : 0  [by t.dp.dly[0]._y:=1]
-	    727937 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
-	    728194 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	    728281 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
-	    728575 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
-	    728576 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
-	    730382 t.dp.dly[1].y : 0  [by t.dp.dly[1]._y:=1]
-	    732389 t.dp.mu2[1]._y : 1  [by t.dp.dly[1].y:=0]
-	    733598 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	    734188 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
-	    734366 t.dp.dly[2].a : 0  [by t.dp.and2[2]._y:=1]
-	    735169 t.dp.dly[2]._y : 1  [by t.dp.dly[2].a:=0]
-	    735333 t.dp.dly[2].y : 0  [by t.dp.dly[2]._y:=1]
-	    737528 t.dp.dly[3]._y : 1  [by t.dp.dly[2].y:=0]
-	    737550 t.dp.dly[3].y : 0  [by t.dp.dly[3]._y:=1]
-	    738397 t.dp.mu2[2]._y : 1  [by t.dp.dly[3].y:=0]
-	    768525 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    768658 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
-	    784320 t.dp.dly[4].a : 0  [by t.dp.and2[3]._y:=1]
-	    784679 t.dp.dly[4]._y : 1  [by t.dp.dly[4].a:=0]
-	    798795 t.dp.dly[4].y : 0  [by t.dp.dly[4]._y:=1]
-	    799016 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
-	    799023 t.dp.dly[5].y : 0  [by t.dp.dly[5]._y:=1]
-	    799053 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
-	    805766 t.dp.dly[6].y : 0  [by t.dp.dly[6]._y:=1]
-	    863227 t.dp.mu2[3]._y : 1  [by t.dp.dly[6].y:=0]
-	    863318 t.y : 0  [by t.dp.mu2[3]._y:=1]
+	   1163644 t.in : 0
+	   1163645 t.dp.and2[0]._y : 1  [by t.in:=0]
+	   1202929 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
+	   1203091 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
+	   1210460 t.dp.dly[0].__y : 0  [by t.dp.dly[0]._y:=1]
+	   1210474 t.dp.dly[0].___y : 1  [by t.dp.dly[0].__y:=0]
+	   1210481 t.dp.dly[0].y : 0  [by t.dp.dly[0].___y:=1]
+	   1210641 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
+	   1232198 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
+	   1232199 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
+	   1232200 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
+	   1232201 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
+	   1234444 t.dp.dly[1].__y : 0  [by t.dp.dly[1]._y:=1]
+	   1234631 t.dp.dly[1].___y : 1  [by t.dp.dly[1].__y:=0]
+	   1234632 t.dp.dly[1].y : 0  [by t.dp.dly[1].___y:=1]
+	   1238814 t.dp.dly[2]._y : 1  [by t.dp.dly[1].y:=0]
+	   1273596 t.dp.dly[2].__y : 0  [by t.dp.dly[2]._y:=1]
+	   1273597 t.dp.dly[2].___y : 1  [by t.dp.dly[2].__y:=0]
+	   1274450 t.dp.dly[2].y : 0  [by t.dp.dly[2].___y:=1]
+	   1274455 t.dp.mu2[1]._y : 1  [by t.dp.dly[2].y:=0]
+	   1275346 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
+	   1275347 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
+	   1275364 t.dp.dly[3].a : 0  [by t.dp.and2[2]._y:=1]
+	   1277937 t.dp.dly[3]._y : 1  [by t.dp.dly[3].a:=0]
+	   1286298 t.dp.dly[3].__y : 0  [by t.dp.dly[3]._y:=1]
+	   1286301 t.dp.dly[3].___y : 1  [by t.dp.dly[3].__y:=0]
+	   1287242 t.dp.dly[3].y : 0  [by t.dp.dly[3].___y:=1]
+	   1346204 t.dp.dly[4]._y : 1  [by t.dp.dly[3].y:=0]
+	   1346205 t.dp.dly[4].__y : 0  [by t.dp.dly[4]._y:=1]
+	   1346247 t.dp.dly[4].___y : 1  [by t.dp.dly[4].__y:=0]
+	   1349064 t.dp.dly[4].y : 0  [by t.dp.dly[4].___y:=1]
+	   1362797 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
+	   1362892 t.dp.dly[5].__y : 0  [by t.dp.dly[5]._y:=1]
+	   1363227 t.dp.dly[5].___y : 1  [by t.dp.dly[5].__y:=0]
+	   1363235 t.dp.dly[5].y : 0  [by t.dp.dly[5].___y:=1]
+	   1363269 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
+	   1377156 t.dp.dly[6].__y : 0  [by t.dp.dly[6]._y:=1]
+	   1378074 t.dp.dly[6].___y : 1  [by t.dp.dly[6].__y:=0]
+	   1378078 t.dp.dly[6].y : 0  [by t.dp.dly[6].___y:=1]
+	   1424456 t.dp.mu2[2]._y : 1  [by t.dp.dly[6].y:=0]
+	   1426854 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
+	   1430069 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
+	   1477188 t.dp.dly[7].a : 0  [by t.dp.and2[3]._y:=1]
+	   1477236 t.dp.dly[7]._y : 1  [by t.dp.dly[7].a:=0]
+	   1477239 t.dp.dly[7].__y : 0  [by t.dp.dly[7]._y:=1]
+	   1477417 t.dp.dly[7].___y : 1  [by t.dp.dly[7].__y:=0]
+	   1498394 t.dp.dly[7].y : 0  [by t.dp.dly[7].___y:=1]
+	   1510293 t.dp.dly[8]._y : 1  [by t.dp.dly[7].y:=0]
+	   1516244 t.dp.dly[8].__y : 0  [by t.dp.dly[8]._y:=1]
+	   1555729 t.dp.dly[8].___y : 1  [by t.dp.dly[8].__y:=0]
+	   1556556 t.dp.dly[8].y : 0  [by t.dp.dly[8].___y:=1]
+	   1556729 t.dp.dly[9]._y : 1  [by t.dp.dly[8].y:=0]
+	   1556913 t.dp.dly[9].__y : 0  [by t.dp.dly[9]._y:=1]
+	   1556914 t.dp.dly[9].___y : 1  [by t.dp.dly[9].__y:=0]
+	   1556987 t.dp.dly[9].y : 0  [by t.dp.dly[9].___y:=1]
+	   1556991 t.dp.dly[10]._y : 1  [by t.dp.dly[9].y:=0]
+	   1594279 t.dp.dly[10].__y : 0  [by t.dp.dly[10]._y:=1]
+	   1594375 t.dp.dly[10].___y : 1  [by t.dp.dly[10].__y:=0]
+	   1594511 t.dp.dly[10].y : 0  [by t.dp.dly[10].___y:=1]
+	   1594512 t.dp.dly[11]._y : 1  [by t.dp.dly[10].y:=0]
+	   1613558 t.dp.dly[11].__y : 0  [by t.dp.dly[11]._y:=1]
+	   1613799 t.dp.dly[11].___y : 1  [by t.dp.dly[11].__y:=0]
+	   1617758 t.dp.dly[11].y : 0  [by t.dp.dly[11].___y:=1]
+	   1617770 t.dp.dly[12]._y : 1  [by t.dp.dly[11].y:=0]
+	   1621670 t.dp.dly[12].__y : 0  [by t.dp.dly[12]._y:=1]
+	   1622699 t.dp.dly[12].___y : 1  [by t.dp.dly[12].__y:=0]
+	   1622700 t.dp.dly[12].y : 0  [by t.dp.dly[12].___y:=1]
+	   1622756 t.dp.dly[13]._y : 1  [by t.dp.dly[12].y:=0]
+	   1667762 t.dp.dly[13].__y : 0  [by t.dp.dly[13]._y:=1]
+	   1667763 t.dp.dly[13].___y : 1  [by t.dp.dly[13].__y:=0]
+	   1667800 t.dp.dly[13].y : 0  [by t.dp.dly[13].___y:=1]
+	   1691175 t.dp.dly[14]._y : 1  [by t.dp.dly[13].y:=0]
+	   1691176 t.dp.dly[14].__y : 0  [by t.dp.dly[14]._y:=1]
+	   1694740 t.dp.dly[14].___y : 1  [by t.dp.dly[14].__y:=0]
+	   1696432 t.dp.mu2[3].b : 0  [by t.dp.dly[14].___y:=1]
+	   1696445 t.dp.mu2[3]._y : 1  [by t.dp.mu2[3].b:=0]
+	   1713429 t.out : 0  [by t.dp.mu2[3]._y:=1]
 [] setting configs low
-	    863318 t.s[0] : 0
-	    863318 t.s[3] : 0
-	    863318 t.s[2] : 0
-	    863318 t.s[1] : 0
-	    863325 t.dp.mu2[3]._s : 1  [by t.s[3]:=0]
-	    863424 t.dp.mu2[1]._s : 1  [by t.s[1]:=0]
-	    865507 t.dp.mu2[0]._s : 1  [by t.s[0]:=0]
-	    866105 t.dp.mu2[2]._s : 1  [by t.s[2]:=0]
+	   1713429 t.s[0] : 0
+	   1713429 t.s[3] : 0
+	   1713429 t.s[2] : 0
+	   1713429 t.s[1] : 0
+	   1713430 t.dp.mu2[1]._s : 1  [by t.s[1]:=0]
+	   1713450 t.dp.mu2[2]._s : 1  [by t.s[2]:=0]
+	   1713454 t.dp.mu2[3]._s : 1  [by t.s[3]:=0]
+	   1713786 t.dp.mu2[0]._s : 1  [by t.s[0]:=0]
 [] setting high
-	    866105 t.a : 1
-	    866183 t.dp.mu2[0]._y : 0  [by t.a:=1]
-	    866458 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
-	    885454 t.dp.mu2[1]._y : 0  [by t.dp._a[1]:=1]
-	    885909 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
-	    885921 t.dp.mu2[2]._y : 0  [by t.dp._a[2]:=1]
-	    886325 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
-	    886337 t.dp.mu2[3]._y : 0  [by t.dp._a[3]:=1]
-	    892253 t.y : 1  [by t.dp.mu2[3]._y:=0]
+	   1713786 t.in : 1
+	   1723434 t.dp.mu2[0]._y : 0  [by t.in:=1]
+	   1723435 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
+	   1723436 t.dp.mu2[1]._y : 0  [by t.dp._a[1]:=1]
+	   1723597 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
+	   1724634 t.dp.mu2[2]._y : 0  [by t.dp._a[2]:=1]
+	   1724639 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
+	   1725220 t.dp.mu2[3]._y : 0  [by t.dp._a[3]:=1]
+	   1725628 t.out : 1  [by t.dp.mu2[3]._y:=0]
 [] setting low
-	    892253 t.a : 0
-	    896529 t.dp.mu2[0]._y : 1  [by t.a:=0]
-	    899428 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	    903723 t.dp.mu2[1]._y : 1  [by t.dp._a[1]:=0]
-	    903725 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	    908260 t.dp.mu2[2]._y : 1  [by t.dp._a[2]:=0]
-	    909509 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    913008 t.dp.mu2[3]._y : 1  [by t.dp._a[3]:=0]
-	    913174 t.y : 0  [by t.dp.mu2[3]._y:=1]
+	   1725628 t.in : 0
+	   1725639 t.dp.mu2[0]._y : 1  [by t.in:=0]
+	   1726686 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
+	   1726700 t.dp.mu2[1]._y : 1  [by t.dp._a[1]:=0]
+	   1726718 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
+	   1726722 t.dp.mu2[2]._y : 1  [by t.dp._a[2]:=0]
+	   1726826 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
+	   1758270 t.dp.mu2[3]._y : 1  [by t.dp._a[3]:=0]
+	   1759474 t.out : 0  [by t.dp.mu2[3]._y:=1]

test/unit_tests/delayprog_4/run/test.prs

@@ -1,11 +1,6 @@
 = "GND" "GND"
 = "Vdd" "Vdd"
 = "Reset" "Reset"
-= "t.y" "t.dp.y"
-= "t.a" "t.dp.a"
-= "t.dp.a" "t.dp.mu2[0].a"
-= "t.dp.a" "t.dp.and2[0].a"
-= "t.dp.a" "t.dp._a[0]"
 "t.dp.and2[0].a"&"t.dp.and2[0].b"->"t.dp.and2[0]._y"-
 ~("t.dp.and2[0].a"&"t.dp.and2[0].b")->"t.dp.and2[0]._y"+
 "t.dp.and2[0]._y"->"t.dp.and2[0].y"-
@@ -102,72 +97,140 @@
 ~("t.dp.mu2[3]._y")->"t.dp.mu2[3].y"+
 "t.dp.dly[0].a"->"t.dp.dly[0]._y"-
 ~("t.dp.dly[0].a")->"t.dp.dly[0]._y"+
-"t.dp.dly[0]._y"->"t.dp.dly[0].y"-
-~("t.dp.dly[0]._y")->"t.dp.dly[0].y"+
+"t.dp.dly[0]._y"->"t.dp.dly[0].__y"-
+~("t.dp.dly[0]._y")->"t.dp.dly[0].__y"+
+"t.dp.dly[0].__y"->"t.dp.dly[0].___y"-
+~("t.dp.dly[0].__y")->"t.dp.dly[0].___y"+
+"t.dp.dly[0].___y"->"t.dp.dly[0].y"-
+~("t.dp.dly[0].___y")->"t.dp.dly[0].y"+
 "t.dp.dly[1].a"->"t.dp.dly[1]._y"-
 ~("t.dp.dly[1].a")->"t.dp.dly[1]._y"+
-"t.dp.dly[1]._y"->"t.dp.dly[1].y"-
-~("t.dp.dly[1]._y")->"t.dp.dly[1].y"+
+"t.dp.dly[1]._y"->"t.dp.dly[1].__y"-
+~("t.dp.dly[1]._y")->"t.dp.dly[1].__y"+
+"t.dp.dly[1].__y"->"t.dp.dly[1].___y"-
+~("t.dp.dly[1].__y")->"t.dp.dly[1].___y"+
+"t.dp.dly[1].___y"->"t.dp.dly[1].y"-
+~("t.dp.dly[1].___y")->"t.dp.dly[1].y"+
 "t.dp.dly[2].a"->"t.dp.dly[2]._y"-
 ~("t.dp.dly[2].a")->"t.dp.dly[2]._y"+
-"t.dp.dly[2]._y"->"t.dp.dly[2].y"-
-~("t.dp.dly[2]._y")->"t.dp.dly[2].y"+
+"t.dp.dly[2]._y"->"t.dp.dly[2].__y"-
+~("t.dp.dly[2]._y")->"t.dp.dly[2].__y"+
+"t.dp.dly[2].__y"->"t.dp.dly[2].___y"-
+~("t.dp.dly[2].__y")->"t.dp.dly[2].___y"+
+"t.dp.dly[2].___y"->"t.dp.dly[2].y"-
+~("t.dp.dly[2].___y")->"t.dp.dly[2].y"+
 "t.dp.dly[3].a"->"t.dp.dly[3]._y"-
 ~("t.dp.dly[3].a")->"t.dp.dly[3]._y"+
-"t.dp.dly[3]._y"->"t.dp.dly[3].y"-
-~("t.dp.dly[3]._y")->"t.dp.dly[3].y"+
+"t.dp.dly[3]._y"->"t.dp.dly[3].__y"-
+~("t.dp.dly[3]._y")->"t.dp.dly[3].__y"+
+"t.dp.dly[3].__y"->"t.dp.dly[3].___y"-
+~("t.dp.dly[3].__y")->"t.dp.dly[3].___y"+
+"t.dp.dly[3].___y"->"t.dp.dly[3].y"-
+~("t.dp.dly[3].___y")->"t.dp.dly[3].y"+
 "t.dp.dly[4].a"->"t.dp.dly[4]._y"-
 ~("t.dp.dly[4].a")->"t.dp.dly[4]._y"+
-"t.dp.dly[4]._y"->"t.dp.dly[4].y"-
-~("t.dp.dly[4]._y")->"t.dp.dly[4].y"+
+"t.dp.dly[4]._y"->"t.dp.dly[4].__y"-
+~("t.dp.dly[4]._y")->"t.dp.dly[4].__y"+
+"t.dp.dly[4].__y"->"t.dp.dly[4].___y"-
+~("t.dp.dly[4].__y")->"t.dp.dly[4].___y"+
+"t.dp.dly[4].___y"->"t.dp.dly[4].y"-
+~("t.dp.dly[4].___y")->"t.dp.dly[4].y"+
 "t.dp.dly[5].a"->"t.dp.dly[5]._y"-
 ~("t.dp.dly[5].a")->"t.dp.dly[5]._y"+
-"t.dp.dly[5]._y"->"t.dp.dly[5].y"-
-~("t.dp.dly[5]._y")->"t.dp.dly[5].y"+
+"t.dp.dly[5]._y"->"t.dp.dly[5].__y"-
+~("t.dp.dly[5]._y")->"t.dp.dly[5].__y"+
+"t.dp.dly[5].__y"->"t.dp.dly[5].___y"-
+~("t.dp.dly[5].__y")->"t.dp.dly[5].___y"+
+"t.dp.dly[5].___y"->"t.dp.dly[5].y"-
+~("t.dp.dly[5].___y")->"t.dp.dly[5].y"+
 "t.dp.dly[6].a"->"t.dp.dly[6]._y"-
 ~("t.dp.dly[6].a")->"t.dp.dly[6]._y"+
-"t.dp.dly[6]._y"->"t.dp.dly[6].y"-
-~("t.dp.dly[6]._y")->"t.dp.dly[6].y"+
+"t.dp.dly[6]._y"->"t.dp.dly[6].__y"-
+~("t.dp.dly[6]._y")->"t.dp.dly[6].__y"+
+"t.dp.dly[6].__y"->"t.dp.dly[6].___y"-
+~("t.dp.dly[6].__y")->"t.dp.dly[6].___y"+
+"t.dp.dly[6].___y"->"t.dp.dly[6].y"-
+~("t.dp.dly[6].___y")->"t.dp.dly[6].y"+
 "t.dp.dly[7].a"->"t.dp.dly[7]._y"-
 ~("t.dp.dly[7].a")->"t.dp.dly[7]._y"+
-"t.dp.dly[7]._y"->"t.dp.dly[7].y"-
-~("t.dp.dly[7]._y")->"t.dp.dly[7].y"+
+"t.dp.dly[7]._y"->"t.dp.dly[7].__y"-
+~("t.dp.dly[7]._y")->"t.dp.dly[7].__y"+
+"t.dp.dly[7].__y"->"t.dp.dly[7].___y"-
+~("t.dp.dly[7].__y")->"t.dp.dly[7].___y"+
+"t.dp.dly[7].___y"->"t.dp.dly[7].y"-
+~("t.dp.dly[7].___y")->"t.dp.dly[7].y"+
 "t.dp.dly[8].a"->"t.dp.dly[8]._y"-
 ~("t.dp.dly[8].a")->"t.dp.dly[8]._y"+
-"t.dp.dly[8]._y"->"t.dp.dly[8].y"-
-~("t.dp.dly[8]._y")->"t.dp.dly[8].y"+
+"t.dp.dly[8]._y"->"t.dp.dly[8].__y"-
+~("t.dp.dly[8]._y")->"t.dp.dly[8].__y"+
+"t.dp.dly[8].__y"->"t.dp.dly[8].___y"-
+~("t.dp.dly[8].__y")->"t.dp.dly[8].___y"+
+"t.dp.dly[8].___y"->"t.dp.dly[8].y"-
+~("t.dp.dly[8].___y")->"t.dp.dly[8].y"+
 "t.dp.dly[9].a"->"t.dp.dly[9]._y"-
 ~("t.dp.dly[9].a")->"t.dp.dly[9]._y"+
-"t.dp.dly[9]._y"->"t.dp.dly[9].y"-
-~("t.dp.dly[9]._y")->"t.dp.dly[9].y"+
+"t.dp.dly[9]._y"->"t.dp.dly[9].__y"-
+~("t.dp.dly[9]._y")->"t.dp.dly[9].__y"+
+"t.dp.dly[9].__y"->"t.dp.dly[9].___y"-
+~("t.dp.dly[9].__y")->"t.dp.dly[9].___y"+
+"t.dp.dly[9].___y"->"t.dp.dly[9].y"-
+~("t.dp.dly[9].___y")->"t.dp.dly[9].y"+
 "t.dp.dly[10].a"->"t.dp.dly[10]._y"-
 ~("t.dp.dly[10].a")->"t.dp.dly[10]._y"+
-"t.dp.dly[10]._y"->"t.dp.dly[10].y"-
-~("t.dp.dly[10]._y")->"t.dp.dly[10].y"+
+"t.dp.dly[10]._y"->"t.dp.dly[10].__y"-
+~("t.dp.dly[10]._y")->"t.dp.dly[10].__y"+
+"t.dp.dly[10].__y"->"t.dp.dly[10].___y"-
+~("t.dp.dly[10].__y")->"t.dp.dly[10].___y"+
+"t.dp.dly[10].___y"->"t.dp.dly[10].y"-
+~("t.dp.dly[10].___y")->"t.dp.dly[10].y"+
 "t.dp.dly[11].a"->"t.dp.dly[11]._y"-
 ~("t.dp.dly[11].a")->"t.dp.dly[11]._y"+
-"t.dp.dly[11]._y"->"t.dp.dly[11].y"-
-~("t.dp.dly[11]._y")->"t.dp.dly[11].y"+
+"t.dp.dly[11]._y"->"t.dp.dly[11].__y"-
+~("t.dp.dly[11]._y")->"t.dp.dly[11].__y"+
+"t.dp.dly[11].__y"->"t.dp.dly[11].___y"-
+~("t.dp.dly[11].__y")->"t.dp.dly[11].___y"+
+"t.dp.dly[11].___y"->"t.dp.dly[11].y"-
+~("t.dp.dly[11].___y")->"t.dp.dly[11].y"+
 "t.dp.dly[12].a"->"t.dp.dly[12]._y"-
 ~("t.dp.dly[12].a")->"t.dp.dly[12]._y"+
-"t.dp.dly[12]._y"->"t.dp.dly[12].y"-
-~("t.dp.dly[12]._y")->"t.dp.dly[12].y"+
+"t.dp.dly[12]._y"->"t.dp.dly[12].__y"-
+~("t.dp.dly[12]._y")->"t.dp.dly[12].__y"+
+"t.dp.dly[12].__y"->"t.dp.dly[12].___y"-
+~("t.dp.dly[12].__y")->"t.dp.dly[12].___y"+
+"t.dp.dly[12].___y"->"t.dp.dly[12].y"-
+~("t.dp.dly[12].___y")->"t.dp.dly[12].y"+
 "t.dp.dly[13].a"->"t.dp.dly[13]._y"-
 ~("t.dp.dly[13].a")->"t.dp.dly[13]._y"+
-"t.dp.dly[13]._y"->"t.dp.dly[13].y"-
-~("t.dp.dly[13]._y")->"t.dp.dly[13].y"+
+"t.dp.dly[13]._y"->"t.dp.dly[13].__y"-
+~("t.dp.dly[13]._y")->"t.dp.dly[13].__y"+
+"t.dp.dly[13].__y"->"t.dp.dly[13].___y"-
+~("t.dp.dly[13].__y")->"t.dp.dly[13].___y"+
+"t.dp.dly[13].___y"->"t.dp.dly[13].y"-
+~("t.dp.dly[13].___y")->"t.dp.dly[13].y"+
 "t.dp.dly[14].a"->"t.dp.dly[14]._y"-
 ~("t.dp.dly[14].a")->"t.dp.dly[14]._y"+
-"t.dp.dly[14]._y"->"t.dp.dly[14].y"-
-~("t.dp.dly[14]._y")->"t.dp.dly[14].y"+
-= "t.dp.dly[6].y" "t.dp.mu2[3].b"
+"t.dp.dly[14]._y"->"t.dp.dly[14].__y"-
+~("t.dp.dly[14]._y")->"t.dp.dly[14].__y"+
+"t.dp.dly[14].__y"->"t.dp.dly[14].___y"-
+~("t.dp.dly[14].__y")->"t.dp.dly[14].___y"+
+"t.dp.dly[14].___y"->"t.dp.dly[14].y"-
+~("t.dp.dly[14].___y")->"t.dp.dly[14].y"+
+= "t.dp.dly[14].y" "t.dp.mu2[3].b"
+= "t.dp.dly[14].a" "t.dp.dly[13].y"
+= "t.dp.dly[13].a" "t.dp.dly[12].y"
+= "t.dp.dly[12].a" "t.dp.dly[11].y"
+= "t.dp.dly[11].a" "t.dp.dly[10].y"
+= "t.dp.dly[10].a" "t.dp.dly[9].y"
+= "t.dp.dly[9].a" "t.dp.dly[8].y"
+= "t.dp.dly[8].a" "t.dp.dly[7].y"
+= "t.dp.dly[7].a" "t.dp.and2[3].y"
+= "t.dp.dly[6].y" "t.dp.mu2[2].b"
 = "t.dp.dly[6].a" "t.dp.dly[5].y"
 = "t.dp.dly[5].a" "t.dp.dly[4].y"
-= "t.dp.dly[4].a" "t.dp.and2[3].y"
-= "t.dp.dly[3].y" "t.dp.mu2[2].b"
-= "t.dp.dly[3].a" "t.dp.dly[2].y"
-= "t.dp.dly[2].a" "t.dp.and2[2].y"
-= "t.dp.dly[1].y" "t.dp.mu2[1].b"
+= "t.dp.dly[4].a" "t.dp.dly[3].y"
+= "t.dp.dly[3].a" "t.dp.and2[2].y"
+= "t.dp.dly[2].y" "t.dp.mu2[1].b"
+= "t.dp.dly[2].a" "t.dp.dly[1].y"
 = "t.dp.dly[1].a" "t.dp.and2[1].y"
 = "t.dp.dly[0].y" "t.dp.mu2[0].b"
 = "t.dp.dly[0].a" "t.dp.and2[0].y"
@@ -180,10 +243,15 @@
 = "t.dp._a[3]" "t.dp.mu2[3].a"
 = "t.dp._a[3]" "t.dp.and2[3].a"
 = "t.dp._a[3]" "t.dp.mu2[2].y"
-= "t.dp.y" "t.dp.mu2[3].y"
-= "t.dp.y" "t.dp._a[4]"
+= "t.dp.out" "t.dp.mu2[3].y"
+= "t.dp.out" "t.dp._a[4]"
+= "t.dp.in" "t.dp.mu2[0].a"
+= "t.dp.in" "t.dp.and2[0].a"
+= "t.dp.in" "t.dp._a[0]"
 = "Vdd" "t.dp.supply.vdd"
 = "GND" "t.dp.supply.vss"
+= "t.out" "t.dp.out"
+= "t.in" "t.dp.in"
 = "t.s[0]" "t.dp.s[0]"
 = "t.s[1]" "t.dp.s[1]"
 = "t.s[2]" "t.dp.s[2]"

test/unit_tests/delayprog_4/test.act

@@ -31,8 +31,8 @@ import globals;
 
 open tmpl::dataflow_neuro;
 
-defproc delayprog_4 (bool? s[4], a; bool! y){
-    delayprog<4> dp(.a=a, .y=y, .s = s);
+defproc delayprog_4 (bool? s[4], in; bool! out){
+    delayprog<4> dp(.in=in, .out=out, .s = s);
     dp.supply.vss = GND;
     dp.supply.vdd = Vdd;
 

test/unit_tests/delayprog_4/test.prsim

@@ -2,7 +2,7 @@ watchall
 
 system "echo '0'"
 
-set t.a  0
+set t.in  0
 set t.s[0] 1
 set t.s[1] 1
 set t.s[2] 1
@@ -11,17 +11,17 @@ set t.s[3] 1
 cycle
 mode run
 
-assert t.y 0
+# assert t.out 0
 
 system "echo '[] setting high'"
-set t.a  1
+set t.in  1
 cycle
-assert t.y 1
+assert t.out 1
 
 system "echo '[] setting low'"
-set t.a  0
+set t.in  0
 cycle
-assert t.y 0
+assert t.out 0
 
 system "echo '[] setting configs low'"
 set t.s[0] 0
@@ -29,14 +29,14 @@ set t.s[1] 0
 set t.s[2] 0
 set t.s[3] 0
 cycle
-assert t.y 0
+assert t.out 0
 
 system "echo '[] setting high'"
-set t.a  1
+set t.in  1
 cycle
-assert t.y 1
+assert t.out 1
 
 system "echo '[] setting low'"
-set t.a  0
+set t.in  0
 cycle
-assert t.y 0
+assert t.out 0

test/unit_tests/demux_7/run/prsim.out

@@ -1,4 +1,4 @@
-my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.tmp[9] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux.vc.tmp[7] my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.C2Els[1]._y my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.tmp[6] my_demux.my_demux.vc.tmp[1] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.C2Els[0]._y my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux.vc.tmp[8] my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_c_v_ my_demux.out2.v my_demux.my_demux._in_v my_demux.my_demux.vc.tmp[4] my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.tmp[0] my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.my_demux.vc.tmp[5] my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux._out_v my_demux.my_demux.vc.C3Els[0]._y my_demux.in.v my_demux.my_demux.vc.C3Els[1]._y my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.tmp[3] my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.vc.tmp[2] my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y 
+my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.cond.v my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.ct.in[4] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.vc.ct.tmp[9] my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.ct.tmp[8] my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.ct.in[5] my_demux.my_demux.vc.ct.in[1] my_demux.my_demux.vc.ct.in[6] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.ct.in[2] my_demux.my_demux.vc.ct.tmp[7] my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_v my_demux.my_demux.vc.ct.C3Els[0]._y my_demux.my_demux.vc.ct.in[0] my_demux.out2.v my_demux.my_demux.vc.ct.C3Els[1]._y my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.ct.C2Els[0]._y my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux.vc.ct.in[3] my_demux.my_demux._out_v my_demux.in.v my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.ct.C2Els[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y 
 	    119199 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
 	    119199 my_demux.my_demux.c_buf_f.in : 0
 	    119199 my_demux.my_demux.c_buf_t.in : 0
@@ -26,7 +26,7 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
 	    119286 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
 	    119311 my_demux.my_demux._out1_a_B : 1  [by my_demux.out1.a:=0]
 	    119333 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    119378 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
+	    119378 my_demux.my_demux.vc.ct.in[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
 	    119403 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
 	    119456 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_f_buf_func[6].n1:=0]
 	    119493 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_f_buf_func[2].n1:=0]
@@ -36,35 +36,35 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
 	    119757 my_demux.my_demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux._en:=1]
 	    119790 my_demux.my_demux._c_f_buf[0] : 0  [by my_demux.my_demux.c_buf_f.buf2._y:=1]
 	    119848 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf2._y:=0]
-	    119852 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
+	    119852 my_demux.my_demux.vc.ct.in[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
 	    119938 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.c_buf_t.in:=0]
 	    120039 my_demux.my_demux._c_t_buf[0] : 0  [by my_demux.my_demux.c_buf_t.buf2._y:=1]
 	    120158 my_demux.my_demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
 	    120165 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
 	    120408 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
 	    121005 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    121111 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
+	    121111 my_demux.my_demux.vc.ct.in[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
 	    121206 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
-	    121284 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
-	    121481 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    121756 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[0]:=0]
+	    121284 my_demux.my_demux.vc.ct.in[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
+	    121481 my_demux.my_demux.vc.ct.in[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
+	    121756 my_demux.my_demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[0]:=0]
 	    122127 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    123195 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
-	    123650 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[3]:=0]
-	    123662 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
+	    123195 my_demux.my_demux.vc.ct.in[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
+	    123650 my_demux.my_demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.vc.ct.in[3]:=0]
+	    123662 my_demux.my_demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
 	    126256 my_demux.my_demux._en2_X_t[0] : 1  [by my_demux.my_demux.out2_en_buf_t.buf2._y:=0]
 	    133652 my_demux.my_demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux._en:=1]
 	    134056 my_demux.my_demux._en2_X_f[0] : 1  [by my_demux.my_demux.out2_en_buf_f.buf2._y:=0]
-	    135118 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    135130 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
-	    140752 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    141046 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    145322 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[9]:=0]
-	    148221 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
+	    135118 my_demux.my_demux.vc.ct.in[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
+	    135130 my_demux.my_demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[6]:=0]
+	    140752 my_demux.my_demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
+	    141046 my_demux.my_demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
+	    145322 my_demux.my_demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.vc.ct.tmp[9]:=0]
+	    148221 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
 	    148223 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._in_v:=0]
 	    149461 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
 	    152516 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    152758 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
+	    152758 my_demux.cond.v : 0  [by my_demux.my_demux.c_el._y:=1]
 	    153765 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
 	    166711 my_demux.my_demux._out2_a_B : 1  [by my_demux.out2.a:=0]
 	    166877 my_demux.my_demux.out2_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out2_a_B:=1]
@@ -94,7 +94,7 @@ Output neutral checked
 	    226364 my_demux.my_demux.vc.OR2_tf[4]._y : 0  [by my_demux.my_demux.out1_t_buf_func[4].n1:=1]
 	    226415 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
 	    226718 my_demux.my_demux.vc.OR2_tf[6]._y : 0  [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
-	    226720 my_demux.my_demux.vc.tmp[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
+	    226720 my_demux.my_demux.vc.ct.in[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
 	    226876 my_demux.my_demux.vc.OR2_tf[3]._y : 0  [by my_demux.my_demux.out1_t_buf_func[3].n1:=1]
 	    226896 my_demux.my_demux.c_buf_t.buf2._y : 0  [by my_demux.my_demux.c_buf_t.in:=1]
 	    226899 my_demux.my_demux._c_t_buf[0] : 1  [by my_demux.my_demux.c_buf_t.buf2._y:=0]
@@ -109,30 +109,30 @@ Output neutral checked
 	    228500 my_demux.my_demux.out1_t_buf_func[2]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
 	    228783 my_demux.my_demux.vc.OR2_tf[2]._y : 0  [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
 	    228989 my_demux.my_demux.vc.OR2_tf[5]._y : 0  [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
-	    229148 my_demux.my_demux.vc.tmp[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
+	    229148 my_demux.my_demux.vc.ct.in[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
 	    229660 my_demux.my_demux.out1_t_buf_func[5]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
 	    230081 my_demux.my_demux.out1_t_buf_func[2].y : 1  [by my_demux.my_demux.out1_t_buf_func[2]._y:=0]
 	    230910 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    232197 my_demux.my_demux.vc.tmp[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    238128 my_demux.my_demux.vc.tmp[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
-	    239456 my_demux.my_demux.vc.tmp[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
+	    232197 my_demux.my_demux.vc.ct.in[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
+	    238128 my_demux.my_demux.vc.ct.in[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
+	    239456 my_demux.my_demux.vc.ct.in[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
 	    240582 my_demux.my_demux.out1_t_buf_func[6]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
 	    240727 my_demux.my_demux.out1_t_buf_func[6].y : 1  [by my_demux.my_demux.out1_t_buf_func[6]._y:=0]
-	    241688 my_demux.my_demux.vc.C2Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[1]:=1]
-	    244520 my_demux.my_demux.vc.tmp[7] : 1  [by my_demux.my_demux.vc.C2Els[0]._y:=0]
+	    241688 my_demux.my_demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[1]:=1]
+	    244520 my_demux.my_demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
 	    249336 my_demux.my_demux.out1_t_buf_func[5].y : 1  [by my_demux.my_demux.out1_t_buf_func[5]._y:=0]
-	    250289 my_demux.my_demux.vc.tmp[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
+	    250289 my_demux.my_demux.vc.ct.in[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
 	    253239 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    256643 my_demux.my_demux.vc.C3Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[4]:=1]
-	    256644 my_demux.my_demux.vc.tmp[9] : 1  [by my_demux.my_demux.vc.C3Els[0]._y:=0]
-	    287834 my_demux.my_demux.vc.tmp[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
-	    327118 my_demux.my_demux.vc.C2Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[3]:=1]
-	    327280 my_demux.my_demux.vc.tmp[8] : 1  [by my_demux.my_demux.vc.C2Els[1]._y:=0]
-	    334649 my_demux.my_demux.vc.C3Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[8]:=1]
-	    334663 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.C3Els[1]._y:=0]
+	    256643 my_demux.my_demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[4]:=1]
+	    256644 my_demux.my_demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
+	    287834 my_demux.my_demux.vc.ct.in[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
+	    327118 my_demux.my_demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.vc.ct.in[3]:=1]
+	    327280 my_demux.my_demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
+	    334649 my_demux.my_demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.vc.ct.tmp[8]:=1]
+	    334663 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
 	    334670 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
 	    334823 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    334824 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
+	    334824 my_demux.cond.v : 1  [by my_demux.my_demux.c_el._y:=0]
 	    356227 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
 	    356227 my_demux.out1.v : 1
 	    356228 my_demux.my_demux.out_or._y : 0  [by my_demux.out1.v:=1]
@@ -158,25 +158,25 @@ Output neutral checked
 	    393460 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_t_buf_func[4].n1:=0]
 	    393462 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
 	    393501 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
-	    393596 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
+	    393596 my_demux.my_demux.vc.ct.in[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
 	    394400 my_demux.my_demux.vc.OR2_tf[5]._y : 1  [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
-	    394735 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
+	    394735 my_demux.my_demux.vc.ct.in[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
 	    396032 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    396040 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    396277 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
+	    396040 my_demux.my_demux.vc.ct.in[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
+	    396277 my_demux.my_demux.vc.ct.in[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
 	    401820 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
-	    401854 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    407195 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
-	    408113 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[2]:=0]
-	    408117 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
-	    415741 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
+	    401854 my_demux.my_demux.vc.ct.in[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
+	    407195 my_demux.my_demux.vc.ct.in[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
+	    408113 my_demux.my_demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.vc.ct.in[2]:=0]
+	    408117 my_demux.my_demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
+	    415741 my_demux.my_demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[6]:=0]
 	    452421 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    454819 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    458034 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[1]:=0]
-	    462119 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    505153 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    505201 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[7]:=0]
-	    505204 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
+	    454819 my_demux.my_demux.vc.ct.in[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
+	    458034 my_demux.my_demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[1]:=0]
+	    462119 my_demux.my_demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
+	    505153 my_demux.my_demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
+	    505201 my_demux.my_demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.vc.ct.tmp[7]:=0]
+	    505204 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
 	    505382 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
 	    526359 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
 First Cond Checked
@@ -214,7 +214,7 @@ Output neutral checked
 	    585101 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
 	    585114 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._c_v:=0]
 	    586919 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
-	    602098 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
+	    602098 my_demux.cond.v : 0  [by my_demux.my_demux.c_el._y:=1]
 	    606729 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
 	    607086 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
 	    628359 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
@@ -241,46 +241,46 @@ Output neutral checked
 	    639106 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_f_buf_func[1].n1:=1]
 	    639116 my_demux.my_demux.c_buf_f.buf2._y : 0  [by my_demux.my_demux.c_buf_f.in:=1]
 	    639120 my_demux.my_demux.vc.OR2_tf[6]._y : 0  [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
-	    639190 my_demux.my_demux.vc.tmp[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
+	    639190 my_demux.my_demux.vc.ct.in[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
 	    639206 my_demux.my_demux.vc.OR2_tf[5]._y : 0  [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
 	    639330 my_demux.my_demux.vc.OR2_tf[2]._y : 0  [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
-	    639341 my_demux.my_demux.vc.tmp[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
-	    639949 my_demux.my_demux.vc.tmp[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
+	    639341 my_demux.my_demux.vc.ct.in[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
+	    639949 my_demux.my_demux.vc.ct.in[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
 	    640149 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.c_buf_f.in:=1]
 	    640152 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
 	    640306 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_f_buf_func[0].n1:=1]
-	    640360 my_demux.my_demux.vc.tmp[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
+	    640360 my_demux.my_demux.vc.ct.in[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
 	    640575 my_demux.my_demux._c_f_buf[0] : 1  [by my_demux.my_demux.c_buf_f.buf2._y:=0]
 	    640656 my_demux.my_demux.out2_t_buf_func[6]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    640667 my_demux.my_demux.out2_f_buf_func[3]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    641280 my_demux.my_demux.out2_f_buf_func[3].y : 1  [by my_demux.my_demux.out2_f_buf_func[3]._y:=0]
-	    641508 my_demux.my_demux.vc.C2Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[0]:=1]
+	    641508 my_demux.my_demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[0]:=1]
 	    641736 my_demux.my_demux.out2_t_buf_func[2]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    641781 my_demux.my_demux.out2_t_buf_func[2].y : 1  [by my_demux.my_demux.out2_t_buf_func[2]._y:=0]
 	    642400 my_demux.my_demux.out2_t_buf_func[6].y : 1  [by my_demux.my_demux.out2_t_buf_func[6]._y:=0]
 	    647557 my_demux.my_demux.vc.OR2_tf[3]._y : 0  [by my_demux.my_demux.out1_f_buf_func[3].n1:=1]
-	    648554 my_demux.my_demux.vc.tmp[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
+	    648554 my_demux.my_demux.vc.ct.in[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
 	    648886 my_demux.my_demux.out2_f_buf_func[4]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    649227 my_demux.my_demux.out2_t_buf_func[5]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    649411 my_demux.my_demux.out2_f_buf_func[4].y : 1  [by my_demux.my_demux.out2_f_buf_func[4]._y:=0]
 	    650127 my_demux.my_demux.out2_t_buf_func[5].y : 1  [by my_demux.my_demux.out2_t_buf_func[5]._y:=0]
-	    650203 my_demux.my_demux.vc.C2Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[3]:=1]
-	    650255 my_demux.my_demux.vc.tmp[8] : 1  [by my_demux.my_demux.vc.C2Els[1]._y:=0]
+	    650203 my_demux.my_demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.vc.ct.in[3]:=1]
+	    650255 my_demux.my_demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
 	    651652 my_demux.my_demux.out2_f_buf_func[0]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    651659 my_demux.my_demux.out2_f_buf_func[0].y : 1  [by my_demux.my_demux.out2_f_buf_func[0]._y:=0]
-	    655530 my_demux.my_demux.vc.tmp[7] : 1  [by my_demux.my_demux.vc.C2Els[0]._y:=0]
+	    655530 my_demux.my_demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
 	    658558 my_demux.my_demux.out2_f_buf_func[1]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
 	    670546 my_demux.my_demux.vc.OR2_tf[4]._y : 0  [by my_demux.my_demux.out1_f_buf_func[4].n1:=1]
 	    674170 my_demux.my_demux.out2_f_buf_func[1].y : 1  [by my_demux.my_demux.out2_f_buf_func[1]._y:=0]
-	    677013 my_demux.my_demux.vc.tmp[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
-	    689628 my_demux.my_demux.vc.tmp[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
-	    689630 my_demux.my_demux.vc.C3Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[5]:=1]
-	    689984 my_demux.my_demux.vc.tmp[9] : 1  [by my_demux.my_demux.vc.C3Els[0]._y:=0]
-	    690117 my_demux.my_demux.vc.C3Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[9]:=1]
-	    690118 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.C3Els[1]._y:=0]
+	    677013 my_demux.my_demux.vc.ct.in[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
+	    689628 my_demux.my_demux.vc.ct.in[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
+	    689630 my_demux.my_demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.vc.ct.in[5]:=1]
+	    689984 my_demux.my_demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
+	    690117 my_demux.my_demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.vc.ct.tmp[9]:=1]
+	    690118 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
 	    690122 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
 	    690664 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    690665 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
+	    690665 my_demux.cond.v : 1  [by my_demux.my_demux.c_el._y:=0]
 	    735685 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
 	    735685 my_demux.out2.v : 1
 	    748063 my_demux.my_demux.out_or._y : 0  [by my_demux.out2.v:=1]
@@ -305,26 +305,26 @@ Output neutral checked
 	    817979 my_demux.my_demux.out1_f_buf_func[3].n1 : 0
 	    817982 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_f_buf_func[3].n1:=0]
 	    817991 my_demux.my_demux.vc.OR2_tf[5]._y : 1  [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
-	    817992 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
-	    818020 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
+	    817992 my_demux.my_demux.vc.ct.in[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
+	    818020 my_demux.my_demux.vc.ct.in[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
 	    818022 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
 	    818106 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_f_buf_func[0].n1:=0]
 	    818148 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
-	    818198 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
+	    818198 my_demux.my_demux.vc.ct.in[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
 	    818212 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
-	    818214 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
+	    818214 my_demux.my_demux.vc.ct.in[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
 	    819258 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_f_buf_func[1].n1:=0]
-	    819259 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    820760 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[1]:=0]
-	    820762 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    820875 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    820893 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
-	    821012 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    830774 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
-	    836494 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[2]:=0]
-	    836502 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
-	    836556 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[8]:=0]
-	    887094 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
+	    819259 my_demux.my_demux.vc.ct.in[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
+	    820760 my_demux.my_demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[1]:=0]
+	    820762 my_demux.my_demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
+	    820875 my_demux.my_demux.vc.ct.in[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
+	    820893 my_demux.my_demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.vc.ct.in[6]:=0]
+	    821012 my_demux.my_demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
+	    830774 my_demux.my_demux.vc.ct.in[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
+	    836494 my_demux.my_demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.vc.ct.in[2]:=0]
+	    836502 my_demux.my_demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
+	    836556 my_demux.my_demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.vc.ct.tmp[8]:=0]
+	    887094 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
 	    887099 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
 	    888166 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
 Second Cond Checked

test/unit_tests/demux_7/run/test.prs

@@ -330,6 +330,7 @@
 = "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.vc.in.d[6].d[0]"
 = "my_demux.my_demux.in.d.d[6].d[1]" "my_demux.my_demux.vc.in.d[6].d[1]"
 = "my_demux.my_demux.in.a" "my_demux.my_demux.en_ctl.c1"
+= "my_demux.my_demux.in.a" "my_demux.my_demux.cond.a"
 = "my_demux.my_demux.in.a" "my_demux.my_demux.inack_ctl.y"
 = "my_demux.my_demux.in.v" "my_demux.my_demux.in_v_buf.y"
 = "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.out2_f_buf_func[6].n1"
@@ -426,8 +427,6 @@
 ~("my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b")->"my_demux.my_demux.out_or._y"+
 "my_demux.my_demux.out_or._y"->"my_demux.my_demux.out_or.y"-
 ~("my_demux.my_demux.out_or._y")->"my_demux.my_demux.out_or.y"+
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.c_el.y"
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.inack_ctl.c2"
 = "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_a_B_buf_f.out[0]"
 = "my_demux.my_demux._out1_a_BX_t[1]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
 = "my_demux.my_demux._out1_a_BX_t[2]" "my_demux.my_demux.out1_a_B_buf_f.out[2]"
@@ -854,12 +853,20 @@
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_f.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out2_en_buf_t.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_t.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_f.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_f.supply.vdd"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_t.supply.vss"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_t.supply.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[6].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_f_buf_func[6].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[5].vdd"
@@ -930,22 +937,59 @@
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.en_ctl.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.inack_ctl.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
-~"my_demux.my_demux.vc.C2Els[0].c1"&~"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"+
-"my_demux.my_demux.vc.C2Els[0].c1"&"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"-
-"my_demux.my_demux.vc.C2Els[0]._y"->"my_demux.my_demux.vc.C2Els[0].y"-
-~("my_demux.my_demux.vc.C2Els[0]._y")->"my_demux.my_demux.vc.C2Els[0].y"+
-~"my_demux.my_demux.vc.C2Els[1].c1"&~"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"+
-"my_demux.my_demux.vc.C2Els[1].c1"&"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"-
-"my_demux.my_demux.vc.C2Els[1]._y"->"my_demux.my_demux.vc.C2Els[1].y"-
-~("my_demux.my_demux.vc.C2Els[1]._y")->"my_demux.my_demux.vc.C2Els[1].y"+
-~"my_demux.my_demux.vc.C3Els[0].c1"&~"my_demux.my_demux.vc.C3Els[0].c2"&~"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"+
-"my_demux.my_demux.vc.C3Els[0].c1"&"my_demux.my_demux.vc.C3Els[0].c2"&"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"-
-"my_demux.my_demux.vc.C3Els[0]._y"->"my_demux.my_demux.vc.C3Els[0].y"-
-~("my_demux.my_demux.vc.C3Els[0]._y")->"my_demux.my_demux.vc.C3Els[0].y"+
-~"my_demux.my_demux.vc.C3Els[1].c1"&~"my_demux.my_demux.vc.C3Els[1].c2"&~"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"+
-"my_demux.my_demux.vc.C3Els[1].c1"&"my_demux.my_demux.vc.C3Els[1].c2"&"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"-
-"my_demux.my_demux.vc.C3Els[1]._y"->"my_demux.my_demux.vc.C3Els[1].y"-
-~("my_demux.my_demux.vc.C3Els[1]._y")->"my_demux.my_demux.vc.C3Els[1].y"+
+~"my_demux.my_demux.vc.ct.C2Els[0].c1"&~"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"+
+"my_demux.my_demux.vc.ct.C2Els[0].c1"&"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"-
+"my_demux.my_demux.vc.ct.C2Els[0]._y"->"my_demux.my_demux.vc.ct.C2Els[0].y"-
+~("my_demux.my_demux.vc.ct.C2Els[0]._y")->"my_demux.my_demux.vc.ct.C2Els[0].y"+
+~"my_demux.my_demux.vc.ct.C2Els[1].c1"&~"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"+
+"my_demux.my_demux.vc.ct.C2Els[1].c1"&"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"-
+"my_demux.my_demux.vc.ct.C2Els[1]._y"->"my_demux.my_demux.vc.ct.C2Els[1].y"-
+~("my_demux.my_demux.vc.ct.C2Els[1]._y")->"my_demux.my_demux.vc.ct.C2Els[1].y"+
+~"my_demux.my_demux.vc.ct.C3Els[0].c1"&~"my_demux.my_demux.vc.ct.C3Els[0].c2"&~"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"+
+"my_demux.my_demux.vc.ct.C3Els[0].c1"&"my_demux.my_demux.vc.ct.C3Els[0].c2"&"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"-
+"my_demux.my_demux.vc.ct.C3Els[0]._y"->"my_demux.my_demux.vc.ct.C3Els[0].y"-
+~("my_demux.my_demux.vc.ct.C3Els[0]._y")->"my_demux.my_demux.vc.ct.C3Els[0].y"+
+~"my_demux.my_demux.vc.ct.C3Els[1].c1"&~"my_demux.my_demux.vc.ct.C3Els[1].c2"&~"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"+
+"my_demux.my_demux.vc.ct.C3Els[1].c1"&"my_demux.my_demux.vc.ct.C3Els[1].c2"&"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"-
+"my_demux.my_demux.vc.ct.C3Els[1]._y"->"my_demux.my_demux.vc.ct.C3Els[1].y"-
+~("my_demux.my_demux.vc.ct.C3Els[1]._y")->"my_demux.my_demux.vc.ct.C3Els[1].y"+
+= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C3Els[1].c1"
+= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C2Els[0].y"
+= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C3Els[1].c2"
+= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C2Els[1].y"
+= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[1].c3"
+= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[0].y"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[1].vdd"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[0].vdd"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[1].vdd"
+= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[0].vdd"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[1].vss"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[0].vss"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[1].vss"
+= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[0].vss"
+= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.C2Els[0].c1"
+= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.tmp[0]"
+= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.C2Els[0].c2"
+= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.tmp[1]"
+= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.C2Els[1].c1"
+= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.tmp[2]"
+= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.C2Els[1].c2"
+= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.tmp[3]"
+= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.C3Els[0].c1"
+= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.tmp[4]"
+= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.C3Els[0].c2"
+= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.tmp[5]"
+= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.C3Els[0].c3"
+= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.tmp[6]"
+= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.C3Els[1].y"
+= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.tmp[10]"
+= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
+= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
+= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
+= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
+= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
+= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
+= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
 "my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
 ~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
 "my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
@@ -974,30 +1018,8 @@
 ~("my_demux.my_demux.vc.OR2_tf[6].a"|"my_demux.my_demux.vc.OR2_tf[6].b")->"my_demux.my_demux.vc.OR2_tf[6]._y"+
 "my_demux.my_demux.vc.OR2_tf[6]._y"->"my_demux.my_demux.vc.OR2_tf[6].y"-
 ~("my_demux.my_demux.vc.OR2_tf[6]._y")->"my_demux.my_demux.vc.OR2_tf[6].y"+
-= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.C2Els[0].c1"
-= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
-= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.C2Els[0].c2"
-= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
-= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.C2Els[1].c1"
-= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
-= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.C2Els[1].c2"
-= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
-= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.C3Els[0].c1"
-= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
-= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.C3Els[0].c2"
-= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
-= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.C3Els[0].c3"
-= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
-= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C3Els[1].c1"
-= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C2Els[0].y"
-= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C3Els[1].c2"
-= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C2Els[1].y"
-= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[1].c3"
-= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[0].y"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[1].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[0].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[1].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[0].vdd"
+= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.ct.supply.vss"
+= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.ct.supply.vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[6].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[5].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[4].vdd"
@@ -1005,10 +1027,6 @@
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[2].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
 = "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[1].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[0].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[1].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[0].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[6].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[5].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[4].vss"
@@ -1016,6 +1034,7 @@
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[2].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
 = "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
+= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.ct.out"
 = "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
 = "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
 = "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
@@ -1072,8 +1091,6 @@
 = "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
 = "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.OR2_tf[0].a"
 = "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.C3Els[1].y"
-= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.tmp[10]"
 "my_demux.my_demux.out2_a_B_buf_f.buf2.a"->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"-
 ~("my_demux.my_demux.out2_a_B_buf_f.buf2.a")->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"+
 "my_demux.my_demux.out2_a_B_buf_f.buf2._y"->"my_demux.my_demux.out2_a_B_buf_f.buf2.y"-
@@ -1110,6 +1127,9 @@
 = "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
 = "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
+= "my_demux.my_demux.cond.v" "my_demux.my_demux.c_el.y"
+= "my_demux.my_demux.cond.v" "my_demux.my_demux.inack_ctl.c2"
+= "my_demux.my_demux.cond.v" "my_demux.my_demux._in_c_v_"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_f_c_t_or.b"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_buf_f.in"
 = "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
@@ -1386,6 +1406,7 @@
 = "my_demux.in.d.d[6].t" "my_demux.my_demux.in.d.d[6].t"
 = "my_demux.in.d.d[6].d[0]" "my_demux.my_demux.in.d.d[6].d[0]"
 = "my_demux.in.d.d[6].d[1]" "my_demux.my_demux.in.d.d[6].d[1]"
+= "my_demux.in.a" "my_demux.cond.a"
 = "my_demux.in.d.d[6].d[0]" "my_demux.in.d.d[6].f"
 = "my_demux.in.d.d[6].d[1]" "my_demux.in.d.d[6].t"
 = "my_demux.in.d.d[5].d[0]" "my_demux.in.d.d[5].f"

test/unit_tests/demux_7/test.prsim

@@ -18,6 +18,7 @@ mode run
 assert-qdi-channel-neutral "my_demux.out1" 7
 assert-qdi-channel-neutral "my_demux.out2" 7
 assert-qdi-channel-neutral "my_demux.in" 7
+assert my_demux.cond.v 0
 cycle
 
 system "echo 'Output neutral checked'"
@@ -28,6 +29,7 @@ set-qdi-channel-valid "my_demux.in" 7 127
 cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
+assert my_demux.cond.v 1
 
 assert-qdi-channel-valid "my_demux.out1" 7 127
 set my_demux.out1.v 1
@@ -68,6 +70,7 @@ set-qdi-channel-valid "my_demux.in" 7 100
 cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
+assert my_demux.cond.v 1
 
 assert-qdi-channel-valid "my_demux.out2" 7 100
 set my_demux.out2.v 1

test/unit_tests/demux_bit_7/run/prsim.out

@@ -0,0 +1,336 @@
+my_demux.in.d.d[5].t my_demux.my_demux.demux._en2_X_t[0] my_demux.in.d.d[2].f my_demux.my_demux.demux._out1_a_BX_f[0] my_demux.my_demux.demux._out2_a_BX_t[0] my_demux.in.d.d[5].f my_demux.my_demux.demux._out1_a_B my_demux.my_demux.demux._en1_X_t[0] my_demux.my_demux.demux._out_v my_demux.in.d.d[1].f my_demux.my_demux.demux._out2_a_BX_f[0] my_demux.my_demux.demux._en1_X_f[0] my_demux.in.d.d[6].f my_demux.in.d.d[2].t my_demux.my_demux.demux.vc.OR2_tf[2]._y my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y my_demux.in.d.d[0].f my_demux.my_demux.demux._c_f_buf[0] my_demux.my_demux.demux.vc.ct.in[1] my_demux.my_demux.demux._out1_a_BX_t[0] my_demux.my_demux.demux._c_t_buf[0] my_demux.out1.a my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[8] my_demux.in.d.d[4].f my_demux.in.d.d[4].t my_demux.my_demux.demux._in_c_v_ my_demux.my_demux.demux.out_or._y my_demux.my_demux.demux._c_v my_demux.my_demux.demux._en2_X_f[0] my_demux.my_demux.demux.vc.ct.in[6] my_demux.in.d.d[6].t my_demux.in.d.d[1].t my_demux.in.d.d[0].t my_demux.my_demux.demux._out2_a_B my_demux.in.d.d[3].f my_demux.out2.a my_demux.in.v my_demux.my_demux.demux.vc.OR2_tf[1]._y my_demux.my_demux.demux.vc.ct.C3Els[0]._y my_demux.my_demux.demux.vc.ct.C2Els[1]._y my_demux.my_demux.demux._en my_demux.in.d.d[3].t my_demux.my_demux.demux.vc.ct.tmp[9] my_demux.my_demux.demux.vc.ct.in[5] my_demux.my_demux.demux.vc.ct.in[4] my_demux.my_demux.demux.vc.ct.in[2] my_demux.out2.v my_demux.my_demux.demux.vc.ct.C3Els[1]._y my_demux.my_demux.demux.vc.ct.C2Els[0]._y my_demux.my_demux.demux.vc.OR2_tf[0]._y my_demux.my_demux.demux.vc.ct.in[3] my_demux.my_demux.demux.c_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[7] my_demux.my_demux.demux.vc.OR2_tf[6]._y my_demux.my_demux.demux.vc.ct.in[0] my_demux.my_demux.demux._in_v my_demux.my_demux.demux.c_buf_t.buf2._y my_demux.out1.v my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.demux.vc.OR2_tf[5]._y my_demux.my_demux.demux.c_el._y my_demux.my_demux.demux.out2_en_buf_t.buf2._y my_demux.my_demux.demux.in_v_buf._y my_demux.my_demux.demux.vc.OR2_tf[4]._y my_demux.my_demux.demux.c_f_c_t_or._y my_demux.my_demux.demux.out1_en_buf_f.buf2._y my_demux.my_demux.demux.out2_en_buf_f.buf2._y my_demux.my_demux.demux.out1_en_buf_t.buf2._y my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.OR2_tf[3]._y 
+	    119199 my_demux.in.d.d[0].f : 0
+	    119199 my_demux.in.d.d[0].t : 0
+	    119199 my_demux.in.d.d[1].f : 0
+	    119199 my_demux.in.d.d[3].f : 0
+	    119199 my_demux.in.d.d[7].f : 0
+	    119199 my_demux.in.d.d[6].t : 0
+	    119199 my_demux.out2.v : 0
+	    119199 my_demux.out2.a : 0
+	    119199 my_demux.out1.v : 0
+	    119199 my_demux.in.d.d[2].t : 0
+	    119199 my_demux.in.d.d[6].f : 0
+	    119199 my_demux.out1.a : 0
+	    119199 my_demux.in.d.d[5].t : 0
+	    119199 my_demux.in.d.d[7].t : 0
+	    119199 my_demux.in.d.d[2].f : 0
+	    119199 my_demux.in.d.d[5].f : 0
+	    119199 my_demux.in.d.d[4].t : 0
+	    119199 my_demux.in.d.d[1].t : 0
+	    119199 my_demux.in.d.d[4].f : 0
+	    119199 my_demux.in.d.d[3].t : 0
+	    119200 my_demux.my_demux.demux.c_buf_f.buf2._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    119200 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1  [by my_demux.in.d.d[5].f:=0]
+	    119236 my_demux.my_demux.demux.c_buf_t.buf2._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    119239 my_demux.my_demux.demux.out_or._y : 1  [by my_demux.out1.v:=0]
+	    119286 my_demux.my_demux.demux._out1_a_B : 1  [by my_demux.out1.a:=0]
+	    119308 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    119311 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    119378 my_demux.my_demux.demux.vc.ct.in[5] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
+	    119403 my_demux.my_demux.demux._out_v : 0  [by my_demux.my_demux.demux.out_or._y:=1]
+	    119456 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1  [by my_demux.in.d.d[6].f:=0]
+	    119493 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1  [by my_demux.in.d.d[2].f:=0]
+	    119536 my_demux.my_demux.demux._en : 1  [by my_demux.my_demux.demux._out_v:=0]
+	    119543 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    119566 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    119757 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    119790 my_demux.my_demux.demux._c_f_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
+	    119848 my_demux.my_demux.demux._en1_X_t[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
+	    119852 my_demux.my_demux.demux.vc.ct.in[2] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
+	    119938 my_demux.my_demux.demux.c_f_c_t_or._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    120039 my_demux.my_demux.demux._c_t_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
+	    120155 my_demux.my_demux.demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
+	    120408 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1  [by my_demux.in.d.d[3].t:=0]
+	    120415 my_demux.my_demux.demux.vc.ct.in[3] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
+	    121005 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1  [by my_demux.in.d.d[1].t:=0]
+	    121111 my_demux.my_demux.demux.vc.ct.in[1] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
+	    121206 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1  [by my_demux.in.d.d[4].f:=0]
+	    121284 my_demux.my_demux.demux.vc.ct.in[4] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
+	    121481 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    121756 my_demux.my_demux.demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
+	    122127 my_demux.my_demux.demux._c_v : 0  [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
+	    123202 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
+	    126256 my_demux.my_demux.demux._en2_X_t[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
+	    133652 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    134107 my_demux.my_demux.demux._en2_X_f[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
+	    135118 my_demux.my_demux.demux.vc.ct.in[6] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
+	    135130 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
+	    135534 my_demux.my_demux.demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
+	    142198 my_demux.my_demux.demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
+	    149439 my_demux.my_demux.demux.vc.ct.in[0] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
+	    149451 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
+	    155367 my_demux.my_demux.demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
+	    159643 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.tmp[7]:=0]
+	    162542 my_demux.my_demux.demux._in_v : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
+	    162544 my_demux.my_demux.demux.c_el._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    166711 my_demux.my_demux.demux._out2_a_B : 1  [by my_demux.out2.a:=0]
+	    166837 my_demux.my_demux.demux.in_v_buf._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    167003 my_demux.in.v : 0  [by my_demux.my_demux.demux.in_v_buf._y:=1]
+	    167079 my_demux.my_demux.demux._in_c_v_ : 0  [by my_demux.my_demux.demux.c_el._y:=1]
+	    167960 my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._out2_a_B:=1]
+	    168035 my_demux.my_demux.demux._out2_a_BX_f[0] : 1  [by my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y:=0]
+	    170210 my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._out2_a_B:=1]
+	    170555 my_demux.my_demux.demux._out2_a_BX_t[0] : 1  [by my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y:=0]
+	    177027 my_demux.my_demux.demux._en1_X_f[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
+System initialized
+	    177027 Reset : 0
+	    177165 my_demux._reset_B : 1  [by Reset:=0]
+	    182428 my_demux.my_demux.demux.reset_buf._y : 0  [by my_demux._reset_B:=1]
+	    182430 my_demux.my_demux.demux._reset_BX : 1  [by my_demux.my_demux.demux.reset_buf._y:=0]
+	    226347 my_demux.my_demux.demux.reset_bufarray.buf4._y : 0  [by my_demux.my_demux.demux._reset_BX:=1]
+	    226348 my_demux.my_demux.demux._reset_BXX[0] : 1  [by my_demux.my_demux.demux.reset_bufarray.buf4._y:=0]
+System reset completed
+
+Output neutral checked
+	    226348 my_demux.in.d.d[0].t : 1
+	    226348 my_demux.in.d.d[7].t : 1
+	    226348 my_demux.in.d.d[2].t : 1
+	    226348 my_demux.in.d.d[6].t : 1
+	    226348 my_demux.in.d.d[5].t : 1
+	    226348 my_demux.in.d.d[1].t : 1
+	    226348 my_demux.in.d.d[4].t : 1
+	    226348 my_demux.in.d.d[3].t : 1
+	    226359 my_demux.my_demux.demux.c_f_c_t_or._y : 0  [by my_demux.in.d.d[0].t:=1]
+	    226364 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0  [by my_demux.in.d.d[5].t:=1]
+	    226415 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0  [by my_demux.in.d.d[2].t:=1]
+	    226718 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0  [by my_demux.in.d.d[0].t:=1]
+	    226720 my_demux.my_demux.demux.vc.ct.in[0] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
+	    226876 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0  [by my_demux.in.d.d[4].t:=1]
+	    226896 my_demux.my_demux.demux.c_buf_t.buf2._y : 0  [by my_demux.in.d.d[0].t:=1]
+	    226899 my_demux.my_demux.demux._c_t_buf[0] : 1  [by my_demux.my_demux.demux.c_buf_t.buf2._y:=0]
+	    226928 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    226929 my_demux.out1.d.d[0].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=0]
+	    226943 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    227052 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    227074 my_demux.out1.d.d[3].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=0]
+	    227160 my_demux.out1.d.d[4].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=0]
+	    227216 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    227217 my_demux.out1.d.d[1].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=0]
+	    228500 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    228783 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0  [by my_demux.in.d.d[3].t:=1]
+	    228989 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0  [by my_demux.in.d.d[6].t:=1]
+	    229148 my_demux.my_demux.demux.vc.ct.in[6] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
+	    229660 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    230081 my_demux.out1.d.d[2].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=0]
+	    230910 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0  [by my_demux.in.d.d[1].t:=1]
+	    232197 my_demux.my_demux.demux.vc.ct.in[1] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
+	    234429 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
+	    234574 my_demux.my_demux.demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
+	    238128 my_demux.my_demux.demux.vc.ct.in[3] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
+	    239456 my_demux.my_demux.demux.vc.ct.in[2] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
+	    240582 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 0  [by my_demux.my_demux.demux._c_t_buf[0]:=1]
+	    242288 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
+	    242289 my_demux.my_demux.demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
+	    246936 my_demux.out1.d.d[6].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=0]
+	    249336 my_demux.out1.d.d[5].t : 1  [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=0]
+	    250289 my_demux.my_demux.demux.vc.ct.in[5] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
+	    253239 my_demux.my_demux.demux._c_v : 1  [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
+	    287834 my_demux.my_demux.demux.vc.ct.in[4] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
+	    327118 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[4]:=1]
+	    327280 my_demux.my_demux.demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
+	    334649 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
+	    334663 my_demux.my_demux.demux._in_v : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
+	    334670 my_demux.my_demux.demux.in_v_buf._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    334823 my_demux.my_demux.demux.c_el._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    334824 my_demux.my_demux.demux._in_c_v_ : 1  [by my_demux.my_demux.demux.c_el._y:=0]
+	    356227 my_demux.in.v : 1  [by my_demux.my_demux.demux.in_v_buf._y:=0]
+	    356227 my_demux.out1.v : 1
+	    356228 my_demux.my_demux.demux.out_or._y : 0  [by my_demux.out1.v:=1]
+	    356229 my_demux.my_demux.demux._out_v : 1  [by my_demux.my_demux.demux.out_or._y:=0]
+	    358472 my_demux.my_demux.demux.inack_ctl._y : 0  [by my_demux.my_demux.demux._out_v:=1]
+	    358659 my_demux.in.a : 1  [by my_demux.my_demux.demux.inack_ctl._y:=0]
+	    358660 my_demux.my_demux.demux._en : 0  [by my_demux.in.a:=1]
+	    358661 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    358666 my_demux.my_demux.demux._en2_X_t[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
+	    359513 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    360404 my_demux.my_demux.demux._en1_X_f[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
+	    362842 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    362843 my_demux.my_demux.demux._en2_X_f[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
+	    393442 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    393459 my_demux.my_demux.demux._en1_X_t[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
+	    393459 my_demux.in.d.d[0].t : 0
+	    393459 my_demux.in.d.d[7].t : 0
+	    393459 my_demux.in.d.d[2].t : 0
+	    393459 my_demux.in.d.d[6].t : 0
+	    393459 my_demux.in.d.d[5].t : 0
+	    393459 my_demux.in.d.d[1].t : 0
+	    393459 my_demux.in.d.d[4].t : 0
+	    393459 my_demux.in.d.d[3].t : 0
+	    393460 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1  [by my_demux.in.d.d[5].t:=0]
+	    393462 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    393501 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1  [by my_demux.in.d.d[1].t:=0]
+	    393509 my_demux.my_demux.demux.vc.ct.in[1] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
+	    393555 my_demux.my_demux.demux.vc.ct.in[5] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
+	    393797 my_demux.my_demux.demux.vc.ct.in[0] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
+	    393831 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
+	    394400 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1  [by my_demux.in.d.d[2].t:=0]
+	    395318 my_demux.my_demux.demux.vc.ct.in[2] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
+	    396032 my_demux.my_demux.demux.c_buf_t.buf2._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    396036 my_demux.my_demux.demux._c_t_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
+	    396276 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1  [by my_demux.in.d.d[4].t:=0]
+	    401820 my_demux.my_demux.demux.c_f_c_t_or._y : 1  [by my_demux.in.d.d[0].t:=0]
+	    404218 my_demux.my_demux.demux._c_v : 0  [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
+	    407192 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1  [by my_demux.in.d.d[3].t:=0]
+	    407718 my_demux.my_demux.demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
+	    410407 my_demux.my_demux.demux.vc.ct.in[3] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
+	    442654 my_demux.my_demux.demux.vc.ct.in[4] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
+	    452421 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1  [by my_demux.in.d.d[6].t:=0]
+	    452469 my_demux.my_demux.demux.vc.ct.in[6] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
+	    452472 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
+	    452650 my_demux.my_demux.demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
+	    457526 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
+	    478503 my_demux.my_demux.demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
+	    490402 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.tmp[8]:=0]
+	    496353 my_demux.my_demux.demux._in_v : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
+	    497180 my_demux.my_demux.demux.c_el._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    497353 my_demux.my_demux.demux._in_c_v_ : 0  [by my_demux.my_demux.demux.c_el._y:=1]
+	    535838 my_demux.my_demux.demux.in_v_buf._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    536022 my_demux.in.v : 0  [by my_demux.my_demux.demux.in_v_buf._y:=1]
+First Cond Checked
+	    536022 my_demux.out1.a : 1
+	    536023 my_demux.my_demux.demux._out1_a_B : 0  [by my_demux.out1.a:=1]
+	    536027 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._out1_a_B:=0]
+	    536096 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._out1_a_B:=0]
+	    536192 my_demux.my_demux.demux._out1_a_BX_t[0] : 0  [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=1]
+	    536193 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    536204 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    536205 my_demux.out1.d.d[5].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=1]
+	    536328 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    536384 my_demux.out1.d.d[0].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=1]
+	    536433 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    537222 my_demux.out1.d.d[1].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=1]
+	    540092 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    540093 my_demux.out1.d.d[6].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=1]
+	    540151 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    540188 my_demux.out1.d.d[4].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=1]
+	    555238 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 1  [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
+	    573315 my_demux.my_demux.demux._out1_a_BX_f[0] : 0  [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=1]
+	    578613 my_demux.out1.d.d[2].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=1]
+	    581439 my_demux.out1.d.d[3].t : 0  [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=1]
+System reset completed
+
+Output neutral checked
+	    581439 my_demux.out1.a : 0
+	    581439 my_demux.out1.v : 0
+	    581440 my_demux.my_demux.demux._out1_a_B : 1  [by my_demux.out1.a:=0]
+	    581453 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    583132 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._out1_a_B:=1]
+	    583489 my_demux.my_demux.demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
+	    585003 my_demux.my_demux.demux.out_or._y : 1  [by my_demux.out1.v:=0]
+	    585028 my_demux.my_demux.demux._out_v : 0  [by my_demux.my_demux.demux.out_or._y:=1]
+	    585049 my_demux.my_demux.demux.inack_ctl._y : 1  [by my_demux.my_demux.demux._out_v:=0]
+	    585050 my_demux.in.a : 0  [by my_demux.my_demux.demux.inack_ctl._y:=1]
+	    594698 my_demux.my_demux.demux._en : 1  [by my_demux.in.a:=0]
+	    594699 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    594699 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    594704 my_demux.my_demux.demux._en2_X_f[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
+	    594859 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    595267 my_demux.my_demux.demux._en2_X_t[0] : 1  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
+	    595280 my_demux.my_demux.demux._en1_X_t[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
+	    595735 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0  [by my_demux.my_demux.demux._en:=1]
+	    595746 my_demux.my_demux.demux._en1_X_f[0] : 1  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
+	    598437 my_demux.my_demux.demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
+	    598437 my_demux.in.d.d[0].f : 1
+	    598437 my_demux.in.d.d[7].f : 1
+	    598437 my_demux.in.d.d[2].t : 1
+	    598437 my_demux.in.d.d[6].t : 1
+	    598437 my_demux.in.d.d[5].t : 1
+	    598437 my_demux.in.d.d[1].f : 1
+	    598437 my_demux.in.d.d[4].f : 1
+	    598437 my_demux.in.d.d[3].f : 1
+	    598441 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0  [by my_demux.in.d.d[2].t:=1]
+	    598451 my_demux.my_demux.demux.c_buf_f.buf2._y : 0  [by my_demux.in.d.d[0].f:=1]
+	    598455 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0  [by my_demux.in.d.d[0].f:=1]
+	    598525 my_demux.my_demux.demux.vc.ct.in[0] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
+	    598541 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0  [by my_demux.in.d.d[6].t:=1]
+	    598665 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0  [by my_demux.in.d.d[3].f:=1]
+	    598676 my_demux.my_demux.demux.vc.ct.in[3] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
+	    599284 my_demux.my_demux.demux.vc.ct.in[2] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
+	    599287 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
+	    599341 my_demux.my_demux.demux.vc.ct.tmp[8] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
+	    599484 my_demux.my_demux.demux.c_f_c_t_or._y : 0  [by my_demux.in.d.d[0].f:=1]
+	    599641 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0  [by my_demux.in.d.d[1].f:=1]
+	    599910 my_demux.my_demux.demux._c_f_buf[0] : 1  [by my_demux.my_demux.demux.c_buf_f.buf2._y:=0]
+	    599991 my_demux.my_demux.demux.out2_t_buf_func[5]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    600002 my_demux.my_demux.demux.out2_f_buf_func[1]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    600604 my_demux.out2.d.d[5].t : 1  [by my_demux.my_demux.demux.out2_t_buf_func[5]._y:=0]
+	    600632 my_demux.my_demux.demux._c_v : 1  [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
+	    600802 my_demux.my_demux.demux.vc.ct.in[1] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
+	    600847 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
+	    601654 my_demux.my_demux.demux.out2_f_buf_func[4]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    601844 my_demux.my_demux.demux.vc.ct.tmp[7] : 1  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
+	    603303 my_demux.out2.d.d[4].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[4]._y:=0]
+	    606892 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0  [by my_demux.in.d.d[4].f:=1]
+	    607417 my_demux.my_demux.demux.vc.ct.in[4] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
+	    608221 my_demux.my_demux.demux.out2_f_buf_func[3]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    608562 my_demux.my_demux.demux.out2_t_buf_func[2]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    608614 my_demux.out2.d.d[2].t : 1  [by my_demux.my_demux.demux.out2_t_buf_func[2]._y:=0]
+	    609121 my_demux.out2.d.d[3].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[3]._y:=0]
+	    610987 my_demux.my_demux.demux.out2_t_buf_func[6]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    610994 my_demux.out2.d.d[6].t : 1  [by my_demux.my_demux.demux.out2_t_buf_func[6]._y:=0]
+	    614024 my_demux.out2.d.d[1].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[1]._y:=0]
+	    617893 my_demux.my_demux.demux.out2_f_buf_func[0]._y : 0  [by my_demux.my_demux.demux._c_f_buf[0]:=1]
+	    629881 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0  [by my_demux.in.d.d[5].t:=1]
+	    633505 my_demux.out2.d.d[0].f : 1  [by my_demux.my_demux.demux.out2_f_buf_func[0]._y:=0]
+	    636348 my_demux.my_demux.demux.vc.ct.in[5] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
+	    648963 my_demux.my_demux.demux.vc.ct.in[6] : 1  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
+	    648965 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0  [by my_demux.my_demux.demux.vc.ct.in[6]:=1]
+	    649319 my_demux.my_demux.demux.vc.ct.tmp[9] : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
+	    649452 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0  [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
+	    649453 my_demux.my_demux.demux._in_v : 1  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
+	    649457 my_demux.my_demux.demux.in_v_buf._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    649999 my_demux.my_demux.demux.c_el._y : 0  [by my_demux.my_demux.demux._in_v:=1]
+	    650000 my_demux.my_demux.demux._in_c_v_ : 1  [by my_demux.my_demux.demux.c_el._y:=0]
+	    695020 my_demux.in.v : 1  [by my_demux.my_demux.demux.in_v_buf._y:=0]
+	    695020 my_demux.out2.v : 1
+	    707398 my_demux.my_demux.demux.out_or._y : 0  [by my_demux.out2.v:=1]
+	    707477 my_demux.my_demux.demux._out_v : 1  [by my_demux.my_demux.demux.out_or._y:=0]
+	    709910 my_demux.my_demux.demux.inack_ctl._y : 0  [by my_demux.my_demux.demux._out_v:=1]
+	    709998 my_demux.in.a : 1  [by my_demux.my_demux.demux.inack_ctl._y:=0]
+	    717780 my_demux.my_demux.demux._en : 0  [by my_demux.in.a:=1]
+	    717810 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    717839 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    719247 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    719932 my_demux.my_demux.demux._en1_X_f[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
+	    737223 my_demux.my_demux.demux._en1_X_t[0] : 0  [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
+	    746107 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1  [by my_demux.my_demux.demux._en:=0]
+	    762822 my_demux.my_demux.demux._en2_X_f[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
+	    777314 my_demux.my_demux.demux._en2_X_t[0] : 0  [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
+	    777314 my_demux.in.d.d[0].f : 0
+	    777314 my_demux.in.d.d[6].t : 0
+	    777314 my_demux.in.d.d[2].t : 0
+	    777314 my_demux.in.d.d[5].t : 0
+	    777314 my_demux.in.d.d[1].f : 0
+	    777314 my_demux.in.d.d[4].f : 0
+	    777314 my_demux.in.d.d[3].f : 0
+	    777315 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1  [by my_demux.in.d.d[3].f:=0]
+	    777317 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1  [by my_demux.in.d.d[1].f:=0]
+	    777326 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1  [by my_demux.in.d.d[6].t:=0]
+	    777352 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1  [by my_demux.in.d.d[4].f:=0]
+	    777354 my_demux.my_demux.demux.vc.ct.in[4] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
+	    777357 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    777358 my_demux.my_demux.demux.vc.ct.in[0] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
+	    777409 my_demux.my_demux.demux.vc.ct.in[1] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
+	    777441 my_demux.my_demux.demux.c_f_c_t_or._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    777443 my_demux.my_demux.demux._c_v : 0  [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
+	    777483 my_demux.my_demux.demux.c_buf_f.buf2._y : 1  [by my_demux.in.d.d[0].f:=0]
+	    777501 my_demux.my_demux.demux._c_f_buf[0] : 0  [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
+	    777547 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1  [by my_demux.in.d.d[5].t:=0]
+	    777666 my_demux.my_demux.demux.vc.ct.in[5] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
+	    778593 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1  [by my_demux.in.d.d[2].t:=0]
+	    778910 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[1]:=0]
+	    778918 my_demux.my_demux.demux.vc.ct.tmp[7] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
+	    780053 my_demux.my_demux.demux.vc.ct.in[6] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
+	    780107 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
+	    784313 my_demux.my_demux.demux.vc.ct.in[2] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
+	    790067 my_demux.my_demux.demux.vc.ct.in[3] : 0  [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
+	    790072 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
+	    791139 my_demux.my_demux.demux.vc.ct.tmp[8] : 0  [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
+	    830645 my_demux.my_demux.demux.vc.ct.tmp[9] : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
+	    830646 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1  [by my_demux.my_demux.demux.vc.ct.tmp[9]:=0]
+	    830784 my_demux.my_demux.demux._in_v : 0  [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
+	    830785 my_demux.my_demux.demux.in_v_buf._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    830848 my_demux.my_demux.demux.c_el._y : 1  [by my_demux.my_demux.demux._in_v:=0]
+	    830850 my_demux.my_demux.demux._in_c_v_ : 0  [by my_demux.my_demux.demux.c_el._y:=1]
+	    830908 my_demux.in.v : 0  [by my_demux.my_demux.demux.in_v_buf._y:=1]
+Second Cond Checked

test/unit_tests/demux_bit_7/test.act

@@ -0,0 +1,49 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+
+defproc demux_bit_7 (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
+
+    demux_bit<7,0> my_demux(.in=in, .out1=out1,.out2 = out2);
+    //Low active Reset 
+    bool _reset_B; 
+    prs {
+    	Reset => _reset_B-
+    }
+    my_demux.supply.vss = GND;
+    my_demux.supply.vdd = Vdd;
+    my_demux.reset_B = _reset_B;
+    
+}
+
+demux_bit_7 my_demux;

test/unit_tests/demux_bit_7/test.prsim

@@ -0,0 +1,77 @@
+watchall
+set-qdi-channel-neutral "my_demux.in" 8
+set my_demux.out1.a 0
+set my_demux.out1.v 0
+set my_demux.out2.a 0
+set my_demux.out2.v 0
+set my_demux.in.d.d[0].t 0
+set my_demux.in.d.d[0].f 0
+cycle
+system "echo 'System initialized'"
+
+set Reset 0
+cycle
+system "echo 'System reset completed'"
+status X
+mode run
+
+assert-qdi-channel-neutral "my_demux.out1" 7
+assert-qdi-channel-neutral "my_demux.out2" 7
+assert-qdi-channel-neutral "my_demux.in" 8
+cycle
+
+system "echo 'Output neutral checked'"
+
+set-qdi-channel-valid "my_demux.in" 8 255
+cycle
+assert my_demux.in.v 1
+assert my_demux.in.a 0
+
+assert-qdi-channel-valid "my_demux.out1" 7 127
+assert-qdi-channel-neutral "my_demux.out2" 7
+set my_demux.out1.v 1
+cycle
+assert my_demux.in.a 1
+set-qdi-channel-neutral "my_demux.in" 8
+cycle
+set my_demux.out1.a 1
+
+
+system "echo 'First Cond Checked'"
+
+
+set Reset 0
+cycle
+system "echo 'System reset completed'"
+status X
+mode run
+
+assert-qdi-channel-neutral "my_demux.out1" 7
+assert-qdi-channel-neutral "my_demux.out2" 7
+assert-qdi-channel-neutral "my_demux.in" 8
+cycle
+
+system "echo 'Output neutral checked'"
+
+set my_demux.out1.a 0
+set my_demux.out1.v 0
+set my_demux.out2.a 0
+set my_demux.out2.v 0
+cycle
+
+set-qdi-channel-valid "my_demux.in" 8 100
+cycle
+assert my_demux.in.v 1
+assert my_demux.in.a 0
+
+assert-qdi-channel-valid "my_demux.out2" 7 100
+set my_demux.out2.v 1
+cycle
+assert my_demux.in.a 1
+set-qdi-channel-neutral "my_demux.in" 7
+cycle
+
+
+system "echo 'Second Cond Checked'"
+
+

test/unit_tests/demux_td_2/run/test.prs

@@ -254,12 +254,15 @@
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_bufarray.supply.vss"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_bufarray.supply.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.token_buf.vdd"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.outt_a_inv.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[1].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[1].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[0].vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[0].vdd"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_inv.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.in_v_buf.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_el.vdd"
+= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_tk_inv.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_f.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_t.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_f_c_t_or.vdd"
@@ -269,12 +272,15 @@
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.inack_ctl.vdd"
 = "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out_or.vdd"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.token_buf.vss"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.outt_a_inv.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[1].vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[1].vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[0].vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[0].vss"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_inv.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.in_v_buf.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_el.vss"
+= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_tk_inv.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_f.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_t.vss"
 = "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_f_c_t_or.vss"

test/unit_tests/dropper_static/run/prsim.out

@@ -0,0 +1,383 @@
+b.b.and_f[0].b b.b.vt.ct.C2Els[0]._y b.b.and_f[3].a b.b.and_f[5].y b.b.and_t[1].a b.b.vt.OR2_tf[6]._y b.b.and_t[6].a b.b.and_f[2].y b.b.and_t[0].y b.b.vt.OR2_tf[4]._y b.b.and_f[2].a b.b.and_t[5].a b.b.and_f[5].a b.b.and_t[1].y b.drop b.b.and_t[4].y b.b.vt.ct.tmp[9] b.b.and_t[4].a b.b.and_f[6].a b.b.and_f[4].y b.b.vt.ct.tmp[7] b.b.vt.ct.in[2] b.b.and_t[0]._y b.b.vt.ct.in[5] b.b.vt.ct.C2Els[1]._y b.out.a b.b.and_t[3].a b.b.and_f[6].y b.in.v b.b.and_f[1].a b.b.and_f[0].c b.b.and_t[2].a b.b.and_t[6].y b.b.and_t[0].a b.b.and_f[1]._y b.b.sb_dropB.buf4._y b.b.and_t[3]._y b.b.or2.b b.b.vt.out b.b.and_f[4].a b.b.vt.OR2_tf[2]._y b.b.and_t[3].y b.b.and_f[1].y b.b._dropB b.b.vt.ct.in[0] b.b.and_t[6]._y b.b.vt.ct.tmp[8] b.b.and_t[2].y b.in.a b.b.and_f[0].a b.b.and_f[3].y b.b.or2.y b.b.vt.ct.in[1] b.b.and_t[5]._y b.b.and_f[0].y b.b.vt.ct.in[6] b.b.and_f[5]._y b.b.and_f[4]._y b.b.and2._y b.b.vt.ct.in[4] b.b.and_f[3]._y b.b.and_t[5].y b.b.vt.ct.in[3] b.b.ack_Cel._y b.b.vt.OR2_tf[3]._y b.b.vt.OR2_tf[5]._y b.b.and_t[4]._y b.b.and_t[2]._y b.b.vt.OR2_tf[1]._y b.b.and_f[0]._y b.b.and_t[1]._y b.b.and_f[2]._y b.b.vt.ct.C3Els[0]._y b.b.vt.ct.C3Els[1]._y b.b.in_v_buf._y b.b.or2._y b.b.vt.OR2_tf[0]._y b.b.and_f[6]._y b.b.sb_in_v.buf4._y 
+	         1 b.b.and_f[0].a : 0
+	         1 b.drop : 0
+	         1 b.b.and_f[1].a : 0
+	         1 b.b.and_f[3].a : 0
+	         1 b.out.a : 0
+	         1 b.b.and_t[6].a : 0
+	         1 b.b.and_t[2].a : 0
+	         1 b.b.and_f[6].a : 0
+	         1 b.b.and_t[5].a : 0
+	         1 b.b.and_t[0].a : 0
+	         1 b.b.and_f[2].a : 0
+	         1 b.b.and_f[5].a : 0
+	         1 b.b.and_t[4].a : 0
+	         1 b.b.and_t[1].a : 0
+	         1 b.b.and_f[4].a : 0
+	         1 b.b.and_t[3].a : 0
+	         1 b.out.v : 0
+	         3 b.b._dropB : 1  [by b.drop:=0]
+	         5 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	        14 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	        16 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_t[3].a:=0]
+	        16 b.b.and_t[5]._y : 1  [by b.b.and_t[5].a:=0]
+	        17 b.b.and_t[1]._y : 1  [by b.b.and_t[1].a:=0]
+	        21 b.b.and_f[5]._y : 1  [by b.b.and_f[5].a:=0]
+	        40 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	        41 b.b.and_f[2]._y : 1  [by b.b.and_f[2].a:=0]
+	        48 b.b.and_t[4]._y : 1  [by b.b.and_t[4].a:=0]
+	        69 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	       115 b.b.and_t[6]._y : 1  [by b.b.and_t[6].a:=0]
+	       116 b.b.and_t[6].y : 0  [by b.b.and_t[6]._y:=1]
+	       416 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_f[2].a:=0]
+	       417 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	       463 b.b.and_f[2].y : 0  [by b.b.and_f[2]._y:=1]
+	       492 b.b.and_t[0]._y : 1  [by b.b.and_t[0].a:=0]
+	      1138 b.b.and_f[3]._y : 1  [by b.b.and_f[3].a:=0]
+	      1420 b.b.and_f[3].y : 0  [by b.b.and_f[3]._y:=1]
+	      1727 b.b.and_f[6]._y : 1  [by b.b.and_f[6].a:=0]
+	      2495 b.b.and_f[6].y : 0  [by b.b.and_f[6]._y:=1]
+	      4754 b.b.and_f[1]._y : 1  [by b.b.and_f[1].a:=0]
+	      4757 b.b.and_f[1].y : 0  [by b.b.and_f[1]._y:=1]
+	      6062 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_f[5].a:=0]
+	      7093 b.b.and_f[0]._y : 1  [by b.b.and_f[0].a:=0]
+	      7644 b.b.and_f[0].y : 0  [by b.b.and_f[0]._y:=1]
+	      9130 b.b.and_t[3]._y : 1  [by b.b.and_t[3].a:=0]
+	     10201 b.b.and_t[3].y : 0  [by b.b.and_t[3]._y:=1]
+	     10468 b.b.and2._y : 1  [by b.drop:=0]
+	     11422 b.b.or2.b : 0  [by b.b.and2._y:=1]
+	     12503 b.b.or2._y : 1  [by b.b.or2.b:=0]
+	     13725 b.b.and_f[4]._y : 1  [by b.b.and_f[4].a:=0]
+	     13866 b.b.and_t[1].y : 0  [by b.b.and_t[1]._y:=1]
+	     14383 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	     14707 b.b.and_f[4].y : 0  [by b.b.and_f[4]._y:=1]
+	     20697 b.b.and_t[0].y : 0  [by b.b.and_t[0]._y:=1]
+	     24833 b.b.and_f[5].y : 0  [by b.b.and_f[5]._y:=1]
+	     28503 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	     29796 b.b.and_t[5].y : 0  [by b.b.and_t[5]._y:=1]
+	     36936 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	     36954 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[4]:=0]
+	     40967 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	     43251 b.b.sb_dropB.buf4._y : 0  [by b.b._dropB:=1]
+	     44099 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_t[1].a:=0]
+	     47254 b.b.and_f[0].b : 1  [by b.b.sb_dropB.buf4._y:=0]
+	     48762 b.b.and_t[4].y : 0  [by b.b.and_t[4]._y:=1]
+	     51669 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	     65367 b.b.and_t[2]._y : 1  [by b.b.and_t[2].a:=0]
+	     66973 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	     70127 b.b.and_t[2].y : 0  [by b.b.and_t[2]._y:=1]
+	     73253 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[3]:=0]
+	     73755 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	     89000 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	     89203 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[1]:=0]
+	     91057 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	     91196 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[7]:=0]
+	    127542 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	    127611 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	    127622 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    127826 b.b.ack_Cel._y : 1  [by b.in.v:=0]
+	    127841 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+	    179408 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	    179409 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]
+[] Set reset 0
+
+	    179409 Reset : 0
+	    179446 b._reset_B : 1  [by Reset:=0]
+
+[] Sending in valid data
+	    179446 b.b.and_t[0].a : 1
+	    179446 b.b.and_f[6].a : 1
+	    179446 b.b.and_t[2].a : 1
+	    179446 b.b.and_t[5].a : 1
+	    179446 b.b.and_f[1].a : 1
+	    179446 b.b.and_f[4].a : 1
+	    179446 b.b.and_t[3].a : 1
+	    179486 b.b.vt.OR2_tf[5]._y : 0  [by b.b.and_t[5].a:=1]
+	    179487 b.b.vt.ct.in[5] : 1  [by b.b.vt.OR2_tf[5]._y:=0]
+	    179533 b.b.vt.OR2_tf[4]._y : 0  [by b.b.and_f[4].a:=1]
+	    179558 b.b.vt.OR2_tf[6]._y : 0  [by b.b.and_f[6].a:=1]
+	    179703 b.b.vt.OR2_tf[1]._y : 0  [by b.b.and_f[1].a:=1]
+	    179740 b.b.vt.OR2_tf[3]._y : 0  [by b.b.and_t[3].a:=1]
+	    180185 b.b.vt.OR2_tf[0]._y : 0  [by b.b.and_t[0].a:=1]
+	    180330 b.b.vt.ct.in[3] : 1  [by b.b.vt.OR2_tf[3]._y:=0]
+	    180363 b.b.vt.ct.in[0] : 1  [by b.b.vt.OR2_tf[0]._y:=0]
+	    180912 b.b.vt.ct.in[1] : 1  [by b.b.vt.OR2_tf[1]._y:=0]
+	    181339 b.b.vt.ct.in[4] : 1  [by b.b.vt.OR2_tf[4]._y:=0]
+	    181565 b.b.vt.ct.in[6] : 1  [by b.b.vt.OR2_tf[6]._y:=0]
+	    181715 b.b.vt.ct.C2Els[0]._y : 0  [by b.b.vt.ct.in[1]:=1]
+	    181729 b.b.vt.ct.C3Els[0]._y : 0  [by b.b.vt.ct.in[6]:=1]
+	    181751 b.b.vt.ct.tmp[9] : 1  [by b.b.vt.ct.C3Els[0]._y:=0]
+	    183910 b.b.vt.ct.tmp[7] : 1  [by b.b.vt.ct.C2Els[0]._y:=0]
+	    226958 b.b.vt.OR2_tf[2]._y : 0  [by b.b.and_t[2].a:=1]
+	    227805 b.b.vt.ct.in[2] : 1  [by b.b.vt.OR2_tf[2]._y:=0]
+	    257933 b.b.vt.ct.C2Els[1]._y : 0  [by b.b.vt.ct.in[2]:=1]
+	    258066 b.b.vt.ct.tmp[8] : 1  [by b.b.vt.ct.C2Els[1]._y:=0]
+	    273728 b.b.vt.ct.C3Els[1]._y : 0  [by b.b.vt.ct.tmp[8]:=1]
+	    274087 b.b.vt.out : 1  [by b.b.vt.ct.C3Els[1]._y:=0]
+	    288203 b.b.in_v_buf._y : 0  [by b.b.vt.out:=1]
+	    288424 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+	    288431 b.b.sb_in_v.buf4._y : 0  [by b.in.v:=1]
+	    288461 b.b.and_f[0].c : 1  [by b.b.sb_in_v.buf4._y:=0]
+	    288468 b.b.and_t[2]._y : 0  [by b.b.and_f[0].c:=1]
+	    288546 b.b.and_t[2].y : 1  [by b.b.and_t[2]._y:=0]
+	    288552 b.b.and_f[4]._y : 0  [by b.b.and_f[0].c:=1]
+	    288567 b.b.and_t[5]._y : 0  [by b.b.and_f[0].c:=1]
+	    288827 b.b.and_f[4].y : 1  [by b.b.and_f[4]._y:=0]
+	    290650 b.b.and_t[0]._y : 0  [by b.b.and_f[0].c:=1]
+	    291105 b.b.and_t[0].y : 1  [by b.b.and_t[0]._y:=0]
+	    291248 b.b.and_t[3]._y : 0  [by b.b.and_f[0].c:=1]
+	    291260 b.b.and_t[3].y : 1  [by b.b.and_t[3]._y:=0]
+	    295174 b.b.and_f[6]._y : 0  [by b.b.and_f[0].c:=1]
+	    295578 b.b.and_f[6].y : 1  [by b.b.and_f[6]._y:=0]
+	    307563 b.b.and_t[5].y : 1  [by b.b.and_t[5]._y:=0]
+	    345922 b.b.and_f[1]._y : 0  [by b.b.and_f[0].c:=1]
+	    345934 b.b.and_f[1].y : 1  [by b.b.and_f[1]._y:=0]
+	    345934 b.out.a : 1
+	    351850 b.b.or2._y : 0  [by b.out.a:=1]
+	    356126 b.b.or2.y : 1  [by b.b.or2._y:=0]
+	    359025 b.b.ack_Cel._y : 0  [by b.b.or2.y:=1]
+	    363320 b.in.a : 1  [by b.b.ack_Cel._y:=0]
+[] Removing data
+	    363320 b.b.and_t[0].a : 0
+	    363320 b.b.and_f[6].a : 0
+	    363320 b.b.and_t[2].a : 0
+	    363320 b.b.and_t[5].a : 0
+	    363320 b.b.and_f[1].a : 0
+	    363320 b.b.and_f[4].a : 0
+	    363320 b.b.and_t[3].a : 0
+	    363321 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    363322 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    363322 b.b.and_t[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    363331 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_t[3].a:=0]
+	    363347 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	    363389 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	    363395 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    363458 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    363486 b.b.and_t[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    363665 b.b.and_t[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    363691 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	    363868 b.b.and_t[3]._y : 1  [by b.b.and_t[3].a:=0]
+	    363986 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	    364569 b.b.and_f[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    365921 b.b.and_t[2].y : 0  [by b.b.and_t[2]._y:=1]
+	    365963 b.b.and_t[0].y : 0  [by b.b.and_t[0]._y:=1]
+	    366819 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    366821 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	    367855 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    367858 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	    367887 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[0]:=0]
+	    367957 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	    368204 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	    368583 b.b.and_f[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    368736 b.b.and_f[1].y : 0  [by b.b.and_f[1]._y:=1]
+	    369558 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[2]:=0]
+	    369602 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	    377610 b.b.and_f[6].y : 0  [by b.b.and_f[6]._y:=1]
+	    387793 b.b.and_t[3].y : 0  [by b.b.and_t[3]._y:=1]
+	    390545 b.b.and_t[5].y : 0  [by b.b.and_t[5]._y:=1]
+	    407237 b.b.and_f[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    409998 b.b.and_f[4].y : 0  [by b.b.and_f[4]._y:=1]
+	    427779 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[6]:=0]
+	    441462 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	    441463 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[9]:=0]
+	    441680 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	    441702 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	    441703 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    443284 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	    452629 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]
+	    452629 b.out.a : 0
+	    452788 b.b.or2._y : 1  [by b.out.a:=0]
+	    472464 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	    473751 b.b.ack_Cel._y : 1  [by b.b.or2.y:=0]
+	    475983 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+[] Sending in valid data
+	    475983 b.b.and_t[0].a : 1
+	    475983 b.b.and_f[6].a : 1
+	    475983 b.b.and_t[2].a : 1
+	    475983 b.b.and_t[5].a : 1
+	    475983 b.b.and_f[1].a : 1
+	    475983 b.b.and_f[4].a : 1
+	    475983 b.b.and_f[3].a : 1
+	    475984 b.b.vt.OR2_tf[5]._y : 0  [by b.b.and_t[5].a:=1]
+	    475998 b.b.vt.ct.in[5] : 1  [by b.b.vt.OR2_tf[5]._y:=0]
+	    476128 b.b.vt.OR2_tf[0]._y : 0  [by b.b.and_t[0].a:=1]
+	    476135 b.b.vt.ct.in[0] : 1  [by b.b.vt.OR2_tf[0]._y:=0]
+	    476145 b.b.vt.OR2_tf[4]._y : 0  [by b.b.and_f[4].a:=1]
+	    476305 b.b.vt.ct.in[4] : 1  [by b.b.vt.OR2_tf[4]._y:=0]
+	    478815 b.b.vt.OR2_tf[6]._y : 0  [by b.b.and_f[6].a:=1]
+	    482337 b.b.vt.OR2_tf[2]._y : 0  [by b.b.and_t[2].a:=1]
+	    482338 b.b.vt.ct.in[2] : 1  [by b.b.vt.OR2_tf[2]._y:=0]
+	    483352 b.b.vt.OR2_tf[3]._y : 0  [by b.b.and_f[3].a:=1]
+	    483353 b.b.vt.ct.in[3] : 1  [by b.b.vt.OR2_tf[3]._y:=0]
+	    483354 b.b.vt.ct.C2Els[1]._y : 0  [by b.b.vt.ct.in[3]:=1]
+	    485597 b.b.vt.ct.tmp[8] : 1  [by b.b.vt.ct.C2Els[1]._y:=0]
+	    500372 b.b.vt.ct.in[6] : 1  [by b.b.vt.OR2_tf[6]._y:=0]
+	    500559 b.b.vt.ct.C3Els[0]._y : 0  [by b.b.vt.ct.in[6]:=1]
+	    500560 b.b.vt.ct.tmp[9] : 1  [by b.b.vt.ct.C3Els[0]._y:=0]
+	    515267 b.b.vt.OR2_tf[1]._y : 0  [by b.b.and_f[1].a:=1]
+	    519449 b.b.vt.ct.in[1] : 1  [by b.b.vt.OR2_tf[1]._y:=0]
+	    554231 b.b.vt.ct.C2Els[0]._y : 0  [by b.b.vt.ct.in[1]:=1]
+	    554232 b.b.vt.ct.tmp[7] : 1  [by b.b.vt.ct.C2Els[0]._y:=0]
+	    555085 b.b.vt.ct.C3Els[1]._y : 0  [by b.b.vt.ct.tmp[7]:=1]
+	    555090 b.b.vt.out : 1  [by b.b.vt.ct.C3Els[1]._y:=0]
+	    555981 b.b.in_v_buf._y : 0  [by b.b.vt.out:=1]
+	    555982 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+	    555999 b.b.sb_in_v.buf4._y : 0  [by b.in.v:=1]
+	    558572 b.b.and_f[0].c : 1  [by b.b.sb_in_v.buf4._y:=0]
+	    558573 b.b.and_t[0]._y : 0  [by b.b.and_f[0].c:=1]
+	    558575 b.b.and_f[1]._y : 0  [by b.b.and_f[0].c:=1]
+	    558614 b.b.and_t[2]._y : 0  [by b.b.and_f[0].c:=1]
+	    558670 b.b.and_f[1].y : 1  [by b.b.and_f[1]._y:=0]
+	    558949 b.b.and_t[2].y : 1  [by b.b.and_t[2]._y:=0]
+	    559513 b.b.and_f[3]._y : 0  [by b.b.and_f[0].c:=1]
+	    559521 b.b.and_f[3].y : 1  [by b.b.and_f[3]._y:=0]
+	    561389 b.b.and_t[5]._y : 0  [by b.b.and_f[0].c:=1]
+	    561423 b.b.and_t[5].y : 1  [by b.b.and_t[5]._y:=0]
+	    566933 b.b.and_f[6]._y : 0  [by b.b.and_f[0].c:=1]
+	    572306 b.b.and_t[0].y : 1  [by b.b.and_t[0]._y:=0]
+	    580820 b.b.and_f[6].y : 1  [by b.b.and_f[6]._y:=0]
+	    617534 b.b.and_f[4]._y : 0  [by b.b.and_f[0].c:=1]
+	    618452 b.b.and_f[4].y : 1  [by b.b.and_f[4]._y:=0]
+	    618452 b.out.a : 1
+	    618456 b.b.or2._y : 0  [by b.out.a:=1]
+	    664834 b.b.or2.y : 1  [by b.b.or2._y:=0]
+	    667232 b.b.ack_Cel._y : 0  [by b.b.or2.y:=1]
+	    670447 b.in.a : 1  [by b.b.ack_Cel._y:=0]
+[] Removing data
+	    670447 b.b.and_t[0].a : 0
+	    670447 b.b.and_f[6].a : 0
+	    670447 b.b.and_t[2].a : 0
+	    670447 b.b.and_t[5].a : 0
+	    670447 b.b.and_f[1].a : 0
+	    670447 b.b.and_f[4].a : 0
+	    670447 b.b.and_f[3].a : 0
+	    670448 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    670450 b.b.and_f[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    670451 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_f[3].a:=0]
+	    670495 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    670496 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	    670520 b.b.and_f[3]._y : 1  [by b.b.and_f[3].a:=0]
+	    670546 b.b.and_f[6].y : 0  [by b.b.and_f[6]._y:=1]
+	    670587 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	    670620 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    670625 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    670631 b.b.and_f[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    670643 b.b.and_f[4].y : 0  [by b.b.and_f[4]._y:=1]
+	    670861 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	    671274 b.b.and_f[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    672303 b.b.and_f[1].y : 0  [by b.b.and_f[1]._y:=1]
+	    674584 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	    674761 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[1]:=0]
+	    674762 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	    676398 b.b.and_t[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    676454 b.b.and_t[5].y : 0  [by b.b.and_t[5]._y:=1]
+	    682346 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    689566 b.b.and_f[3].y : 0  [by b.b.and_f[3]._y:=1]
+	    691424 b.b.and_t[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    691425 b.b.and_t[2].y : 0  [by b.b.and_t[2]._y:=1]
+	    707736 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	    709932 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    709969 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	    717566 b.b.and_t[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    717567 b.b.and_t[0].y : 0  [by b.b.and_t[0]._y:=1]
+	    727352 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	    730916 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[2]:=0]
+	    732608 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	    733344 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[5]:=0]
+	    733357 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	    750341 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[9]:=0]
+	    750698 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	    750723 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	    750744 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	    750745 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	    760393 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]
+	    760393 b.out.a : 0
+	    760394 b.b.or2._y : 1  [by b.out.a:=0]
+	    760395 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	    760556 b.b.ack_Cel._y : 1  [by b.b.or2.y:=0]
+	    761593 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+[] Enabling drop
+	    761593 b.drop : 1
+	    761598 b.b._dropB : 0  [by b.drop:=1]
+	    762179 b.b.sb_dropB.buf4._y : 1  [by b.b._dropB:=0]
+	    762587 b.b.and_f[0].b : 0  [by b.b.sb_dropB.buf4._y:=1]
+[] Sending in valid data
+	    762587 b.b.and_t[0].a : 1
+	    762587 b.b.and_f[6].a : 1
+	    762587 b.b.and_t[2].a : 1
+	    762587 b.b.and_t[5].a : 1
+	    762587 b.b.and_f[1].a : 1
+	    762587 b.b.and_f[4].a : 1
+	    762587 b.b.and_t[3].a : 1
+	    762591 b.b.vt.OR2_tf[1]._y : 0  [by b.b.and_f[1].a:=1]
+	    762598 b.b.vt.OR2_tf[0]._y : 0  [by b.b.and_t[0].a:=1]
+	    762601 b.b.vt.OR2_tf[2]._y : 0  [by b.b.and_t[2].a:=1]
+	    762605 b.b.vt.OR2_tf[5]._y : 0  [by b.b.and_t[5].a:=1]
+	    762691 b.b.vt.OR2_tf[4]._y : 0  [by b.b.and_f[4].a:=1]
+	    762829 b.b.vt.ct.in[2] : 1  [by b.b.vt.OR2_tf[2]._y:=0]
+	    763448 b.b.vt.ct.in[5] : 1  [by b.b.vt.OR2_tf[5]._y:=0]
+	    763634 b.b.vt.OR2_tf[6]._y : 0  [by b.b.and_f[6].a:=1]
+	    763704 b.b.vt.ct.in[6] : 1  [by b.b.vt.OR2_tf[6]._y:=0]
+	    763795 b.b.vt.ct.in[1] : 1  [by b.b.vt.OR2_tf[1]._y:=0]
+	    764150 b.b.vt.ct.in[4] : 1  [by b.b.vt.OR2_tf[4]._y:=0]
+	    771053 b.b.vt.ct.in[0] : 1  [by b.b.vt.OR2_tf[0]._y:=0]
+	    771064 b.b.vt.ct.C2Els[0]._y : 0  [by b.b.vt.ct.in[0]:=1]
+	    771067 b.b.vt.ct.tmp[7] : 1  [by b.b.vt.ct.C2Els[0]._y:=0]
+	    794031 b.b.vt.OR2_tf[3]._y : 0  [by b.b.and_t[3].a:=1]
+	    794085 b.b.vt.ct.in[3] : 1  [by b.b.vt.OR2_tf[3]._y:=0]
+	    795233 b.b.vt.ct.C2Els[1]._y : 0  [by b.b.vt.ct.in[3]:=1]
+	    796394 b.b.vt.ct.tmp[8] : 1  [by b.b.vt.ct.C2Els[1]._y:=0]
+	    814572 b.b.vt.ct.C3Els[0]._y : 0  [by b.b.vt.ct.in[4]:=1]
+	    823224 b.b.vt.ct.tmp[9] : 1  [by b.b.vt.ct.C3Els[0]._y:=0]
+	    823305 b.b.vt.ct.C3Els[1]._y : 0  [by b.b.vt.ct.tmp[9]:=1]
+	    834382 b.b.vt.out : 1  [by b.b.vt.ct.C3Els[1]._y:=0]
+	    852365 b.b.in_v_buf._y : 0  [by b.b.vt.out:=1]
+	    852457 b.in.v : 1  [by b.b.in_v_buf._y:=0]
+	    854201 b.b.sb_in_v.buf4._y : 0  [by b.in.v:=1]
+	    854814 b.b.and_f[0].c : 1  [by b.b.sb_in_v.buf4._y:=0]
+	    860768 b.b.and2._y : 0  [by b.in.v:=1]
+	    874790 b.b.or2.b : 1  [by b.b.and2._y:=0]
+	    874835 b.b.or2._y : 0  [by b.b.or2.b:=1]
+	    875832 b.b.or2.y : 1  [by b.b.or2._y:=0]
+	    877481 b.b.ack_Cel._y : 0  [by b.b.or2.y:=1]
+	    878006 b.in.a : 1  [by b.b.ack_Cel._y:=0]
+[] Removing data
+	    878006 b.b.and_t[0].a : 0
+	    878006 b.b.and_f[6].a : 0
+	    878006 b.b.and_t[2].a : 0
+	    878006 b.b.and_t[5].a : 0
+	    878006 b.b.and_f[1].a : 0
+	    878006 b.b.and_f[4].a : 0
+	    878006 b.b.and_t[3].a : 0
+	    878008 b.b.vt.OR2_tf[4]._y : 1  [by b.b.and_f[4].a:=0]
+	    878013 b.b.vt.OR2_tf[2]._y : 1  [by b.b.and_t[2].a:=0]
+	    878014 b.b.vt.ct.in[2] : 0  [by b.b.vt.OR2_tf[2]._y:=1]
+	    878058 b.b.vt.OR2_tf[6]._y : 1  [by b.b.and_f[6].a:=0]
+	    878062 b.b.vt.ct.in[6] : 0  [by b.b.vt.OR2_tf[6]._y:=1]
+	    878141 b.b.vt.ct.in[4] : 0  [by b.b.vt.OR2_tf[4]._y:=1]
+	    878360 b.b.vt.OR2_tf[3]._y : 1  [by b.b.and_t[3].a:=0]
+	    878906 b.b.vt.OR2_tf[0]._y : 1  [by b.b.and_t[0].a:=0]
+	    878906 b.b.vt.ct.in[3] : 0  [by b.b.vt.OR2_tf[3]._y:=1]
+	    878907 b.b.vt.ct.C2Els[1]._y : 1  [by b.b.vt.ct.in[3]:=0]
+	    884473 b.b.vt.OR2_tf[1]._y : 1  [by b.b.and_f[1].a:=0]
+	    884552 b.b.vt.ct.in[1] : 0  [by b.b.vt.OR2_tf[1]._y:=1]
+	    891285 b.b.vt.ct.tmp[8] : 0  [by b.b.vt.ct.C2Els[1]._y:=1]
+	    893618 b.b.vt.OR2_tf[5]._y : 1  [by b.b.and_t[5].a:=0]
+	    896051 b.b.vt.ct.in[5] : 0  [by b.b.vt.OR2_tf[5]._y:=1]
+	    896139 b.b.vt.ct.C3Els[0]._y : 1  [by b.b.vt.ct.in[5]:=0]
+	    903921 b.b.vt.ct.tmp[9] : 0  [by b.b.vt.ct.C3Els[0]._y:=1]
+	    924469 b.b.vt.ct.in[0] : 0  [by b.b.vt.OR2_tf[0]._y:=1]
+	    952796 b.b.vt.ct.C2Els[0]._y : 1  [by b.b.vt.ct.in[0]:=0]
+	    952855 b.b.vt.ct.tmp[7] : 0  [by b.b.vt.ct.C2Els[0]._y:=1]
+	    952885 b.b.vt.ct.C3Els[1]._y : 1  [by b.b.vt.ct.tmp[7]:=0]
+	    954352 b.b.vt.out : 0  [by b.b.vt.ct.C3Els[1]._y:=1]
+	   1013856 b.b.in_v_buf._y : 1  [by b.b.vt.out:=0]
+	   1033240 b.in.v : 0  [by b.b.in_v_buf._y:=1]
+	   1033925 b.b.and2._y : 1  [by b.in.v:=0]
+	   1034052 b.b.or2.b : 0  [by b.b.and2._y:=1]
+	   1034221 b.b.or2._y : 1  [by b.b.or2.b:=0]
+	   1034264 b.b.or2.y : 0  [by b.b.or2._y:=1]
+	   1034276 b.b.ack_Cel._y : 1  [by b.b.or2.y:=0]
+	   1035555 b.in.a : 0  [by b.b.ack_Cel._y:=1]
+	   1049955 b.b.sb_in_v.buf4._y : 1  [by b.in.v:=0]
+	   1050188 b.b.and_f[0].c : 0  [by b.b.sb_in_v.buf4._y:=1]

test/unit_tests/dropper_static/run/test.prs

@@ -0,0 +1,717 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"Reset"->"b._reset_B"-
+~("Reset")->"b._reset_B"+
+= "b.b._dropB" "b.b.sb_dropB.in"
+= "b.b._dropB" "b.b.inv.y"
+"b.b.in_v_buf.a"->"b.b.in_v_buf._y"-
+~("b.b.in_v_buf.a")->"b.b.in_v_buf._y"+
+"b.b.in_v_buf._y"->"b.b.in_v_buf.y"-
+~("b.b.in_v_buf._y")->"b.b.in_v_buf.y"+
+"b.b.sb_dropB.buf4.a"->"b.b.sb_dropB.buf4._y"-
+~("b.b.sb_dropB.buf4.a")->"b.b.sb_dropB.buf4._y"+
+"b.b.sb_dropB.buf4._y"->"b.b.sb_dropB.buf4.y"-
+~("b.b.sb_dropB.buf4._y")->"b.b.sb_dropB.buf4.y"+
+= "b.b.sb_dropB.supply.vdd" "b.b.sb_dropB.buf4.vdd"
+= "b.b.sb_dropB.supply.vss" "b.b.sb_dropB.buf4.vss"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[13]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[12]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[11]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[10]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[9]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[8]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[7]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[6]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[5]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[4]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[3]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[2]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.out[1]"
+= "b.b.sb_dropB.out[0]" "b.b.sb_dropB.buf4.y"
+= "b.b.sb_dropB.in" "b.b.sb_dropB.buf4.a"
+= "b.b.supply.vss" "b.b.sb_in_v.supply.vss"
+= "b.b.supply.vdd" "b.b.sb_in_v.supply.vdd"
+= "b.b.supply.vss" "b.b.sb_dropB.supply.vss"
+= "b.b.supply.vdd" "b.b.sb_dropB.supply.vdd"
+= "b.b.supply.vss" "b.b.vt.supply.vss"
+= "b.b.supply.vdd" "b.b.vt.supply.vdd"
+= "b.b.supply.vdd" "b.b.and_t[6].vdd"
+= "b.b.supply.vdd" "b.b.and_t[5].vdd"
+= "b.b.supply.vdd" "b.b.and_t[4].vdd"
+= "b.b.supply.vdd" "b.b.and_t[3].vdd"
+= "b.b.supply.vdd" "b.b.and_t[2].vdd"
+= "b.b.supply.vdd" "b.b.and_t[1].vdd"
+= "b.b.supply.vdd" "b.b.and_t[0].vdd"
+= "b.b.supply.vdd" "b.b.or2.vdd"
+= "b.b.supply.vdd" "b.b.and2.vdd"
+= "b.b.supply.vdd" "b.b.in_v_buf.vdd"
+= "b.b.supply.vdd" "b.b.inv.vdd"
+= "b.b.supply.vss" "b.b.and_t[6].vss"
+= "b.b.supply.vss" "b.b.and_t[5].vss"
+= "b.b.supply.vss" "b.b.and_t[4].vss"
+= "b.b.supply.vss" "b.b.and_t[3].vss"
+= "b.b.supply.vss" "b.b.and_t[2].vss"
+= "b.b.supply.vss" "b.b.and_t[1].vss"
+= "b.b.supply.vss" "b.b.and_t[0].vss"
+= "b.b.supply.vss" "b.b.or2.vss"
+= "b.b.supply.vss" "b.b.and2.vss"
+= "b.b.supply.vss" "b.b.in_v_buf.vss"
+= "b.b.supply.vss" "b.b.inv.vss"
+= "b.b.cond" "b.b.and2.a"
+= "b.b.cond" "b.b._drop"
+= "b.b.cond" "b.b.inv.a"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.out.a" "b.b.or2.a"
+= "b.b.out.d.d[6].d[0]" "b.b.and_f[6].y"
+= "b.b.out.d.d[6].d[0]" "b.b.out.d.d[6].f"
+= "b.b.out.d.d[6].d[1]" "b.b.and_t[6].y"
+= "b.b.out.d.d[6].d[1]" "b.b.out.d.d[6].t"
+= "b.b.out.d.d[5].d[0]" "b.b.and_f[5].y"
+= "b.b.out.d.d[5].d[0]" "b.b.out.d.d[5].f"
+= "b.b.out.d.d[5].d[1]" "b.b.and_t[5].y"
+= "b.b.out.d.d[5].d[1]" "b.b.out.d.d[5].t"
+= "b.b.out.d.d[4].d[0]" "b.b.and_f[4].y"
+= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
+= "b.b.out.d.d[4].d[1]" "b.b.and_t[4].y"
+= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
+= "b.b.out.d.d[3].d[0]" "b.b.and_f[3].y"
+= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
+= "b.b.out.d.d[3].d[1]" "b.b.and_t[3].y"
+= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
+= "b.b.out.d.d[2].d[0]" "b.b.and_f[2].y"
+= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
+= "b.b.out.d.d[2].d[1]" "b.b.and_t[2].y"
+= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
+= "b.b.out.d.d[1].d[0]" "b.b.and_f[1].y"
+= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
+= "b.b.out.d.d[1].d[1]" "b.b.and_t[1].y"
+= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
+= "b.b.out.d.d[0].d[0]" "b.b.and_f[0].y"
+= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
+= "b.b.out.d.d[0].d[1]" "b.b.and_t[0].y"
+= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+= "b.b.in.d.d[0].f" "b.b.vt.in.d[0].f"
+= "b.b.in.d.d[0].t" "b.b.vt.in.d[0].t"
+= "b.b.in.d.d[0].d[0]" "b.b.vt.in.d[0].d[0]"
+= "b.b.in.d.d[0].d[1]" "b.b.vt.in.d[0].d[1]"
+= "b.b.in.d.d[1].f" "b.b.vt.in.d[1].f"
+= "b.b.in.d.d[1].t" "b.b.vt.in.d[1].t"
+= "b.b.in.d.d[1].d[0]" "b.b.vt.in.d[1].d[0]"
+= "b.b.in.d.d[1].d[1]" "b.b.vt.in.d[1].d[1]"
+= "b.b.in.d.d[2].f" "b.b.vt.in.d[2].f"
+= "b.b.in.d.d[2].t" "b.b.vt.in.d[2].t"
+= "b.b.in.d.d[2].d[0]" "b.b.vt.in.d[2].d[0]"
+= "b.b.in.d.d[2].d[1]" "b.b.vt.in.d[2].d[1]"
+= "b.b.in.d.d[3].f" "b.b.vt.in.d[3].f"
+= "b.b.in.d.d[3].t" "b.b.vt.in.d[3].t"
+= "b.b.in.d.d[3].d[0]" "b.b.vt.in.d[3].d[0]"
+= "b.b.in.d.d[3].d[1]" "b.b.vt.in.d[3].d[1]"
+= "b.b.in.d.d[4].f" "b.b.vt.in.d[4].f"
+= "b.b.in.d.d[4].t" "b.b.vt.in.d[4].t"
+= "b.b.in.d.d[4].d[0]" "b.b.vt.in.d[4].d[0]"
+= "b.b.in.d.d[4].d[1]" "b.b.vt.in.d[4].d[1]"
+= "b.b.in.d.d[5].f" "b.b.vt.in.d[5].f"
+= "b.b.in.d.d[5].t" "b.b.vt.in.d[5].t"
+= "b.b.in.d.d[5].d[0]" "b.b.vt.in.d[5].d[0]"
+= "b.b.in.d.d[5].d[1]" "b.b.vt.in.d[5].d[1]"
+= "b.b.in.d.d[6].f" "b.b.vt.in.d[6].f"
+= "b.b.in.d.d[6].t" "b.b.vt.in.d[6].t"
+= "b.b.in.d.d[6].d[0]" "b.b.vt.in.d[6].d[0]"
+= "b.b.in.d.d[6].d[1]" "b.b.vt.in.d[6].d[1]"
+= "b.b.in.a" "b.b.ack_Cel.y"
+= "b.b.in.v" "b.b.sb_in_v.in"
+= "b.b.in.v" "b.b.ack_Cel.c2"
+= "b.b.in.v" "b.b.and2.b"
+= "b.b.in.v" "b.b.in_v_buf.y"
+= "b.b.in.v" "b.b._in_vX"
+= "b.b.in.d.d[6].d[0]" "b.b.and_f[6].a"
+= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
+= "b.b.in.d.d[6].d[1]" "b.b.and_t[6].a"
+= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
+= "b.b.in.d.d[5].d[0]" "b.b.and_f[5].a"
+= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
+= "b.b.in.d.d[5].d[1]" "b.b.and_t[5].a"
+= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
+= "b.b.in.d.d[4].d[0]" "b.b.and_f[4].a"
+= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
+= "b.b.in.d.d[4].d[1]" "b.b.and_t[4].a"
+= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
+= "b.b.in.d.d[3].d[0]" "b.b.and_f[3].a"
+= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
+= "b.b.in.d.d[3].d[1]" "b.b.and_t[3].a"
+= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
+= "b.b.in.d.d[2].d[0]" "b.b.and_f[2].a"
+= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
+= "b.b.in.d.d[2].d[1]" "b.b.and_t[2].a"
+= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
+= "b.b.in.d.d[1].d[0]" "b.b.and_f[1].a"
+= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
+= "b.b.in.d.d[1].d[1]" "b.b.and_t[1].a"
+= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
+= "b.b.in.d.d[0].d[0]" "b.b.and_f[0].a"
+= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
+= "b.b.in.d.d[0].d[1]" "b.b.and_t[0].a"
+= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
+"b.b.or2.a"|"b.b.or2.b"->"b.b.or2._y"-
+~("b.b.or2.a"|"b.b.or2.b")->"b.b.or2._y"+
+"b.b.or2._y"->"b.b.or2.y"-
+~("b.b.or2._y")->"b.b.or2.y"+
+= "b.b.or2.y" "b.b.ack_Cel.c1"
+= "b.b.or2.b" "b.b.and2.y"
+"b.b.and2.a"&"b.b.and2.b"->"b.b.and2._y"-
+~("b.b.and2.a"&"b.b.and2.b")->"b.b.and2._y"+
+"b.b.and2._y"->"b.b.and2.y"-
+~("b.b.and2._y")->"b.b.and2.y"+
+"b.b.sb_in_v.buf4.a"->"b.b.sb_in_v.buf4._y"-
+~("b.b.sb_in_v.buf4.a")->"b.b.sb_in_v.buf4._y"+
+"b.b.sb_in_v.buf4._y"->"b.b.sb_in_v.buf4.y"-
+~("b.b.sb_in_v.buf4._y")->"b.b.sb_in_v.buf4.y"+
+= "b.b.sb_in_v.supply.vdd" "b.b.sb_in_v.buf4.vdd"
+= "b.b.sb_in_v.supply.vss" "b.b.sb_in_v.buf4.vss"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[13]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[12]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[11]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[10]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[9]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[8]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[7]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[6]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[5]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[4]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[3]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[2]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.out[1]"
+= "b.b.sb_in_v.out[0]" "b.b.sb_in_v.buf4.y"
+= "b.b.sb_in_v.in" "b.b.sb_in_v.buf4.a"
+"b.b.and_f[0].a"&"b.b.and_f[0].b"&"b.b.and_f[0].c"->"b.b.and_f[0]._y"-
+~("b.b.and_f[0].a"&"b.b.and_f[0].b"&"b.b.and_f[0].c")->"b.b.and_f[0]._y"+
+"b.b.and_f[0]._y"->"b.b.and_f[0].y"-
+~("b.b.and_f[0]._y")->"b.b.and_f[0].y"+
+"b.b.and_f[1].a"&"b.b.and_f[1].b"&"b.b.and_f[1].c"->"b.b.and_f[1]._y"-
+~("b.b.and_f[1].a"&"b.b.and_f[1].b"&"b.b.and_f[1].c")->"b.b.and_f[1]._y"+
+"b.b.and_f[1]._y"->"b.b.and_f[1].y"-
+~("b.b.and_f[1]._y")->"b.b.and_f[1].y"+
+"b.b.and_f[2].a"&"b.b.and_f[2].b"&"b.b.and_f[2].c"->"b.b.and_f[2]._y"-
+~("b.b.and_f[2].a"&"b.b.and_f[2].b"&"b.b.and_f[2].c")->"b.b.and_f[2]._y"+
+"b.b.and_f[2]._y"->"b.b.and_f[2].y"-
+~("b.b.and_f[2]._y")->"b.b.and_f[2].y"+
+"b.b.and_f[3].a"&"b.b.and_f[3].b"&"b.b.and_f[3].c"->"b.b.and_f[3]._y"-
+~("b.b.and_f[3].a"&"b.b.and_f[3].b"&"b.b.and_f[3].c")->"b.b.and_f[3]._y"+
+"b.b.and_f[3]._y"->"b.b.and_f[3].y"-
+~("b.b.and_f[3]._y")->"b.b.and_f[3].y"+
+"b.b.and_f[4].a"&"b.b.and_f[4].b"&"b.b.and_f[4].c"->"b.b.and_f[4]._y"-
+~("b.b.and_f[4].a"&"b.b.and_f[4].b"&"b.b.and_f[4].c")->"b.b.and_f[4]._y"+
+"b.b.and_f[4]._y"->"b.b.and_f[4].y"-
+~("b.b.and_f[4]._y")->"b.b.and_f[4].y"+
+"b.b.and_f[5].a"&"b.b.and_f[5].b"&"b.b.and_f[5].c"->"b.b.and_f[5]._y"-
+~("b.b.and_f[5].a"&"b.b.and_f[5].b"&"b.b.and_f[5].c")->"b.b.and_f[5]._y"+
+"b.b.and_f[5]._y"->"b.b.and_f[5].y"-
+~("b.b.and_f[5]._y")->"b.b.and_f[5].y"+
+"b.b.and_f[6].a"&"b.b.and_f[6].b"&"b.b.and_f[6].c"->"b.b.and_f[6]._y"-
+~("b.b.and_f[6].a"&"b.b.and_f[6].b"&"b.b.and_f[6].c")->"b.b.and_f[6]._y"+
+"b.b.and_f[6]._y"->"b.b.and_f[6].y"-
+~("b.b.and_f[6]._y")->"b.b.and_f[6].y"+
+= "b.b.and_f[6].b" "b.b.and_t[6].b"
+= "b.b.and_f[6].b" "b.b.and_t[5].b"
+= "b.b.and_f[6].b" "b.b.and_t[4].b"
+= "b.b.and_f[6].b" "b.b.and_t[3].b"
+= "b.b.and_f[6].b" "b.b.and_t[2].b"
+= "b.b.and_f[6].b" "b.b.and_t[1].b"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[13]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[12]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[11]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[10]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[9]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[8]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[7]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[6]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[5]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[4]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[3]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[2]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[1]"
+= "b.b.and_f[6].b" "b.b.sb_dropB.out[0]"
+= "b.b.and_f[6].b" "b.b.and_t[0].b"
+= "b.b.and_f[6].b" "b.b.and_f[0].b"
+= "b.b.and_f[6].b" "b.b.and_f[1].b"
+= "b.b.and_f[6].b" "b.b.and_f[2].b"
+= "b.b.and_f[6].b" "b.b.and_f[3].b"
+= "b.b.and_f[6].b" "b.b.and_f[4].b"
+= "b.b.and_f[6].b" "b.b.and_f[5].b"
+= "b.b.and_f[6].c" "b.b.and_t[6].c"
+= "b.b.and_f[6].c" "b.b.and_t[5].c"
+= "b.b.and_f[6].c" "b.b.and_t[4].c"
+= "b.b.and_f[6].c" "b.b.and_t[3].c"
+= "b.b.and_f[6].c" "b.b.and_t[2].c"
+= "b.b.and_f[6].c" "b.b.and_t[1].c"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[13]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[12]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[11]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[10]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[9]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[8]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[7]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[6]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[5]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[4]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[3]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[2]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[1]"
+= "b.b.and_f[6].c" "b.b.sb_in_v.out[0]"
+= "b.b.and_f[6].c" "b.b.and_t[0].c"
+= "b.b.and_f[6].c" "b.b.and_f[0].c"
+= "b.b.and_f[6].c" "b.b.and_f[1].c"
+= "b.b.and_f[6].c" "b.b.and_f[2].c"
+= "b.b.and_f[6].c" "b.b.and_f[3].c"
+= "b.b.and_f[6].c" "b.b.and_f[4].c"
+= "b.b.and_f[6].c" "b.b.and_f[5].c"
+"b.b.and_t[0].a"&"b.b.and_t[0].b"&"b.b.and_t[0].c"->"b.b.and_t[0]._y"-
+~("b.b.and_t[0].a"&"b.b.and_t[0].b"&"b.b.and_t[0].c")->"b.b.and_t[0]._y"+
+"b.b.and_t[0]._y"->"b.b.and_t[0].y"-
+~("b.b.and_t[0]._y")->"b.b.and_t[0].y"+
+"b.b.and_t[1].a"&"b.b.and_t[1].b"&"b.b.and_t[1].c"->"b.b.and_t[1]._y"-
+~("b.b.and_t[1].a"&"b.b.and_t[1].b"&"b.b.and_t[1].c")->"b.b.and_t[1]._y"+
+"b.b.and_t[1]._y"->"b.b.and_t[1].y"-
+~("b.b.and_t[1]._y")->"b.b.and_t[1].y"+
+"b.b.and_t[2].a"&"b.b.and_t[2].b"&"b.b.and_t[2].c"->"b.b.and_t[2]._y"-
+~("b.b.and_t[2].a"&"b.b.and_t[2].b"&"b.b.and_t[2].c")->"b.b.and_t[2]._y"+
+"b.b.and_t[2]._y"->"b.b.and_t[2].y"-
+~("b.b.and_t[2]._y")->"b.b.and_t[2].y"+
+"b.b.and_t[3].a"&"b.b.and_t[3].b"&"b.b.and_t[3].c"->"b.b.and_t[3]._y"-
+~("b.b.and_t[3].a"&"b.b.and_t[3].b"&"b.b.and_t[3].c")->"b.b.and_t[3]._y"+
+"b.b.and_t[3]._y"->"b.b.and_t[3].y"-
+~("b.b.and_t[3]._y")->"b.b.and_t[3].y"+
+"b.b.and_t[4].a"&"b.b.and_t[4].b"&"b.b.and_t[4].c"->"b.b.and_t[4]._y"-
+~("b.b.and_t[4].a"&"b.b.and_t[4].b"&"b.b.and_t[4].c")->"b.b.and_t[4]._y"+
+"b.b.and_t[4]._y"->"b.b.and_t[4].y"-
+~("b.b.and_t[4]._y")->"b.b.and_t[4].y"+
+"b.b.and_t[5].a"&"b.b.and_t[5].b"&"b.b.and_t[5].c"->"b.b.and_t[5]._y"-
+~("b.b.and_t[5].a"&"b.b.and_t[5].b"&"b.b.and_t[5].c")->"b.b.and_t[5]._y"+
+"b.b.and_t[5]._y"->"b.b.and_t[5].y"-
+~("b.b.and_t[5]._y")->"b.b.and_t[5].y"+
+"b.b.and_t[6].a"&"b.b.and_t[6].b"&"b.b.and_t[6].c"->"b.b.and_t[6]._y"-
+~("b.b.and_t[6].a"&"b.b.and_t[6].b"&"b.b.and_t[6].c")->"b.b.and_t[6]._y"+
+"b.b.and_t[6]._y"->"b.b.and_t[6].y"-
+~("b.b.and_t[6]._y")->"b.b.and_t[6].y"+
+"b.b.inv.a"->"b.b.inv.y"-
+~("b.b.inv.a")->"b.b.inv.y"+
+~"b.b.vt.ct.C2Els[0].c1"&~"b.b.vt.ct.C2Els[0].c2"->"b.b.vt.ct.C2Els[0]._y"+
+"b.b.vt.ct.C2Els[0].c1"&"b.b.vt.ct.C2Els[0].c2"->"b.b.vt.ct.C2Els[0]._y"-
+"b.b.vt.ct.C2Els[0]._y"->"b.b.vt.ct.C2Els[0].y"-
+~("b.b.vt.ct.C2Els[0]._y")->"b.b.vt.ct.C2Els[0].y"+
+~"b.b.vt.ct.C2Els[1].c1"&~"b.b.vt.ct.C2Els[1].c2"->"b.b.vt.ct.C2Els[1]._y"+
+"b.b.vt.ct.C2Els[1].c1"&"b.b.vt.ct.C2Els[1].c2"->"b.b.vt.ct.C2Els[1]._y"-
+"b.b.vt.ct.C2Els[1]._y"->"b.b.vt.ct.C2Els[1].y"-
+~("b.b.vt.ct.C2Els[1]._y")->"b.b.vt.ct.C2Els[1].y"+
+~"b.b.vt.ct.C3Els[0].c1"&~"b.b.vt.ct.C3Els[0].c2"&~"b.b.vt.ct.C3Els[0].c3"->"b.b.vt.ct.C3Els[0]._y"+
+"b.b.vt.ct.C3Els[0].c1"&"b.b.vt.ct.C3Els[0].c2"&"b.b.vt.ct.C3Els[0].c3"->"b.b.vt.ct.C3Els[0]._y"-
+"b.b.vt.ct.C3Els[0]._y"->"b.b.vt.ct.C3Els[0].y"-
+~("b.b.vt.ct.C3Els[0]._y")->"b.b.vt.ct.C3Els[0].y"+
+~"b.b.vt.ct.C3Els[1].c1"&~"b.b.vt.ct.C3Els[1].c2"&~"b.b.vt.ct.C3Els[1].c3"->"b.b.vt.ct.C3Els[1]._y"+
+"b.b.vt.ct.C3Els[1].c1"&"b.b.vt.ct.C3Els[1].c2"&"b.b.vt.ct.C3Els[1].c3"->"b.b.vt.ct.C3Els[1]._y"-
+"b.b.vt.ct.C3Els[1]._y"->"b.b.vt.ct.C3Els[1].y"-
+~("b.b.vt.ct.C3Els[1]._y")->"b.b.vt.ct.C3Els[1].y"+
+= "b.b.vt.ct.tmp[7]" "b.b.vt.ct.C3Els[1].c1"
+= "b.b.vt.ct.tmp[7]" "b.b.vt.ct.C2Els[0].y"
+= "b.b.vt.ct.tmp[8]" "b.b.vt.ct.C3Els[1].c2"
+= "b.b.vt.ct.tmp[8]" "b.b.vt.ct.C2Els[1].y"
+= "b.b.vt.ct.tmp[9]" "b.b.vt.ct.C3Els[1].c3"
+= "b.b.vt.ct.tmp[9]" "b.b.vt.ct.C3Els[0].y"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C3Els[1].vdd"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C3Els[0].vdd"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C2Els[1].vdd"
+= "b.b.vt.ct.supply.vdd" "b.b.vt.ct.C2Els[0].vdd"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C3Els[1].vss"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C3Els[0].vss"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C2Els[1].vss"
+= "b.b.vt.ct.supply.vss" "b.b.vt.ct.C2Els[0].vss"
+= "b.b.vt.ct.in[0]" "b.b.vt.ct.C2Els[0].c1"
+= "b.b.vt.ct.in[0]" "b.b.vt.ct.tmp[0]"
+= "b.b.vt.ct.in[1]" "b.b.vt.ct.C2Els[0].c2"
+= "b.b.vt.ct.in[1]" "b.b.vt.ct.tmp[1]"
+= "b.b.vt.ct.in[2]" "b.b.vt.ct.C2Els[1].c1"
+= "b.b.vt.ct.in[2]" "b.b.vt.ct.tmp[2]"
+= "b.b.vt.ct.in[3]" "b.b.vt.ct.C2Els[1].c2"
+= "b.b.vt.ct.in[3]" "b.b.vt.ct.tmp[3]"
+= "b.b.vt.ct.in[4]" "b.b.vt.ct.C3Els[0].c1"
+= "b.b.vt.ct.in[4]" "b.b.vt.ct.tmp[4]"
+= "b.b.vt.ct.in[5]" "b.b.vt.ct.C3Els[0].c2"
+= "b.b.vt.ct.in[5]" "b.b.vt.ct.tmp[5]"
+= "b.b.vt.ct.in[6]" "b.b.vt.ct.C3Els[0].c3"
+= "b.b.vt.ct.in[6]" "b.b.vt.ct.tmp[6]"
+= "b.b.vt.ct.out" "b.b.vt.ct.C3Els[1].y"
+= "b.b.vt.ct.out" "b.b.vt.ct.tmp[10]"
+= "b.b.vt.ct.in[0]" "b.b.vt.OR2_tf[0].y"
+= "b.b.vt.ct.in[1]" "b.b.vt.OR2_tf[1].y"
+= "b.b.vt.ct.in[2]" "b.b.vt.OR2_tf[2].y"
+= "b.b.vt.ct.in[3]" "b.b.vt.OR2_tf[3].y"
+= "b.b.vt.ct.in[4]" "b.b.vt.OR2_tf[4].y"
+= "b.b.vt.ct.in[5]" "b.b.vt.OR2_tf[5].y"
+= "b.b.vt.ct.in[6]" "b.b.vt.OR2_tf[6].y"
+"b.b.vt.OR2_tf[0].a"|"b.b.vt.OR2_tf[0].b"->"b.b.vt.OR2_tf[0]._y"-
+~("b.b.vt.OR2_tf[0].a"|"b.b.vt.OR2_tf[0].b")->"b.b.vt.OR2_tf[0]._y"+
+"b.b.vt.OR2_tf[0]._y"->"b.b.vt.OR2_tf[0].y"-
+~("b.b.vt.OR2_tf[0]._y")->"b.b.vt.OR2_tf[0].y"+
+"b.b.vt.OR2_tf[1].a"|"b.b.vt.OR2_tf[1].b"->"b.b.vt.OR2_tf[1]._y"-
+~("b.b.vt.OR2_tf[1].a"|"b.b.vt.OR2_tf[1].b")->"b.b.vt.OR2_tf[1]._y"+
+"b.b.vt.OR2_tf[1]._y"->"b.b.vt.OR2_tf[1].y"-
+~("b.b.vt.OR2_tf[1]._y")->"b.b.vt.OR2_tf[1].y"+
+"b.b.vt.OR2_tf[2].a"|"b.b.vt.OR2_tf[2].b"->"b.b.vt.OR2_tf[2]._y"-
+~("b.b.vt.OR2_tf[2].a"|"b.b.vt.OR2_tf[2].b")->"b.b.vt.OR2_tf[2]._y"+
+"b.b.vt.OR2_tf[2]._y"->"b.b.vt.OR2_tf[2].y"-
+~("b.b.vt.OR2_tf[2]._y")->"b.b.vt.OR2_tf[2].y"+
+"b.b.vt.OR2_tf[3].a"|"b.b.vt.OR2_tf[3].b"->"b.b.vt.OR2_tf[3]._y"-
+~("b.b.vt.OR2_tf[3].a"|"b.b.vt.OR2_tf[3].b")->"b.b.vt.OR2_tf[3]._y"+
+"b.b.vt.OR2_tf[3]._y"->"b.b.vt.OR2_tf[3].y"-
+~("b.b.vt.OR2_tf[3]._y")->"b.b.vt.OR2_tf[3].y"+
+"b.b.vt.OR2_tf[4].a"|"b.b.vt.OR2_tf[4].b"->"b.b.vt.OR2_tf[4]._y"-
+~("b.b.vt.OR2_tf[4].a"|"b.b.vt.OR2_tf[4].b")->"b.b.vt.OR2_tf[4]._y"+
+"b.b.vt.OR2_tf[4]._y"->"b.b.vt.OR2_tf[4].y"-
+~("b.b.vt.OR2_tf[4]._y")->"b.b.vt.OR2_tf[4].y"+
+"b.b.vt.OR2_tf[5].a"|"b.b.vt.OR2_tf[5].b"->"b.b.vt.OR2_tf[5]._y"-
+~("b.b.vt.OR2_tf[5].a"|"b.b.vt.OR2_tf[5].b")->"b.b.vt.OR2_tf[5]._y"+
+"b.b.vt.OR2_tf[5]._y"->"b.b.vt.OR2_tf[5].y"-
+~("b.b.vt.OR2_tf[5]._y")->"b.b.vt.OR2_tf[5].y"+
+"b.b.vt.OR2_tf[6].a"|"b.b.vt.OR2_tf[6].b"->"b.b.vt.OR2_tf[6]._y"-
+~("b.b.vt.OR2_tf[6].a"|"b.b.vt.OR2_tf[6].b")->"b.b.vt.OR2_tf[6]._y"+
+"b.b.vt.OR2_tf[6]._y"->"b.b.vt.OR2_tf[6].y"-
+~("b.b.vt.OR2_tf[6]._y")->"b.b.vt.OR2_tf[6].y"+
+= "b.b.vt.supply.vss" "b.b.vt.ct.supply.vss"
+= "b.b.vt.supply.vdd" "b.b.vt.ct.supply.vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[6].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[5].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[4].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[3].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[2].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[1].vdd"
+= "b.b.vt.supply.vdd" "b.b.vt.OR2_tf[0].vdd"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[6].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[5].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[4].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[3].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[2].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[1].vss"
+= "b.b.vt.supply.vss" "b.b.vt.OR2_tf[0].vss"
+= "b.b.vt.out" "b.b.vt.ct.out"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.OR2_tf[6].b"
+= "b.b.vt.in.d[6].d[0]" "b.b.vt.in.d[6].f"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.OR2_tf[6].a"
+= "b.b.vt.in.d[6].d[1]" "b.b.vt.in.d[6].t"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.OR2_tf[5].b"
+= "b.b.vt.in.d[5].d[0]" "b.b.vt.in.d[5].f"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.OR2_tf[5].a"
+= "b.b.vt.in.d[5].d[1]" "b.b.vt.in.d[5].t"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.OR2_tf[4].b"
+= "b.b.vt.in.d[4].d[0]" "b.b.vt.in.d[4].f"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.OR2_tf[4].a"
+= "b.b.vt.in.d[4].d[1]" "b.b.vt.in.d[4].t"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.OR2_tf[3].b"
+= "b.b.vt.in.d[3].d[0]" "b.b.vt.in.d[3].f"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.OR2_tf[3].a"
+= "b.b.vt.in.d[3].d[1]" "b.b.vt.in.d[3].t"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.OR2_tf[2].b"
+= "b.b.vt.in.d[2].d[0]" "b.b.vt.in.d[2].f"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.OR2_tf[2].a"
+= "b.b.vt.in.d[2].d[1]" "b.b.vt.in.d[2].t"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.OR2_tf[1].b"
+= "b.b.vt.in.d[1].d[0]" "b.b.vt.in.d[1].f"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.OR2_tf[1].a"
+= "b.b.vt.in.d[1].d[1]" "b.b.vt.in.d[1].t"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.OR2_tf[0].b"
+= "b.b.vt.in.d[0].d[0]" "b.b.vt.in.d[0].f"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.OR2_tf[0].a"
+= "b.b.vt.in.d[0].d[1]" "b.b.vt.in.d[0].t"
+= "b.b.vt.out" "b.b.in_v_buf.a"
+~"b.b.ack_Cel.c1"&~"b.b.ack_Cel.c2"->"b.b.ack_Cel._y"+
+"b.b.ack_Cel.c1"&"b.b.ack_Cel.c2"->"b.b.ack_Cel._y"-
+"b.b.ack_Cel._y"->"b.b.ack_Cel.y"-
+~("b.b.ack_Cel._y")->"b.b.ack_Cel.y"+
+= "b.supply.vss" "b.b.supply.vss"
+= "b.supply.vdd" "b.b.supply.vdd"
+= "Vdd" "b.supply.vdd"
+= "GND" "b.supply.vss"
+= "b.drop" "b.b.cond"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.out.v" "b.b.out.v"
+= "b.out.a" "b.b.out.a"
+= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
+= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
+= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
+= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
+= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
+= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
+= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
+= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
+= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
+= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
+= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
+= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
+= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
+= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
+= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
+= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
+= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
+= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
+= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
+= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
+= "b.out.d.d[5].f" "b.b.out.d.d[5].f"
+= "b.out.d.d[5].t" "b.b.out.d.d[5].t"
+= "b.out.d.d[5].d[0]" "b.b.out.d.d[5].d[0]"
+= "b.out.d.d[5].d[1]" "b.b.out.d.d[5].d[1]"
+= "b.out.d.d[6].f" "b.b.out.d.d[6].f"
+= "b.out.d.d[6].t" "b.b.out.d.d[6].t"
+= "b.out.d.d[6].d[0]" "b.b.out.d.d[6].d[0]"
+= "b.out.d.d[6].d[1]" "b.b.out.d.d[6].d[1]"
+= "b.out.d.d[6].d[0]" "b.out.d.d[6].f"
+= "b.out.d.d[6].d[1]" "b.out.d.d[6].t"
+= "b.out.d.d[5].d[0]" "b.out.d.d[5].f"
+= "b.out.d.d[5].d[1]" "b.out.d.d[5].t"
+= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
+= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
+= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
+= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
+= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
+= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
+= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
+= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
+= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
+= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
+= "b.in.v" "b.b.in.v"
+= "b.in.a" "b.b.in.a"
+= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
+= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
+= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
+= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
+= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
+= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
+= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
+= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
+= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
+= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
+= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
+= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
+= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
+= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
+= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
+= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
+= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
+= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
+= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
+= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
+= "b.in.d.d[5].f" "b.b.in.d.d[5].f"
+= "b.in.d.d[5].t" "b.b.in.d.d[5].t"
+= "b.in.d.d[5].d[0]" "b.b.in.d.d[5].d[0]"
+= "b.in.d.d[5].d[1]" "b.b.in.d.d[5].d[1]"
+= "b.in.d.d[6].f" "b.b.in.d.d[6].f"
+= "b.in.d.d[6].t" "b.b.in.d.d[6].t"
+= "b.in.d.d[6].d[0]" "b.b.in.d.d[6].d[0]"
+= "b.in.d.d[6].d[1]" "b.b.in.d.d[6].d[1]"
+= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
+= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
+= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
+= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
+= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
+= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
+= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
+= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
+= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
+= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
+= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
+= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
+= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
+= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

test/unit_tests/dropper_static/test.act

@@ -0,0 +1,52 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc dropper_static_7 (avMx1of2<7> in; avMx1of2<7> out; bool? drop){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    dropper_static<7, true> b(.in = in, .out = out, .cond = drop, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+dropper_static_7 b;

test/unit_tests/dropper_static/test.prsim

@@ -0,0 +1,73 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 7
+set b.out.a 0
+set b.out.v 0
+set b.drop 0
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+status X
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 45
+cycle
+assert-qdi-channel-valid "b.out" 7 45
+assert b.in.v 1
+cycle
+set b.out.a 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+set b.out.a 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 37
+cycle
+assert-qdi-channel-valid "b.out" 7 37
+assert b.in.v 1
+cycle
+set b.out.a 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+set b.out.a 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Enabling drop'"
+set b.drop 1
+cycle
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 45
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 1
+assert b.in.a 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+assert b.in.a 0

test/unit_tests/encoder1d_7/run/prsim.in

@@ -0,0 +1,268 @@
+random_seed 99
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+watchall
+
+system "echo '[] Set Reset 1'"
+
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 0
+set e.out.v 0
+set Reset 1
+
+cycle
+status X
+system "echo '[] Set Reset 0'"
+set Reset 0
+cycle
+status X
+
+
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 6 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 1
+cycle
+assert-qdi-channel-valid "e.out" 3 6
+assert e.in[6].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[6].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+

test/unit_tests/encoder1d_7/test.act

@@ -0,0 +1,54 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc encoder1d_simple_test(a1of1 in[7]; avMx1of2<3> out){
+    power supply;
+    supply.vss = GND;
+    supply.vdd = Vdd; 
+
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    
+    encoder1d_simple<3,7> e(.in = in, .supply = supply, .reset_B = _reset_B);
+
+    fifo<3, 5> fifo_post(.in = e.out, .out = out, .supply = supply, .reset_B = _reset_B);
+
+
+}
+
+encoder1d_simple_test e;

test/unit_tests/encoder1d_7/test.prsim

@@ -0,0 +1,257 @@
+watchall
+
+system "echo '[] Set Reset 1'"
+
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 0
+set e.out.v 0
+set Reset 1
+
+cycle
+status X
+system "echo '[] Set Reset 0'"
+set Reset 0
+cycle
+status X
+
+
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 6 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 1
+cycle
+assert-qdi-channel-valid "e.out" 3 6
+assert e.in[6].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[6].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+

test/unit_tests/encoder1d_bd/run/prsim.in

@@ -0,0 +1,92 @@
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+watchall
+
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+set c.in[4].r 0
+set c.in[5].r 0
+set c.in[6].r 0
+
+set c.out.a 0
+
+set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set Reset 0
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 3
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+assert c.in[4].a 0
+assert c.in[5].a 0
+assert c.in[6].a 0
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 3 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 3
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 3 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 6
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+

test/unit_tests/encoder1d_bd/test.act

@@ -0,0 +1,61 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+pint N = 7;
+pint Nc = std::ceil_log2(N);
+pint N_BUFFERS = 5;
+pint N_BD_DLY_CFG = 4;
+
+defproc _encoder1d_bd (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
+
+    bool _reset_B;
+    prs {
+       Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+    encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
+        .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+_encoder1d_bd c; 

test/unit_tests/encoder1d_bd/test.prsim

@@ -0,0 +1,82 @@
+watchall
+
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+set c.in[4].r 0
+set c.in[5].r 0
+set c.in[6].r 0
+
+set c.out.a 0
+
+set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set Reset 0
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 3
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+assert c.in[4].a 0
+assert c.in[5].a 0
+assert c.in[6].a 0
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 3 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 3
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 3 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 6
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+

test/unit_tests/encoder2D_2x2/run/prsim.out

@@ -0,0 +1,798 @@
+e.y[0].r e.e.Yarb.arbs[0].or_cell._y e.e.x_ack_arb[0].buf1._y e.e.vtree_x.OR2_tf[0]._y e.e.buf_s_func._in_vX e.e._arb_out_x.r e.e.buf_s_func._en_X_t[0] e.y[0].a e.out.v e.e.buf_s_func._in_vXX_t[0] e.e.Yarb.arbs[0].ack_cell2._y e.e.y_ack_arb[1].buf1._y e.e._y_temp[1].a e.e.buf_s_func.out_a_B_buf_f.buf1._y e.e.buf_s_func._out_a_B e.e.buf_s_func._out_a_BX_t[0] e.e.x_enc_out.d[0].t e.x[0].r e.y[1].r e.e._x_temp[1].a e.e.Xarb.arbs[0]._y2_arb e.e._arb_out_y.r e.e._in_x_v e.out.a e.x[1].r e.e.y_enc_out.d[0].t e.e.x_enc_out.d[0].f e.e.y_enc_out.d[0].f e.e.y_encoder.ors_f[0].b._y e.e.vtree_y.OR2_tf[0]._y e.e.buf_s_func._in_vXX_f[0] e.e.buf_s_func._en_X_f[0] e.x[0].a e.e._y_temp[0].a e.e._in_xy_v.y e.e.vtree_x.ct.b._y e.e._x_temp[0].a e.e._en e.e.x_encoder.ors_t[0].b._y e.x[1].a e.e.buf_s_func.in_v_buf_f.buf1._y e.e.Yarb.arbs[0].ack_cell1._y e.e._in_y_v e.e.Yarb.arbs[0]._y1_arb e.e.vtree_x.ct.in[0] e.e.buf_s_func._out_a_BX_f[0] e.e.buf_s_func.in_v_prebuf._y e.e.vtree_y.ct.in[0] e.y[1].a e.e._x_v e.e.Xarb.arbs[0].arbiter._y1 e.e.Xarb.arbs[0].or_cell._y e.e._in_xy_v._y e.e.Xarb.arbs[0].ack_cell1._y e.e.Xarb.arbs[0]._y1_arb e.e.x_encoder.ors_f[0].b._y e.e.Yarb.arbs[0].arbiter._y1 e.e.y_encoder.ors_t[0].b._y e.e.vtree_y.ct.b._y e.e.buf_s_func.out_a_B_buf_t.buf1._y e.e._x_v_B e.e.Yarb.arbs[0]._y2_arb e.e.Xarb.arbs[0].arbiter._y2 e.e.Xarb.arbs[0].ack_cell2._y e.e.buf_s_func.in_v_buf_t.buf1._y e.e.y_ack_arb[0].buf1._y e.e.x_ack_arb[1].buf1._y e.e.Yarb.arbs[0].arbiter._y2 e.e.x_req_ortree.or2s[0]._y e.e.buf_s_func.en_buf_f.buf1._y e.e.buf_s_func.en_buf_t.buf1._y 
+[] Set Out Ack/Valid Low
+	     97124 e.out.a : 0
+	     97124 e.out.v : 0
+	     97141 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
+	     97142 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	     97188 e.e._en : 1  [by e.out.v:=0]
+	     97189 e.e.buf_s_func.en_buf_f.buf1._y : 0  [by e.e._en:=1]
+	     97546 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	     97722 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
+	    108612 e.e.buf_s_func.en_buf_t.buf1._y : 0  [by e.e._en:=1]
+	    108613 e.e.buf_s_func._en_X_t[0] : 1  [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
+	    109949 e.e.buf_s_func._en_X_f[0] : 1  [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
+	    162289 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
+[] Setting Neuron Req Low
+	    162289 e.y[0].r : 0
+	    162289 e.x[1].r : 0
+	    162289 e.x[0].r : 0
+	    162289 e.y[1].r : 0
+	    162292 e.e.Xarb.arbs[0].arbiter._y1 : 1  [by e.x[0].r:=0]
+	    162296 e.e.Xarb.arbs[0].arbiter._y2 : 1  [by e.x[1].r:=0]
+	    165550 e.e.Xarb.arbs[0]._y1_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y1:=1]
+	    165556 e.e.Xarb.arbs[0].ack_cell1._y : 1  [by e.e.Xarb.arbs[0]._y1_arb:=0]
+	    165810 e.e._x_temp[0].a : 0  [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
+	    165992 e.e.x_ack_arb[0].buf1._y : 1  [by e.e._x_temp[0].a:=0]
+	    169472 e.e.Yarb.arbs[0].arbiter._y2 : 1  [by e.y[1].r:=0]
+	    169619 e.e.Yarb.arbs[0]._y2_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y2:=1]
+	    169620 e.e.Yarb.arbs[0].ack_cell2._y : 1  [by e.e.Yarb.arbs[0]._y2_arb:=0]
+	    175703 e.e.x_req_ortree.or2s[0]._y : 1  [by e.x[0].r:=0]
+	    175777 e.e._x_v : 0  [by e.e.x_req_ortree.or2s[0]._y:=1]
+	    177674 e.e._x_v_B : 1  [by e.e._x_v:=0]
+	    212927 e.e.Yarb.arbs[0].arbiter._y1 : 1  [by e.y[0].r:=0]
+	    212928 e.e.Yarb.arbs[0]._y1_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y1:=1]
+	    212939 e.e.Yarb.arbs[0].ack_cell1._y : 1  [by e.e.Yarb.arbs[0]._y1_arb:=0]
+	    212940 e.e._y_temp[0].a : 0  [by e.e.Yarb.arbs[0].ack_cell1._y:=1]
+	    213039 e.e.y_ack_arb[0].buf1._y : 1  [by e.e._y_temp[0].a:=0]
+	    213107 e.e.Yarb.arbs[0].or_cell._y : 1  [by e.e.Yarb.arbs[0]._y1_arb:=0]
+	    213139 e.e._arb_out_y.r : 0  [by e.e.Yarb.arbs[0].or_cell._y:=1]
+	    213498 e.x[0].a : 0  [by e.e.x_ack_arb[0].buf1._y:=1]
+	    218276 e.e.Xarb.arbs[0]._y2_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y2:=1]
+	    218496 e.e.Xarb.arbs[0].ack_cell2._y : 1  [by e.e.Xarb.arbs[0]._y2_arb:=0]
+	    218554 e.e._x_temp[1].a : 0  [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
+	    218782 e.e._y_temp[1].a : 0  [by e.e.Yarb.arbs[0].ack_cell2._y:=1]
+	    218783 e.e.y_ack_arb[1].buf1._y : 1  [by e.e._y_temp[1].a:=0]
+	    219117 e.e.x_encoder.ors_f[0].b._y : 1  [by e.x[0].a:=0]
+	    219167 e.e.x_enc_out.d[0].f : 0  [by e.e.x_encoder.ors_f[0].b._y:=1]
+	    219353 e.e.x_ack_arb[1].buf1._y : 1  [by e.e._x_temp[1].a:=0]
+	    219882 e.y[0].a : 0  [by e.e.y_ack_arb[0].buf1._y:=1]
+	    219902 e.e.y_encoder.ors_f[0].b._y : 1  [by e.y[0].a:=0]
+	    226848 e.y[1].a : 0  [by e.e.y_ack_arb[1].buf1._y:=1]
+	    226983 e.x[1].a : 0  [by e.e.x_ack_arb[1].buf1._y:=1]
+	    228056 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y2_arb:=0]
+	    229957 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
+	    232524 e.e.x_encoder.ors_t[0].b._y : 1  [by e.x[1].a:=0]
+	    233746 e.e.y_enc_out.d[0].f : 0  [by e.e.y_encoder.ors_f[0].b._y:=1]
+	    243058 e.e.x_enc_out.d[0].t : 0  [by e.e.x_encoder.ors_t[0].b._y:=1]
+	    264915 e.e.y_encoder.ors_t[0].b._y : 1  [by e.y[1].a:=0]
+	    267412 e.e.y_enc_out.d[0].t : 0  [by e.e.y_encoder.ors_t[0].b._y:=1]
+	    267413 e.e.vtree_y.OR2_tf[0]._y : 1  [by e.e.y_enc_out.d[0].t:=0]
+	    267797 e.e.vtree_y.ct.in[0] : 0  [by e.e.vtree_y.OR2_tf[0]._y:=1]
+	    285642 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].t:=0]
+	    285744 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
+	    285846 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
+	    285913 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
+	    296652 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
+	    296665 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
+	    299810 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
+	    299928 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
+	    299930 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	    299938 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	    299952 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
+	    299959 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
+	    308558 e.e.vtree_y.ct.b._y : 1  [by e.e.vtree_y.ct.in[0]:=0]
+	    308622 e.e._in_y_v : 0  [by e.e.vtree_y.ct.b._y:=1]
+	    308622 Reset : 0
+	    316374 e._reset_B : 1  [by Reset:=0]
+	    316405 e.e.reset_buf._y : 0  [by e._reset_B:=1]
+	    316427 e.e._reset_BX : 1  [by e.e.reset_buf._y:=0]
+	    321791 e.e.buf_s_func.reset_buf._y : 0  [by e._reset_B:=1]
+	    322907 e.e.buf_s_func._reset_BX : 1  [by e.e.buf_s_func.reset_buf._y:=0]
+	    323689 e.e.buf_s_func.reset_bufarray.buf1._y : 0  [by e.e.buf_s_func._reset_BX:=1]
+	    323972 e.e.buf_s_func._reset_BXX[0] : 1  [by e.e.buf_s_func.reset_bufarray.buf1._y:=0]
+	    379361 e.e.reset_bufarray.buf1._y : 0  [by e.e._reset_BX:=1]
+	    389772 e.e._reset_BXX[0] : 1  [by e.e.reset_bufarray.buf1._y:=0]
+[] Single Neuron Spikes (0,0)
+	    389772 e.y[0].r : 1
+	    389772 e.x[0].r : 1
+	    389773 e.e.Xarb.arbs[0].arbiter._y1 : 0  [by e.x[0].r:=1]
+	    389780 e.e.Yarb.arbs[0].arbiter._y1 : 0  [by e.y[0].r:=1]
+	    389780 e.e.Xarb.arbs[0]._y1_arb : 1  [by e.e.Xarb.arbs[0].arbiter._y1:=0]
+	    389804 e.e.Yarb.arbs[0]._y1_arb : 1  [by e.e.Yarb.arbs[0].arbiter._y1:=0]
+	    389813 e.e.Yarb.arbs[0].or_cell._y : 0  [by e.e.Yarb.arbs[0]._y1_arb:=1]
+	    389842 e.e._arb_out_y.r : 1  [by e.e.Yarb.arbs[0].or_cell._y:=0]
+	    389843 e.e.Y_ack_confirm._y : 0  [by e.e._arb_out_y.r:=1]
+	    390326 e.e._arb_out_y.a : 1  [by e.e.Y_ack_confirm._y:=0]
+	    390426 e.e.Yarb.arbs[0].ack_cell1._y : 0  [by e.e._arb_out_y.a:=1]
+	    390428 e.e._y_temp[0].a : 1  [by e.e.Yarb.arbs[0].ack_cell1._y:=0]
+	    392431 e.e.y_ack_arb[0].buf1._y : 0  [by e.e._y_temp[0].a:=1]
+	    393052 e.e.x_req_ortree.or2s[0]._y : 0  [by e.x[0].r:=1]
+	    394911 e.e.Xarb.arbs[0].or_cell._y : 0  [by e.e.Xarb.arbs[0]._y1_arb:=1]
+	    394914 e.e._arb_out_x.r : 1  [by e.e.Xarb.arbs[0].or_cell._y:=0]
+	    413074 e.e._x_v : 1  [by e.e.x_req_ortree.or2s[0]._y:=0]
+	    413075 e.e._x_v_B : 0  [by e.e._x_v:=1]
+	    434462 e.y[0].a : 1  [by e.e.y_ack_arb[0].buf1._y:=0]
+	    434466 e.e.y_encoder.ors_f[0].b._y : 0  [by e.y[0].a:=1]
+	    434795 e.e.y_enc_out.d[0].f : 1  [by e.e.y_encoder.ors_f[0].b._y:=0]
+	    436021 e.e.vtree_y.OR2_tf[0]._y : 0  [by e.e.y_enc_out.d[0].f:=1]
+	    458869 e.e.X_ack_confirm._y : 0  [by e.e._arb_out_x.r:=1]
+	    459476 e.e._arb_out_x.a : 1  [by e.e.X_ack_confirm._y:=0]
+	    461370 e.e.Xarb.arbs[0].ack_cell1._y : 0  [by e.e._arb_out_x.a:=1]
+	    463151 e.e._x_temp[0].a : 1  [by e.e.Xarb.arbs[0].ack_cell1._y:=0]
+	    463205 e.e.x_ack_arb[0].buf1._y : 0  [by e.e._x_temp[0].a:=1]
+	    488653 e.x[0].a : 1  [by e.e.x_ack_arb[0].buf1._y:=0]
+	    489010 e.e.x_encoder.ors_f[0].b._y : 0  [by e.x[0].a:=1]
+	    494123 e.e.vtree_y.ct.in[0] : 1  [by e.e.vtree_y.OR2_tf[0]._y:=0]
+	    494145 e.e.vtree_y.ct.b._y : 0  [by e.e.vtree_y.ct.in[0]:=1]
+	    494154 e.e._in_y_v : 1  [by e.e.vtree_y.ct.b._y:=0]
+	    515290 e.e.x_enc_out.d[0].f : 1  [by e.e.x_encoder.ors_f[0].b._y:=0]
+	    515476 e.e.vtree_x.OR2_tf[0]._y : 0  [by e.e.x_enc_out.d[0].f:=1]
+	    523146 e.e.vtree_x.ct.in[0] : 1  [by e.e.vtree_x.OR2_tf[0]._y:=0]
+	    523151 e.e.vtree_x.ct.b._y : 0  [by e.e.vtree_x.ct.in[0]:=1]
+	    523449 e.e._in_x_v : 1  [by e.e.vtree_x.ct.b._y:=0]
+	    531696 e.e._in_xy_v._y : 0  [by e.e._in_x_v:=1]
+	    531697 e.e._in_xy_v.y : 1  [by e.e._in_xy_v._y:=0]
+	    531900 e.e.buf_s_func.in_v_prebuf._y : 0  [by e.e._in_xy_v.y:=1]
+	    531901 e.e.buf_s_func._in_vX : 1  [by e.e.buf_s_func.in_v_prebuf._y:=0]
+	    531926 e.e.buf_s_func.in_v_buf_t.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	    533933 e.e.buf_s_func._in_vXX_t[0] : 1  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
+	    554229 e.e.buf_s_func.in_v_buf_f.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	    554230 e.e.buf_s_func._in_vXX_f[0] : 1  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
+	    554243 e.e.buf_s_func.f_buf_func[1]._y : 0  [by e.e.buf_s_func._in_vXX_f[0]:=1]
+	    554273 e.out.d.d[1].f : 1  [by e.e.buf_s_func.f_buf_func[1]._y:=0]
+	    563252 e.e.buf_s_func.f_buf_func[0]._y : 0  [by e.e.buf_s_func._in_vXX_f[0]:=1]
+	    563486 e.out.d.d[0].f : 1  [by e.e.buf_s_func.f_buf_func[0]._y:=0]
+[] Check Arbiter Acks
+[] Check Encoders
+[] Check Buffer
+[] Finish Neuron Handshake
+	    563486 e.y[0].r : 0
+	    563486 e.x[0].r : 0
+	    563515 e.e.x_req_ortree.or2s[0]._y : 1  [by e.x[0].r:=0]
+	    563516 e.e._x_v : 0  [by e.e.x_req_ortree.or2s[0]._y:=1]
+	    563536 e.e.Yarb.arbs[0].arbiter._y1 : 1  [by e.y[0].r:=0]
+	    563566 e.e.Xarb.arbs[0].arbiter._y1 : 1  [by e.x[0].r:=0]
+	    563915 e.e.Xarb.arbs[0]._y1_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y1:=1]
+	    565505 e.e.Yarb.arbs[0]._y1_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y1:=1]
+	    567529 e.e.Yarb.arbs[0].or_cell._y : 1  [by e.e.Yarb.arbs[0]._y1_arb:=0]
+	    567530 e.e._arb_out_y.r : 0  [by e.e.Yarb.arbs[0].or_cell._y:=1]
+	    582131 e.e._x_v_B : 1  [by e.e._x_v:=0]
+	    586219 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y1_arb:=0]
+	    586223 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
+	    586223 e.out.a : 1
+	    586223 e.out.v : 1
+	    586224 e.e.buf_s_func._out_a_B : 0  [by e.out.a:=1]
+	    586229 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	    586326 e.e._x_a_B : 0  [by e.out.v:=1]
+	    586363 e.e.X_ack_confirm._y : 1  [by e.e._x_a_B:=0]
+	    586365 e.e._arb_out_x.a : 0  [by e.e.X_ack_confirm._y:=1]
+	    586367 e.e.Xarb.arbs[0].ack_cell1._y : 1  [by e.e._arb_out_x.a:=0]
+	    586429 e.e._x_temp[0].a : 0  [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
+	    586457 e.e.buf_s_func._out_a_BX_f[0] : 0  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
+	    586493 e.e.x_ack_arb[0].buf1._y : 1  [by e.e._x_temp[0].a:=0]
+	    589727 e.x[0].a : 0  [by e.e.x_ack_arb[0].buf1._y:=1]
+	    589728 e.e.x_encoder.ors_f[0].b._y : 1  [by e.x[0].a:=0]
+	    589796 e.e.x_enc_out.d[0].f : 0  [by e.e.x_encoder.ors_f[0].b._y:=1]
+	    590025 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].f:=0]
+	    590319 e.e._x_a : 1  [by e.e._x_a_B:=0]
+	    590320 e.e._en : 0  [by e.e._x_a:=1]
+	    590322 e.e.buf_s_func.en_buf_t.buf1._y : 1  [by e.e._en:=0]
+	    590445 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	    590452 e.e.buf_s_func._out_a_BX_t[0] : 0  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
+	    599706 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
+	    602847 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
+	    616394 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
+	    616396 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
+	    616922 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
+	    618520 e.e.buf_s_func.en_buf_f.buf1._y : 1  [by e.e._en:=0]
+	    618610 e.e.buf_s_func._en_X_f[0] : 0  [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
+	    618614 e.e.buf_s_func.f_buf_func[1]._y : 1  [by e.e.buf_s_func._en_X_f[0]:=0]
+	    623363 e.e.buf_s_func._en_X_t[0] : 0  [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
+	    624924 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
+	    625043 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
+	    625057 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	    625800 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
+	    627134 e.out.d.d[1].f : 0  [by e.e.buf_s_func.f_buf_func[1]._y:=1]
+	    627372 e.e.Y_ack_confirm._y : 1  [by e.e._in_x_v:=0]
+	    628660 e.e._arb_out_y.a : 0  [by e.e.Y_ack_confirm._y:=1]
+	    629508 e.e.Yarb.arbs[0].ack_cell1._y : 1  [by e.e._arb_out_y.a:=0]
+	    629750 e.e._y_temp[0].a : 0  [by e.e.Yarb.arbs[0].ack_cell1._y:=1]
+	    629778 e.e.y_ack_arb[0].buf1._y : 1  [by e.e._y_temp[0].a:=0]
+	    634136 e.y[0].a : 0  [by e.e.y_ack_arb[0].buf1._y:=1]
+	    635046 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	    635201 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
+	    643929 e.e.y_encoder.ors_f[0].b._y : 1  [by e.y[0].a:=0]
+	    644056 e.e.y_enc_out.d[0].f : 0  [by e.e.y_encoder.ors_f[0].b._y:=1]
+	    650472 e.e.buf_s_func.f_buf_func[0]._y : 1  [by e.e.buf_s_func._en_X_f[0]:=0]
+	    650474 e.out.d.d[0].f : 0  [by e.e.buf_s_func.f_buf_func[0]._y:=1]
+	    665066 e.e.vtree_y.OR2_tf[0]._y : 1  [by e.e.y_enc_out.d[0].f:=0]
+	    665067 e.e.vtree_y.ct.in[0] : 0  [by e.e.vtree_y.OR2_tf[0]._y:=1]
+	    670826 e.e.vtree_y.ct.b._y : 1  [by e.e.vtree_y.ct.in[0]:=0]
+	    734592 e.e._in_y_v : 0  [by e.e.vtree_y.ct.b._y:=1]
+	    734989 e.e._x_a_B : 1  [by e.e._in_y_v:=0]
+	    737310 e.e._x_a : 0  [by e.e._x_a_B:=1]
+	    737310 e.out.a : 0
+	    737310 e.out.v : 0
+	    737380 e.e._en : 1  [by e.out.v:=0]
+	    737381 e.e.buf_s_func.en_buf_f.buf1._y : 0  [by e.e._en:=1]
+	    737388 e.e.buf_s_func._en_X_f[0] : 1  [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
+	    737814 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
+	    749082 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	    749115 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
+	    767327 e.e.buf_s_func.en_buf_t.buf1._y : 0  [by e.e._en:=1]
+	    767330 e.e.buf_s_func._en_X_t[0] : 1  [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
+	    784477 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	    784500 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
+[] Neuron (0,0) Encoded
+[] Single Neuron Spikes (1,1)
+	    784500 e.y[1].r : 1
+	    784500 e.x[1].r : 1
+	    784501 e.e.x_req_ortree.or2s[0]._y : 0  [by e.x[1].r:=1]
+	    784521 e.e.Xarb.arbs[0].arbiter._y2 : 0  [by e.x[1].r:=1]
+	    788853 e.e._x_v : 1  [by e.e.x_req_ortree.or2s[0]._y:=0]
+	    792400 e.e.Xarb.arbs[0]._y2_arb : 1  [by e.e.Xarb.arbs[0].arbiter._y2:=0]
+	    803719 e.e._x_v_B : 0  [by e.e._x_v:=1]
+	    808636 e.e.Yarb.arbs[0].arbiter._y2 : 0  [by e.y[1].r:=1]
+	    808667 e.e.Yarb.arbs[0]._y2_arb : 1  [by e.e.Yarb.arbs[0].arbiter._y2:=0]
+	    808845 e.e.Yarb.arbs[0].or_cell._y : 0  [by e.e.Yarb.arbs[0]._y2_arb:=1]
+	    808858 e.e._arb_out_y.r : 1  [by e.e.Yarb.arbs[0].or_cell._y:=0]
+	    818105 e.e.Y_ack_confirm._y : 0  [by e.e._arb_out_y.r:=1]
+	    818876 e.e._arb_out_y.a : 1  [by e.e.Y_ack_confirm._y:=0]
+	    822694 e.e.Yarb.arbs[0].ack_cell2._y : 0  [by e.e._arb_out_y.a:=1]
+	    822730 e.e._y_temp[1].a : 1  [by e.e.Yarb.arbs[0].ack_cell2._y:=0]
+	    822731 e.e.y_ack_arb[1].buf1._y : 0  [by e.e._y_temp[1].a:=1]
+	    841269 e.e.Xarb.arbs[0].or_cell._y : 0  [by e.e.Xarb.arbs[0]._y2_arb:=1]
+	    850480 e.e._arb_out_x.r : 1  [by e.e.Xarb.arbs[0].or_cell._y:=0]
+	    850824 e.e.X_ack_confirm._y : 0  [by e.e._arb_out_x.r:=1]
+	    850854 e.e._arb_out_x.a : 1  [by e.e.X_ack_confirm._y:=0]
+	    852159 e.e.Xarb.arbs[0].ack_cell2._y : 0  [by e.e._arb_out_x.a:=1]
+	    852509 e.e._x_temp[1].a : 1  [by e.e.Xarb.arbs[0].ack_cell2._y:=0]
+	    858620 e.e.x_ack_arb[1].buf1._y : 0  [by e.e._x_temp[1].a:=1]
+	    860849 e.y[1].a : 1  [by e.e.y_ack_arb[1].buf1._y:=0]
+	    861151 e.e.y_encoder.ors_t[0].b._y : 0  [by e.y[1].a:=1]
+	    869979 e.e.y_enc_out.d[0].t : 1  [by e.e.y_encoder.ors_t[0].b._y:=0]
+	    869987 e.e.vtree_y.OR2_tf[0]._y : 0  [by e.e.y_enc_out.d[0].t:=1]
+	    870119 e.e.vtree_y.ct.in[0] : 1  [by e.e.vtree_y.OR2_tf[0]._y:=0]
+	    874552 e.e.vtree_y.ct.b._y : 0  [by e.e.vtree_y.ct.in[0]:=1]
+	    878673 e.e._in_y_v : 1  [by e.e.vtree_y.ct.b._y:=0]
+	    897313 e.x[1].a : 1  [by e.e.x_ack_arb[1].buf1._y:=0]
+	    908590 e.e.x_encoder.ors_t[0].b._y : 0  [by e.x[1].a:=1]
+	    908604 e.e.x_enc_out.d[0].t : 1  [by e.e.x_encoder.ors_t[0].b._y:=0]
+	    908614 e.e.vtree_x.OR2_tf[0]._y : 0  [by e.e.x_enc_out.d[0].t:=1]
+	    908615 e.e.vtree_x.ct.in[0] : 1  [by e.e.vtree_x.OR2_tf[0]._y:=0]
+	    909459 e.e.vtree_x.ct.b._y : 0  [by e.e.vtree_x.ct.in[0]:=1]
+	    912160 e.e._in_x_v : 1  [by e.e.vtree_x.ct.b._y:=0]
+	    927845 e.e._in_xy_v._y : 0  [by e.e._in_x_v:=1]
+	    927855 e.e._in_xy_v.y : 1  [by e.e._in_xy_v._y:=0]
+	    927856 e.e.buf_s_func.in_v_prebuf._y : 0  [by e.e._in_xy_v.y:=1]
+	    929754 e.e.buf_s_func._in_vX : 1  [by e.e.buf_s_func.in_v_prebuf._y:=0]
+	    929759 e.e.buf_s_func.in_v_buf_t.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	    929782 e.e.buf_s_func._in_vXX_t[0] : 1  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
+	    929785 e.e.buf_s_func.t_buf_func[0]._y : 0  [by e.e.buf_s_func._in_vXX_t[0]:=1]
+	    929801 e.e.buf_s_func.t_buf_func[1]._y : 0  [by e.e.buf_s_func._in_vXX_t[0]:=1]
+	    929904 e.e.buf_s_func.in_v_buf_f.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	    931135 e.out.d.d[0].t : 1  [by e.e.buf_s_func.t_buf_func[0]._y:=0]
+	    932725 e.out.d.d[1].t : 1  [by e.e.buf_s_func.t_buf_func[1]._y:=0]
+	    989049 e.e.buf_s_func._in_vXX_f[0] : 1  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
+[] Check Arbiter Acks
+[] Check Encoders
+[] Check Buffer
+[] Finish Neuron Handshake
+	    989049 e.y[1].r : 0
+	    989049 e.x[1].r : 0
+	    989053 e.e.x_req_ortree.or2s[0]._y : 1  [by e.x[1].r:=0]
+	    989230 e.e.Xarb.arbs[0].arbiter._y2 : 1  [by e.x[1].r:=0]
+	    989261 e.e.Xarb.arbs[0]._y2_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y2:=1]
+	    989342 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y2_arb:=0]
+	    989343 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
+	    989427 e.e.Yarb.arbs[0].arbiter._y2 : 1  [by e.y[1].r:=0]
+	    993056 e.e.Yarb.arbs[0]._y2_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y2:=1]
+	    993677 e.e.Yarb.arbs[0].or_cell._y : 1  [by e.e.Yarb.arbs[0]._y2_arb:=0]
+	   1000029 e.e._x_v : 0  [by e.e.x_req_ortree.or2s[0]._y:=1]
+	   1000075 e.e._x_v_B : 1  [by e.e._x_v:=0]
+	   1004028 e.e._arb_out_y.r : 0  [by e.e.Yarb.arbs[0].or_cell._y:=1]
+	   1004028 e.out.a : 1
+	   1004028 e.out.v : 1
+	   1004078 e.e._x_a_B : 0  [by e.out.v:=1]
+	   1004079 e.e.X_ack_confirm._y : 1  [by e.e._x_a_B:=0]
+	   1004208 e.e._x_a : 1  [by e.e._x_a_B:=0]
+	   1005641 e.e.buf_s_func._out_a_B : 0  [by e.out.a:=1]
+	   1005645 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   1006742 e.e._en : 0  [by e.e._x_a:=1]
+	   1006748 e.e.buf_s_func.en_buf_f.buf1._y : 1  [by e.e._en:=0]
+	   1006749 e.e.buf_s_func._en_X_f[0] : 0  [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
+	   1006755 e.e._arb_out_x.a : 0  [by e.e.X_ack_confirm._y:=1]
+	   1006791 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   1008619 e.e.buf_s_func.en_buf_t.buf1._y : 1  [by e.e._en:=0]
+	   1010085 e.e.buf_s_func._out_a_BX_f[0] : 0  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
+	   1010672 e.e.buf_s_func._en_X_t[0] : 0  [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
+	   1021976 e.e.Xarb.arbs[0].ack_cell2._y : 1  [by e.e._arb_out_x.a:=0]
+	   1022037 e.e._x_temp[1].a : 0  [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
+	   1022097 e.e.x_ack_arb[1].buf1._y : 1  [by e.e._x_temp[1].a:=0]
+	   1023667 e.x[1].a : 0  [by e.e.x_ack_arb[1].buf1._y:=1]
+	   1042073 e.e.x_encoder.ors_t[0].b._y : 1  [by e.x[1].a:=0]
+	   1042741 e.e.x_enc_out.d[0].t : 0  [by e.e.x_encoder.ors_t[0].b._y:=1]
+	   1042797 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].t:=0]
+	   1042886 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
+	   1042887 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
+	   1042888 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
+	   1042960 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
+	   1043249 e.e.Y_ack_confirm._y : 1  [by e.e._in_x_v:=0]
+	   1043260 e.e._arb_out_y.a : 0  [by e.e.Y_ack_confirm._y:=1]
+	   1043261 e.e.Yarb.arbs[0].ack_cell2._y : 1  [by e.e._arb_out_y.a:=0]
+	   1043316 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
+	   1043390 e.e._y_temp[1].a : 0  [by e.e.Yarb.arbs[0].ack_cell2._y:=1]
+	   1043399 e.e.y_ack_arb[1].buf1._y : 1  [by e.e._y_temp[1].a:=0]
+	   1046479 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
+	   1046484 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
+	   1046493 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   1046589 e.e.buf_s_func._out_a_BX_t[0] : 0  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
+	   1046662 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
+	   1046846 e.e.buf_s_func.t_buf_func[1]._y : 1  [by e.e.buf_s_func._out_a_BX_t[0]:=0]
+	   1046847 e.out.d.d[1].t : 0  [by e.e.buf_s_func.t_buf_func[1]._y:=1]
+	   1047071 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   1047108 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
+	   1047458 e.y[1].a : 0  [by e.e.y_ack_arb[1].buf1._y:=1]
+	   1047574 e.e.y_encoder.ors_t[0].b._y : 1  [by e.y[1].a:=0]
+	   1048525 e.e.y_enc_out.d[0].t : 0  [by e.e.y_encoder.ors_t[0].b._y:=1]
+	   1048526 e.e.vtree_y.OR2_tf[0]._y : 1  [by e.e.y_enc_out.d[0].t:=0]
+	   1048792 e.e.vtree_y.ct.in[0] : 0  [by e.e.vtree_y.OR2_tf[0]._y:=1]
+	   1051657 e.e.buf_s_func.t_buf_func[0]._y : 1  [by e.e.buf_s_func._out_a_BX_t[0]:=0]
+	   1054257 e.out.d.d[0].t : 0  [by e.e.buf_s_func.t_buf_func[0]._y:=1]
+	   1110617 e.e.vtree_y.ct.b._y : 1  [by e.e.vtree_y.ct.in[0]:=0]
+	   1110618 e.e._in_y_v : 0  [by e.e.vtree_y.ct.b._y:=1]
+	   1112139 e.e._x_a_B : 1  [by e.e._in_y_v:=0]
+	   1114785 e.e._x_a : 0  [by e.e._x_a_B:=1]
+	   1114785 e.out.a : 0
+	   1114785 e.out.v : 0
+	   1115291 e.e._en : 1  [by e.out.v:=0]
+	   1116226 e.e.buf_s_func.en_buf_f.buf1._y : 0  [by e.e._en:=1]
+	   1120661 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
+	   1120761 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   1124929 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
+	   1127979 e.e.buf_s_func.en_buf_t.buf1._y : 0  [by e.e._en:=1]
+	   1127981 e.e.buf_s_func._en_X_t[0] : 1  [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
+	   1132851 e.e.buf_s_func._en_X_f[0] : 1  [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
+	   1182244 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   1183241 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
+[] Neuron (1,1) Encoded
+[] Neuron Spikes (0,0), (1,0)
+	   1183241 e.x[0].r : 1
+	   1183241 e.x[1].r : 1
+	   1183241 e.y[0].r : 1
+	   1183243 e.e.Yarb.arbs[0].arbiter._y1 : 0  [by e.y[0].r:=1]
+	   1187978 e.e.x_req_ortree.or2s[0]._y : 0  [by e.x[0].r:=1]
+	   1188075 e.e._x_v : 1  [by e.e.x_req_ortree.or2s[0]._y:=0]
+	   1188141 e.e._x_v_B : 0  [by e.e._x_v:=1]
+	   1196259 e.e.Xarb.arbs[0].arbiter._y1 : 0  [by e.x[0].r:=1]
+	   1196260 e.e.Xarb.arbs[0]._y1_arb : 1  [by e.e.Xarb.arbs[0].arbiter._y1:=0]
+	   1196407 e.e.Xarb.arbs[0].or_cell._y : 0  [by e.e.Xarb.arbs[0]._y1_arb:=1]
+	   1202758 e.e._arb_out_x.r : 1  [by e.e.Xarb.arbs[0].or_cell._y:=0]
+	   1202769 e.e.X_ack_confirm._y : 0  [by e.e._arb_out_x.r:=1]
+	   1205050 e.e._arb_out_x.a : 1  [by e.e.X_ack_confirm._y:=0]
+	   1205122 e.e.Xarb.arbs[0].ack_cell1._y : 0  [by e.e._arb_out_x.a:=1]
+	   1205136 e.e._x_temp[0].a : 1  [by e.e.Xarb.arbs[0].ack_cell1._y:=0]
+	   1205148 e.e.x_ack_arb[0].buf1._y : 0  [by e.e._x_temp[0].a:=1]
+	   1217465 e.x[0].a : 1  [by e.e.x_ack_arb[0].buf1._y:=0]
+	   1239712 e.e.x_encoder.ors_f[0].b._y : 0  [by e.x[0].a:=1]
+	   1243805 e.e.Yarb.arbs[0]._y1_arb : 1  [by e.e.Yarb.arbs[0].arbiter._y1:=0]
+	   1244705 e.e.Yarb.arbs[0].or_cell._y : 0  [by e.e.Yarb.arbs[0]._y1_arb:=1]
+	   1246272 e.e._arb_out_y.r : 1  [by e.e.Yarb.arbs[0].or_cell._y:=0]
+	   1247160 e.e.x_enc_out.d[0].f : 1  [by e.e.x_encoder.ors_f[0].b._y:=0]
+	   1247310 e.e.vtree_x.OR2_tf[0]._y : 0  [by e.e.x_enc_out.d[0].f:=1]
+	   1249875 e.e.Y_ack_confirm._y : 0  [by e.e._arb_out_y.r:=1]
+	   1250000 e.e._arb_out_y.a : 1  [by e.e.Y_ack_confirm._y:=0]
+	   1250005 e.e.Yarb.arbs[0].ack_cell1._y : 0  [by e.e._arb_out_y.a:=1]
+	   1250024 e.e._y_temp[0].a : 1  [by e.e.Yarb.arbs[0].ack_cell1._y:=0]
+	   1250197 e.e.y_ack_arb[0].buf1._y : 0  [by e.e._y_temp[0].a:=1]
+	   1277800 e.e.vtree_x.ct.in[0] : 1  [by e.e.vtree_x.OR2_tf[0]._y:=0]
+	   1277859 e.e.vtree_x.ct.b._y : 0  [by e.e.vtree_x.ct.in[0]:=1]
+	   1278700 e.e._in_x_v : 1  [by e.e.vtree_x.ct.b._y:=0]
+	   1290184 e.y[0].a : 1  [by e.e.y_ack_arb[0].buf1._y:=0]
+	   1290553 e.e.y_encoder.ors_f[0].b._y : 0  [by e.y[0].a:=1]
+	   1355853 e.e.y_enc_out.d[0].f : 1  [by e.e.y_encoder.ors_f[0].b._y:=0]
+	   1356441 e.e.vtree_y.OR2_tf[0]._y : 0  [by e.e.y_enc_out.d[0].f:=1]
+	   1356912 e.e.vtree_y.ct.in[0] : 1  [by e.e.vtree_y.OR2_tf[0]._y:=0]
+	   1357181 e.e.vtree_y.ct.b._y : 0  [by e.e.vtree_y.ct.in[0]:=1]
+	   1357582 e.e._in_y_v : 1  [by e.e.vtree_y.ct.b._y:=0]
+	   1357649 e.e._in_xy_v._y : 0  [by e.e._in_y_v:=1]
+	   1360731 e.e._in_xy_v.y : 1  [by e.e._in_xy_v._y:=0]
+	   1364009 e.e.buf_s_func.in_v_prebuf._y : 0  [by e.e._in_xy_v.y:=1]
+	   1364011 e.e.buf_s_func._in_vX : 1  [by e.e.buf_s_func.in_v_prebuf._y:=0]
+	   1365213 e.e.buf_s_func.in_v_buf_t.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   1365236 e.e.buf_s_func._in_vXX_t[0] : 1  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
+	   1382466 e.e.buf_s_func.in_v_buf_f.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   1382505 e.e.buf_s_func._in_vXX_f[0] : 1  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
+	   1392997 e.e.buf_s_func.f_buf_func[0]._y : 0  [by e.e.buf_s_func._in_vXX_f[0]:=1]
+	   1396403 e.e.buf_s_func.f_buf_func[1]._y : 0  [by e.e.buf_s_func._in_vXX_f[0]:=1]
+	   1396419 e.out.d.d[1].f : 1  [by e.e.buf_s_func.f_buf_func[1]._y:=0]
+	   1408426 e.out.d.d[0].f : 1  [by e.e.buf_s_func.f_buf_func[0]._y:=0]
+[] Check Arbiter Acks (0,0)
+[] Check Encoders
+[] Check Buffer
+[] Finish Neuron Handshake (0,0)
+	   1408426 e.x[0].r : 0
+	   1424214 e.e.Xarb.arbs[0].arbiter._y1 : 1  [by e.x[0].r:=0]
+	   1424216 e.e.Xarb.arbs[0].arbiter._y2 : 0  [by e.e.Xarb.arbs[0].arbiter._y1:=1]
+	   1424221 e.e.Xarb.arbs[0]._y1_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y1:=1]
+	   1424249 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y1_arb:=0]
+	   1437982 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
+	   1437982 e.out.a : 1
+	   1437982 e.out.v : 1
+	   1439757 e.e._x_a_B : 0  [by e.out.v:=1]
+	   1439759 e.e.X_ack_confirm._y : 1  [by e.e._x_a_B:=0]
+	   1439769 e.e._arb_out_x.a : 0  [by e.e.X_ack_confirm._y:=1]
+	   1444804 e.e.buf_s_func._out_a_B : 0  [by e.out.a:=1]
+	   1444826 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   1444842 e.e.buf_s_func._out_a_BX_t[0] : 0  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
+	   1461429 e.e._x_a : 1  [by e.e._x_a_B:=0]
+	   1462134 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   1465425 e.e.Xarb.arbs[0].ack_cell1._y : 1  [by e.e._arb_out_x.a:=0]
+	   1466607 e.e._en : 0  [by e.e._x_a:=1]
+	   1466691 e.e._x_temp[0].a : 0  [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
+	   1466692 e.e.x_ack_arb[0].buf1._y : 1  [by e.e._x_temp[0].a:=0]
+	   1466750 e.e.Xarb.arbs[0]._y2_arb : 1  [by e.e._x_temp[0].a:=0]
+	   1466777 e.e.Xarb.arbs[0].or_cell._y : 0  [by e.e.Xarb.arbs[0]._y2_arb:=1]
+	   1466793 e.x[0].a : 0  [by e.e.x_ack_arb[0].buf1._y:=1]
+	   1468582 e.e.buf_s_func.en_buf_f.buf1._y : 1  [by e.e._en:=0]
+	   1468583 e.e.buf_s_func._en_X_f[0] : 0  [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
+	   1469198 e.e.x_encoder.ors_f[0].b._y : 1  [by e.x[0].a:=0]
+	   1475110 e.e.x_enc_out.d[0].f : 0  [by e.e.x_encoder.ors_f[0].b._y:=1]
+	   1476279 e.e.buf_s_func._out_a_BX_f[0] : 0  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
+	   1477549 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].f:=0]
+	   1478015 e.e.buf_s_func.f_buf_func[0]._y : 1  [by e.e.buf_s_func._out_a_BX_f[0]:=0]
+	   1478349 e.out.d.d[0].f : 0  [by e.e.buf_s_func.f_buf_func[0]._y:=1]
+	   1484495 e.e.buf_s_func.en_buf_t.buf1._y : 1  [by e.e._en:=0]
+	   1484501 e.e.buf_s_func._en_X_t[0] : 0  [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
+	   1491868 e.e.buf_s_func.f_buf_func[1]._y : 1  [by e.e.buf_s_func._out_a_BX_f[0]:=0]
+	   1492991 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
+	   1494228 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
+	   1494305 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
+	   1494315 e.e._x_a_B : 1  [by e.e._in_x_v:=0]
+	   1494446 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
+	   1494447 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
+	   1499774 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
+	   1499775 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
+	   1499776 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   1499797 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
+	   1503641 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   1503971 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
+	   1509570 e.e._x_a : 0  [by e.e._x_a_B:=1]
+	   1519547 e.e._arb_out_x.r : 1  [by e.e.Xarb.arbs[0].or_cell._y:=0]
+	   1544566 e.out.d.d[1].f : 0  [by e.e.buf_s_func.f_buf_func[1]._y:=1]
+	   1566419 e.e.X_ack_confirm._y : 0  [by e.e._arb_out_x.r:=1]
+	   1566421 e.e._arb_out_x.a : 1  [by e.e.X_ack_confirm._y:=0]
+	   1575291 e.e.Xarb.arbs[0].ack_cell2._y : 0  [by e.e._arb_out_x.a:=1]
+	   1575474 e.e._x_temp[1].a : 1  [by e.e.Xarb.arbs[0].ack_cell2._y:=0]
+	   1604634 e.e.x_ack_arb[1].buf1._y : 0  [by e.e._x_temp[1].a:=1]
+	   1617744 e.x[1].a : 1  [by e.e.x_ack_arb[1].buf1._y:=0]
+	   1617856 e.e.x_encoder.ors_t[0].b._y : 0  [by e.x[1].a:=1]
+	   1649639 e.e.x_enc_out.d[0].t : 1  [by e.e.x_encoder.ors_t[0].b._y:=0]
+	   1649711 e.e.vtree_x.OR2_tf[0]._y : 0  [by e.e.x_enc_out.d[0].t:=1]
+	   1650819 e.e.vtree_x.ct.in[0] : 1  [by e.e.vtree_x.OR2_tf[0]._y:=0]
+	   1674016 e.e.vtree_x.ct.b._y : 0  [by e.e.vtree_x.ct.in[0]:=1]
+	   1674020 e.e._in_x_v : 1  [by e.e.vtree_x.ct.b._y:=0]
+	   1674419 e.e._in_xy_v._y : 0  [by e.e._in_x_v:=1]
+	   1674462 e.e._in_xy_v.y : 1  [by e.e._in_xy_v._y:=0]
+	   1688288 e.e.buf_s_func.in_v_prebuf._y : 0  [by e.e._in_xy_v.y:=1]
+	   1688289 e.e.buf_s_func._in_vX : 1  [by e.e.buf_s_func.in_v_prebuf._y:=0]
+	   1688308 e.e.buf_s_func.in_v_buf_t.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   1696423 e.e.buf_s_func.in_v_buf_f.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   1701517 e.e.buf_s_func._in_vXX_t[0] : 1  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
+	   1711988 e.e.buf_s_func._in_vXX_f[0] : 1  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
+	   1711988 e.out.a : 0
+	   1711988 e.out.v : 0
+	   1712363 e.e._en : 1  [by e.out.v:=0]
+	   1712389 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
+	   1712390 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   1712471 e.e.buf_s_func.en_buf_t.buf1._y : 0  [by e.e._en:=1]
+	   1712697 e.e.buf_s_func.en_buf_f.buf1._y : 0  [by e.e._en:=1]
+	   1712722 e.e.buf_s_func._en_X_t[0] : 1  [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
+	   1712856 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   1712875 e.e.buf_s_func._en_X_f[0] : 1  [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
+	   1713798 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
+	   1713799 e.e.buf_s_func.t_buf_func[0]._y : 0  [by e.e.buf_s_func._out_a_BX_t[0]:=1]
+	   1713800 e.out.d.d[0].t : 1  [by e.e.buf_s_func.t_buf_func[0]._y:=0]
+	   1717122 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
+	   1717342 e.e.buf_s_func.f_buf_func[1]._y : 0  [by e.e.buf_s_func._out_a_BX_f[0]:=1]
+	   1717905 e.out.d.d[1].f : 1  [by e.e.buf_s_func.f_buf_func[1]._y:=0]
+[] Neuron (0,0) Encoded
+[] Check Neuron (1,0) Waiting
+[] Check Arbiter Acks (1,0)
+[] Check Encoders
+[] Check Buffer
+[] Finish Neuron Handshake (1,0)
+	   1717905 e.x[1].r : 0
+	   1717905 e.y[0].r : 0
+	   1717983 e.e.x_req_ortree.or2s[0]._y : 1  [by e.x[1].r:=0]
+	   1718134 e.e._x_v : 0  [by e.e.x_req_ortree.or2s[0]._y:=1]
+	   1718234 e.e.Xarb.arbs[0].arbiter._y2 : 1  [by e.x[1].r:=0]
+	   1718235 e.e.Xarb.arbs[0]._y2_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y2:=1]
+	   1718236 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y2_arb:=0]
+	   1723161 e.e.Yarb.arbs[0].arbiter._y1 : 1  [by e.y[0].r:=0]
+	   1723189 e.e.Yarb.arbs[0]._y1_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y1:=1]
+	   1723190 e.e.Yarb.arbs[0].or_cell._y : 1  [by e.e.Yarb.arbs[0]._y1_arb:=0]
+	   1723463 e.e._arb_out_y.r : 0  [by e.e.Yarb.arbs[0].or_cell._y:=1]
+	   1726003 e.e._x_v_B : 1  [by e.e._x_v:=0]
+	   1727849 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
+	   1727849 e.out.a : 1
+	   1727849 e.out.v : 1
+	   1727851 e.e._x_a_B : 0  [by e.out.v:=1]
+	   1727852 e.e.X_ack_confirm._y : 1  [by e.e._x_a_B:=0]
+	   1727857 e.e._arb_out_x.a : 0  [by e.e.X_ack_confirm._y:=1]
+	   1727871 e.e.buf_s_func._out_a_B : 0  [by e.out.a:=1]
+	   1727872 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   1728191 e.e.Xarb.arbs[0].ack_cell2._y : 1  [by e.e._arb_out_x.a:=0]
+	   1728581 e.e._x_temp[1].a : 0  [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
+	   1728782 e.e.x_ack_arb[1].buf1._y : 1  [by e.e._x_temp[1].a:=0]
+	   1729056 e.x[1].a : 0  [by e.e.x_ack_arb[1].buf1._y:=1]
+	   1729082 e.e.x_encoder.ors_t[0].b._y : 1  [by e.x[1].a:=0]
+	   1729178 e.e.x_enc_out.d[0].t : 0  [by e.e.x_encoder.ors_t[0].b._y:=1]
+	   1729222 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].t:=0]
+	   1729669 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   1740651 e.e.buf_s_func._out_a_BX_f[0] : 0  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
+	   1743927 e.e.buf_s_func._out_a_BX_t[0] : 0  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
+	   1744997 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
+	   1744999 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
+	   1745006 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
+	   1745115 e.e.Y_ack_confirm._y : 1  [by e.e._in_x_v:=0]
+	   1745478 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
+	   1745490 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
+	   1747869 e.e._arb_out_y.a : 0  [by e.e.Y_ack_confirm._y:=1]
+	   1747896 e.e.Yarb.arbs[0].ack_cell1._y : 1  [by e.e._arb_out_y.a:=0]
+	   1748176 e.e._y_temp[0].a : 0  [by e.e.Yarb.arbs[0].ack_cell1._y:=1]
+	   1748177 e.e.y_ack_arb[0].buf1._y : 1  [by e.e._y_temp[0].a:=0]
+	   1748212 e.y[0].a : 0  [by e.e.y_ack_arb[0].buf1._y:=1]
+	   1748676 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
+	   1781936 e.e._x_a : 1  [by e.e._x_a_B:=0]
+	   1784614 e.e._en : 0  [by e.e._x_a:=1]
+	   1784697 e.e.buf_s_func.en_buf_f.buf1._y : 1  [by e.e._en:=0]
+	   1784698 e.e.buf_s_func._en_X_f[0] : 0  [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
+	   1787131 e.e.buf_s_func.f_buf_func[1]._y : 1  [by e.e.buf_s_func._en_X_f[0]:=0]
+	   1788425 e.out.d.d[1].f : 0  [by e.e.buf_s_func.f_buf_func[1]._y:=1]
+	   1810223 e.e.buf_s_func.en_buf_t.buf1._y : 1  [by e.e._en:=0]
+	   1812632 e.e.y_encoder.ors_f[0].b._y : 1  [by e.y[0].a:=0]
+	   1813810 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
+	   1814058 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   1818030 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   1818085 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
+	   1821686 e.e.y_enc_out.d[0].f : 0  [by e.e.y_encoder.ors_f[0].b._y:=1]
+	   1821864 e.e.vtree_y.OR2_tf[0]._y : 1  [by e.e.y_enc_out.d[0].f:=0]
+	   1821872 e.e.vtree_y.ct.in[0] : 0  [by e.e.vtree_y.OR2_tf[0]._y:=1]
+	   1821905 e.e.vtree_y.ct.b._y : 1  [by e.e.vtree_y.ct.in[0]:=0]
+	   1823077 e.e._in_y_v : 0  [by e.e.vtree_y.ct.b._y:=1]
+	   1823101 e.e._x_a_B : 1  [by e.e._in_y_v:=0]
+	   1839904 e.e._x_a : 0  [by e.e._x_a_B:=1]
+	   1852952 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
+	   1855655 e.e.buf_s_func._en_X_t[0] : 0  [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
+	   1855985 e.e.buf_s_func.t_buf_func[0]._y : 1  [by e.e.buf_s_func._en_X_t[0]:=0]
+	   1856043 e.out.d.d[0].t : 0  [by e.e.buf_s_func.t_buf_func[0]._y:=1]
+	   1856043 e.out.a : 0
+	   1856043 e.out.v : 0
+	   1856055 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
+	   1856063 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   1856196 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
+	   1858380 e.e._en : 1  [by e.out.v:=0]
+	   1858381 e.e.buf_s_func.en_buf_t.buf1._y : 0  [by e.e._en:=1]
+	   1858386 e.e.buf_s_func._en_X_t[0] : 1  [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
+	   1861414 e.e.buf_s_func.en_buf_f.buf1._y : 0  [by e.e._en:=1]
+	   1861808 e.e.buf_s_func._en_X_f[0] : 1  [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
+	   1920867 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   1923663 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
+[] Neuron (1,0) Encoded
+[] Neuron Spikes (1,0), (0,1)
+	   1923663 e.x[1].r : 1
+	   1923663 e.y[1].r : 1
+	   1923663 e.x[0].r : 1
+	   1923663 e.y[0].r : 1
+	   1923678 e.e.Xarb.arbs[0].arbiter._y2 : 0  [by e.x[1].r:=1]
+	   1923689 e.e.Xarb.arbs[0]._y2_arb : 1  [by e.e.Xarb.arbs[0].arbiter._y2:=0]
+	   1923963 e.e.Xarb.arbs[0].or_cell._y : 0  [by e.e.Xarb.arbs[0]._y2_arb:=1]
+	   1924013 e.e._arb_out_x.r : 1  [by e.e.Xarb.arbs[0].or_cell._y:=0]
+	   1925427 e.e.Yarb.arbs[0].arbiter._y2 : 0  [by e.y[1].r:=1]
+	   1925428 e.e.Yarb.arbs[0]._y2_arb : 1  [by e.e.Yarb.arbs[0].arbiter._y2:=0]
+	   1927376 e.e.X_ack_confirm._y : 0  [by e.e._arb_out_x.r:=1]
+	   1927379 e.e._arb_out_x.a : 1  [by e.e.X_ack_confirm._y:=0]
+	   1927788 e.e.x_req_ortree.or2s[0]._y : 0  [by e.x[1].r:=1]
+	   1928039 e.e.Xarb.arbs[0].ack_cell2._y : 0  [by e.e._arb_out_x.a:=1]
+	   1928422 e.e._x_v : 1  [by e.e.x_req_ortree.or2s[0]._y:=0]
+	   1928429 e.e._x_v_B : 0  [by e.e._x_v:=1]
+	   1955687 e.e._x_temp[1].a : 1  [by e.e.Xarb.arbs[0].ack_cell2._y:=0]
+	   1970275 e.e.x_ack_arb[1].buf1._y : 0  [by e.e._x_temp[1].a:=1]
+	   1970305 e.x[1].a : 1  [by e.e.x_ack_arb[1].buf1._y:=0]
+	   1971382 e.e.Yarb.arbs[0].or_cell._y : 0  [by e.e.Yarb.arbs[0]._y2_arb:=1]
+	   1975226 e.e._arb_out_y.r : 1  [by e.e.Yarb.arbs[0].or_cell._y:=0]
+	   1975341 e.e.Y_ack_confirm._y : 0  [by e.e._arb_out_y.r:=1]
+	   1975348 e.e._arb_out_y.a : 1  [by e.e.Y_ack_confirm._y:=0]
+	   1978383 e.e.x_encoder.ors_t[0].b._y : 0  [by e.x[1].a:=1]
+	   1979045 e.e.x_enc_out.d[0].t : 1  [by e.e.x_encoder.ors_t[0].b._y:=0]
+	   1979064 e.e.vtree_x.OR2_tf[0]._y : 0  [by e.e.x_enc_out.d[0].t:=1]
+	   1979065 e.e.vtree_x.ct.in[0] : 1  [by e.e.vtree_x.OR2_tf[0]._y:=0]
+	   1979389 e.e.vtree_x.ct.b._y : 0  [by e.e.vtree_x.ct.in[0]:=1]
+	   1979466 e.e._in_x_v : 1  [by e.e.vtree_x.ct.b._y:=0]
+	   2001633 e.e.Yarb.arbs[0].ack_cell2._y : 0  [by e.e._arb_out_y.a:=1]
+	   2011174 e.e._y_temp[1].a : 1  [by e.e.Yarb.arbs[0].ack_cell2._y:=0]
+	   2038849 e.e.y_ack_arb[1].buf1._y : 0  [by e.e._y_temp[1].a:=1]
+	   2040377 e.y[1].a : 1  [by e.e.y_ack_arb[1].buf1._y:=0]
+	   2045980 e.e.y_encoder.ors_t[0].b._y : 0  [by e.y[1].a:=1]
+	   2046044 e.e.y_enc_out.d[0].t : 1  [by e.e.y_encoder.ors_t[0].b._y:=0]
+	   2046053 e.e.vtree_y.OR2_tf[0]._y : 0  [by e.e.y_enc_out.d[0].t:=1]
+	   2107723 e.e.vtree_y.ct.in[0] : 1  [by e.e.vtree_y.OR2_tf[0]._y:=0]
+	   2130322 e.e.vtree_y.ct.b._y : 0  [by e.e.vtree_y.ct.in[0]:=1]
+	   2131361 e.e._in_y_v : 1  [by e.e.vtree_y.ct.b._y:=0]
+	   2131369 e.e._in_xy_v._y : 0  [by e.e._in_y_v:=1]
+	   2139656 e.e._in_xy_v.y : 1  [by e.e._in_xy_v._y:=0]
+	   2139748 e.e.buf_s_func.in_v_prebuf._y : 0  [by e.e._in_xy_v.y:=1]
+	   2139784 e.e.buf_s_func._in_vX : 1  [by e.e.buf_s_func.in_v_prebuf._y:=0]
+	   2139819 e.e.buf_s_func.in_v_buf_f.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   2139841 e.e.buf_s_func.in_v_buf_t.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   2140109 e.e.buf_s_func._in_vXX_f[0] : 1  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
+	   2140812 e.e.buf_s_func._in_vXX_t[0] : 1  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
+	   2140855 e.e.buf_s_func.t_buf_func[1]._y : 0  [by e.e.buf_s_func._in_vXX_t[0]:=1]
+	   2148253 e.e.buf_s_func.t_buf_func[0]._y : 0  [by e.e.buf_s_func._in_vXX_t[0]:=1]
+	   2148268 e.out.d.d[0].t : 1  [by e.e.buf_s_func.t_buf_func[0]._y:=0]
+	   2157991 e.out.d.d[1].t : 1  [by e.e.buf_s_func.t_buf_func[1]._y:=0]
+[] Check Arbiter Acks (1,0)
+[] Check Encoders
+[] Check Buffer
+[] Finish Neuron Handshake (1,0)
+	   2157991 e.x[1].r : 0
+	   2157991 e.y[0].r : 0
+	   2160804 e.e.Xarb.arbs[0].arbiter._y2 : 1  [by e.x[1].r:=0]
+	   2161176 e.e.Xarb.arbs[0].arbiter._y1 : 0  [by e.e.Xarb.arbs[0].arbiter._y2:=1]
+	   2164956 e.e.Xarb.arbs[0]._y2_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y2:=1]
+	   2165027 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y2_arb:=0]
+	   2174083 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
+	   2174083 e.out.a : 1
+	   2174083 e.out.v : 1
+	   2180951 e.e._x_a_B : 0  [by e.out.v:=1]
+	   2180952 e.e.X_ack_confirm._y : 1  [by e.e._x_a_B:=0]
+	   2181021 e.e._arb_out_x.a : 0  [by e.e.X_ack_confirm._y:=1]
+	   2181040 e.e.Xarb.arbs[0].ack_cell2._y : 1  [by e.e._arb_out_x.a:=0]
+	   2187170 e.e.buf_s_func._out_a_B : 0  [by e.out.a:=1]
+	   2188142 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   2188242 e.e.buf_s_func._out_a_BX_f[0] : 0  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
+	   2192682 e.e._x_a : 1  [by e.e._x_a_B:=0]
+	   2199026 e.e._x_temp[1].a : 0  [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
+	   2199027 e.e.x_ack_arb[1].buf1._y : 1  [by e.e._x_temp[1].a:=0]
+	   2199100 e.e.Xarb.arbs[0]._y1_arb : 1  [by e.e._x_temp[1].a:=0]
+	   2199110 e.e.Xarb.arbs[0].or_cell._y : 0  [by e.e.Xarb.arbs[0]._y1_arb:=1]
+	   2199123 e.e._arb_out_x.r : 1  [by e.e.Xarb.arbs[0].or_cell._y:=0]
+	   2199143 e.x[1].a : 0  [by e.e.x_ack_arb[1].buf1._y:=1]
+	   2199598 e.e.x_encoder.ors_t[0].b._y : 1  [by e.x[1].a:=0]
+	   2207940 e.e.x_enc_out.d[0].t : 0  [by e.e.x_encoder.ors_t[0].b._y:=1]
+	   2208247 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].t:=0]
+	   2209490 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
+	   2214908 e.e._en : 0  [by e.e._x_a:=1]
+	   2214960 e.e.buf_s_func.en_buf_f.buf1._y : 1  [by e.e._en:=0]
+	   2214965 e.e.buf_s_func._en_X_f[0] : 0  [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
+	   2217525 e.e.buf_s_func.en_buf_t.buf1._y : 1  [by e.e._en:=0]
+	   2218603 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
+	   2218623 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
+	   2218675 e.e._x_a_B : 1  [by e.e._in_x_v:=0]
+	   2218918 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
+	   2219146 e.e.X_ack_confirm._y : 0  [by e.e._x_a_B:=1]
+	   2220500 e.e._arb_out_x.a : 1  [by e.e.X_ack_confirm._y:=0]
+	   2222037 e.e.Xarb.arbs[0].ack_cell1._y : 0  [by e.e._arb_out_x.a:=1]
+	   2222361 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
+	   2222362 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
+	   2222415 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
+	   2224088 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   2224090 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
+	   2225272 e.e.buf_s_func._en_X_t[0] : 0  [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
+	   2230095 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   2230125 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
+	   2231524 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   2231821 e.e.buf_s_func._out_a_BX_t[0] : 0  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
+	   2233455 e.e._x_temp[0].a : 1  [by e.e.Xarb.arbs[0].ack_cell1._y:=0]
+	   2233698 e.e.x_ack_arb[0].buf1._y : 0  [by e.e._x_temp[0].a:=1]
+	   2236810 e.x[0].a : 1  [by e.e.x_ack_arb[0].buf1._y:=0]
+	   2237371 e.e.x_encoder.ors_f[0].b._y : 0  [by e.x[0].a:=1]
+	   2237384 e.e.x_enc_out.d[0].f : 1  [by e.e.x_encoder.ors_f[0].b._y:=0]
+	   2239108 e.e.buf_s_func.t_buf_func[1]._y : 1  [by e.e.buf_s_func._out_a_BX_t[0]:=0]
+	   2239109 e.out.d.d[1].t : 0  [by e.e.buf_s_func.t_buf_func[1]._y:=1]
+	   2257408 e.e.buf_s_func.t_buf_func[0]._y : 1  [by e.e.buf_s_func._out_a_BX_t[0]:=0]
+	   2265227 e.out.d.d[0].t : 0  [by e.e.buf_s_func.t_buf_func[0]._y:=1]
+	   2265638 e.e.vtree_x.OR2_tf[0]._y : 0  [by e.e.x_enc_out.d[0].f:=1]
+	   2265687 e.e.vtree_x.ct.in[0] : 1  [by e.e.vtree_x.OR2_tf[0]._y:=0]
+	   2276185 e.e.vtree_x.ct.b._y : 0  [by e.e.vtree_x.ct.in[0]:=1]
+	   2276891 e.e._x_a : 0  [by e.e._x_a_B:=1]
+	   2287272 e.e._in_x_v : 1  [by e.e.vtree_x.ct.b._y:=0]
+	   2287425 e.e._in_xy_v._y : 0  [by e.e._in_x_v:=1]
+	   2287487 e.e._in_xy_v.y : 1  [by e.e._in_xy_v._y:=0]
+	   2287489 e.e.buf_s_func.in_v_prebuf._y : 0  [by e.e._in_xy_v.y:=1]
+	   2288204 e.e.buf_s_func._in_vX : 1  [by e.e.buf_s_func.in_v_prebuf._y:=0]
+	   2288235 e.e.buf_s_func.in_v_buf_f.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   2288285 e.e.buf_s_func._in_vXX_f[0] : 1  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
+	   2305580 e.e.buf_s_func.in_v_buf_t.buf1._y : 0  [by e.e.buf_s_func._in_vX:=1]
+	   2305616 e.e.buf_s_func._in_vXX_t[0] : 1  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
+	   2305616 e.out.a : 0
+	   2305616 e.out.v : 0
+	   2305622 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
+	   2305626 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   2305654 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
+	   2305784 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   2307525 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
+	   2318778 e.e._en : 1  [by e.out.v:=0]
+	   2318779 e.e.buf_s_func.en_buf_t.buf1._y : 0  [by e.e._en:=1]
+	   2318828 e.e.buf_s_func._en_X_t[0] : 1  [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
+	   2332495 e.e.buf_s_func.en_buf_f.buf1._y : 0  [by e.e._en:=1]
+	   2332518 e.e.buf_s_func._en_X_f[0] : 1  [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
+	   2332604 e.e.buf_s_func.f_buf_func[0]._y : 0  [by e.e.buf_s_func._en_X_f[0]:=1]
+	   2332614 e.out.d.d[0].f : 1  [by e.e.buf_s_func.f_buf_func[0]._y:=0]
+	   2383473 e.e.buf_s_func.t_buf_func[1]._y : 0  [by e.e.buf_s_func._en_X_t[0]:=1]
+	   2384067 e.out.d.d[1].t : 1  [by e.e.buf_s_func.t_buf_func[1]._y:=0]
+[] Neuron (1,0) Encoded
+[] Check Neuron (0,1) Waiting
+[] Check Arbiter Acks (0,1)
+[] Check Encoders
+[] Check Buffer
+[] Finish Neuron Handshake (1,0)
+	   2384067 e.x[0].r : 0
+	   2384067 e.y[1].r : 0
+	   2384070 e.e.Xarb.arbs[0].arbiter._y1 : 1  [by e.x[0].r:=0]
+	   2384081 e.e.Xarb.arbs[0]._y1_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y1:=1]
+	   2387687 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y1_arb:=0]
+	   2388990 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
+	   2391381 e.e.x_req_ortree.or2s[0]._y : 1  [by e.x[0].r:=0]
+	   2399331 e.e._x_v : 0  [by e.e.x_req_ortree.or2s[0]._y:=1]
+	   2399837 e.e._x_v_B : 1  [by e.e._x_v:=0]
+	   2434772 e.e.Yarb.arbs[0].arbiter._y2 : 1  [by e.y[1].r:=0]
+	   2434773 e.e.Yarb.arbs[0]._y2_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y2:=1]
+	   2434775 e.e.Yarb.arbs[0].or_cell._y : 1  [by e.e.Yarb.arbs[0]._y2_arb:=0]
+	   2434776 e.e._arb_out_y.r : 0  [by e.e.Yarb.arbs[0].or_cell._y:=1]
+	   2434776 e.out.a : 1
+	   2434776 e.out.v : 1
+	   2434791 e.e._x_a_B : 0  [by e.out.v:=1]
+	   2434838 e.e._x_a : 1  [by e.e._x_a_B:=0]
+	   2435200 e.e.X_ack_confirm._y : 1  [by e.e._x_a_B:=0]
+	   2435247 e.e._en : 0  [by e.e._x_a:=1]
+	   2435275 e.e.buf_s_func.en_buf_f.buf1._y : 1  [by e.e._en:=0]
+	   2435397 e.e.buf_s_func._en_X_f[0] : 0  [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
+	   2436697 e.e._arb_out_x.a : 0  [by e.e.X_ack_confirm._y:=1]
+	   2436732 e.e.Xarb.arbs[0].ack_cell1._y : 1  [by e.e._arb_out_x.a:=0]
+	   2437302 e.e.buf_s_func.en_buf_t.buf1._y : 1  [by e.e._en:=0]
+	   2437305 e.e.buf_s_func._en_X_t[0] : 0  [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
+	   2437424 e.e._x_temp[0].a : 0  [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
+	   2437591 e.e.x_ack_arb[0].buf1._y : 1  [by e.e._x_temp[0].a:=0]
+	   2437592 e.x[0].a : 0  [by e.e.x_ack_arb[0].buf1._y:=1]
+	   2438672 e.e.x_encoder.ors_f[0].b._y : 1  [by e.x[0].a:=0]
+	   2439331 e.e.x_enc_out.d[0].f : 0  [by e.e.x_encoder.ors_f[0].b._y:=1]
+	   2439346 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].f:=0]
+	   2439614 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
+	   2441871 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
+	   2441872 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
+	   2441873 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
+	   2441875 e.e.Y_ack_confirm._y : 1  [by e.e._in_x_v:=0]
+	   2441876 e.e._arb_out_y.a : 0  [by e.e.Y_ack_confirm._y:=1]
+	   2441885 e.e.Yarb.arbs[0].ack_cell2._y : 1  [by e.e._arb_out_y.a:=0]
+	   2441905 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
+	   2442491 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
+	   2444195 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
+	   2444204 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   2444205 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
+	   2445044 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
+	   2445683 e.e._y_temp[1].a : 0  [by e.e.Yarb.arbs[0].ack_cell2._y:=1]
+	   2446299 e.e.y_ack_arb[1].buf1._y : 1  [by e.e._y_temp[1].a:=0]
+	   2454986 e.e.buf_s_func._out_a_B : 0  [by e.out.a:=1]
+	   2455310 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   2455311 e.e.buf_s_func._out_a_BX_f[0] : 0  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
+	   2456060 e.e.buf_s_func.f_buf_func[0]._y : 1  [by e.e.buf_s_func._out_a_BX_f[0]:=0]
+	   2457691 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1  [by e.e.buf_s_func._out_a_B:=0]
+	   2458138 e.e.buf_s_func._out_a_BX_t[0] : 0  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
+	   2458139 e.e.buf_s_func.t_buf_func[1]._y : 1  [by e.e.buf_s_func._out_a_BX_t[0]:=0]
+	   2458280 e.out.d.d[1].t : 0  [by e.e.buf_s_func.t_buf_func[1]._y:=1]
+	   2460246 e.out.d.d[0].f : 0  [by e.e.buf_s_func.f_buf_func[0]._y:=1]
+	   2461163 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
+	   2466090 e.y[1].a : 0  [by e.e.y_ack_arb[1].buf1._y:=1]
+	   2507916 e.e.y_encoder.ors_t[0].b._y : 1  [by e.y[1].a:=0]
+	   2508120 e.e.y_enc_out.d[0].t : 0  [by e.e.y_encoder.ors_t[0].b._y:=1]
+	   2508171 e.e.vtree_y.OR2_tf[0]._y : 1  [by e.e.y_enc_out.d[0].t:=0]
+	   2508611 e.e.vtree_y.ct.in[0] : 0  [by e.e.vtree_y.OR2_tf[0]._y:=1]
+	   2536780 e.e.vtree_y.ct.b._y : 1  [by e.e.vtree_y.ct.in[0]:=0]
+	   2536964 e.e._in_y_v : 0  [by e.e.vtree_y.ct.b._y:=1]
+	   2540299 e.e._x_a_B : 1  [by e.e._in_y_v:=0]
+	   2540343 e.e._x_a : 0  [by e.e._x_a_B:=1]
+	   2540343 e.out.a : 0
+	   2540343 e.out.v : 0
+	   2540344 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
+	   2541410 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   2541422 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
+	   2542137 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
+	   2543304 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
+	   2543348 e.e._en : 1  [by e.out.v:=0]
+	   2544188 e.e.buf_s_func.en_buf_t.buf1._y : 0  [by e.e._en:=1]
+	   2545169 e.e.buf_s_func._en_X_t[0] : 1  [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
+	   2553279 e.e.buf_s_func.en_buf_f.buf1._y : 0  [by e.e._en:=1]
+	   2603344 e.e.buf_s_func._en_X_f[0] : 1  [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
+[] Neuron (1,0) Encoded

test/unit_tests/encoder2D_2x2/run/test.prs

@@ -238,7 +238,7 @@ mk_excllo("e.e.Xarb.arbs[0].arbiter._y1","e.e.Xarb.arbs[0].arbiter._y2")
 = "e.e.vtree_y.in.d[0].d[1]" "e.e.vtree_y.in.d[0].t"
 = "e.e._in_y_v" "e.e._in_xy_v.b"
 = "e.e._in_y_v" "e.e.vtree_y.out"
-= "e.e._in_y_v" "e.e.x_ack.p4"
+= "e.e._in_y_v" "e.e.x_ack.p2"
 = "e.e._arb_out_x.d.d[0]" "e.e._arb_out_x.r"
 = "e.e._arb_out_x.r" "e.e.Xarb.out.r"
 = "e.e._arb_out_x.a" "e.e.Xarb.out.a"
@@ -264,7 +264,7 @@ mk_excllo("e.e.Xarb.arbs[0].arbiter._y1","e.e.Xarb.arbs[0].arbiter._y2")
 = "e.e.x_ack_arb[1].supply.vss" "e.e.x_ack_arb[1].buf1.vss"
 = "e.e.x_ack_arb[1].out" "e.e.x_ack_arb[1].buf1.y"
 = "e.e.x_ack_arb[1].in" "e.e.x_ack_arb[1].buf1.a"
-= "e.e._x_v_B" "e.e.x_ack.p2"
+= "e.e._x_v_B" "e.e.x_ack.p5"
 = "e.e._x_v_B" "e.e.not_x_req_ortree.y"
 "e.e.x_req_ortree.or2s[0].a"|"e.e.x_req_ortree.or2s[0].b"->"e.e.x_req_ortree.or2s[0]._y"-
 ~("e.e.x_req_ortree.or2s[0].a"|"e.e.x_req_ortree.or2s[0].b")->"e.e.x_req_ortree.or2s[0]._y"+
@@ -301,7 +301,7 @@ mk_excllo("e.e.Xarb.arbs[0].arbiter._y1","e.e.Xarb.arbs[0].arbiter._y2")
 = "e.e._reset_BXX[0]" "e.e._reset_BXX[3]"
 = "e.e._reset_BXX[0]" "e.e._reset_BXX[2]"
 = "e.e._reset_BXX[0]" "e.e._reset_BXX[1]"
-= "e.e._x_v" "e.e.x_ack.p5"
+= "e.e._x_v" "e.e.x_ack.p3"
 = "e.e._x_v" "e.e.not_x_req_ortree.a"
 = "e.e._x_v" "e.e.x_req_ortree.out"
 = "e.e._x_v" "e.e.Y_ack_confirm.p1"
@@ -597,8 +597,8 @@ mk_excllo("e.e.Xarb.arbs[0].arbiter._y1","e.e.Xarb.arbs[0].arbiter._y2")
 = "e.e._in_x_v" "e.e._in_xy_v.a"
 = "e.e._in_x_v" "e.e.vtree_x.out"
 = "e.e._in_x_v" "e.e.x_ack.n2"
-= "e.e._in_x_v" "e.e.x_ack.p3"
 = "e.e._in_x_v" "e.e.x_ack.p1"
+= "e.e._in_x_v" "e.e.x_ack.p4"
 = "e.e._in_x_v" "e.e.Y_ack_confirm.p2"
 = "e.e.out.d.d[0].d[0]" "e.e.out.d.d[0].f"
 = "e.e.out.d.d[0].d[1]" "e.e.out.d.d[0].t"

test/unit_tests/encoder2D_2x2/test.prsim

@@ -0,0 +1,377 @@
+watchall
+mode run
+
+system "echo '[] Set Out Ack/Valid Low'"
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Setting Neuron Req Low'"
+
+set e.y[0].r 0
+set e.y[1].r 0
+
+set e.x[0].r 0
+set e.x[1].r 0
+cycle
+
+# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
+# # status X
+# # set Reset 1
+# # cycle
+
+cycle 
+set Reset 0
+cycle
+
+system "echo '[] Single Neuron Spikes (0,0)'"
+
+set e.y[0].r 1
+set e.x[0].r 1
+
+cycle
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+
+assert e.e._x_v 1
+
+system "echo '[] Check Arbiter Acks'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 1
+assert e.y[1].a 0
+assert e.e.Yarb.out.a 1
+assert e.x[0].a 1
+assert e.x[1].a 0
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.y_enc_out.d[0].t 0
+assert e.e.y_enc_out.d[0].f 1
+
+assert e.e.x_enc_out.d[0].t 0
+assert e.e.x_enc_out.d[0].f 1
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 0
+assert e.out.d.d[0].f 1
+assert e.out.d.d[1].t 0
+assert e.out.d.d[1].f 1
+
+system "echo '[] Finish Neuron Handshake'"
+
+set e.y[0].r 0
+set e.x[0].r 0
+cycle
+
+assert e.e.Yarb.out.r 0
+assert e.e.Xarb.out.r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+assert e.e.Yarb.out.a 0
+assert e.e.Xarb.out.a 0
+assert e.y[0].a 0
+assert e.x[0].a 0
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (0,0) Encoded'"
+
+system "echo '[] Single Neuron Spikes (1,1)'"
+
+set e.y[1].r 1
+set e.x[1].r 1
+cycle
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+
+system "echo '[] Check Arbiter Acks'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 0
+assert e.y[1].a 1
+assert e.e.Yarb.out.a 1
+assert e.x[0].a 0
+assert e.x[1].a 1
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.y_enc_out.d[0].t 1
+assert e.e.y_enc_out.d[0].f 0
+
+assert e.e.x_enc_out.d[0].t 1
+assert e.e.x_enc_out.d[0].f 0
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 1
+assert e.out.d.d[0].f 0
+assert e.out.d.d[1].t 1
+assert e.out.d.d[1].f 0
+
+system "echo '[] Finish Neuron Handshake'"
+
+set e.y[1].r 0
+set e.x[1].r 0
+cycle
+
+assert e.e.Yarb.out.r 0
+assert e.e.Xarb.out.r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+assert e.e.Yarb.out.a 0
+assert e.e.Xarb.out.a 0
+assert e.y[1].a 0
+assert e.x[1].a 0
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (1,1) Encoded'"
+
+system "echo '[] Neuron Spikes (0,0), (1,0)'"
+
+set e.x[0].r 1
+set e.y[0].r 1
+set e.x[1].r 1
+cycle
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+
+system "echo '[] Check Arbiter Acks (0,0)'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 1
+assert e.y[1].a 0
+assert e.e.Yarb.out.a 1
+assert e.x[0].a 1
+assert e.x[1].a 0
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.y_enc_out.d[0].t 0
+assert e.e.y_enc_out.d[0].f 1
+
+assert e.e.x_enc_out.d[0].t 0
+assert e.e.x_enc_out.d[0].f 1
+
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 0
+assert e.out.d.d[0].f 1
+assert e.out.d.d[1].t 0
+assert e.out.d.d[1].f 1
+
+system "echo '[] Finish Neuron Handshake (0,0)'"
+
+set e.x[0].r 0
+cycle
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (0,0) Encoded'"
+
+system "echo '[] Check Neuron (1,0) Waiting'"
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+
+system "echo '[] Check Arbiter Acks (1,0)'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 1
+assert e.y[1].a 0
+assert e.e.Yarb.out.a 1
+assert e.x[0].a 0
+assert e.x[1].a 1
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.y_enc_out.d[0].t 0
+assert e.e.y_enc_out.d[0].f 1
+
+assert e.e.x_enc_out.d[0].t 1
+assert e.e.x_enc_out.d[0].f 0
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 1
+assert e.out.d.d[0].f 0
+assert e.out.d.d[1].t 0
+assert e.out.d.d[1].f 1
+
+
+system "echo '[] Finish Neuron Handshake (1,0)'"
+
+set e.x[1].r 0
+set e.y[0].r 0
+cycle
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (1,0) Encoded'"
+
+system "echo '[] Neuron Spikes (1,0), (0,1)'"
+
+set e.x[1].r 1
+set e.y[0].r 1
+
+set e.x[0].r 1
+set e.y[1].r 1
+cycle
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+
+system "echo '[] Check Arbiter Acks (1,0)'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 0
+assert e.y[1].a 1
+assert e.e.Yarb.out.a 1
+assert e.x[0].a 0
+assert e.x[1].a 1
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.y_enc_out.d[0].t 1
+assert e.e.y_enc_out.d[0].f 0
+
+assert e.e.x_enc_out.d[0].t 1
+assert e.e.x_enc_out.d[0].f 0
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 1
+assert e.out.d.d[0].f 0
+assert e.out.d.d[1].t 1
+assert e.out.d.d[1].f 0
+
+system "echo '[] Finish Neuron Handshake (1,0)'"
+
+set e.x[1].r 0
+set e.y[0].r 0
+cycle
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (1,0) Encoded'"
+
+system "echo '[] Check Neuron (0,1) Waiting'"
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+
+
+system "echo '[] Check Arbiter Acks (0,1)'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 0
+assert e.y[1].a 1
+assert e.e.Yarb.out.a 1
+assert e.x[0].a 1
+assert e.x[1].a 0
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.y_enc_out.d[0].t 1
+assert e.e.y_enc_out.d[0].f 0
+
+assert e.e.x_enc_out.d[0].t 0
+assert e.e.x_enc_out.d[0].f 1
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 0
+assert e.out.d.d[0].f 1
+assert e.out.d.d[1].t 1
+assert e.out.d.d[1].f 0
+
+system "echo '[] Finish Neuron Handshake (1,0)'"
+
+set e.x[0].r 0
+set e.y[1].r 0
+cycle
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+assert e.e._in_x_v 0
+assert e.e._in_y_v 0
+assert e.e._x_v 0
+
+system "echo '[] Neuron (1,0) Encoded'"

test/unit_tests/encoder2D_7/run/prsim.out

@@ -1,143 +0,0 @@
-e.y[0].r e.e.Yarb.arbs[0].or_cell._y e.e.x_ack_arb[0].buf1._y e.e.vtree_x.OR2_tf[0]._y e.e.buf_s_func._in_vX e.e._arb_out_x.r e.e.buf_s_func._en_X_t[0] e.y[0].a e.out.v e.e.buf_s_func._in_vXX_t[0] e.e.Yarb.arbs[0].ack_cell2._y e.e.y_ack_arb[1].buf1._y e.e._y_temp[1].a e.e.buf_s_func.out_a_B_buf_f.buf1._y e.e.buf_s_func._out_a_B e.e.buf_s_func._out_a_BX_t[0] e.e.x_enc_out.d[0].t e.x[0].r e.y[1].r e.e._x_temp[1].a e.e.Xarb.arbs[0]._y2_arb e.e._arb_out_y.r e.e._in_x_v e.out.a e.x[1].r e.e.y_enc_out.d[0].t e.e.x_enc_out.d[0].f e.e.y_enc_out.d[0].f e.e.y_encoder.ors_f[0].b._y e.e.vtree_y.OR2_tf[0]._y e.e.buf_s_func._in_vXX_f[0] e.e.buf_s_func._en_X_f[0] e.x[0].a e.e._y_temp[0].a e.e._in_xy_v.y e.e._in_y_v e.e.vtree_x.ct.b._y e.e._x_temp[0].a e.e._en e.e.x_encoder.ors_t[0].b._y e.x[1].a e.e.buf_s_func.in_v_buf_f.buf1._y e.e.Yarb.arbs[0].ack_cell1._y e.e._x_v_B e.e.Yarb.arbs[0]._y1_arb e.e.vtree_x.ct.in[0] e.e.buf_s_func._out_a_BX_f[0] e.e.buf_s_func.in_v_prebuf._y e.e.vtree_y.ct.in[0] e.y[1].a e.e._x_v e.e.Xarb.arbs[0].arbiter._y1 e.e.Xarb.arbs[0].or_cell._y e.e._in_xy_v._y e.e.Xarb.arbs[0].ack_cell1._y e.e.Xarb.arbs[0]._y1_arb e.e.x_encoder.ors_f[0].b._y e.e.Yarb.arbs[0].arbiter._y1 e.e.y_encoder.ors_t[0].b._y e.e.vtree_y.ct.b._y e.e.buf_s_func.out_a_B_buf_t.buf1._y e.e.Yarb.arbs[0]._y2_arb e.e.Xarb.arbs[0].arbiter._y2 e.e.Xarb.arbs[0].ack_cell2._y e.e.buf_s_func.in_v_buf_t.buf1._y e.e.y_ack_arb[0].buf1._y e.e.x_ack_arb[1].buf1._y e.e.Yarb.arbs[0].arbiter._y2 e.e.x_req_ortree.or2s[0]._y e.e.buf_s_func.en_buf_f.buf1._y e.e.buf_s_func.en_buf_t.buf1._y 
-	     81590 Reset : 0
-	     81605 e._reset_B : 1  [by Reset:=0]
-	    118536 e.e.buf_s_func.reset_buf._y : 0  [by e._reset_B:=1]
-	    118591 e.e.buf_s_func._reset_BX : 1  [by e.e.buf_s_func.reset_buf._y:=0]
-	    124853 e.e.reset_buf._y : 0  [by e._reset_B:=1]
-	    154633 e.e._reset_BX : 1  [by e.e.reset_buf._y:=0]
-	    155055 e.e.X_ack_confirm._y : X  [by e.e._reset_BX:=1]
-	    168482 e.e.reset_bufarray.buf1._y : 0  [by e.e._reset_BX:=1]
-	    168483 e.e._reset_BXX[0] : 1  [by e.e.reset_bufarray.buf1._y:=0]
-	    168976 e.e.Y_ack_confirm._y : X  [by e.e._reset_BX:=1]
-	    168977 e.e._arb_out_y.a : X  [by e.e.Y_ack_confirm._y:=X]
-	    170244 e.e.buf_s_func.reset_bufarray.buf1._y : 0  [by e.e.buf_s_func._reset_BX:=1]
-	    179445 e.e._x_a_B : X  [by e.e._reset_BX:=1]
-	    179727 e.e._x_a : X  [by e.e._x_a_B:=X]
-	    190449 e.e.buf_s_func._reset_BXX[0] : 1  [by e.e.buf_s_func.reset_bufarray.buf1._y:=0]
-	    190452 e.e.buf_s_func.f_buf_func[1]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    191000 e.e.buf_s_func.t_buf_func[1]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    191217 e.e.buf_s_func.f_buf_func[0]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    191523 e.out.d.d[1].f : X  [by e.e.buf_s_func.f_buf_func[1]._y:=X]
-	    191954 e.out.d.d[1].t : X  [by e.e.buf_s_func.t_buf_func[1]._y:=X]
-	    192298 e.out.d.d[0].f : X  [by e.e.buf_s_func.f_buf_func[0]._y:=X]
-	    203769 e.e._arb_out_x.a : X  [by e.e.X_ack_confirm._y:=X]
-	    212890 e.e.buf_s_func.t_buf_func[0]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    267360 e.out.d.d[0].t : X  [by e.e.buf_s_func.t_buf_func[0]._y:=X]
-	    267360 Reset : 1
-	    268342 e._reset_B : 0  [by Reset:=1]
-	    268360 e.e.reset_buf._y : 1  [by e._reset_B:=0]
-	    272355 e.e.buf_s_func.reset_buf._y : 1  [by e._reset_B:=0]
-	    272363 e.e._reset_BX : 0  [by e.e.reset_buf._y:=1]
-	    272566 e.e.X_ack_confirm._y : 1  [by e.e._reset_BX:=0]
-	    272865 e.e.Y_ack_confirm._y : 1  [by e.e._reset_BX:=0]
-	    273004 e.e._arb_out_y.a : 0  [by e.e.Y_ack_confirm._y:=1]
-	    274420 e.e._arb_out_x.a : 0  [by e.e.X_ack_confirm._y:=1]
-	    277123 e.e._x_a_B : 1  [by e.e._reset_BX:=0]
-	    293947 e.e.reset_bufarray.buf1._y : 1  [by e.e._reset_BX:=0]
-	    294016 e.e._reset_BXX[0] : 0  [by e.e.reset_bufarray.buf1._y:=1]
-	    313469 e.e._x_a : 0  [by e.e._x_a_B:=1]
-	    317256 e.e.buf_s_func._reset_BX : 0  [by e.e.buf_s_func.reset_buf._y:=1]
-	    317267 e.e.buf_s_func.reset_bufarray.buf1._y : 1  [by e.e.buf_s_func._reset_BX:=0]
-	    369053 e.e.buf_s_func._reset_BXX[0] : 0  [by e.e.buf_s_func.reset_bufarray.buf1._y:=1]
-	    369054 e.e.buf_s_func.t_buf_func[0]._y : 1  [by e.e.buf_s_func._reset_BXX[0]:=0]
-	    369068 e.e.buf_s_func.f_buf_func[1]._y : 1  [by e.e.buf_s_func._reset_BXX[0]:=0]
-	    369090 e.e.buf_s_func.t_buf_func[1]._y : 1  [by e.e.buf_s_func._reset_BXX[0]:=0]
-	    369180 e.out.d.d[1].f : 0  [by e.e.buf_s_func.f_buf_func[1]._y:=1]
-	    369257 e.e.buf_s_func.f_buf_func[0]._y : 1  [by e.e.buf_s_func._reset_BXX[0]:=0]
-	    369297 e.out.d.d[0].f : 0  [by e.e.buf_s_func.f_buf_func[0]._y:=1]
-	    369793 e.out.d.d[0].t : 0  [by e.e.buf_s_func.t_buf_func[0]._y:=1]
-	    416602 e.out.d.d[1].t : 0  [by e.e.buf_s_func.t_buf_func[1]._y:=1]
-[] Setting output ack/val low
-	    416602 Reset : 0
-	    416859 e._reset_B : 1  [by Reset:=0]
-	    416946 e.e.reset_buf._y : 0  [by e._reset_B:=1]
-	    416947 e.e._reset_BX : 1  [by e.e.reset_buf._y:=0]
-	    417153 e.e.buf_s_func.reset_buf._y : 0  [by e._reset_B:=1]
-	    417331 e.e.buf_s_func._reset_BX : 1  [by e.e.buf_s_func.reset_buf._y:=0]
-	    417537 e.e.X_ack_confirm._y : X  [by e.e._reset_BX:=1]
-	    417701 e.e._arb_out_x.a : X  [by e.e.X_ack_confirm._y:=X]
-	    418134 e.e.buf_s_func.reset_bufarray.buf1._y : 0  [by e.e.buf_s_func._reset_BX:=1]
-	    418156 e.e.Y_ack_confirm._y : X  [by e.e._reset_BX:=1]
-	    418178 e.e._arb_out_y.a : X  [by e.e.Y_ack_confirm._y:=X]
-	    418753 e.e.reset_bufarray.buf1._y : 0  [by e.e._reset_BX:=1]
-	    418954 e.e._x_a_B : X  [by e.e._reset_BX:=1]
-	    419600 e.e._reset_BXX[0] : 1  [by e.e.reset_bufarray.buf1._y:=0]
-	    420329 e.e.buf_s_func._reset_BXX[0] : 1  [by e.e.buf_s_func.reset_bufarray.buf1._y:=0]
-	    420462 e.e.buf_s_func.f_buf_func[0]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    420683 e.out.d.d[0].f : X  [by e.e.buf_s_func.f_buf_func[0]._y:=X]
-	    420688 e.e.buf_s_func.t_buf_func[0]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    420695 e.out.d.d[0].t : X  [by e.e.buf_s_func.t_buf_func[0]._y:=X]
-	    434445 e.e.buf_s_func.t_buf_func[1]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    434475 e.out.d.d[1].t : X  [by e.e.buf_s_func.t_buf_func[1]._y:=X]
-	    435991 e.e.buf_s_func.f_buf_func[1]._y : X  [by e.e.buf_s_func._reset_BXX[0]:=1]
-	    442704 e.out.d.d[1].f : X  [by e.e.buf_s_func.f_buf_func[1]._y:=X]
-	    449082 e.e._x_a : X  [by e.e._x_a_B:=X]
-	    449082 e.out.a : 0
-	    449082 e.x[1].a : 0
-	    449082 e.y[0].r : 0
-	    449082 e.x[0].r : 0
-	    449082 e.y[1].a : 0
-	    449082 e.out.v : 0
-	    449082 e.y[0].a : 0
-	    449082 e.y[1].r : 0
-	    449082 e.x[0].a : 0
-	    449082 e.x[1].r : 0
-	    449089 e.e.Xarb.arbs[0].arbiter._y1 : 1  [by e.x[0].r:=0]
-	    449101 e.e.Xarb.arbs[0]._y1_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y1:=1]
-	    449160 e.e.Yarb.arbs[0].arbiter._y2 : 1  [by e.y[1].r:=0]
-	    449173 e.e.x_encoder.ors_t[0].b._y : 1  [by e.x[1].a:=0]
-	    449185 e.e.x_enc_out.d[0].t : 0  [by e.e.x_encoder.ors_t[0].b._y:=1]
-	    449188 e.e.y_encoder.ors_f[0].b._y : 1  [by e.y[0].a:=0]
-	    449357 e.e.x_encoder.ors_f[0].b._y : 1  [by e.x[0].a:=0]
-	    449537 e.e.Xarb.arbs[0].arbiter._y2 : 1  [by e.x[1].r:=0]
-	    449564 e.e.Yarb.arbs[0]._y2_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y2:=1]
-	    451271 e.e.Yarb.arbs[0].arbiter._y1 : 1  [by e.y[0].r:=0]
-	    451869 e.e.y_encoder.ors_t[0].b._y : 1  [by e.y[1].a:=0]
-	    451871 e.e.y_enc_out.d[0].t : 0  [by e.e.y_encoder.ors_t[0].b._y:=1]
-	    452436 e.e.Xarb.arbs[0]._y2_arb : 0  [by e.e.Xarb.arbs[0].arbiter._y2:=1]
-	    453633 e.e.x_enc_out.d[0].f : 0  [by e.e.x_encoder.ors_f[0].b._y:=1]
-	    454882 e.e.vtree_x.OR2_tf[0]._y : 1  [by e.e.x_enc_out.d[0].f:=0]
-	    455104 e.e.y_enc_out.d[0].f : 0  [by e.e.y_encoder.ors_f[0].b._y:=1]
-	    455270 e.e.vtree_y.OR2_tf[0]._y : 1  [by e.e.y_enc_out.d[0].f:=0]
-	    455345 e.e.vtree_y.ct.in[0] : 0  [by e.e.vtree_y.OR2_tf[0]._y:=1]
-	    455566 e.e.Yarb.arbs[0]._y1_arb : 0  [by e.e.Yarb.arbs[0].arbiter._y1:=1]
-	    455690 e.e.vtree_y.ct.b._y : 1  [by e.e.vtree_y.ct.in[0]:=0]
-	    455704 e.e.Yarb.arbs[0].or_cell._y : 1  [by e.e.Yarb.arbs[0]._y1_arb:=0]
-	    455706 e.e._arb_out_y.r : 0  [by e.e.Yarb.arbs[0].or_cell._y:=1]
-	    456971 e.e.Xarb.arbs[0].or_cell._y : 1  [by e.e.Xarb.arbs[0]._y2_arb:=0]
-	    458381 e.e.vtree_x.ct.in[0] : 0  [by e.e.vtree_x.OR2_tf[0]._y:=1]
-	    458382 e.e.vtree_x.ct.b._y : 1  [by e.e.vtree_x.ct.in[0]:=0]
-	    458930 e.e._in_x_v : 0  [by e.e.vtree_x.ct.b._y:=1]
-	    458941 e.e._in_xy_v._y : 1  [by e.e._in_x_v:=0]
-	    459311 e.e._in_xy_v.y : 0  [by e.e._in_xy_v._y:=1]
-	    459378 e.e.buf_s_func.in_v_prebuf._y : 1  [by e.e._in_xy_v.y:=0]
-	    460953 e.e._in_y_v : 0  [by e.e.vtree_y.ct.b._y:=1]
-	    462019 e.e.buf_s_func._in_vX : 0  [by e.e.buf_s_func.in_v_prebuf._y:=1]
-	    462035 e.e.buf_s_func.in_v_buf_f.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
-	    462563 e.e.buf_s_func._in_vXX_f[0] : 0  [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
-	    466581 e.e.buf_s_func.in_v_buf_t.buf1._y : 1  [by e.e.buf_s_func._in_vX:=0]
-	    468078 e.e.x_req_ortree.or2s[0]._y : 1  [by e.x[1].r:=0]
-	    469016 e.e.buf_s_func._in_vXX_t[0] : 0  [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
-	    494958 e.e._x_v : 0  [by e.e.x_req_ortree.or2s[0]._y:=1]
-	    500888 e.e._arb_out_x.r : 0  [by e.e.Xarb.arbs[0].or_cell._y:=1]
-	    506543 e.e.buf_s_func._out_a_B : 1  [by e.out.a:=0]
-	    506545 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
-	    518883 e.e._x_v_B : 1  [by e.e._x_v:=0]
-	    519584 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0  [by e.e.buf_s_func._out_a_B:=1]
-	    519587 e.e.buf_s_func._out_a_BX_f[0] : 1  [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
-	    567503 e.e.buf_s_func._out_a_BX_t[0] : 1  [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
-	    567503 e.y[0].r : 1
-	    567503 e.y[1].r : 1
-	    567532 e.e.Yarb.arbs[0].arbiter._y1 : 0  [by e.y[0].r:=1]
-	    569133 e.e.Yarb.arbs[0]._y1_arb : X  [by e.e.Yarb.arbs[0].arbiter._y1:=0]
-	    569286 e.e.Yarb.arbs[0].or_cell._y : X  [by e.e.Yarb.arbs[0]._y1_arb:=X]
-	    569330 e.e._arb_out_y.r : X  [by e.e.Yarb.arbs[0].or_cell._y:=X]
-	    569330 e.x[0].r : 1
-	    569330 e.x[1].r : 1
-	    572091 e.e.Xarb.arbs[0].arbiter._y1 : 0  [by e.x[0].r:=1]
-	    572308 e.e.Xarb.arbs[0]._y1_arb : X  [by e.e.Xarb.arbs[0].arbiter._y1:=0]
-	    572330 e.e.Xarb.arbs[0].or_cell._y : X  [by e.e.Xarb.arbs[0]._y1_arb:=X]
-	    572331 e.e._arb_out_x.r : X  [by e.e.Xarb.arbs[0].or_cell._y:=X]
-	    583013 e.e.x_req_ortree.or2s[0]._y : 0  [by e.x[0].r:=1]
-	    584594 e.e._x_v : 1  [by e.e.x_req_ortree.or2s[0]._y:=0]
-	    593939 e.e._x_v_B : 0  [by e.e._x_v:=1]

test/unit_tests/encoder2D_7/test.prsim

@@ -1,74 +0,0 @@
-watchall
-
-cycle
-set Reset 1
-cycle 
-set Reset 0 
-cycle
-set Reset 1
-cycle 
-set Reset 0 
-
-# mode run
-
-# assert e.e.Yarb.out.a 0
-
-
-system "echo '[] Setting output ack/val low'"
-
-set e.e.Yarb.out.a 0
-set e.e.Xarb.out.a 0
-cycle
-
-set e.out.a 0
-set e.out.v 0
-
-set e.y[0].r 0
-set e.y[1].r 0
-set e.y[0].a 0
-set e.y[1].a 0
-
-set e.x[0].r 0
-set e.x[1].r 0
-set e.x[0].a 0
-set e.x[1].a 0
-cycle
-
-
-set e.y[0].r 1
-set e.y[1].r 1
-cycle
-
-set e.x[0].r 1
-set e.x[1].r 1
-cycle
-
-
-# system "echo '[] Setting input low'"
-
-
-# # set e.e.Yarb.arbs[0].arbiter._y1 0
-# # set e.e.Yarb.arbs[0].arbiter._y2 0
-
-
-# set e.y[0].r 0
-# set e.y[1].r 0
-# set e.y[0].a 0
-# set e.y[1].a 0
-
-# set e.x[0].r 0
-# set e.x[1].r 0
-# set e.x[0].a 0
-# set e.x[1].a 0
-
-# cycle
-
-# system "echo '[] Setting y[0,1] req high'"
-# # assert e.e.Yarb.out.a 0
-# # assert e.e.Y_ack_confirm.y 0
-
-# # set e.y[0].r 1
-# # set e.y[1].r 1
-
-# cycle
-

test/unit_tests/encoder2D_8x7/test.act

@@ -0,0 +1,49 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc encoder2D_2x2 (a1of1 x[8]; a1of1 y[7]; avMx1of2<6> out){
+    encoder2D<3, 3, 8, 7, 1> e(.x=x, .y=y, .out=out);
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    e.supply.vss = GND;
+    e.supply.vdd = Vdd;
+    e.reset_B = _reset_B;
+
+}
+
+encoder2D_2x2 e;

test/unit_tests/encoder2D_8x7/test.prsim

@@ -0,0 +1,246 @@
+watchall
+mode run
+
+system "echo '[] Set Out Ack/Valid Low'"
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Setting Neuron Req Low'"
+
+set e.y[0].r 0
+set e.y[1].r 0
+set e.y[2].r 0
+set e.y[3].r 0
+set e.y[4].r 0
+set e.y[5].r 0
+set e.y[6].r 0
+# set e.y[7].r 0
+
+set e.x[0].r 0
+set e.x[1].r 0
+set e.x[2].r 0
+set e.x[3].r 0
+set e.x[4].r 0
+set e.x[5].r 0
+set e.x[6].r 0
+set e.x[7].r 0
+cycle
+
+# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
+# # status X
+# # set Reset 1
+# # cycle
+
+cycle 
+
+mode run
+status X
+status 0
+set Reset 0
+cycle
+
+
+
+system "echo '[] Single Neuron Spikes (2,5), raise y[5].r'"
+
+set e.y[5].r 1
+# set e.x[2].r 1
+cycle
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 0
+assert e.e._x_v 0
+
+
+
+system "echo '[] Raise x[2].r'"
+# set e.y[5].r 1
+set e.x[2].r 1
+cycle
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+assert e.e._x_v 1
+
+
+system "echo '[] Check Arbiter Acks'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 0
+assert e.y[1].a 0
+assert e.y[2].a 0
+assert e.y[3].a 0
+assert e.y[4].a 0
+assert e.y[5].a 1
+assert e.y[6].a 0
+# assert e.y[7].a 0
+assert e.e.Yarb.out.a 1
+
+
+assert e.x[0].a 0
+assert e.x[1].a 0
+assert e.x[2].a 1
+assert e.x[3].a 0
+assert e.x[4].a 0
+assert e.x[5].a 0
+assert e.x[6].a 0
+assert e.x[7].a 0
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.x_enc_out.d[0].t 0
+assert e.e.x_enc_out.d[0].f 1
+assert e.e.x_enc_out.d[1].t 1
+assert e.e.x_enc_out.d[1].f 0
+assert e.e.x_enc_out.d[2].t 0
+assert e.e.x_enc_out.d[2].f 1
+
+assert e.e.y_enc_out.d[0].t 1
+assert e.e.y_enc_out.d[0].f 0
+assert e.e.y_enc_out.d[1].t 0
+assert e.e.y_enc_out.d[1].f 1
+assert e.e.y_enc_out.d[2].t 1
+assert e.e.y_enc_out.d[2].f 0
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 0
+assert e.out.d.d[0].f 1
+assert e.out.d.d[1].t 1
+assert e.out.d.d[1].f 0
+assert e.out.d.d[2].t 0
+assert e.out.d.d[2].f 1
+assert e.out.d.d[3].t 1
+assert e.out.d.d[3].f 0
+assert e.out.d.d[4].t 0
+assert e.out.d.d[4].f 1
+assert e.out.d.d[5].t 1
+assert e.out.d.d[5].f 0
+
+
+system "echo '[] Finish Neuron Handshake'"
+
+set e.y[5].r 0
+set e.x[2].r 0
+cycle
+
+assert e.e.Yarb.out.r 0
+assert e.e.Xarb.out.r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+assert e.e.Yarb.out.a 0
+assert e.e.Xarb.out.a 0
+assert e.y[5].a 0
+assert e.x[2].a 0
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (2,5) Encoded'"
+
+system "echo '[] Single Neuron Spikes (0,0)'"
+
+set e.y[0].r 1
+set e.x[0].r 1
+
+cycle
+
+assert e.e.Yarb.out.r 1
+assert e.e.Xarb.out.r 1
+
+assert e.e._x_v 1
+
+system "echo '[] Check Arbiter Acks'"
+
+assert e.e._x_a_B 1
+
+assert e.y[0].a 1
+assert e.y[1].a 0
+assert e.y[2].a 0
+assert e.y[3].a 0
+assert e.y[4].a 0
+assert e.y[5].a 0
+assert e.y[6].a 0
+# assert e.y[7].a 0
+assert e.e.Yarb.out.a 1
+
+
+assert e.x[0].a 1
+assert e.x[1].a 0
+assert e.x[2].a 0
+assert e.x[3].a 0
+assert e.x[4].a 0
+assert e.x[5].a 0
+assert e.x[6].a 0
+assert e.x[7].a 0
+assert e.e.Xarb.out.a 1
+
+system "echo '[] Check Encoders'"
+
+assert e.e.y_enc_out.d[0].t 0
+assert e.e.y_enc_out.d[0].f 1
+assert e.e.y_enc_out.d[1].t 0
+assert e.e.y_enc_out.d[1].f 1
+assert e.e.y_enc_out.d[2].t 0
+assert e.e.y_enc_out.d[2].f 1
+
+assert e.e.x_enc_out.d[0].t 0
+assert e.e.x_enc_out.d[0].f 1
+assert e.e.x_enc_out.d[1].t 0
+assert e.e.x_enc_out.d[1].f 1
+assert e.e.x_enc_out.d[2].t 0
+assert e.e.x_enc_out.d[2].f 1
+
+system "echo '[] Check Buffer'"
+
+assert e.e._in_x_v 1
+assert e.e._in_y_v 1
+assert e.e._en 1
+
+assert e.out.d.d[0].t 0
+assert e.out.d.d[0].f 1
+assert e.out.d.d[1].t 0
+assert e.out.d.d[1].f 1
+assert e.out.d.d[2].t 0
+assert e.out.d.d[2].f 1
+assert e.out.d.d[3].t 0
+assert e.out.d.d[3].f 1
+assert e.out.d.d[4].t 0
+assert e.out.d.d[4].f 1
+assert e.out.d.d[5].t 0
+assert e.out.d.d[5].f 1
+
+system "echo '[] Finish Neuron Handshake'"
+
+set e.y[0].r 0
+set e.x[0].r 0
+cycle
+
+assert e.e.Yarb.out.r 0
+assert e.e.Xarb.out.r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+
+assert e.e.Yarb.out.a 0
+assert e.e.Xarb.out.a 0
+assert e.y[0].a 0
+assert e.x[0].a 0
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (0,0) Encoded'"