removed texel_singlecore: is never used, and is a simplification of dualcore

Obv not simulated yet and not sure all wires are correct. still need to repass through them

.gitignore

@@ -6,3 +6,5 @@ arm64_*
 *.arm64_*
 *~
 *.deps
+
+test/unit_tests/**/run/

dataflow_neuro/cell_lib_async.act

@@ -26,6 +26,30 @@
 
 namespace tmpl {
     namespace dataflow_neuro{
+        export defcell KEEP (bool y; bool vdd, vss) {
+            bool _y;
+             prs{
+                 // y => _y-
+            //     [weak=1] _y -> y-
+            //     [weak=1] ~_y -> y+
+
+                 }
+        }
+
+        export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
+            bool _y;
+            prs{
+                (~c1)|~pr_B -> _y+
+                c1 & n1 & n2 & sr_B -> _y-
+                _y => y-
+                }
+            sizing {
+                    leak_adjust <- 1; 
+                    p_n_mode <- 1;
+                    y {-1}; _y{-1} 
+                    }
+        }
+
         export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
             bool _y;
             prs{
@@ -41,6 +65,22 @@ namespace tmpl {
                     }
         }
 
+
+        export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
+            bool _y;
+            prs{
+                (~p1 & ~c1 & ~c2)|~pr_B -> _y+
+                c1 & c2 & n1 & sr_B -> _y-
+                _y => y-
+
+                }
+            sizing {
+                    leak_adjust <- 1; 
+                    p_n_mode <- 1;
+                    y {-1}; _y{-1} 
+                    }
+        }
+
         export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
             prs{
                 (~p1 & ~c1)|~pr_B -> y-
@@ -64,7 +104,8 @@ namespace tmpl {
                 p_n_mode <- 1;
             y {-1}}
         }
-
+        //Maybe deprecated?
+        //@TODO Check if it exist, otherwise delete
         export defcell A_1C1P_B (bool! y; bool? c1, p1; bool vdd, vss)
         {
         bool _y;
@@ -90,6 +131,94 @@ namespace tmpl {
             y {-1}}
         }
 
+        export defcell A_1C1N_X1 (bool! y; bool? c1, n1; bool vdd, vss)
+        {
+        prs{
+            ~c1 -> y+
+            c1&n1-> y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-1}}
+        }
+
+        // export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 | ~pr_B-> _y+
+        //     c1&n1&sr_B -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+        // export defcell A_1C1N_SB_X4 (bool! y; bool? c1, n1, pr, sr; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 & ~sr-> _y+
+        //     c1&n1 | pr -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+        export defcell A_1C2N_R_X1 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
+        {
+        prs{
+            ~c1 | ~pr_B-> y+
+            c1&n1&n2&sr_B -> y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}}
+        }
+
+        export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 | ~pr_B-> _y+
+            c1&n1&n2&sr_B -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+        export defcell A_1C2N_SB_X4 (bool! y; bool? c1, n1, n2, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~sr-> _y+
+            c1&n1&n2 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+        export defcell A_2C1N_SB_X4 (bool! y; bool? c1, c2, n1, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~c2 & ~sr-> _y+
+            c1&c2&n1 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+
         export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
         {
         prs{
@@ -137,12 +266,12 @@ namespace tmpl {
             y {-1}}
         }
 
-        export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss)
+        export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, na1, na2, nb1, nb2, pr_B, sr_B; bool vdd, vss)
         {
         bool _y;
         prs{
             (~c1 & ~c2) | ~pr_B -> _y+
-            c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
+            c1 & c2 & ((na1 & na2) | (nb1 & nb2)) & sr_B -> _y-
             _y => y-
         }
         sizing {    
@@ -314,6 +443,19 @@ namespace tmpl {
                 p_n_mode <- 1;
             y {-1}; _y{-1}}
         }
+
+        export defcell A_2C1N_R_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
+        {
+        prs{
+            (~c1 & ~c2) | ~pr_B -> y+
+            c1 & c2 & n1 & sr_B -> y-
+        }
+        sizing {    
+                leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-1}}
+        }
+
         export defcell A_2C1N_RB_X4(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
         {
             bool _y;
@@ -482,11 +624,11 @@ namespace tmpl {
             y {-1}; _y{-1} }
         }
 
-        export defcell A_4P1N1N_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
+        export defcell A_4P1N1N_X1 (bool! y; bool? na1, nb1, p1, p2, p3, p4; bool? vdd, vss)
         {
         prs{
             ~p1 & ~p2 & ~p3 & ~p4 -> y+
-            n1 | n2 -> y-
+            na1 | nb1 -> y-
             }
         sizing {leak_adjust <- 1; 
                 p_n_mode <- 1;
@@ -524,6 +666,67 @@ namespace tmpl {
             mk_excllo(_y1, _y2)
           }
         }
+        export
+        defproc A_1N_U_X4(bool? n1; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] n1 -> y-
+        }
+        }
+
+        export
+        defproc A_2N_U_X4(bool? n1, n2; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] n1 & n2 -> y-
+        }
+        }
+        
+        export
+        defproc A_1P_U_X4(bool? p1; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] ~p1 -> y+
+        }
+        }
+
+        export
+        defproc A_2P_U_X4(bool? p1, p2; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] ~p1 & ~p2 -> y+
+        }
+        }
+
+        export
+        defproc A_3P_U_X4(bool? p1, p2, p3; bool! y; bool? vdd, vss)
+        {
+        prs{
+        [keeper=0] ~p1 & ~p2 & ~p3-> y+
+        }
+        }
+
+        export
+        defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
+            A_1N_U_X4 cell(.n1 = a, .y = y, .vdd = vdd, .vss = vss);
+        }
+
+        export
+        defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) {
+            A_1P_U_X4 cell(.p1 = a, .y = y, .vdd = vdd, .vss = vss);
+        }
+
+        defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
+            bool _y;
+            prs{
+                (~p1 & ~p2 & ~c1 & ~c2)|~reset_B -> _y+
+                (c1 & c2 & reset_B) -> _y-
+                _y => y-
+            }
+            sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+                y {-1}; _y{-1} }
+        }
         }}
 
 

dataflow_neuro/cell_lib_std.act

@@ -27,14 +27,29 @@
 namespace tmpl {
   namespace dataflow_neuro {
 
+
+    // We have to add a pretend buffer in here
+    // to ensure that act2v doesn't simplify things
+    // and just connect y to vss/vdd lol
     export defproc TIELO_X1(bool! y; bool vdd, vss)
     {
-      y = vss;
+      bool _y, a;
+      a = vss;
+      prs {
+        a => _y-
+        _y => y-
+      }
+
     }
 
     export defproc TIEHI_X1(bool! y; bool vdd, vss)
     {
-      y = vdd;
+      bool _y, a;
+      a = vdd;
+      prs {
+        a => _y-
+        _y => y-
+      }      
     }
 
     /*-- inverters --*/
@@ -94,7 +109,19 @@ namespace tmpl {
     {
       sizing { _y {-4,2}; y {-8,4} }
     }
-        export defcell BUF_X12<: buf()
+    export defcell BUF_X12<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X16<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X24<: buf()
+    {
+      sizing { _y {-6,2}; y {-12,4} }
+    }
+    export defcell BUF_X32<: buf()
     {
       sizing { _y {-6,2}; y {-12,4} }
     }
@@ -102,13 +129,23 @@ namespace tmpl {
     /*-- delay cells --*/
     // TODO properly
 
+    // export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
+    // {
+    //   bool _y, __y, ___y;
+    //   prs {
+    //     a => _y-
+    //     _y => __y-
+    //     __y => ___y-
+    //     ___y => y-
+    //   }
+    // }
+
     export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
     {
-      bool _y;
-      prs {
-        a => _y-
-        _y => y-
-      }
+        BUF_X1 bufchain[16];
+        (i:0..14: bufchain[i].y = bufchain[i+1].a;)
+        bufchain[0].a = a;
+        bufchain[15].y = y;
     }
 
       
@@ -272,7 +309,9 @@ namespace tmpl {
 
     export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
     {
-      // y = !( S ? a : b )
+      // y = !( S ? b : a )
+      // Actually looks more like
+      // if s = 0 -> use A
       // Adjusted to fit the XFAB Muxes
       bool _s;
       bool _y;
@@ -354,8 +393,8 @@ namespace tmpl {
       prs {
         en => _en-
 
-      ~a & ~_en -> y+
-        a & en -> y-
+      ~a & ~_en -> y-
+        a & en -> y+
       }
       sizing { _en{-1}; y{-1} }
     }
@@ -366,11 +405,49 @@ namespace tmpl {
       prs {
         en => _en-
 
-      ~a & ~_en -> y+
-        a & en -> y-
+      ~a & ~_en -> y-
+        a & en -> y+
       }
       sizing { _en{-2}; y{-2,2} }
     }
+
+    export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
+    {
+      bool _en;
+      prs {
+        en => _en-
+
+      ~a & ~_en -> y-
+        a & en -> y+
+      }
+      sizing { _en{-4}; y{-4,4} }
+    }
+
+    export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
+    {
+      bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
+      prs {
+
+        // Creating delayed versions of the clock
+        clk_B => _clk_B-
+        _clk_B => __clk_B-
+
+        (~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
+        ((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
+
+        _mqib => _mqi-
+
+        (~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
+        ((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
+
+        _sqib => _sqi-
+        _sqib => q-
+
+        q => q_B-
+
+
+      }
+    } 
   }
 }
 

dataflow_neuro/chips.act

@@ -0,0 +1,479 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+REG_NCA, REG_NCW, REG_M>
+
+defproc texel_core (avMx1of2<N_IN> in, out;
+    Mx1of2<REG_NCW> reg_data[REG_M];
+
+    // Dummy synapses and neurons in the handshake blocks
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
+    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
+    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
+    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
+    reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
+
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    pint index = 0; // Just useful
+
+    // Onwards
+    fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Register
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
+    register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
+        .supply = supply, .reset_B = reset_reg_B);
+    fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Spike Decoder
+    pint NC_SYN;
+    NC_SYN = NC_SYN_X + NC_SYN_Y;
+    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
+    fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
+    decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
+        .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
+        .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
+        .supply = supply, .reset_B = _reset_BX);
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    )
+
+    // Synapse handshake circuits, to be removed for innovus
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    //     .synapses = synapses,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
+    //     .to_pu = syn_pu,
+    //     .out_ackB_decoder = dec_ackB,
+    //     .supply = supply);
+
+    // Neurons + encoder
+    pint NC_NRN;
+    NC_NRN = NC_NRN_X + NC_NRN_Y;
+    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
+    fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // Neuron handshake circuits, to be removed for innovus
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    //     .outx = enc_inx, .outy = enc_iny,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
+    //     .supply = supply, .reset_B = _reset_BX);
+
+
+
+    // Merge
+    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
+    append<N_IN-2, 2, 2> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
+    merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+
+    // Output
+    fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
+        .reset_B = _reset_BX, .supply = supply);
+
+
+    // Neuron/synapse monitor targeters
+    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
+    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
+    pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
+    pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
+
+    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
+    nrn_mon_dec_x.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_X:
+        nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
+    )
+    sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
+    nrn_mon_dec_y.en = register.data[1].d[0].t;
+    (i:NC_NRN_MON_Y:
+        nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
+    )
+    sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
+        .supply = supply);
+    syn_mon_dec_x.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_X:
+        syn_mon_dec_x.in.d[i] = register.data[3].d[i];
+    )
+    sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
+
+    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
+    syn_mon_dec_y.en = register.data[1].d[1].t;
+    (i:NC_SYN_MON_Y:
+        syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
+    )
+    sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
+
+    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
+    // Stops the possibility of dev_mon being high while some other sig is high.
+    // Otherwise boom.
+    // Also the 4th monitor line to each synapse is active LOW, needs inverter.
+    bool DEV_DEBUG;
+    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
+    sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+        .supply = supply);
+    DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    INV_X1 syn_targ_set_high_inv[NSMX4];
+    [NSMX4 >= 1 ->
+        AND2_X1 ands_devmon[NSMX4];
+        (i:NSMX4:
+            ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
+            ands_devmon[i].b = DEV_DEBUG;
+            ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
+            ands_devmon[i].vdd = supply.vdd;
+            ands_devmon[i].vss = supply.vss;
+
+            syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
+            syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
+            syn_targ_set_high_inv[i].vdd = supply.vdd;
+            syn_targ_set_high_inv[i].vss = supply.vss;
+
+        )
+        // Wire up the remaining lines.
+        (i:N_SYN_MON_X:
+            [(~(i%4 = 1)) & (~(i%4=3))->
+                syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
+            ]
+        )
+    ]
+
+    // Create TBUFs for each synapse column,
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
+    KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
+    sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
+    (j:N_MON_AMZO_PER_SYN:
+        (i:N_SYN_X:
+            index = i*N_MON_AMZO_PER_SYN + j;
+            syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
+            syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
+            syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
+        )
+
+        syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
+        syn_AMZO_keeps[j].vdd = supply.vdd;
+        syn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+
+    // Create TBUFs for each neuron column, and add keeps.
+    // ctrl wired to mon line (first in each 4).
+    TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
+    KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
+    sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply); 
+    (j:N_MON_AMZO_PER_NRN:
+        (i:N_NRN_X:
+            index = i*N_MON_AMZO_PER_NRN + j;
+            nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
+            nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
+            nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
+        )
+
+        nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
+        nrn_AMZO_keeps[j].vdd = supply.vdd;
+        nrn_AMZO_keeps[j].vss = supply.vss;
+
+    )
+
+    // Create buffered signals from register to nrns.
+    sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
+    (i:N_FLAGS_PER_NRN:
+        sb_nrn_EFO.in[i] = register.data[5].d[i].t;
+    )
+
+    // Create  buffered signals from register to synapses.
+    // Includes safety on the first 3 flags with dev mon.
+    sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
+    (i:3..N_FLAGS_PER_SYN-1:
+        sb_syn_EFO.in[i] = register.data[4].d[i].t;
+    )  
+    AND2_X1 syn_flags_dev_safety[3];
+    (i:0..2:
+        syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
+        syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
+
+        syn_flags_dev_safety[i].vdd = supply.vdd;
+        syn_flags_dev_safety[i].vss = supply.vss;
+    )
+
+    // Create non-buffered reset signals for the neuron/syn handshakes
+    // Since sigs are buffered before each neuron.
+    sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
+    sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
+    sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
+    INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
+    sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
+
+}
+
+
+
+
+
+
+export template<pint N_IN,  // Size of input data from outside world
+N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
+NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+N_SYN_DLY_CFG,
+N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
+N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
+N_BUFFERS,
+N_LINE_PD_DLY, // Number of dummy delays to add line pull down
+N_BD_DLY_CFG, N_BD_DLY_CFG2,
+REG_NCA, REG_NCW, REG_M>
+defproc texel_dualcore (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    power supply;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
+    ){
+
+    // Reset buffers
+    bool _reset_BX;
+    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
+
+    bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
+        .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
+
+    fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
+
+    // Loopback
+    fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
+    dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
+        .supply = supply);
+    fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
+
+
+    // Onwards to core demux
+    fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
+    demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
+
+    // Cores
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core1(.in = fifo_dmx2core1.out,
+
+            .reg_data = c1_reg_data,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
+            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
+            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
+            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
+            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
+            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
+            .supply = supply
+            );
+
+
+    texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
+        core2(.in = fifo_dmx2core2.out,
+
+            .reg_data = c2_reg_data,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
+            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
+            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
+            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
+            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
+            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
+
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
+            .supply = supply
+            );
+
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
+   
+    // Merge cores
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
+    merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
+        .supply = supply, .reset_B = _reset_BX);
+
+    // Merge cores and loopback
+    merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
+        .reset_B = _reset_BX, .supply = supply);
+
+    // qdi2bd
+    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
+        .reset_B = _reset_BX, .supply = supply);
+    qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
+        .reset_B = _reset_BX, .supply = supply);
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+}
+}
+

dataflow_neuro/dummy.act

@@ -0,0 +1,94 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+/**
+ * Creates a synapse-neuron dummy block, 
+ * where any synapse being triggered makes the neuron "spike".
+ */
+export template<pint N_SYN>
+defproc dummy_neuron_block (a1of1 synapses[N_SYN], neuron; power supply){
+    // OR over reqs from syn in to neuron out
+    ortree<N_SYN> _ortree(.out = neuron.r, .supply = supply);
+    (i:N_SYN: _ortree.in[i] = synapses[i].r;)
+
+    // ANDs piping the ack back to the proper synapse
+
+    BUF_X12 nrn_ack_buf(.a = neuron.a, .vdd = supply.vdd, .vss = supply.vss);
+
+    AND2_X1 ands[N_SYN];
+    (i:N_SYN:
+        ands[i].a = nrn_ack_buf.y;
+        ands[i].b = synapses[i].r;
+        ands[i].y = synapses[i].a;
+
+        ands[i].vss = supply.vss;
+        ands[i].vdd = supply.vdd;
+    )
+}
+
+/**
+ * Create an array of neuron dummy blocks.
+ * Note that this is custom made for the indexing on the texel chip.
+ * And so should be reused *with care*.
+ */
+export template<pint N_SYN_PER_NRN, N_NRN, N_NRN_X>
+defproc dummy_neuron_core (a1of1 synapses[N_SYN_PER_NRN * N_NRN], neurons[N_NRN]; power supply){
+    dummy_neuron_block<N_SYN_PER_NRN> blocks[N_NRN];
+    pint Xn, Yn, Xs, Ys;
+    (i:N_NRN:
+        Yn = i/N_NRN_X;
+        Xn = i-Yn*N_NRN_X;
+        neurons[i] = blocks[i].neuron;
+        blocks[i].supply = supply;
+        (j:N_SYN_PER_NRN: // moron, need to think about neuron indexxing too
+            Xs = Xn;
+            Ys = Yn*N_SYN_PER_NRN + j;
+            blocks[i].synapses[j] = synapses[Ys*N_NRN_X + Xs];
+        )
+    )
+}
+
+
+
+
+}
+}

dataflow_neuro/dynapse.act

@@ -0,0 +1,66 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export
+defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
+	bool _en;
+	bool _out_a_B;
+
+	INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
+
+	A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_1C1P_X1 A_en(.c1 = in.a, .p1 =  out.r, .y = _en,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+}
+
+}
+}
+

dataflow_neuro/interfaces.act

@@ -0,0 +1,174 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import std::channel;
+open std::channel;
+
+// import std::func;
+open std;
+
+import std::data;
+open std::data;
+
+
+namespace tmpl {
+	namespace dataflow_neuro {
+
+		/**
+		 * Bundled data (non dual rail, with req)
+		 * 2
+		 * quasi delay insensitive channel (dual rail).
+		 * Basically a buffer with a bitwise conversion in front of it.
+		 */
+		export template<pint N, N_dly_cfg, N_dly_cfg2>
+		defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
+			power supply; bool? reset_B) {
+			
+			// Delay on req_in
+			bool _req;
+			delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
+
+			// sig buff the reset signal
+			bool _reset_BX, _reset_BXX[N*2];
+			BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+            sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
+
+            // sig buff the req
+			bool _reqX, _reqXX[N*2];
+			BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
+        	sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
+
+			// For reasons of pure spice, the control circuitry 
+			// requires a req signal that FALLS SLOWER than the req going to the function block.
+			// Thus need another delay prog.
+			bool _req_slowfall;
+			delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
+			OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
+				.vss = supply.vss, .vdd = supply.vdd);
+
+            // bd2qdi conversion
+            // Each line goes to a t pin, its not to an f.
+            bool _inB[N];
+            INV_X1 input_invs[N];
+            (i:N:
+            	input_invs[i].a = in.d[i];
+            	input_invs[i].y = _inB[i];
+            	input_invs[i].vss = supply.vss;
+            	input_invs[i].vdd = supply.vdd;
+            )
+
+			// BUFFER
+			// Basically the buffer_s but with the validity tree ripped out
+			// and just connected to in_req instead.
+
+			// And probably need a delay on the in_ack to ensure en has time to disable
+			// before the inputs go to another state.
+			// Actually apparently no: there is a fixed, huge delay, already incurred
+			// by communicating with pads-> uC -> windows 95 and back again.
+
+            // Since the input is never invalid, also need a mechanism
+            // for the output to become invalid, when an out_ack is received. 
+
+            //control
+            bool _en;
+            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+            A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
+
+            //function
+            bool _out_a_B;
+            A_2C2N_RB_X4 f_buf_func[N];
+            A_2C2N_RB_X4 t_buf_func[N];
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
+            INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
+            // check if you can also do single var to array connect a=b[N]
+            // and remove them from the loop
+            (i:N: 
+                f_buf_func[i].y=out.d.d[i].f;
+                t_buf_func[i].y=out.d.d[i].t;
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=out_a_B_buf.out[i];
+                t_buf_func[i].c2=out_a_B_buf.out[i+N];
+                f_buf_func[i].n1=_inB[i];
+                t_buf_func[i].n1=in.d[i];
+                f_buf_func[i].n2=_reqXX[i];
+                t_buf_func[i].n2=_reqXX[i+N];
+                f_buf_func[i].vdd=supply.vdd;
+                t_buf_func[i].vdd=supply.vdd;
+                f_buf_func[i].vss=supply.vss;
+                t_buf_func[i].vss=supply.vss;
+                t_buf_func[i].pr_B = _reset_BXX[i];
+                t_buf_func[i].sr_B = _reset_BXX[i];
+                f_buf_func[i].pr_B = _reset_BXX[i+N];
+                f_buf_func[i].sr_B = _reset_BXX[i+N];
+            )
+
+		}
+
+
+		
+		/**
+		 * quasi delay insensitive channel (dual rail).
+		 * 2
+		 * Bundled data (non dual rail, with req)
+		 */
+		export template<pint N, N_dly_cfg>
+		defproc qdi2bd(avMx1of2<N> in; bd<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
+
+            // Buffer
+            buffer<N> buf(.in = in, .supply = supply, .reset_B = reset_B);
+            buf.out.a = out.a;
+            
+            // Vtree
+            vtree<N> out_vtree(.supply = supply);
+            (i:N:
+            	out_vtree.in.d[i].t = buf.out.d.d[i].t;
+            	out_vtree.in.d[i].f = buf.out.d.d[i].f;
+            )
+            buf.out.v = out_vtree.out;
+
+            // Delay
+            delayprog<N_dly_cfg> dly(.in = out_vtree.out, .out = out.r, .s = dly_cfg, .supply = supply);
+            out_vtree.out = dly.in;
+
+            // Wire output data bits to buffer True lines
+            (i:N:
+            	buf.out.d.d[i].t = out.d[i];
+            )
+
+		}
+
+
+
+	}
+
+}

dataflow_neuro/primitives.act

@@ -33,6 +33,9 @@ import "../../dataflow_neuro/treegates.act";
 import std::channel;
 open std::channel;
 
+// import std::func;
+
+
 namespace tmpl {
     namespace dataflow_neuro {
 
@@ -75,8 +78,8 @@ namespace tmpl {
               [(&i:M: d.d[i].t | d.d[i].f)];
               self := 0;
               (;i:M: [ d.d[i].t -> self := self | (1 << i)
-        	     [] else -> skip
-        	     ]
+               [] else -> skip
+               ]
               )
             }
         
@@ -108,37 +111,35 @@ namespace tmpl {
         export template<pint N>
         defproc buffer (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
             //control
-            bool _en, _reset_BX,_reset_BXX[N];
+            bool _en, _reset_BX,_reset_BXX[N*2];
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
 
 
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-	          sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
-	    
+            sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
+      
             //validity
             bool _in_v;
             vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
             BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
             
             //function
-            bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
+            bool _out_a_BX[N*2],_out_a_B;
             A_2C1N_RB_X4 f_buf_func[N];
             A_2C1N_RB_X4 t_buf_func[N];
-            sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
-            sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
-            INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
+            INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B,.out=_out_a_BX, .supply = supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
                 f_buf_func[i].y=out.d.d[i].f;
                 t_buf_func[i].y=out.d.d[i].t;
-                f_buf_func[i].c1=_en_X_f[i];
-                t_buf_func[i].c1=_en_X_t[i];
-                f_buf_func[i].c2=_out_a_BX_f[i];
-                t_buf_func[i].c2=_out_a_BX_t[i];
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=_out_a_BX[i];
+                t_buf_func[i].c2=_out_a_BX[i+N];
                 f_buf_func[i].n1=in.d.d[i].f;
                 t_buf_func[i].n1=in.d.d[i].t;
                 f_buf_func[i].vdd=supply.vdd;
@@ -147,8 +148,8 @@ namespace tmpl {
                 t_buf_func[i].vss=supply.vss;
                 t_buf_func[i].pr_B = _reset_BXX[i];
                 t_buf_func[i].sr_B = _reset_BXX[i];
-                f_buf_func[i].pr_B = _reset_BXX[i];
-                f_buf_func[i].sr_B = _reset_BXX[i];
+                f_buf_func[i].pr_B = _reset_BXX[i+N];
+                f_buf_func[i].sr_B = _reset_BXX[i+N];
             )
         }
         // A template creating a FIFO of M buffers with N bits each
@@ -165,7 +166,7 @@ namespace tmpl {
             fifo_element[i].supply = supply;
             fifo_element[i].reset_B = _reset_BXX[i];
           )
-          fifo_element[N-1].out = out;
+          fifo_element[M-1].out = out;
 
           // reset buffers
           bool _reset_BX;
@@ -193,33 +194,31 @@ namespace tmpl {
             sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
         
             //validity
-            bool _in_v, _in_vX[N];
+            bool _in_v;
             vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
             BUF_X4 in_v_buf4(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N> in_v_bufN(.in = in.v, .out = _in_vX, .supply = supply);
+            sigbuf<N*2> in_v_bufN(.in = in.v, .supply = supply);
 
             //function
-            bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
+            bool _out_a_B;
             A_2C2N_RB_X4 f_buf_func[N];
             A_2C2N_RB_X4 t_buf_func[N];
-            sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
-            sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
-            INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
-            sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
-            sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
+            sigbuf<N*2> en_buf(.in=_en, .supply=supply);
+            INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
+            sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
             // check if you can also do single var to array connect a=b[N]
             // and remove them from the loop
             (i:N: 
                 f_buf_func[i].y=out.d.d[i].f;
                 t_buf_func[i].y=out.d.d[i].t;
-                f_buf_func[i].c1=_en_X_f[i];
-                t_buf_func[i].c1=_en_X_t[i];
-                f_buf_func[i].c2=_out_a_BX_f[i];
-                t_buf_func[i].c2=_out_a_BX_t[i];
+                f_buf_func[i].c1=en_buf.out[i];
+                t_buf_func[i].c1=en_buf.out[i+N];
+                f_buf_func[i].c2=out_a_B_buf.out[i];
+                t_buf_func[i].c2=out_a_B_buf.out[i+N];
                 f_buf_func[i].n1=in.d.d[i].f;
                 t_buf_func[i].n1=in.d.d[i].t;
-                f_buf_func[i].n2=_in_vX[i];
-                t_buf_func[i].n2=_in_vX[i];
+                f_buf_func[i].n2=in_v_bufN.out[i];
+                t_buf_func[i].n2=in_v_bufN.out[i+N];
                 f_buf_func[i].vdd=supply.vdd;
                 t_buf_func[i].vdd=supply.vdd;
                 f_buf_func[i].vss=supply.vss;
@@ -230,7 +229,9 @@ namespace tmpl {
                 f_buf_func[i].sr_B = _reset_BXX[i];
             )
         }
-    
+        
+        // Note that in token false/0 is send on out1, true/1 is send on out2.
+        // test
         export template<pint N>
         defproc demux (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; avMx1of2<1> cond; power supply) {
             //control
@@ -238,6 +239,9 @@ namespace tmpl {
             
             OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+            cond.a = in.a; // @TODO THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
+            // actually it might be fine 
+            cond.v = _in_c_v_;
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
@@ -256,21 +260,19 @@ namespace tmpl {
             
             //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C2N_RB_X4 out1_f_buf_func[N];
             A_2C2N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
-            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
+            sigbuf<N*4> out_en_buf(.in=_en, .supply=supply);
+            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vdd = supply.vdd, .vss = supply.vss);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out_en_buf.out[i];
+                out1_t_buf_func[i].c1=out_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -281,38 +283,36 @@ namespace tmpl {
                 out1_t_buf_func[i].sr_B = _reset_BXX[i];
                 out1_f_buf_func[i].pr_B = _reset_BXX[i];
                 out1_f_buf_func[i].sr_B = _reset_BXX[i];
-                out1_f_buf_func[i].n2=_c_t_buf[i];
-                out1_t_buf_func[i].n2=_c_t_buf[i];
+                out1_f_buf_func[i].n2=_c_f_buf[i];
+                out1_t_buf_func[i].n2=_c_f_buf[i];
             )
 
             //func buffer out2
-            bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
+            bool _out2_a_B;
             A_2C2N_RB_X4 out2_f_buf_func[N];
             A_2C2N_RB_X4 out2_t_buf_func[N];
-            sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
-            sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
-            INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
-            sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
-            sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
+            // sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
+            INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B, .vdd = supply.vdd, .vss = supply.vss);
+            sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
             (i:N: 
                 out2_f_buf_func[i].y=out2.d.d[i].f;
                 out2_t_buf_func[i].y=out2.d.d[i].t;
-                out2_f_buf_func[i].c1=_en2_X_f[i];
-                out2_t_buf_func[i].c1=_en2_X_t[i];
-                out2_f_buf_func[i].c2=_out2_a_BX_f[i];
-                out2_t_buf_func[i].c2=_out2_a_BX_t[i];
+                out2_f_buf_func[i].c1=out_en_buf.out[i+2*N];
+                out2_t_buf_func[i].c1=out_en_buf.out[i+3*N];
+                out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
+                out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
                 out2_f_buf_func[i].n1=in.d.d[i].f;
                 out2_t_buf_func[i].n1=in.d.d[i].t;
                 out2_f_buf_func[i].vdd=supply.vdd;
                 out2_t_buf_func[i].vdd=supply.vdd;
                 out2_f_buf_func[i].vss=supply.vss;
                 out2_t_buf_func[i].vss=supply.vss;
-                out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].n2=_c_f_buf[i];
-                out2_t_buf_func[i].n2=_c_f_buf[i];
+                out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
+                out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
+                out2_f_buf_func[i].n2=_c_t_buf[i];
+                out2_t_buf_func[i].n2=_c_t_buf[i];
             )
         }
 
@@ -337,21 +337,19 @@ namespace tmpl {
 
           //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C1N_RB_X4 out1_f_buf_func[N];
             A_2C1N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
+            sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
             INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out1_en_buf.out[i];
+                out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -364,60 +362,65 @@ namespace tmpl {
                 out1_f_buf_func[i].sr_B = _reset_BXX[i];
             )
             //func buffer out2
-            bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N];
+            bool _out2_a_B;
             A_2C1N_RB_X4 out2_f_buf_func[N];
             A_2C1N_RB_X4 out2_t_buf_func[N];
-            sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
-            sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
+            sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
             INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
-            sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
-            sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
+            sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
             (i:N: 
                 out2_f_buf_func[i].y=out2.d.d[i].f;
                 out2_t_buf_func[i].y=out2.d.d[i].t;
-                out2_f_buf_func[i].c1=_en2_X_f[i];
-                out2_t_buf_func[i].c1=_en2_X_t[i];
-                out2_f_buf_func[i].c2=_out2_a_BX_f[i];
-                out2_t_buf_func[i].c2=_out2_a_BX_t[i];
+                out2_f_buf_func[i].c1=out2_en_buf.out[i];
+                out2_t_buf_func[i].c1=out2_en_buf.out[i+N];
+                out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
+                out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
                 out2_f_buf_func[i].n1=in.d.d[i].f;
                 out2_t_buf_func[i].n1=in.d.d[i].t;
                 out2_f_buf_func[i].vdd=supply.vdd;
                 out2_t_buf_func[i].vdd=supply.vdd;
                 out2_f_buf_func[i].vss=supply.vss;
                 out2_t_buf_func[i].vss=supply.vss;
-                out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
+                out2_t_buf_func[i].pr_B = _reset_BXX[i];
+                out2_t_buf_func[i].sr_B = _reset_BXX[i];
+                out2_f_buf_func[i].pr_B = _reset_BXX[i];
+                out2_f_buf_func[i].sr_B = _reset_BXX[i];
             )
         }
         
-        
+        // Demux 
         export template<pint N; pbool CONDITION_SIGN>
-        defproc demux_td (avMx1of2<N> in; avMx1of2<N> out1; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
+        // @TODO docs
+        // also note this is not used in the final texel chip
+        defproc demux_td (avMx1of2<N> in; avMx1of2<N> out; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
             //control
             bool _en, _reset_BX,_reset_BXX[N], _out_v, _in_c_v_, _reset_BXt;
+            avMx1of2<N> out1 = out;
+
             
             OR2_X1 out_or(.a=out1.v, .b=token.r, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
             A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
             BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             BUF_X1 reset_buf_token(.a=_reset_BX, .y=_reset_BXt,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
+            sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
             //validity
             bool _in_v, _c_tk_buf, _c_d_buf[N], _c_v, cond_inv_t, cond_inv_f;
+
+
+            cond.a = in.a;
+            cond.v = _c_v;
             
             OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
             
             //orientation of condition
             [ CONDITION_SIGN ->
-            BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf);
-            sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf);
+            BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
+            sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf, .supply=supply);
             [] else ->
-            INV_X1 invout_t(.a = cond.d.d[0].t,.y=cond_inv_t,.vdd = supply.vdd,.vss=supply.vss);
-            INV_X1 invout_f(.a = cond.d.d[0].f,.y=cond_inv_f,.vdd = supply.vdd,.vss=supply.vss);
-            BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf);
-            sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf);
+            
+            BUF_X1 c_buf_tk(.a=cond.d.d[0].f, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
+            sigbuf<N> c_buf_d(.in=cond.d.d[0].t, .out=_c_d_buf, .supply=supply);
             ]
 
             
@@ -429,21 +432,19 @@ namespace tmpl {
             
             //function
             //func buffer out1
-            bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N];
+            bool _out1_a_B;
             A_2C2N_RB_X4 out1_f_buf_func[N];
             A_2C2N_RB_X4 out1_t_buf_func[N];
-            sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
-            sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
-            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
-            sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t);
-            sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f);
+            sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
+            INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vss = supply.vss, .vdd = supply.vdd);
+            sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
             (i:N: 
                 out1_f_buf_func[i].y=out1.d.d[i].f;
                 out1_t_buf_func[i].y=out1.d.d[i].t;
-                out1_f_buf_func[i].c1=_en1_X_f[i];
-                out1_t_buf_func[i].c1=_en1_X_t[i];
-                out1_f_buf_func[i].c2=_out1_a_BX_f[i];
-                out1_t_buf_func[i].c2=_out1_a_BX_t[i];
+                out1_f_buf_func[i].c1=out1_en_buf.out[i];
+                out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
+                out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
+                out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
                 out1_f_buf_func[i].n1=in.d.d[i].f;
                 out1_t_buf_func[i].n1=in.d.d[i].t;
                 out1_f_buf_func[i].vdd=supply.vdd;
@@ -462,7 +463,8 @@ namespace tmpl {
            
           bool token_a_out;
           A_2C2N_RB_X4 token_buf;
-          INV_X1 outt_a_inv(.a=token.a,.y=token_a_out);
+          INV_X1 outt_a_inv(.a=token.a,.y=token_a_out, .vss = supply.vss, .vdd = supply.vdd);
+
           
           token_buf.y = token.r;
           token_buf.c1 = _en;
@@ -475,6 +477,64 @@ namespace tmpl {
           token_buf.pr_B = _reset_BXt;
           token_buf.sr_B = _reset_BXt;
         }
+
+        /** 
+         * Drops a packet if condition is met, otherwise passes it on.
+         * This is a very lazy implementation, where the cond MUST NOT CHANGE DURING OPERATION.
+         * Means that this should be used in a very small set of circumstances.
+         * 
+         * params:
+         * N: size of packet
+         * CONDITION_DROP: value of cond when packets are dropped.
+         */
+        export template<pint N; pbool CONDITION_DROP>
+        defproc dropper_static (avMx1of2<N> in; avMx1of2<N> out; bool? cond; power supply) {
+            bool _drop, _dropB;
+            INV_X1 inv(.a = cond, .vss = supply.vss, .vdd = supply.vdd);
+
+            [~CONDITION_DROP ->
+                _dropB = cond;
+                _drop = inv.y;
+            [] CONDITION_DROP ->
+                _drop = cond;
+                _dropB = inv.y;
+            ]
+
+            bool _in_vX;
+            vtree<N> vt(.in = in.d, .supply = supply);
+            BUF_X4 in_v_buf(.a = vt.out, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
+            AND2_X1 and2(.a = _drop, .b = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
+            OR2_X1 or2(.a = out.a, .b = and2.y, .vss = supply.vss, .vdd = supply.vdd);
+            A_2C_B_X1 ack_Cel(.c1 = or2.y, .c2 = _in_vX, .y = in.a);
+            // _in_vX = in.v;
+
+            // Sigbufs
+            sigbuf<N*2> sb_dropB(.in = _dropB, .supply = supply);
+            sigbuf<N*2+1> sb_in_v(.in = _in_vX, .supply = supply);
+            sb_in_v.out[2*N] = in.v;
+
+            AND3_X1 and_t[N];
+            AND3_X1 and_f[N];
+            (i:N:
+                and_t[i].a = in.d.d[i].t;
+                and_f[i].a = in.d.d[i].f;
+
+                and_t[i].y = out.d.d[i].t;
+                and_f[i].y = out.d.d[i].f;
+                
+                and_t[i].b = sb_dropB.out[i];
+                and_f[i].b = sb_dropB.out[i+N];
+
+                and_t[i].c = sb_in_v.out[i];
+                and_f[i].c = sb_in_v.out[i+N];
+
+                and_t[i].vss = supply.vss;
+                and_t[i].vdd = supply.vdd;
+            )
+
+
+
+        }
         
         
         export 
@@ -489,23 +549,25 @@ namespace tmpl {
           
         }
         //The buffer_t_valid doesn't work
-        export 
-        defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
-        {
-            //control
-            bool _en, _reset_BX;
-            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-            A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
+        // export 
+        // defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
+        // {
+        //     //control
+        //     bool _en, _reset_BX;
+        //     A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+        //     A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
             
-            //function
-            bool _out_a_B;
-            INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
-            A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
+        //     //function
+        //     bool _out_a_B;
+        //     INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
+        //     A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
 
             
-            //reset buffers
-            BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-        }
+        //     //reset buffers
+        //     BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+        // }
+
+        
 
         export template<pint N>
         defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
@@ -520,7 +582,7 @@ namespace tmpl {
           bool _in1_arb,_in2_arb,_in1_arb_X[2*N],_in2_arb_X[2*N];
           A_4C_RB_X4 in1ack_ctl(.c1=_in1_arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
           A_4C_RB_X4 in2ack_ctl(.c1=_in2_arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-          A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .n1 = in1.a,.n2 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
+          A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .na1 = in1.a,.nb1 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
           sigbuf<2*N> en_buffer(.in = _en,.out = _en_X,.supply=supply);
           INV_X1 in1ack_ctl_inv(.a=in1.a,.y=_in1_a_B,.vdd=supply.vdd,.vss=supply.vss);
           INV_X1 in2ack_ctl_inv(.a=in2.a,.y=_in2_a_B,.vdd=supply.vdd,.vss=supply.vss);
@@ -551,10 +613,10 @@ namespace tmpl {
           (i:N: 
             merge_func_t[i].c1 = _en_X[i];
             merge_func_t[i].c2 = _out_a_BX[i];
-            merge_func_t[i].n1 = _in1_arb_X[i];
-            merge_func_t[i].n2 = in1.d.d[i].t;
-            merge_func_t[i].n3 = _in2_arb_X[i];
-            merge_func_t[i].n4 = in2.d.d[i].t;
+            merge_func_t[i].na1 = _in1_arb_X[i];
+            merge_func_t[i].na2 = in1.d.d[i].t;
+            merge_func_t[i].nb1 = _in2_arb_X[i];
+            merge_func_t[i].nb2 = in2.d.d[i].t;
             merge_func_t[i].y = out.d.d[i].t;
             merge_func_t[i].vdd=supply.vdd;
             merge_func_t[i].vss=supply.vss;
@@ -563,10 +625,10 @@ namespace tmpl {
 
             merge_func_f[i].c1 = _en_X[i+N];
             merge_func_f[i].c2 = _out_a_BX[i+N];
-            merge_func_f[i].n1 = _in1_arb_X[i+N];
-            merge_func_f[i].n2 = in1.d.d[i].f;
-            merge_func_f[i].n3 = _in2_arb_X[i+N];
-            merge_func_f[i].n4 = in2.d.d[i].f;
+            merge_func_f[i].na1 = _in1_arb_X[i+N];
+            merge_func_f[i].na2 = in1.d.d[i].f;
+            merge_func_f[i].nb1 = _in2_arb_X[i+N];
+            merge_func_f[i].nb2 = in2.d.d[i].f;
             merge_func_f[i].y = out.d.d[i].f;
             merge_func_f[i].vdd=supply.vdd;
             merge_func_f[i].vss=supply.vss;
@@ -614,18 +676,27 @@ namespace tmpl {
           // reset buffers
           bool _reset_BX;
           BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-          sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX; power supply);
+          sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply = supply);
         }
 
         // Programmable delay line.
         // N is the number of layers,
         // the longest layer having 2**N DLY elements
+        // Circuit for creating delays, there are N delay layers.  
+        // The block has the parameters:
+        // N -> the number is the number of layers with the longest being 2**N elements
+        // wl -> word length, length of each word 
+        // N_dly_cfg -> the number of config bits in the ACK delay line
+        // The block has the pins:
+        // in -> input data
+        // out -> output data
+        // s -> bit word with size N that sets delay configuration. int(s) = number of delays
         export template<pint N>
-        defproc delayprog (bool! y; bool? a, s[N]; power supply)
+        defproc delayprog (bool! out; bool? in, s[N]; power supply)
         {
             
             { N >= 0 : "What?" };
-            { N < 9 : "Delay prog size is given in 2**N. Given N is too big." };
+            { N < 10 : "Delay prog size is given in 2**N. Given N is ridiculous." };
 
 
             AND2_X1 and2[N];
@@ -634,7 +705,7 @@ namespace tmpl {
 
             bool _a[N+1]; // Holds the input to each row
          
-            _a[0] = a;
+            _a[0] = in;
 
             pint i_delay;
             i_delay = 0; // Index of the last connected delay element
@@ -647,7 +718,7 @@ namespace tmpl {
                 // Delays
                 dly[i_delay].a = and2[i].y;
                 i_delay = i_delay + 1;
-                (j:1..i-1:
+                (j:1..(1<<i)-1:
                     dly[i_delay].a = dly[i_delay-1].y;
                     i_delay = i_delay +1;
                 )
@@ -659,7 +730,7 @@ namespace tmpl {
                 _a[i+1] = mu2[i].y;
             )
 
-            y = mu2[N-1].y;
+            out = mu2[N-1].y;
 
 
             // Connect everything to vdd/gnd
@@ -671,4 +742,177 @@ namespace tmpl {
             (i:N:mu2[i].vss = supply.vss;)
             (i:((1<<N)-1):dly[i].vss = supply.vss;)
         }
+
+        // Non programmable delays
+        // N is number of delays to have in series (not log!!).
+        // Is useful for testing purposes.
+        // But should probably remove before running innovus etc.
+        export template<pint N>
+        defproc delay_chain (bool out; bool in; power supply) {
+            { N >= 0 : "What?" };
+            [N >= 1 ->
+              DLY4_X1 dly[N];
+
+              dly[0].vdd = supply.vdd;
+              dly[0].vss = supply.vss;
+              dly[0].a = in;
+
+              (i:1..N-1:
+                  dly[i].vdd = supply.vdd;
+                  dly[i].vss = supply.vss;
+                  dly[i].a = dly[i-1].y;
+              )
+
+              dly[N-1].vdd = supply.vdd;
+              dly[N-1].vss = supply.vss;
+              dly[N-1].y = out;
+            [] N = 0 ->
+              in = out;
+            ]
+            
+        }
+
+
+        /**
+         * Appends a hard-coded word "VAL" to an input.
+         * Works by piping through all sigs, but adding
+         * some extra sigs when the input is valid.
+         * N is size of channel to pipe through.
+         * NVAL is size of word to be put on output.
+         * VAL is word to be put on output.
+         * Output looks like
+         * 0..............N........N+NVAL-1
+         * --input_data----LSB....MSB
+         *
+         */
+        export template<pint N, NVAL, VAL>
+        defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
+        {
+            { N >= 0 : "What?" };
+            { NVAL >= 0 : "What?" };
+            { VAL < 1<<NVAL : "VAL too big!" };
+
+            // valid tree
+            vtree<N> in_val(.supply = supply);
+            (i:N:
+                in_val.in.d[i].t = in.d.d[i].t;
+                in_val.in.d[i].f = in.d.d[i].f;
+            )
+
+            // wire through most signals
+            (i:N:
+                in.d.d[i].t = out.d.d[i].t;
+                in.d.d[i].f = out.d.d[i].f;
+            )
+            in.a = out.a;
+            in.v = out.v;
+
+            // appender
+            pint bitval;
+            sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
+            TIELO_X1 tielows[NVAL];
+            (i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
+            (i:0..NVAL-1:
+                bitval = (VAL & ( 1 << i )) >> i;
+                [  bitval = 1 ->
+                    out.d.d[i+N].t = sb.out[i];
+                    out.d.d[i+N].f = tielows[i].y;
+                [] bitval = 0 ->
+                    out.d.d[i+N].f = sb.out[i];
+                    out.d.d[i+N].t = tielows[i].y;
+                [] bitval >= 2 -> {false : "fuck"};        
+                ]
+            )
+
+        }
+/**
+* Drops bits. Slices lines. Crop in. Enhance.
+* Useful if say, have an 8 bit packet coming in, but 
+* receiver only needs 3 of them.
+* KEEPS all bits between the two bounds.
+* e.g. drop_lines(8, 0, 3) would keep lines [0,1,2]
+**/
+export template<pint N, N0, N1>
+defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out; power supply) {
+    // {N0 >= 0 : "N0 can be minimum 0!"};
+    // {N1 <= N : "N1 can be maximum N"};
+
+    pint _N1, _N0;
+
+    _N1 = std::min(N1,N);
+    _N0 = std::max(N0,0);
+
+    [_N0 = 0 & _N1 = N ->
+      in = out;
+    [] _N0 != 0 | _N1 != N ->
+
+      vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
+      (i:_N1-_N0:
+          in.d.d[i + _N0] = out.d.d[i];
+      )
+
+      // in.a = out.a;
+
+      A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
+
+    ]
+
+
+
+}
+
+  // this is a wrapper for the demux, such that the condition bit is absorbed into the data
+  // and demux msb is just defaulting it to the msb
+  export template<pint N; pint CONDITION_BIT>
+        defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
+        {
+            demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
+
+            in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
+            in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
+
+            A_2C_B_X1 val_Cel(.c1 = demux.in.v, .c2 = demux.cond.v, .y = in.v,
+                .vdd = supply.vdd, .vss = supply.vss);
+
+            // Not actually needed bc the current version of demux
+            // Something like below should be added once the handshakes are properly decoupled.
+            // wires the data and cond ack lines together anyway.
+            // A_2C_B_X1 ack_Cel(.c1 = demux.in.a, .c2 = demux.cond.a, .y = in.a,
+            //     .vdd = supply.vdd, .vss = supply.vss);
+
+            // in.v = demux.in.v;
+            in.a = demux.in.a;
+
+            (i:0..CONDITION_BIT-1:
+                in.d.d[i].f = demux.in.d.d[i].f;
+                in.d.d[i].t = demux.in.d.d[i].t;)
+
+            (i:CONDITION_BIT+1..N:
+                in.d.d[i].f = demux.in.d.d[i-1].f;
+                in.d.d[i].t = demux.in.d.d[i-1].t;)
+
+        }
+
+      export template<pint N>
+        defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
+        {
+            demux_bit<N,N> demux(.in = in, .out1 = out1, .out2 = out2, .reset_B = reset_B, .out1=out1, .out2=out2);
+        }
+
+/**
+* Create M sigbufs to buffer an M bool array to N strength.
+* Done lazily.
+**/
+export template<pint M, N>
+defproc sigbuf_boolarray(bool? in[M]; bool! out[M]; power supply) {
+    sigbuf<N> sb[M];
+    (i:M:
+        sb[i].in = in[i];
+        sb[i].out[0] = out[i];
+        sb[i].supply = supply;
+    )
+
+}
+
+
 }}

dataflow_neuro/registers.act

@@ -0,0 +1,352 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/coders.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+/**
+ * A single register made out of A cells.
+ * MSB is whether to read or write.
+ * Currently only handles writing.
+ * NOTE: this does not handle in.v properly, and instead has in.v = in.a
+ */
+ //@TODO Get rid of scarying warning
+export template<pint N>
+defproc register_acells_improved(avMx1of2<N+1> in; Mx1of2<N> out;
+    bool? reset_B; power supply) {
+
+bool _resetX[N], _reset_BX[N];
+bool _en, _enBX;
+bool _flush, _flushBX;
+bool _out_v, _out_vB;
+bool _w = in.d.d[N].t;
+
+INV_X2 out_val_inv(.a = _out_v, .y = _out_vB,
+    .vdd = supply.vdd, .vss= supply.vss);
+
+// Reset sigs
+INV_X1 reset_inv(.a = reset_B, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N> reset_sb(.in = reset_inv.y, .out = _resetX, .supply = supply);
+sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
+
+A_2C1N_RB_X1 A_flush(.c1 = _en, .c2 = _out_v, .n1 = _w, .y = _flush,
+    .vdd = supply.vdd, .vss = supply.vss, .pr_B = _reset_BX[0], .sr_B = _reset_BX[0]);
+
+A_2C_X1 A_en(.c1  = _w, .c2 = _out_vB, .y = _en,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+INV_X1 flush_inv(.a = _flush, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_flushB(.in = flush_inv.y, .supply = supply);
+sb_flushB.out[0] = _flushBX;
+
+INV_X1 en_inv(.a = _en, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_enB(.in = en_inv.y, .supply = supply);
+sb_enB.out[0] = _enBX;
+
+vtree<N> vc(.in = out, .out = _out_v, .supply = supply);
+
+// WARNING WARNING
+in.v = in.a;
+
+A_1C1P_X1 A_ack(.c1 = _en, .p1 = _out_vB, .y = in.a,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+//function
+A_2C1N_SB_X4 f_buf_func[N];
+A_2C1N_RB_X4 t_buf_func[N];
+(i:N: 
+    f_buf_func[i].y=out.d[i].f;
+    t_buf_func[i].y=out.d[i].t;
+
+    f_buf_func[i].c1=_flushBX;
+    t_buf_func[i].c1=_flushBX;
+
+    f_buf_func[i].c2=_enBX;
+    t_buf_func[i].c2=_enBX;
+    
+    f_buf_func[i].n1=in.d.d[i].f;
+    t_buf_func[i].n1=in.d.d[i].t;
+
+    f_buf_func[i].vdd=supply.vdd;
+    t_buf_func[i].vdd=supply.vdd;
+    f_buf_func[i].vss=supply.vss;
+    t_buf_func[i].vss=supply.vss;
+    
+    f_buf_func[i].pr = _resetX[i];
+    f_buf_func[i].sr = _resetX[i];
+    t_buf_func[i].pr_B = _reset_BX[i];
+    t_buf_func[i].sr_B = _reset_BX[i];
+)
+
+}
+
+
+
+
+/** 
+ * Array of registers made out of A-cells
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * [-addr-][-word-][r/w]
+ */
+export template<pint NcA, NcW, M>
+defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
+    bool? reset_B; power supply) {
+
+
+// Input valid tree
+vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+bool _write_ack;
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+// Bit to join the acks either from read or write
+bool _read_ack;
+_read_ack = out.a;
+OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
+    .vdd = supply.vdd, .vss = supply.vss);
+A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
+
+// Write bit selector
+bool _w = in.d.d[NcA+NcW].t;
+bool _wX[M];
+sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
+A_2C_B_X1 write_selectors[M];
+(i:M:
+    write_selectors[i].c1 = _wX[i];
+    write_selectors[i].c2 = decoder.out[i];
+    write_selectors[i].vdd = supply.vdd;
+    write_selectors[i].vss = supply.vss;
+)
+
+
+// Registers
+register_acells_improved<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
+    )
+
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcW].t = write_selectors[i].y;
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
+
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
+
+    // Connect outputs
+    data[i] = registers[i].out;
+
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+// Read bit selector
+bool _r = in.d.d[NcA+NcW].f;
+bool _rX[M+NcA];
+sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
+A_2C_B_X1 read_selectors[M];
+sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
+(i:M:
+    read_selectors[i].c1 = _rX[i];
+    read_selectors[i].c2 = decoder.out[i];
+    read_selectors[i].vdd = supply.vdd;
+    read_selectors[i].vss = supply.vss;
+
+    read_selectorsX.in[i] = read_selectors[i].y;
+)
+
+// OrTrees for each output word bit on read
+ortree<M> out_ortrees_t[NcW];
+ortree<M> out_ortrees_f[NcW];
+(i:NcW:
+    out_ortrees_t[i].out = out.d.d[i+NcA].t;
+    out_ortrees_f[i].out = out.d.d[i+NcA].f;
+
+    out_ortrees_t[i].supply = supply;
+    out_ortrees_f[i].supply = supply;
+)
+
+// ANDs over each reg's data
+// and whether it is selected for read.
+AND2_X1 and_reads_t[NcW * M];
+AND2_X1 and_reads_f[NcW * M];
+pint index;
+(i:NcW:
+    (j:M:
+        index = i + j*NcW;
+
+        and_reads_t[index].a = data[j].d[i].t;
+        and_reads_t[index].b = read_selectorsX.out[j];
+        and_reads_f[index].a = data[j].d[i].f;
+        and_reads_f[index].b = read_selectorsX.out[j];
+
+        and_reads_t[index].y = out_ortrees_t[i].in[j];
+        and_reads_f[index].y = out_ortrees_f[i].in[j];
+
+        and_reads_t[index].vss = supply.vss;
+        and_reads_t[index].vdd = supply.vdd;
+        and_reads_f[index].vss = supply.vss;
+        and_reads_f[index].vdd = supply.vdd;
+    )
+
+)
+
+// C elements passing address to out on read.
+A_2C_B_X1 addr_read_t[NcA];
+A_2C_B_X1 addr_read_f[NcA];
+(i:NcA:
+    addr_read_t[i].c1 = in.d.d[i].t;
+    addr_read_f[i].c1 = in.d.d[i].f;
+
+    addr_read_t[i].c2 = _rX[M+i];
+    addr_read_f[i].c2 = _rX[M+i];
+
+    addr_read_t[i].y = out.d.d[i].t;
+    addr_read_f[i].y = out.d.d[i].f;
+
+    addr_read_t[i].vdd = supply.vdd;
+    addr_read_t[i].vss = supply.vss;
+    addr_read_f[i].vdd = supply.vdd;
+    addr_read_f[i].vss = supply.vss;
+
+
+)
+
+
+
+}
+
+
+
+
+
+
+/** 
+ * Array of registers made out of A-cells.
+ * !!!Registers ONLY have write functionality!!!
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * LSB [-addr-][-word-] MSB
+ */
+ //@TODO check if it is used
+export template<pint NcA, NcW, M>
+defproc register_w_array(avMx1of2<NcA + NcW> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
+    bool? reset_B; power supply) {
+
+
+// Input valid tree
+vtree<NcA + NcW> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+bool _write_ack;
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+A_2C_B_X1 ack_safety(.c1 = _write_ack, .c2 = in.v, .y = in.a);
+
+
+// Registers
+register_acells_improved<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
+    )
+
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcW].t = decoder.out[i];
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
+
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
+
+    // Connect outputs
+    data[i] = registers[i].out;
+
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+
+}
+
+
+
+
+}}
+

dataflow_neuro/treegates.act

@@ -26,6 +26,7 @@
  **************************************************************************/
 import "../../dataflow_neuro/cell_lib_async.act";
 import "../../dataflow_neuro/cell_lib_std.act";
+
 import std::channel;
 open std::channel;
 namespace tmpl {
@@ -47,6 +48,9 @@ defproc ortree (bool? in[N]; bool! out; power supply)
 
   { N > 0 : "What?" };
 
+  [N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
+  []  N > 1 ->
+
   pint i, end, j;
   i = 0;
   end = N-1;
@@ -83,18 +87,18 @@ defproc ortree (bool? in[N]; bool! out; power supply)
   /* array to hold the actual C-elments, either A2C or A3C */
   
   [lenTree2Count > 0 ->
-    OR2_X1 C2Els[lenTree2Count];
+    OR2_X1 or2s[lenTree2Count];
   ]
   
   [lenTree3Count > 0 ->
-    OR3_X1 C3Els[lenTree3Count];
+    OR3_X1 or3s[lenTree3Count];
   ]
   
-  (h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
-  (h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
+  (h:lenTree2Count:or2s[h].vdd = supply.vdd;)
+  (h:lenTree3Count:or3s[h].vdd = supply.vdd;)
 
-  (h:lenTree2Count:C2Els[h].vss = supply.vss;)
-  (h:lenTree3Count:C3Els[h].vss = supply.vss;)
+  (h:lenTree2Count:or2s[h].vss = supply.vss;)
+  (h:lenTree3Count:or3s[h].vss = supply.vss;)
 
   /* Reset the variables we just stole lol */
   i = 0;
@@ -117,25 +121,25 @@ defproc ortree (bool? in[N]; bool! out; power supply)
         j = j + 1;
         [ i+1 >= end ->
           /*-- last piece: use either a 2 input C-element --*/
-          C2Els[tree2Index].a = tmp[i];
-          C2Els[tree2Index].b = tmp[i+1];
-          C2Els[tree2Index].y = tmp[end+j];
+          or2s[tree2Index].a = tmp[i];
+          or2s[tree2Index].b = tmp[i+1];
+          or2s[tree2Index].y = tmp[end+j];
           tree2Index = tree2Index +1;
           i = end;
         [] i+2 >= end ->
           /*-- last piece: use either a 3 input C-element --*/
-          C3Els[tree3Index].a = tmp[i];
-          C3Els[tree3Index].b = tmp[i+1];
-          C3Els[tree3Index].c = tmp[i+2];
-          C3Els[tree3Index].y = tmp[end+j];
+          or3s[tree3Index].a = tmp[i];
+          or3s[tree3Index].b = tmp[i+1];
+          or3s[tree3Index].c = tmp[i+2];
+          or3s[tree3Index].y = tmp[end+j];
 
           tree3Index = tree3Index +1;
           i = end;
         [] else ->
           /*-- more to come; so use a two input C-element --*/
-          C2Els[tree2Index].a = tmp[i];
-          C2Els[tree2Index].b = tmp[i+1];
-          C2Els[tree2Index].y = tmp[end+j];
+          or2s[tree2Index].a = tmp[i];
+          or2s[tree2Index].b = tmp[i+1];
+          or2s[tree2Index].y = tmp[end+j];
           tree2Index = tree2Index +1;
           i = i + 2;
         ]
@@ -147,6 +151,8 @@ defproc ortree (bool? in[N]; bool! out; power supply)
   ]
   
     out = tmp[end];
+
+  ]
 }
 
 export template<pint N>
@@ -156,6 +162,11 @@ defproc andtree (bool? in[N]; bool! out; power supply)
 
   { N > 0 : "What?" };
 
+
+
+  [N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
+  []  N > 1 ->
+
   pint i, end, j;
   i = 0;
   end = N-1;
@@ -192,18 +203,18 @@ defproc andtree (bool? in[N]; bool! out; power supply)
   /* array to hold the actual C-elments, either A2C or A3C */
   
     [lenTree2Count > 0 ->
-    AND2_X1 C2Els[lenTree2Count];
+    AND2_X1 and2s[lenTree2Count];
   ]
   
   [lenTree3Count > 0 ->
-     AND3_X1 C3Els[lenTree3Count];
+     AND3_X1 and3s[lenTree3Count];
   ]
   
-  (h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
-  (h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
+  (h:lenTree2Count:and2s[h].vdd = supply.vdd;)
+  (h:lenTree3Count:and3s[h].vdd = supply.vdd;)
 
-  (h:lenTree2Count:C2Els[h].vss = supply.vss;)
-  (h:lenTree3Count:C3Els[h].vss = supply.vss;)
+  (h:lenTree2Count:and2s[h].vss = supply.vss;)
+  (h:lenTree3Count:and3s[h].vss = supply.vss;)
 
   /* Reset the variables we just stole lol */
   i = 0;
@@ -226,25 +237,25 @@ defproc andtree (bool? in[N]; bool! out; power supply)
         j = j + 1;
         [ i+1 >= end ->
           /*-- last piece: use either a 2 input C-element --*/
-          C2Els[tree2Index].a = tmp[i];
-          C2Els[tree2Index].b = tmp[i+1];
-          C2Els[tree2Index].y = tmp[end+j];
+          and2s[tree2Index].a = tmp[i];
+          and2s[tree2Index].b = tmp[i+1];
+          and2s[tree2Index].y = tmp[end+j];
           tree2Index = tree2Index +1;
           i = end;
         [] i+2 >= end ->
           /*-- last piece: use either a 3 input C-element --*/
-          C3Els[tree3Index].a = tmp[i];
-          C3Els[tree3Index].b = tmp[i+1];
-          C3Els[tree3Index].c = tmp[i+2];
-          C3Els[tree3Index].y = tmp[end+j];
+          and3s[tree3Index].a = tmp[i];
+          and3s[tree3Index].b = tmp[i+1];
+          and3s[tree3Index].c = tmp[i+2];
+          and3s[tree3Index].y = tmp[end+j];
 
           tree3Index = tree3Index +1;
           i = end;
         [] else ->
           /*-- more to come; so use a two input C-element --*/
-          C2Els[tree2Index].a = tmp[i];
-          C2Els[tree2Index].b = tmp[i+1];
-          C2Els[tree2Index].y = tmp[end+j];
+          and2s[tree2Index].a = tmp[i];
+          and2s[tree2Index].b = tmp[i+1];
+          and2s[tree2Index].y = tmp[end+j];
           tree2Index = tree2Index +1;
           i = i + 2;
         ]
@@ -256,6 +267,8 @@ defproc andtree (bool? in[N]; bool! out; power supply)
   ]
   
     out = tmp[end];
+
+  ]
 }
   
 /*
@@ -269,6 +282,10 @@ defproc ctree (bool? in[N]; bool! out; power supply)
 
   { N > 0 : "What?" };
 
+  bool meaningless_var;
+
+  [N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
+  []  N > 1 ->
   pint i, end, j;
   i = 0;
   end = N-1;
@@ -372,6 +389,11 @@ defproc ctree (bool? in[N]; bool! out; power supply)
   ]
   
   out = tmp[end];
+
+
+    ]
+
+  
   
 }
 
@@ -380,23 +402,23 @@ defproc vtree (std::data::Mx1of2?<N> in; bool! out; power supply)
 {
     // OR layer for making OR between true and false of in (they are then sent to Ctree)
     OR2_X1 OR2_tf[N];
-    ctree<N> myctree;
+    ctree<N> ct;
   (l:N:
       OR2_tf[l].a = in.d[l].t;
       OR2_tf[l].b = in.d[l].f;
-      OR2_tf[l].y = myctree.in[l];
+      OR2_tf[l].y = ct.in[l];
       OR2_tf[l].vdd = supply.vdd;
       OR2_tf[l].vss = supply.vss;
   )
-  myctree.supply = supply;
-  out = myctree.out;
+  ct.supply = supply;
+  out = ct.out;
 }
 export template<pint N>
 defproc sigbuf (bool? in; bool! out[N]; power supply)
 {
 
   { N >= 0 : "sigbuf: parameter error" };
-  { N <= 43 : "sigbuf: parameter error, N too big" };
+//  { N <= 43 : "sigbuf: parameter error, N too big" };
 
 	  /* -- just use in sized driver here -- */
     [ N <= 4 ->
@@ -411,10 +433,49 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
     BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
    [] N >= 19 & N <= 29 -> 
     BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
-   [] N >= 30 & N <= 42 -> 
+   [] N >= 30 & N<= 48-> 
     BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 49 & N <= 64 -> 
+    BUF_X16 buf16 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 65 & N <= 96 -> 
+    BUF_X24 buf24 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 97 -> 
+    BUF_X32 buf32 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+  //  [] N >= 129 & N <=192 -> 
+  //   BUF_X48 buf48 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
+  // [] N >= 193 & N <= 256-> 
+  //   BUF_X64 buf64 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
    ]
    (i:1..N-1:out[i]=out[0];)
 }
+
+//Sigbuf in which there is only 1 output. Made for outputs that cannot have multiple wires.
+export template<pint N>
+defproc sigbuf_1output (bool? in; bool! out; power supply)
+{
+
+  { N >= 0 : "sigbuf: parameter error" };
+  { N <= 43 : "sigbuf: parameter error, N too big" }; 
+
+    /* -- just use in sized driver here -- */
+    [ N <= 4 ->
+    BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
+    [] N >= 5 & N <= 7 -> 
+    BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
+    [] N >= 8 & N <= 10 -> 
+    BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 11 & N <= 14 -> 
+    BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 15 & N <= 18 -> 
+    BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 19 & N <= 29 -> 
+    BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
+   [] N >= 30 & N <= 42 -> 
+    BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
+   ]
+}
+
+
+
 }}
 

test/prsim_plot.py

@@ -1,4 +1,4 @@
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 import sys
 import glob
@@ -54,17 +54,21 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 				raise Exception("Unknown colour given. I cba to code up general colours atm.")
 
 	# Check if start time given
+	t0 = None
 	for arg in argv:
 		r = re.findall(r'-t0=(\d+)', arg)
 		if len(r) >= 1:
 			print(f"Filtering by start time t0 = {r[0]}")
+			t0 = int[r[0]]
 			entries = [e for e in entries if int(e[0]) >= int(r[0])]
 
 	# Check if end time given
+	t1 = None
 	for arg in argv:
 		r = re.findall(r'-t1=(\d+)', arg)
 		if len(r) >= 1:
 			print(f"Filtering by end time t1 = {r[0]}")
+			t1 = int[r[0]]
 			entries = [e for e in entries if int(e[0]) <= int(r[0])]
 
 
@@ -95,10 +99,18 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 		if len(r) >= 1:
 			include_all_times = True
 
+
+	# Check if user gave "nowarn" flag
+	plot_warn = True
+	for arg in argv:
+		r = re.findall(r'(-nowarn?)', arg)
+		if len(r) >= 1:
+			plot_warn = False
+
 	# Get list of all times (before filtering)
 	unique_times = np.unique([int(e[0]) for e in entries])
 
-	assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
+	# assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
 	if include_given: print(f"Including signals that match regex {include_re}")
 	if exclude_given: print(f"Excluding signals that match regex {exclude_re}")
 
@@ -115,6 +127,7 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 	# Get list of all times (after filtering)
 	times = np.array([int(e[0]) for e in entries])
 	if not include_all_times: unique_times = np.unique(times)
+	num_times = unique_times.shape[0]
 
 	# Get list of all sigs
 	sigs = np.array([e[1] for e in entries])
@@ -173,8 +186,12 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 	# ax.set_ylabel("Signal")
 	ax.set_yticks([])
 
+	# Plot signal names
+	sig_repeat_period = 20
 	for sig in unique_sigs:
 		ax.text(-1, sig_to_index(sig), sig, ha = "right", va = "center", size = 10)
+		ax.text(num_times, sig_to_index(sig), sig, ha = "left", va = "center", size = 10)	
+
 
 	for i in range(num_sigs-1):
 		ax.axhline(i+0.5, c = "white", lw = 2)
@@ -216,8 +233,8 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 		ax.text(time_to_index(time), num_sigs, time, ha = "center", va = "top", size = 10, rotation = 90)
 
 	# Find and plot wrong Assert statements
-	asserts = re.findall(r"\t *(\d+) .*\nWRONG ASSERT:\t(.+)", f)
-	if len(asserts): print("Failed asserts found!")
+	asserts = re.findall(r"\t *(\d+) .*\n(WRONG ASSERT|WARNING):\t?(.+)", f)
+	if len(asserts): print("Warnings found!")
 	for a in asserts:
 		print(a)
 		time = int(a[0])
@@ -225,11 +242,12 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
 			try:
 				time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
 			except:
-				print(f"Couldn't find an appropriate time for assert {a}")
+				print(f"Couldn't find an appropriate time for warning {a}")
 				continue
 		index = time_to_index(time)
-		ax.axvline(index+0.5, c = "red", lw = 2)
-		ax.text(index+0.5, -1, a[1], rotation = 90, ha = "center", va = "bottom", c = "red")
+		if plot_warn:
+			ax.axvline(index+0.5, c = "red", lw = 2)
+			ax.text(index+0.5, -1, a[2], rotation = 90, ha = "center", va = "bottom", c = "red")
 
 	# Find echoed statements of the form "[digits] text"
 	echoes = re.findall(r"\t *(\d+) [^\t]*\n(\[\d*\].+)", f)

test/repeat_unit.sh

@@ -1,85 +1,94 @@
-# repeatedly run prsim on one unit_test's PRs
+#!/bin/sh
 
+fail=0
+faildirs=""
+proc=""
 bold=$(tput bold)
 normal=$(tput sgr0)
 und=$(tput smul)
-i=${unit}
-proc="$i<>"
 
-echo ""
-echo "${bold}******************************************"
-echo "* ${i} repetitions , show warnings=${warning}*"
-echo "******************************************${normal}"
+faildirs=""
+failed=0
+iteration=0
+numberofruns=100
+
+#
+#  run_test name [option]
+#
+run_test () {
+    echo "Testing ${bold}$1 ${normal} for $2 random delay runs"
+    # clear run directory
+    if [ -d $1/run ]; then
+	    rm -rf $1/run
+    fi
+    mkdir $1/run
+    cp init.prs $1/run/test.prs
+    if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
+            echo "random_seed $2" > $1/run/prsim.in
+	    cat init_qdi.prsim $1/test.prsim >> $1/run/prsim.in
+	    cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
+	    if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
+	        echo "${bold}*** simulation failed seed: $2 ***${normal}"
+	        faildirs="${faildirs} ${1}-sim($2)"
+	        failed=1
+	        echo	
+	    fi
+    else
+	    echo "${bold}*** circuit construction failed ***${normal}"
+	    faildirs="${faildirs} ${1}-ckt"
+	    failed=1
+        echo
+    fi
+}
+
+if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
+    echo "${bold}Error:${bold} aflat & prsim necessary for tests."
+    exit 1
+fi
+
+if [ ! -d "unit_tests" ];
+then
+    echo "${bold}Error:${bold} no unit_tests directory."
+    exit 1
+fi    
 
 cd "unit_tests"
-echo "${bold}... checking aflat${normal}"
 
-# check aflat
-if ($ACT_HOME/bin/aflat "$i/test_final.act" > "$i/test.prs");
-then
-    echo "${bold}... aflat complete, checking in prsim${normal}"
-    
-  # run prsim on prs
-    (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test.prsim") > "$i/prsim.out");
-    if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found")
-    then
-        echo "FAILED in first prsim"
-    else
-        
-        # show warnings setting
-        if [ "${warning}" = "1" ];
-        then
-          echo "${bold}Exit on prsim warnings turned ON${normal}"
-        else
-          echo "${bold}Exit on prsim warnings turned OFF${normal}"
-        fi
-        echo ""
-        
-        # begin prsim test loop
-        has_failed=0
-        iter=0
-        echo "${bold}using random_seed${normal}"
-        echo "\nusing random_seed" >> "$i/prsim.out"
-        while [ has_failed=0 ]
-        do
-            # write prsim test file with random seed appended to top of file
-            (echo "random_seed $iter \nrandom" > "$i/test_rand.prsim");
-            (cat "$i/test.prsim" >> "$i/test_rand.prsim");
-            (echo "\nTEST $iter\n" >> "$i/prsim.out");
-            
-            # validate prsim output
-            if (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test_rand.prsim") >> "$i/prsim.out");
-            then
-                if [ "${warning}" = "1" ];
-                then
-                  if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found" -e "WARNING:");
-                  then
-                      echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
-                      has_failed=1
-                      exit 0
-                  else
-                      echo "==> passed test #${iter}"
-                      iter=$(($iter + 1))
-                  fi
-                else
-                  if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found");
-                  then
-                      echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
-                      has_failed=1
-                      exit 0
-                  else
-                      echo "==> passed test #${iter}"
-                      iter=$(($iter + 1))
-                  fi
-                fi
-            else
-                has_failed=1
-                exit 0
-            fi
-        done
-        (cd ".."; pwd);
-        exit 1
-    fi
-else
-    echo "FAILED in aflat conversion"
+# run all test except single one is specified
+if [ ! -z $3 ]; then 
+  iteration=$3
 fi
+if [ ! -z $2 ]; then 
+  numberofruns=$2
+fi
+  
+if [ -z $1 ]; then
+    for i in *
+    do
+        if [ -d $i -a -f $i/test.act ]; then
+        	while [ $iteration -lt $numberofruns ]
+        	do
+	        	run_test $iteration
+                iteration=$iteration+1
+	        done 
+        fi
+    done
+else
+       while [ $iteration -lt $numberofruns ]
+       do
+	       run_test $1 $iteration
+           iteration=$((iteration+1))
+       done 
+    
+fi
+
+if [ $failed -eq 1 ]; then
+    echo ""
+    echo "${bold}*********************************"
+    echo "* FAILED DIRECTORIES:${normal}$faildirs ${bold}*"
+    echo "*********************************${normal}"
+fi
+
+exit $failed
+
+

test/run.sh

@@ -22,7 +22,8 @@ run_test () {
     mkdir $1/run
     cp init.prs $1/run/test.prs
     if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
-	    cat init_qdi.prsim $1/test.prsim | prsim -r $1/run/test.prs > $1/run/prsim.out
+	    cat init_qdi.prsim $1/test.prsim > $1/run/prsim.in
+	    cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
 	    if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
 	        echo "${bold}*** simulation failed ***${normal}"
 	        faildirs="${faildirs} ${1}-sim"

test/unit_tests/andtree_15/run/prsim.out

@@ -1,118 +0,0 @@
-t.in[0] t.at.tmp[22] t.in[5] t.in[2] t.at.tmp[15] t.in[3] t.at.tmp[23] t.at.C2Els[0]._y t.in[7] t.in[6] t.at.C2Els[3]._y t.in[4] t.at.C3Els[0]._y t.in[12] t.out t.at.tmp[21] t.at.C2Els[6]._y t.in[11] t.at.tmp[17] t.in[14] t.in[1] t.in[10] t.in[9] t.at.C2Els[5]._y t.at.tmp[19] t.at.tmp[20] t.at.tmp[24] t.in[13] t.at.tmp[16] t.at.C2Els[4]._y t.in[8] t.at.tmp[18] t.at.C2Els[2]._y t.at.C3Els[2]._y t.at.C2Els[1]._y t.at.C2Els[7]._y t.at.C3Els[1]._y 
-0
-1
-	         0 t.in[0] : 0
-	         0 t.in[14] : 0
-	         0 t.in[2] : 0
-	         0 t.in[6] : 0
-	         0 t.in[13] : 0
-	         0 t.in[5] : 0
-	         0 t.in[12] : 0
-	         0 t.in[11] : 0
-	         0 t.in[1] : 0
-	         0 t.in[4] : 0
-	         0 t.in[10] : 0
-	         0 t.in[9] : 0
-	         0 t.in[3] : 0
-	         0 t.in[8] : 0
-	         0 t.in[7] : 0
-	         1 t.at.C2Els[0]._y : 1  [by t.in[0]:=0]
-	         2 t.at.C2Els[3]._y : 1  [by t.in[6]:=0]
-	       114 t.at.C2Els[4]._y : 1  [by t.in[9]:=0]
-	       153 t.at.tmp[19] : 0  [by t.at.C2Els[4]._y:=1]
-	       168 t.at.C3Els[1]._y : 1  [by t.at.tmp[19]:=0]
-	       659 t.at.tmp[24] : 0  [by t.at.C3Els[1]._y:=1]
-	       672 t.at.C3Els[2]._y : 1  [by t.at.tmp[24]:=0]
-	       712 t.out : 0  [by t.at.C3Els[2]._y:=1]
-	      1137 t.at.C2Els[5]._y : 1  [by t.in[11]:=0]
-	      1552 t.at.tmp[20] : 0  [by t.at.C2Els[5]._y:=1]
-	      1728 t.at.tmp[18] : 0  [by t.at.C2Els[3]._y:=1]
-	      1748 t.at.C2Els[7]._y : 1  [by t.at.tmp[18]:=0]
-	      4753 t.at.C2Els[2]._y : 1  [by t.in[5]:=0]
-	      4800 t.at.tmp[17] : 0  [by t.at.C2Els[2]._y:=1]
-	      7092 t.at.C3Els[0]._y : 1  [by t.in[14]:=0]
-	      7108 t.at.tmp[21] : 0  [by t.at.C3Els[0]._y:=1]
-	      7809 t.at.tmp[23] : 0  [by t.at.C2Els[7]._y:=1]
-	     10467 t.at.C2Els[1]._y : 1  [by t.in[2]:=0]
-	     54565 t.at.tmp[16] : 0  [by t.at.C2Els[1]._y:=1]
-	     65367 t.at.tmp[15] : 0  [by t.at.C2Els[0]._y:=1]
-	     68289 t.at.C2Els[6]._y : 1  [by t.at.tmp[16]:=0]
-	     68293 t.at.tmp[22] : 0  [by t.at.C2Els[6]._y:=1]
-[] setting some bits high
-	     68293 t.in[0] : 1
-	     68293 t.in[11] : 1
-	     68293 t.in[10] : 1
-	     68293 t.in[9] : 1
-	     68293 t.in[2] : 1
-	     68293 t.in[8] : 1
-	     68293 t.in[7] : 1
-	     68293 t.in[6] : 1
-	     68293 t.in[5] : 1
-	     68293 t.in[1] : 1
-	     68293 t.in[4] : 1
-	     68293 t.in[3] : 1
-	     68308 t.at.C2Els[4]._y : 0  [by t.in[8]:=1]
-	     68348 t.at.C2Els[2]._y : 0  [by t.in[4]:=1]
-	     77422 t.at.C2Els[5]._y : 0  [by t.in[10]:=1]
-	     82197 t.at.tmp[17] : 1  [by t.at.C2Els[2]._y:=0]
-	     98088 t.at.tmp[19] : 1  [by t.at.C2Els[4]._y:=0]
-	    102234 t.at.tmp[20] : 1  [by t.at.C2Els[5]._y:=0]
-	    105224 t.at.C2Els[0]._y : 0  [by t.in[1]:=1]
-	    111541 t.at.C2Els[3]._y : 0  [by t.in[6]:=1]
-	    111963 t.at.tmp[18] : 1  [by t.at.C2Els[3]._y:=0]
-	    119567 t.at.tmp[15] : 1  [by t.at.C2Els[0]._y:=0]
-	    119946 t.at.C2Els[1]._y : 0  [by t.in[3]:=1]
-	    119947 t.at.tmp[16] : 1  [by t.at.C2Els[1]._y:=0]
-	    119948 t.at.C2Els[6]._y : 0  [by t.at.tmp[16]:=1]
-	    140153 t.at.tmp[22] : 1  [by t.at.C2Els[6]._y:=0]
-	    160677 t.at.C2Els[7]._y : 0  [by t.at.tmp[18]:=1]
-	    160959 t.at.tmp[23] : 1  [by t.at.C2Els[7]._y:=0]
-[] setting all bits high
-	    160959 t.in[12] : 1
-	    160959 t.in[14] : 1
-	    160959 t.in[13] : 1
-	    161727 t.at.C3Els[0]._y : 0  [by t.in[13]:=1]
-	    161730 t.at.tmp[21] : 1  [by t.at.C3Els[0]._y:=0]
-	    184171 t.at.C3Els[1]._y : 0  [by t.at.tmp[21]:=1]
-	    184722 t.at.tmp[24] : 1  [by t.at.C3Els[1]._y:=0]
-	    185793 t.at.C3Els[2]._y : 0  [by t.at.tmp[24]:=1]
-	    186747 t.out : 1  [by t.at.C3Els[2]._y:=0]
-[] setting some low
-	    186747 t.in[10] : 0
-	    187828 t.at.C2Els[5]._y : 1  [by t.in[10]:=0]
-	    242298 t.at.tmp[20] : 0  [by t.at.C2Els[5]._y:=1]
-	    243280 t.at.C3Els[1]._y : 1  [by t.at.tmp[20]:=0]
-	    243298 t.at.tmp[24] : 0  [by t.at.C3Els[1]._y:=1]
-	    247311 t.at.C3Els[2]._y : 1  [by t.at.tmp[24]:=0]
-	    251314 t.out : 0  [by t.at.C3Els[2]._y:=1]
-[] setting all low
-	    251314 t.in[0] : 0
-	    251314 t.in[14] : 0
-	    251314 t.in[2] : 0
-	    251314 t.in[6] : 0
-	    251314 t.in[5] : 0
-	    251314 t.in[13] : 0
-	    251314 t.in[12] : 0
-	    251314 t.in[1] : 0
-	    251314 t.in[4] : 0
-	    251314 t.in[11] : 0
-	    251314 t.in[9] : 0
-	    251314 t.in[3] : 0
-	    251314 t.in[8] : 0
-	    251314 t.in[7] : 0
-	    251517 t.at.C2Els[2]._y : 1  [by t.in[5]:=0]
-	    251656 t.at.tmp[17] : 0  [by t.at.C2Els[2]._y:=1]
-	    251816 t.at.C2Els[3]._y : 1  [by t.in[6]:=0]
-	    251885 t.at.tmp[18] : 0  [by t.at.C2Els[3]._y:=1]
-	    253168 t.at.C2Els[4]._y : 1  [by t.in[9]:=0]
-	    253179 t.at.tmp[19] : 0  [by t.at.C2Els[4]._y:=1]
-	    256074 t.at.C2Els[1]._y : 1  [by t.in[2]:=0]
-	    272898 t.at.C3Els[0]._y : 1  [by t.in[14]:=0]
-	    273102 t.at.tmp[21] : 0  [by t.at.C3Els[0]._y:=1]
-	    288002 t.at.C2Els[7]._y : 1  [by t.at.tmp[17]:=0]
-	    288017 t.at.tmp[23] : 0  [by t.at.C2Els[7]._y:=1]
-	    296215 t.at.C2Els[0]._y : 1  [by t.in[0]:=0]
-	    296216 t.at.tmp[15] : 0  [by t.at.C2Els[0]._y:=1]
-	    296253 t.at.C2Els[6]._y : 1  [by t.at.tmp[15]:=0]
-	    296992 t.at.tmp[22] : 0  [by t.at.C2Els[6]._y:=1]
-	    307860 t.at.tmp[16] : 0  [by t.at.C2Els[1]._y:=1]

test/unit_tests/andtree_15/run/test.prs

@@ -1,139 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
-~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
-"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
-~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
-"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
-~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
-"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
-~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
-"t.at.C2Els[2].a"&"t.at.C2Els[2].b"->"t.at.C2Els[2]._y"-
-~("t.at.C2Els[2].a"&"t.at.C2Els[2].b")->"t.at.C2Els[2]._y"+
-"t.at.C2Els[2]._y"->"t.at.C2Els[2].y"-
-~("t.at.C2Els[2]._y")->"t.at.C2Els[2].y"+
-"t.at.C2Els[3].a"&"t.at.C2Els[3].b"->"t.at.C2Els[3]._y"-
-~("t.at.C2Els[3].a"&"t.at.C2Els[3].b")->"t.at.C2Els[3]._y"+
-"t.at.C2Els[3]._y"->"t.at.C2Els[3].y"-
-~("t.at.C2Els[3]._y")->"t.at.C2Els[3].y"+
-"t.at.C2Els[4].a"&"t.at.C2Els[4].b"->"t.at.C2Els[4]._y"-
-~("t.at.C2Els[4].a"&"t.at.C2Els[4].b")->"t.at.C2Els[4]._y"+
-"t.at.C2Els[4]._y"->"t.at.C2Els[4].y"-
-~("t.at.C2Els[4]._y")->"t.at.C2Els[4].y"+
-"t.at.C2Els[5].a"&"t.at.C2Els[5].b"->"t.at.C2Els[5]._y"-
-~("t.at.C2Els[5].a"&"t.at.C2Els[5].b")->"t.at.C2Els[5]._y"+
-"t.at.C2Els[5]._y"->"t.at.C2Els[5].y"-
-~("t.at.C2Els[5]._y")->"t.at.C2Els[5].y"+
-"t.at.C2Els[6].a"&"t.at.C2Els[6].b"->"t.at.C2Els[6]._y"-
-~("t.at.C2Els[6].a"&"t.at.C2Els[6].b")->"t.at.C2Els[6]._y"+
-"t.at.C2Els[6]._y"->"t.at.C2Els[6].y"-
-~("t.at.C2Els[6]._y")->"t.at.C2Els[6].y"+
-"t.at.C2Els[7].a"&"t.at.C2Els[7].b"->"t.at.C2Els[7]._y"-
-~("t.at.C2Els[7].a"&"t.at.C2Els[7].b")->"t.at.C2Els[7]._y"+
-"t.at.C2Els[7]._y"->"t.at.C2Els[7].y"-
-~("t.at.C2Els[7]._y")->"t.at.C2Els[7].y"+
-"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
-~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
-"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
-~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
-"t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c"->"t.at.C3Els[1]._y"-
-~("t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c")->"t.at.C3Els[1]._y"+
-"t.at.C3Els[1]._y"->"t.at.C3Els[1].y"-
-~("t.at.C3Els[1]._y")->"t.at.C3Els[1].y"+
-"t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c"->"t.at.C3Els[2]._y"-
-~("t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c")->"t.at.C3Els[2]._y"+
-"t.at.C3Els[2]._y"->"t.at.C3Els[2].y"-
-~("t.at.C3Els[2]._y")->"t.at.C3Els[2].y"+
-= "t.at.tmp[15]" "t.at.C2Els[6].a"
-= "t.at.tmp[15]" "t.at.C2Els[0].y"
-= "t.at.tmp[16]" "t.at.C2Els[6].b"
-= "t.at.tmp[16]" "t.at.C2Els[1].y"
-= "t.at.tmp[17]" "t.at.C2Els[7].a"
-= "t.at.tmp[17]" "t.at.C2Els[2].y"
-= "t.at.tmp[18]" "t.at.C2Els[7].b"
-= "t.at.tmp[18]" "t.at.C2Els[3].y"
-= "t.at.tmp[19]" "t.at.C3Els[1].a"
-= "t.at.tmp[19]" "t.at.C2Els[4].y"
-= "t.at.tmp[20]" "t.at.C3Els[1].b"
-= "t.at.tmp[20]" "t.at.C2Els[5].y"
-= "t.at.tmp[21]" "t.at.C3Els[1].c"
-= "t.at.tmp[21]" "t.at.C3Els[0].y"
-= "t.at.tmp[22]" "t.at.C3Els[2].a"
-= "t.at.tmp[22]" "t.at.C2Els[6].y"
-= "t.at.tmp[23]" "t.at.C3Els[2].b"
-= "t.at.tmp[23]" "t.at.C2Els[7].y"
-= "t.at.tmp[24]" "t.at.C3Els[2].c"
-= "t.at.tmp[24]" "t.at.C3Els[1].y"
-= "t.at.supply.vdd" "t.at.C3Els[2].vdd"
-= "t.at.supply.vdd" "t.at.C3Els[1].vdd"
-= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[7].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[6].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[5].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[4].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[3].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[2].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
-= "t.at.supply.vss" "t.at.C3Els[2].vss"
-= "t.at.supply.vss" "t.at.C3Els[1].vss"
-= "t.at.supply.vss" "t.at.C3Els[0].vss"
-= "t.at.supply.vss" "t.at.C2Els[7].vss"
-= "t.at.supply.vss" "t.at.C2Els[6].vss"
-= "t.at.supply.vss" "t.at.C2Els[5].vss"
-= "t.at.supply.vss" "t.at.C2Els[4].vss"
-= "t.at.supply.vss" "t.at.C2Els[3].vss"
-= "t.at.supply.vss" "t.at.C2Els[2].vss"
-= "t.at.supply.vss" "t.at.C2Els[1].vss"
-= "t.at.supply.vss" "t.at.C2Els[0].vss"
-= "t.at.in[0]" "t.at.C2Els[0].a"
-= "t.at.in[0]" "t.at.tmp[0]"
-= "t.at.in[1]" "t.at.C2Els[0].b"
-= "t.at.in[1]" "t.at.tmp[1]"
-= "t.at.in[2]" "t.at.C2Els[1].a"
-= "t.at.in[2]" "t.at.tmp[2]"
-= "t.at.in[3]" "t.at.C2Els[1].b"
-= "t.at.in[3]" "t.at.tmp[3]"
-= "t.at.in[4]" "t.at.C2Els[2].a"
-= "t.at.in[4]" "t.at.tmp[4]"
-= "t.at.in[5]" "t.at.C2Els[2].b"
-= "t.at.in[5]" "t.at.tmp[5]"
-= "t.at.in[6]" "t.at.C2Els[3].a"
-= "t.at.in[6]" "t.at.tmp[6]"
-= "t.at.in[7]" "t.at.C2Els[3].b"
-= "t.at.in[7]" "t.at.tmp[7]"
-= "t.at.in[8]" "t.at.C2Els[4].a"
-= "t.at.in[8]" "t.at.tmp[8]"
-= "t.at.in[9]" "t.at.C2Els[4].b"
-= "t.at.in[9]" "t.at.tmp[9]"
-= "t.at.in[10]" "t.at.C2Els[5].a"
-= "t.at.in[10]" "t.at.tmp[10]"
-= "t.at.in[11]" "t.at.C2Els[5].b"
-= "t.at.in[11]" "t.at.tmp[11]"
-= "t.at.in[12]" "t.at.C3Els[0].a"
-= "t.at.in[12]" "t.at.tmp[12]"
-= "t.at.in[13]" "t.at.C3Els[0].b"
-= "t.at.in[13]" "t.at.tmp[13]"
-= "t.at.in[14]" "t.at.C3Els[0].c"
-= "t.at.in[14]" "t.at.tmp[14]"
-= "t.at.out" "t.at.C3Els[2].y"
-= "t.at.out" "t.at.tmp[25]"
-= "Vdd" "t.at.supply.vdd"
-= "GND" "t.at.supply.vss"
-= "t.out" "t.at.out"
-= "t.in[0]" "t.at.in[0]"
-= "t.in[1]" "t.at.in[1]"
-= "t.in[2]" "t.at.in[2]"
-= "t.in[3]" "t.at.in[3]"
-= "t.in[4]" "t.at.in[4]"
-= "t.in[5]" "t.at.in[5]"
-= "t.in[6]" "t.at.in[6]"
-= "t.in[7]" "t.at.in[7]"
-= "t.in[8]" "t.at.in[8]"
-= "t.in[9]" "t.at.in[9]"
-= "t.in[10]" "t.at.in[10]"
-= "t.in[11]" "t.at.in[11]"
-= "t.in[12]" "t.at.in[12]"
-= "t.in[13]" "t.at.in[13]"
-= "t.in[14]" "t.at.in[14]"

test/unit_tests/andtree_5/run/prsim.out

@@ -1,40 +0,0 @@
-t.in[0] t.in[2] t.at.tmp[5] t.in[3] t.at.C2Els[0]._y t.in[4] t.at.C3Els[0]._y t.at.tmp[6] t.in[1] t.out t.at.C2Els[1]._y 
-0
-1
-	         0 t.in[0] : 0
-	         0 t.in[4] : 0
-	         0 t.in[2] : 0
-	         0 t.in[1] : 0
-	         0 t.in[3] : 0
-	         1 t.at.C2Els[0]._y : 1  [by t.in[0]:=0]
-	      7092 t.at.C3Els[0]._y : 1  [by t.in[4]:=0]
-	      7094 t.at.tmp[6] : 0  [by t.at.C3Els[0]._y:=1]
-	     10468 t.at.tmp[5] : 0  [by t.at.C2Els[0]._y:=1]
-	     11847 t.at.C2Els[1]._y : 1  [by t.at.tmp[6]:=0]
-	     12984 t.out : 0  [by t.at.C2Els[1]._y:=1]
-[] setting some bits high
-	     12984 t.in[0] : 1
-	     12984 t.in[2] : 1
-	     12984 t.in[1] : 1
-	     13098 t.at.C2Els[0]._y : 0  [by t.in[1]:=1]
-	     78464 t.at.tmp[5] : 1  [by t.at.C2Els[0]._y:=0]
-[] setting all bits high
-	     78464 t.in[3] : 1
-	     78464 t.in[4] : 1
-	     80190 t.at.C3Els[0]._y : 0  [by t.in[4]:=1]
-	     80229 t.at.tmp[6] : 1  [by t.at.C3Els[0]._y:=0]
-	     80244 t.at.C2Els[1]._y : 0  [by t.at.tmp[6]:=1]
-	     80735 t.out : 1  [by t.at.C2Els[1]._y:=0]
-[] setting some low
-	     80735 t.in[0] : 0
-	     80735 t.in[1] : 0
-	     80748 t.at.C2Els[0]._y : 1  [by t.in[0]:=0]
-	     80788 t.at.tmp[5] : 0  [by t.at.C2Els[0]._y:=1]
-	     81203 t.at.C2Els[1]._y : 1  [by t.at.tmp[5]:=0]
-	     81223 t.out : 0  [by t.at.C2Els[1]._y:=1]
-[] setting all low
-	     81223 t.in[2] : 0
-	     81223 t.in[4] : 0
-	     81223 t.in[3] : 0
-	     87284 t.at.C3Els[0]._y : 1  [by t.in[2]:=0]
-	     87331 t.at.tmp[6] : 0  [by t.at.C3Els[0]._y:=1]

test/unit_tests/andtree_5/run/test.prs

@@ -1,45 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
-~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
-"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
-~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
-"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
-~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
-"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
-~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
-"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
-~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
-"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
-~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
-= "t.at.tmp[5]" "t.at.C2Els[1].a"
-= "t.at.tmp[5]" "t.at.C2Els[0].y"
-= "t.at.tmp[6]" "t.at.C2Els[1].b"
-= "t.at.tmp[6]" "t.at.C3Els[0].y"
-= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
-= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
-= "t.at.supply.vss" "t.at.C3Els[0].vss"
-= "t.at.supply.vss" "t.at.C2Els[1].vss"
-= "t.at.supply.vss" "t.at.C2Els[0].vss"
-= "t.at.in[0]" "t.at.C2Els[0].a"
-= "t.at.in[0]" "t.at.tmp[0]"
-= "t.at.in[1]" "t.at.C2Els[0].b"
-= "t.at.in[1]" "t.at.tmp[1]"
-= "t.at.in[2]" "t.at.C3Els[0].a"
-= "t.at.in[2]" "t.at.tmp[2]"
-= "t.at.in[3]" "t.at.C3Els[0].b"
-= "t.at.in[3]" "t.at.tmp[3]"
-= "t.at.in[4]" "t.at.C3Els[0].c"
-= "t.at.in[4]" "t.at.tmp[4]"
-= "t.at.out" "t.at.C2Els[1].y"
-= "t.at.out" "t.at.tmp[7]"
-= "Vdd" "t.at.supply.vdd"
-= "GND" "t.at.supply.vss"
-= "t.out" "t.at.out"
-= "t.in[0]" "t.at.in[0]"
-= "t.in[1]" "t.at.in[1]"
-= "t.in[2]" "t.at.in[2]"
-= "t.in[3]" "t.at.in[3]"
-= "t.in[4]" "t.at.in[4]"

test/unit_tests/append_5_3_2/test.act

@@ -0,0 +1,53 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ *  It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc append_5_3_2(avMx1of2<5> in; avMx1of2<8> out)
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+
+  fifo<5,4> fifo_pre(.in = in, .reset_B = _reset_B);
+  append<5,3,3> app(.in = fifo_pre.out);
+  fifo<5+3,4> fifo_post(.in = app.out, .out = out, .reset_B = _reset_B);
+
+  app.supply.vdd = Vdd;
+  app.supply.vss = GND;
+  fifo_pre.supply.vdd = Vdd;
+  fifo_pre.supply.vss = GND;
+  fifo_post.supply.vdd = Vdd;
+  fifo_post.supply.vss = GND;
+}
+
+append_5_3_2 b;

test/unit_tests/append_5_3_2/test.prsim

@@ -0,0 +1,78 @@
+watchall
+
+set b.out.a 0
+set b.out.v 0
+set Reset 0
+set-qdi-channel-neutral "b.in" 5
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+status X
+assert-qdi-channel-neutral "b.out" 8
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] sending in a 31'"
+set-qdi-channel-valid "b.in" 5 31
+cycle
+assert-qdi-channel-valid "b.out" 8 127
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] removing input'"
+set-qdi-channel-neutral "b.in" 5
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] sending in a 0'"
+set-qdi-channel-valid "b.in" 5 0
+cycle
+# assert-qdi-channel-valid "b.out" 8 96
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] removing input'"
+set-qdi-channel-neutral "b.in" 5
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+
+system "echo '[] receiving out ack/val'"
+set b.out.a 1
+set b.out.v 1
+cycle
+assert-qdi-channel-neutral "b.out" 8
+
+
+system "echo '[] removing out ack/val'"
+set b.out.a 0
+set b.out.v 0
+cycle
+assert-qdi-channel-valid "b.out" 8 96
+
+
+system "echo '[] receiving out ack/val'"
+set b.out.a 1
+set b.out.v 1
+cycle
+assert-qdi-channel-neutral "b.out" 8
+
+
+system "echo '[] removing out ack/val'"
+set b.out.a 0
+set b.out.v 0
+cycle
+assert-qdi-channel-neutral "b.out" 8
+
+
+
+

test/unit_tests/arbiter/run/prsim.out

@@ -1,39 +0,0 @@
-a._v a.a a.u a.v a._u a.b 
-reset done
-	         0 a.a : 0
-	         0 a.b : 0
-	         1 a._u : 1  [by a.a:=0]
-	      7092 a._v : 1  [by a.b:=0]
-	      7094 a.v : 0  [by a._v:=1]
-	     10468 a.u : 0  [by a._u:=1]
-
-step 1.1 finished
-	     10468 a.a : 1
-	     10468 a.b : 1
-	     15221 a._u : 0  [by a.a:=1]
-	     15335 a.u : 1  [by a._u:=0]
-
-step 1.2 finished
-	     15335 a.a : 0
-	     15335 a.b : 0
-	     80701 a._u : 1  [by a.a:=0]
-	     82427 a.u : 0  [by a._u:=1]
-
-step 2.1 finished
-	     82427 a.a : 1
-	     82427 a.b : 1
-	     82466 a._u : 0  [by a.a:=1]
-	     82957 a.u : 1  [by a._u:=0]
-
-step 2.2 finished
-	     82957 a.a : 0
-	     82957 a.b : 0
-	     82970 a._u : 1  [by a.a:=0]
-	     83010 a.u : 0  [by a._u:=1]
-
-step 3.1 finished
-	     83010 a.b : 1
-	     83425 a._v : 0  [by a.b:=1]
-	     83445 a.v : 1  [by a._v:=0]
-
-step 3.2 finished

test/unit_tests/arbiter/run/test.prs

@@ -1,3 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"

test/unit_tests/arbiter_2/run/prsim.out

@@ -1,39 +0,0 @@
-a._v a.a a.u a.v a._u a.b 
-reset done
-	         0 a.a : 0
-	         0 a.b : 0
-	         1 a._u : 1  [by a.a:=0]
-	      7092 a._v : 1  [by a.b:=0]
-	      7094 a.v : 0  [by a._v:=1]
-	     10468 a.u : 0  [by a._u:=1]
-
-step 1.1 finished
-	     10468 a.a : 1
-	     10468 a.b : 1
-	     15221 a._u : 0  [by a.a:=1]
-	     15335 a.u : 1  [by a._u:=0]
-
-step 1.2 finished
-	     15335 a.a : 0
-	     15335 a.b : 0
-	     80701 a._u : 1  [by a.a:=0]
-	     82427 a.u : 0  [by a._u:=1]
-
-step 2.1 finished
-	     82427 a.a : 1
-	     82427 a.b : 1
-	     82466 a._u : 0  [by a.a:=1]
-	     82957 a.u : 1  [by a._u:=0]
-
-step 2.2 finished
-	     82957 a.a : 0
-	     82957 a.b : 0
-	     82970 a._u : 1  [by a.a:=0]
-	     83010 a.u : 0  [by a._u:=1]
-
-step 3.1 finished
-	     83010 a.b : 1
-	     83425 a._v : 0  [by a.b:=1]
-	     83445 a.v : 1  [by a._v:=0]
-
-step 3.2 finished

test/unit_tests/arbiter_2/run/test.prs

@@ -1,12 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-"a.a"&"a._v"->"a._u"-
-~"a.a"|~"a._v"->"a._u"+
-"a.b"&"a._u"->"a._v"-
-~"a.b"|~"a._u"->"a._v"+
-"a._u"->"a.u"-
-~("a._u")->"a.u"+
-"a._v"->"a.v"-
-~("a._v")->"a.v"+
-mk_excllo("a._u","a._v")

test/unit_tests/arbiter_handshake_adv/run/prsim.out

@@ -1,357 +0,0 @@
-t.fifo_in1.fifo_element[2].in.r t.fifo_in1.fifo_element[1]._en t.in1.r t.in2.r t.fifo_in2.fifo_element[3].in.r t.out.r t._out1.r t.fifo_in2.fifo_element[3].inack_ctl._y t._out1.a t.arb._y1_arb t.fifo_in2.fifo_element[1].in.a t.fifo_in1.fifo_element[2].in.a t.fifo_in1.fifo_element[3]._out_a_B t.fifo_in1.fifo_element[1].in.r t.in2.a t.fifo_in2.fifo_element[3].in.a t._out2.a t.fifo_in2.fifo_element[1].in.r t.fifo_in1.fifo_element[3]._en t.fifo_in1.fifo_element[0].buf_func._y t.fifo_in2.fifo_element[0].inack_ctl._y t.fifo_in1.fifo_element[3].in.r t.fifo_in2.fifo_element[2].in.a t.fifo_in2.fifo_element[1]._out_a_B t.fifo_in2.fifo_element[3]._out_a_B t.fifo_in2.fifo_element[2].inack_ctl._y t.fifo_in2.fifo_element[0]._en t.fifo_in1.fifo_element[2]._en t._out2.r t.fifo_in1.fifo_element[1].in.a t.in1.a t.arb.ack_cell1._y t.fifo_in1.fifo_element[2].buf_func._y t.fifo_in1.fifo_element[0]._en t.fifo_in2.fifo_element[0]._out_a_B t.fifo_in1.fifo_element[2].inack_ctl._y t.fifo_in2.fifo_element[2]._out_a_B t.fifo_in1.fifo_element[1]._out_a_B t.fifo_in2.fifo_element[3]._en t.fifo_in2.fifo_element[1].buf_func._y t.fifo_in1.fifo_element[0].inack_ctl._y t.arb.or_cell._y t.arb.arbiter._y1 t.arb._y2_arb t.fifo_in1.fifo_element[1].inack_ctl._y t.fifo_in1.fifo_element[0]._out_a_B t.fifo_in2.fifo_element[1]._en t.fifo_in2.fifo_element[2]._en t.fifo_in2.fifo_element[0].buf_func._y t.fifo_in2.fifo_element[3].buf_func._y t.fifo_in1.fifo_element[2]._out_a_B t.fifo_in1.fifo_element[3].in.a t.fifo_in2.fifo_element[2].buf_func._y t.arb.arbiter._y2 t.fifo_in1.fifo_element[3].inack_ctl._y t.fifo_in2.fifo_element[2].in.r t.fifo_in1.fifo_element[1].buf_func._y t.fifo_in2.fifo_element[1].inack_ctl._y t.out.a t.fifo_in1.fifo_element[3].buf_func._y t.arb.ack_cell2._y 
-[0] code starts
-	     77100 t.in1.r : 0
-	     77100 Reset : 0
-	     77100 t.out.a : 0
-	     77100 t.in2.r : 0
-	    114031 t.fifo_in1.reset_buf._y : 1  [by Reset:=0]
-	    114086 t.fifo_in1._reset_BX : 0  [by t.fifo_in1.reset_buf._y:=1]
-	    120348 t.fifo_in2.reset_buf._y : 1  [by Reset:=0]
-	    150128 t.fifo_in2._reset_BX : 0  [by t.fifo_in2.reset_buf._y:=1]
-	    163977 t.fifo_in2.reset_bufarray.buf1._y : 1  [by t.fifo_in2._reset_BX:=0]
-	    165739 t.fifo_in1.reset_bufarray.buf1._y : 1  [by t.fifo_in1._reset_BX:=0]
-	    180082 t.fifo_in1._reset_BXX[0] : 0  [by t.fifo_in1.reset_bufarray.buf1._y:=1]
-	    180083 t.fifo_in1.fifo_element[0].reset_buf._y : 1  [by t.fifo_in1._reset_BXX[0]:=0]
-	    180083 t.fifo_in1.fifo_element[3].reset_buf._y : 1  [by t.fifo_in1._reset_BXX[0]:=0]
-	    180365 t.fifo_in1.fifo_element[3]._reset_BX : 0  [by t.fifo_in1.fifo_element[3].reset_buf._y:=1]
-	    180368 t.fifo_in1.fifo_element[3].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[3]._reset_BX:=0]
-	    180504 t.fifo_in1.fifo_element[2].reset_buf._y : 1  [by t.fifo_in1._reset_BXX[0]:=0]
-	    181055 t.fifo_in1.fifo_element[2]._reset_BX : 0  [by t.fifo_in1.fifo_element[2].reset_buf._y:=1]
-	    181133 t.fifo_in1.fifo_element[3].buf_func._y : 1  [by t.fifo_in1.fifo_element[3]._reset_BX:=0]
-	    182009 t.fifo_in1.fifo_element[2].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[2]._reset_BX:=0]
-	    182126 t.fifo_in1.fifo_element[2].buf_func._y : 1  [by t.fifo_in1.fifo_element[2]._reset_BX:=0]
-	    182214 t._out1.r : 0  [by t.fifo_in1.fifo_element[3].buf_func._y:=1]
-	    182232 t.arb.arbiter._y1 : 1  [by t._out1.r:=0]
-	    183108 t.fifo_in1.fifo_element[3].in.r : 0  [by t.fifo_in1.fifo_element[2].buf_func._y:=1]
-	    186245 t.arb._y1_arb : 0  [by t.arb.arbiter._y1:=1]
-	    188789 t.fifo_in2._reset_BXX[0] : 0  [by t.fifo_in2.reset_bufarray.buf1._y:=1]
-	    189291 t.fifo_in2.fifo_element[3].reset_buf._y : 1  [by t.fifo_in2._reset_BXX[0]:=0]
-	    189494 t.fifo_in2.fifo_element[3]._reset_BX : 0  [by t.fifo_in2.fifo_element[3].reset_buf._y:=1]
-	    189633 t.fifo_in2.fifo_element[3].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[3]._reset_BX:=0]
-	    190248 t.arb.ack_cell1._y : 1  [by t.arb._y1_arb:=0]
-	    190317 t._out1.a : 0  [by t.arb.ack_cell1._y:=1]
-	    190328 t.fifo_in1.fifo_element[3]._out_a_B : 1  [by t._out1.a:=0]
-	    191348 t.fifo_in2.fifo_element[3].buf_func._y : 1  [by t.fifo_in2.fifo_element[3]._reset_BX:=0]
-	    193549 t.fifo_in2.fifo_element[0].reset_buf._y : 1  [by t.fifo_in2._reset_BXX[0]:=0]
-	    193753 t.fifo_in2.fifo_element[0]._reset_BX : 0  [by t.fifo_in2.fifo_element[0].reset_buf._y:=1]
-	    193754 t.fifo_in2.fifo_element[0].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[0]._reset_BX:=0]
-	    193768 t.fifo_in2.fifo_element[0].buf_func._y : 1  [by t.fifo_in2.fifo_element[0]._reset_BX:=0]
-	    193791 t.in2.a : 0  [by t.fifo_in2.fifo_element[0].inack_ctl._y:=1]
-	    194507 t.fifo_in2.fifo_element[1].in.r : 0  [by t.fifo_in2.fifo_element[0].buf_func._y:=1]
-	    194619 t.fifo_in2.fifo_element[0]._en : 1  [by t.fifo_in2.fifo_element[1].in.r:=0]
-	    200288 t.fifo_in1.fifo_element[0]._reset_BX : 0  [by t.fifo_in1.fifo_element[0].reset_buf._y:=1]
-	    200328 t.fifo_in1.fifo_element[0].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[0]._reset_BX:=0]
-	    200585 t.in1.a : 0  [by t.fifo_in1.fifo_element[0].inack_ctl._y:=1]
-	    202809 t.fifo_in1.fifo_element[3].in.a : 0  [by t.fifo_in1.fifo_element[3].inack_ctl._y:=1]
-	    202896 t.fifo_in1.fifo_element[3]._en : 1  [by t.fifo_in1.fifo_element[3].in.a:=0]
-	    203103 t.fifo_in1.fifo_element[2]._out_a_B : 1  [by t.fifo_in1.fifo_element[3].in.a:=0]
-	    210373 t.fifo_in2.fifo_element[1].reset_buf._y : 1  [by t.fifo_in2._reset_BXX[0]:=0]
-	    210374 t.fifo_in2.fifo_element[1]._reset_BX : 0  [by t.fifo_in2.fifo_element[1].reset_buf._y:=1]
-	    212180 t.fifo_in2.fifo_element[1].buf_func._y : 1  [by t.fifo_in2.fifo_element[1]._reset_BX:=0]
-	    212381 t.fifo_in2.fifo_element[1].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[1]._reset_BX:=0]
-	    212971 t.fifo_in2.fifo_element[1].in.a : 0  [by t.fifo_in2.fifo_element[1].inack_ctl._y:=1]
-	    213149 t.fifo_in2.fifo_element[0]._out_a_B : 1  [by t.fifo_in2.fifo_element[1].in.a:=0]
-	    213389 t.fifo_in2.fifo_element[2].in.r : 0  [by t.fifo_in2.fifo_element[1].buf_func._y:=1]
-	    214192 t.fifo_in2.fifo_element[1]._en : 1  [by t.fifo_in2.fifo_element[2].in.r:=0]
-	    225979 t.fifo_in2.fifo_element[3].in.a : 0  [by t.fifo_in2.fifo_element[3].inack_ctl._y:=1]
-	    226143 t.fifo_in2.fifo_element[2]._out_a_B : 1  [by t.fifo_in2.fifo_element[3].in.a:=0]
-	    228796 t.fifo_in1.fifo_element[1].reset_buf._y : 1  [by t.fifo_in1._reset_BXX[0]:=0]
-	    230991 t.fifo_in1.fifo_element[1]._reset_BX : 0  [by t.fifo_in1.fifo_element[1].reset_buf._y:=1]
-	    231013 t.fifo_in1.fifo_element[1].buf_func._y : 1  [by t.fifo_in1.fifo_element[1]._reset_BX:=0]
-	    231838 t.fifo_in1.fifo_element[1].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[1]._reset_BX:=0]
-	    231971 t.fifo_in1.fifo_element[1].in.a : 0  [by t.fifo_in1.fifo_element[1].inack_ctl._y:=1]
-	    233690 t.fifo_in2.fifo_element[2].reset_buf._y : 1  [by t.fifo_in2._reset_BXX[0]:=0]
-	    234049 t.fifo_in2.fifo_element[2]._reset_BX : 0  [by t.fifo_in2.fifo_element[2].reset_buf._y:=1]
-	    234270 t.fifo_in2.fifo_element[2].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[2]._reset_BX:=0]
-	    234277 t.fifo_in2.fifo_element[2].in.a : 0  [by t.fifo_in2.fifo_element[2].inack_ctl._y:=1]
-	    234307 t.fifo_in2.fifo_element[1]._out_a_B : 1  [by t.fifo_in2.fifo_element[2].in.a:=0]
-	    236479 t.fifo_in1.fifo_element[2].in.a : 0  [by t.fifo_in1.fifo_element[2].inack_ctl._y:=1]
-	    243134 t._out2.r : 0  [by t.fifo_in2.fifo_element[3].buf_func._y:=1]
-	    243192 t.fifo_in1.fifo_element[2]._en : 1  [by t.fifo_in1.fifo_element[2].in.a:=0]
-	    243225 t.fifo_in2.fifo_element[3]._en : 1  [by t._out2.r:=0]
-	    245323 t.arb.arbiter._y2 : 1  [by t._out2.r:=0]
-	    245330 t.arb._y2_arb : 0  [by t.arb.arbiter._y2:=1]
-	    245436 t.arb.ack_cell2._y : 1  [by t.arb._y2_arb:=0]
-	    245514 t._out2.a : 0  [by t.arb.ack_cell2._y:=1]
-	    245789 t.fifo_in2.fifo_element[3]._out_a_B : 1  [by t._out2.a:=0]
-	    247633 t.fifo_in1.fifo_element[0]._out_a_B : 1  [by t.fifo_in1.fifo_element[1].in.a:=0]
-	    247800 t.fifo_in1.fifo_element[0].buf_func._y : 1  [by t.fifo_in1.fifo_element[0]._reset_BX:=0]
-	    248117 t.arb.or_cell._y : 1  [by t.arb._y2_arb:=0]
-	    248165 t.fifo_in2.fifo_element[2].buf_func._y : 1  [by t.fifo_in2.fifo_element[2]._reset_BX:=0]
-	    248177 t.fifo_in2.fifo_element[3].in.r : 0  [by t.fifo_in2.fifo_element[2].buf_func._y:=1]
-	    248572 t.out.r : 0  [by t.arb.or_cell._y:=1]
-	    248581 t.fifo_in2.fifo_element[2]._en : 1  [by t.fifo_in2.fifo_element[3].in.r:=0]
-	    261141 t.fifo_in1.fifo_element[2].in.r : 0  [by t.fifo_in1.fifo_element[1].buf_func._y:=1]
-	    261153 t.fifo_in1.fifo_element[1]._en : 1  [by t.fifo_in1.fifo_element[2].in.r:=0]
-	    266796 t.fifo_in1.fifo_element[1].in.r : 0  [by t.fifo_in1.fifo_element[0].buf_func._y:=1]
-	    272712 t.fifo_in1.fifo_element[0]._en : 1  [by t.fifo_in1.fifo_element[1].in.r:=0]
-	    293940 t.fifo_in1.fifo_element[1]._out_a_B : 1  [by t.fifo_in1.fifo_element[2].in.a:=0]
-
-	    293940 Reset : 1
-	    296839 t.fifo_in1.reset_buf._y : 0  [by Reset:=1]
-	    298216 t.fifo_in2.reset_buf._y : 0  [by Reset:=1]
-	    298218 t.fifo_in2._reset_BX : 1  [by t.fifo_in2.reset_buf._y:=0]
-	    301134 t.fifo_in1._reset_BX : 1  [by t.fifo_in1.reset_buf._y:=0]
-	    302383 t.fifo_in1.reset_bufarray.buf1._y : 0  [by t.fifo_in1._reset_BX:=1]
-	    302753 t.fifo_in2.reset_bufarray.buf1._y : 0  [by t.fifo_in2._reset_BX:=1]
-	    302919 t.fifo_in2._reset_BXX[0] : 1  [by t.fifo_in2.reset_bufarray.buf1._y:=0]
-	    302994 t.fifo_in2.fifo_element[2].reset_buf._y : 0  [by t.fifo_in2._reset_BXX[0]:=1]
-	    302996 t.fifo_in2.fifo_element[2]._reset_BX : 1  [by t.fifo_in2.fifo_element[2].reset_buf._y:=0]
-	    303057 t.fifo_in2.fifo_element[0].reset_buf._y : 0  [by t.fifo_in2._reset_BXX[0]:=1]
-	    303264 t.fifo_in2.fifo_element[1].reset_buf._y : 0  [by t.fifo_in2._reset_BXX[0]:=1]
-	    303265 t.fifo_in2.fifo_element[1]._reset_BX : 1  [by t.fifo_in2.fifo_element[1].reset_buf._y:=0]
-	    305882 t.fifo_in1._reset_BXX[0] : 1  [by t.fifo_in1.reset_bufarray.buf1._y:=0]
-	    305893 t.fifo_in1.fifo_element[1].reset_buf._y : 0  [by t.fifo_in1._reset_BXX[0]:=1]
-	    305949 t.fifo_in1.fifo_element[3].reset_buf._y : 0  [by t.fifo_in1._reset_BXX[0]:=1]
-	    305965 t.fifo_in1.fifo_element[3]._reset_BX : 1  [by t.fifo_in1.fifo_element[3].reset_buf._y:=0]
-	    306252 t.fifo_in1.fifo_element[0].reset_buf._y : 0  [by t.fifo_in1._reset_BXX[0]:=1]
-	    306430 t.fifo_in1.fifo_element[2].reset_buf._y : 0  [by t.fifo_in1._reset_BXX[0]:=1]
-	    306958 t.fifo_in1.fifo_element[2]._reset_BX : 1  [by t.fifo_in1.fifo_element[2].reset_buf._y:=0]
-	    308182 t.fifo_in2.fifo_element[3].reset_buf._y : 0  [by t.fifo_in2._reset_BXX[0]:=1]
-	    308534 t.fifo_in1.fifo_element[1]._reset_BX : 1  [by t.fifo_in1.fifo_element[1].reset_buf._y:=0]
-	    310617 t.fifo_in2.fifo_element[3]._reset_BX : 1  [by t.fifo_in2.fifo_element[3].reset_buf._y:=0]
-	    310814 t.fifo_in1.fifo_element[0]._reset_BX : 1  [by t.fifo_in1.fifo_element[0].reset_buf._y:=0]
-	    346974 t.fifo_in2.fifo_element[0]._reset_BX : 1  [by t.fifo_in2.fifo_element[0].reset_buf._y:=0]
-[1] reset done
-----------------------------------------------------------------------------------------------------
-	    346974 t.in1.r : 1
-	    346974 t.in2.r : 1
-	    370899 t.fifo_in2.fifo_element[0].buf_func._y : 0  [by t.in2.r:=1]
-	    373854 t.fifo_in1.fifo_element[0].buf_func._y : 0  [by t.in1.r:=1]
-	    373856 t.fifo_in1.fifo_element[1].in.r : 1  [by t.fifo_in1.fifo_element[0].buf_func._y:=0]
-	    373859 t.fifo_in1.fifo_element[0].inack_ctl._y : 0  [by t.fifo_in1.fifo_element[1].in.r:=1]
-	    373888 t.in1.a : 1  [by t.fifo_in1.fifo_element[0].inack_ctl._y:=0]
-	    374205 t.fifo_in1.fifo_element[0]._en : 0  [by t.in1.a:=1]
-	    383940 t.fifo_in2.fifo_element[1].in.r : 1  [by t.fifo_in2.fifo_element[0].buf_func._y:=0]
-	    384093 t.fifo_in2.fifo_element[0].inack_ctl._y : 0  [by t.fifo_in2.fifo_element[1].in.r:=1]
-	    384137 t.in2.a : 1  [by t.fifo_in2.fifo_element[0].inack_ctl._y:=0]
-	    385541 t.fifo_in2.fifo_element[1].buf_func._y : 0  [by t.fifo_in2.fifo_element[1].in.r:=1]
-	    386898 t.fifo_in2.fifo_element[0]._en : 0  [by t.in2.a:=1]
-	    399224 t.fifo_in2.fifo_element[2].in.r : 1  [by t.fifo_in2.fifo_element[1].buf_func._y:=0]
-	    399225 t.fifo_in2.fifo_element[2].buf_func._y : 0  [by t.fifo_in2.fifo_element[2].in.r:=1]
-	    399247 t.fifo_in2.fifo_element[3].in.r : 1  [by t.fifo_in2.fifo_element[2].buf_func._y:=0]
-	    399248 t.fifo_in2.fifo_element[3].buf_func._y : 0  [by t.fifo_in2.fifo_element[3].in.r:=1]
-	    399441 t.fifo_in2.fifo_element[1].inack_ctl._y : 0  [by t.fifo_in2.fifo_element[2].in.r:=1]
-	    399600 t.fifo_in2.fifo_element[1].in.a : 1  [by t.fifo_in2.fifo_element[1].inack_ctl._y:=0]
-	    400828 t.fifo_in2.fifo_element[2].inack_ctl._y : 0  [by t.fifo_in2.fifo_element[3].in.r:=1]
-	    400887 t.fifo_in2.fifo_element[0]._out_a_B : 0  [by t.fifo_in2.fifo_element[1].in.a:=1]
-	    401032 t.fifo_in2.fifo_element[0].buf_func._y : 1  [by t.fifo_in2.fifo_element[0]._out_a_B:=0]
-	    403060 t.fifo_in2.fifo_element[2].in.a : 1  [by t.fifo_in2.fifo_element[2].inack_ctl._y:=0]
-	    403061 t.fifo_in2.fifo_element[1]._out_a_B : 0  [by t.fifo_in2.fifo_element[2].in.a:=1]
-	    403864 t.fifo_in2.fifo_element[1].in.r : 0  [by t.fifo_in2.fifo_element[0].buf_func._y:=1]
-	    408593 t._out2.r : 1  [by t.fifo_in2.fifo_element[3].buf_func._y:=0]
-	    408755 t.fifo_in2.fifo_element[3].inack_ctl._y : 0  [by t._out2.r:=1]
-	    409414 t.fifo_in2.fifo_element[2]._en : 0  [by t.fifo_in2.fifo_element[2].in.a:=1]
-	    416124 t.fifo_in2.fifo_element[3].in.a : 1  [by t.fifo_in2.fifo_element[3].inack_ctl._y:=0]
-	    416131 t.fifo_in2.fifo_element[2]._out_a_B : 0  [by t.fifo_in2.fifo_element[3].in.a:=1]
-	    416138 t.fifo_in2.fifo_element[3]._en : 0  [by t.fifo_in2.fifo_element[3].in.a:=1]
-	    416291 t.fifo_in2.fifo_element[2].buf_func._y : 1  [by t.fifo_in2.fifo_element[2]._out_a_B:=0]
-	    419276 t.fifo_in2.fifo_element[1]._en : 0  [by t.fifo_in2.fifo_element[1].in.a:=1]
-	    419277 t.fifo_in2.fifo_element[1].buf_func._y : 1  [by t.fifo_in2.fifo_element[1]._en:=0]
-	    419277 t.fifo_in2.fifo_element[1].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[1]._en:=0]
-	    419278 t.fifo_in2.fifo_element[2].in.r : 0  [by t.fifo_in2.fifo_element[1].buf_func._y:=1]
-	    419465 t.fifo_in2.fifo_element[2].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[2].in.r:=0]
-	    419466 t.fifo_in2.fifo_element[2].in.a : 0  [by t.fifo_in2.fifo_element[2].inack_ctl._y:=1]
-	    421520 t.fifo_in2.fifo_element[1].in.a : 0  [by t.fifo_in2.fifo_element[1].inack_ctl._y:=1]
-	    421521 t.fifo_in2.fifo_element[0]._out_a_B : 1  [by t.fifo_in2.fifo_element[1].in.a:=0]
-	    423648 t.fifo_in2.fifo_element[1]._out_a_B : 1  [by t.fifo_in2.fifo_element[2].in.a:=0]
-	    434814 t.fifo_in1.fifo_element[1].buf_func._y : 0  [by t.fifo_in1.fifo_element[1].in.r:=1]
-	    435667 t.fifo_in1.fifo_element[2].in.r : 1  [by t.fifo_in1.fifo_element[1].buf_func._y:=0]
-	    435672 t.fifo_in1.fifo_element[2].buf_func._y : 0  [by t.fifo_in1.fifo_element[2].in.r:=1]
-	    435673 t.fifo_in1.fifo_element[3].in.r : 1  [by t.fifo_in1.fifo_element[2].buf_func._y:=0]
-	    435690 t.fifo_in1.fifo_element[3].buf_func._y : 0  [by t.fifo_in1.fifo_element[3].in.r:=1]
-	    436558 t.fifo_in1.fifo_element[1].inack_ctl._y : 0  [by t.fifo_in1.fifo_element[2].in.r:=1]
-	    436561 t.fifo_in1.fifo_element[1].in.a : 1  [by t.fifo_in1.fifo_element[1].inack_ctl._y:=0]
-	    437502 t.fifo_in1.fifo_element[1]._en : 0  [by t.fifo_in1.fifo_element[1].in.a:=1]
-	    437848 t.fifo_in2.fifo_element[3].in.r : 0  [by t.fifo_in2.fifo_element[2].buf_func._y:=1]
-	    437849 t.fifo_in2.fifo_element[3].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[3].in.r:=0]
-	    437890 t.fifo_in2.fifo_element[2]._en : 1  [by t.fifo_in2.fifo_element[3].in.r:=0]
-	    438246 t.fifo_in1.fifo_element[2].inack_ctl._y : 0  [by t.fifo_in1.fifo_element[3].in.r:=1]
-	    440666 t.fifo_in2.fifo_element[3].in.a : 0  [by t.fifo_in2.fifo_element[3].inack_ctl._y:=1]
-	    440761 t.fifo_in2.fifo_element[2]._out_a_B : 1  [by t.fifo_in2.fifo_element[3].in.a:=0]
-	    444051 t._out1.r : 1  [by t.fifo_in1.fifo_element[3].buf_func._y:=0]
-	    444059 t.fifo_in1.fifo_element[3].inack_ctl._y : 0  [by t._out1.r:=1]
-	    444093 t.fifo_in1.fifo_element[3].in.a : 1  [by t.fifo_in1.fifo_element[3].inack_ctl._y:=0]
-	    445011 t.fifo_in1.fifo_element[2]._out_a_B : 0  [by t.fifo_in1.fifo_element[3].in.a:=1]
-	    447877 t.arb.arbiter._y2 : 0  [by t._out2.r:=1]
-	    447881 t.arb._y2_arb : 1  [by t.arb.arbiter._y2:=0]
-	    451979 t.fifo_in1.fifo_element[2].in.a : 1  [by t.fifo_in1.fifo_element[2].inack_ctl._y:=0]
-	    454377 t.fifo_in1.fifo_element[2]._en : 0  [by t.fifo_in1.fifo_element[2].in.a:=1]
-	    455194 t.fifo_in1.fifo_element[1]._out_a_B : 0  [by t.fifo_in1.fifo_element[2].in.a:=1]
-	    455242 t.fifo_in1.fifo_element[1].buf_func._y : 1  [by t.fifo_in1.fifo_element[1]._out_a_B:=0]
-	    455245 t.fifo_in1.fifo_element[2].in.r : 0  [by t.fifo_in1.fifo_element[1].buf_func._y:=1]
-	    455423 t.fifo_in1.fifo_element[2].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[2].in.r:=0]
-	    456302 t.fifo_in2.fifo_element[1]._en : 1  [by t.fifo_in2.fifo_element[1].in.a:=0]
-	    457980 t.fifo_in1.fifo_element[3]._en : 0  [by t.fifo_in1.fifo_element[3].in.a:=1]
-	    476400 t.fifo_in1.fifo_element[2].in.a : 0  [by t.fifo_in1.fifo_element[2].inack_ctl._y:=1]
-	    488299 t.fifo_in1.fifo_element[1]._out_a_B : 1  [by t.fifo_in1.fifo_element[2].in.a:=0]
-	    494259 t.arb.or_cell._y : 0  [by t.arb._y2_arb:=1]
-	    495523 t.fifo_in1.fifo_element[0]._out_a_B : 0  [by t.fifo_in1.fifo_element[1].in.a:=1]
-	    500210 t.out.r : 1  [by t.arb.or_cell._y:=0]
-	    501496 t.fifo_in1.fifo_element[2].buf_func._y : 1  [by t.fifo_in1.fifo_element[2]._en:=0]
-	    502323 t.fifo_in1.fifo_element[3].in.r : 0  [by t.fifo_in1.fifo_element[2].buf_func._y:=1]
-	    502496 t.fifo_in1.fifo_element[3].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[3].in.r:=0]
-	    502497 t.fifo_in1.fifo_element[3].in.a : 0  [by t.fifo_in1.fifo_element[3].inack_ctl._y:=1]
-	    502507 t.fifo_in1.fifo_element[2]._en : 1  [by t.fifo_in1.fifo_element[3].in.r:=0]
-	    502570 t.fifo_in1.fifo_element[2]._out_a_B : 1  [by t.fifo_in1.fifo_element[3].in.a:=0]
-	    535008 t.fifo_in1.fifo_element[0].buf_func._y : 1  [by t.fifo_in1.fifo_element[0]._out_a_B:=0]
-	    535012 t.fifo_in1.fifo_element[1].in.r : 0  [by t.fifo_in1.fifo_element[0].buf_func._y:=1]
-	    572300 t.fifo_in1.fifo_element[1].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[1].in.r:=0]
-	    572396 t.fifo_in1.fifo_element[1].in.a : 0  [by t.fifo_in1.fifo_element[1].inack_ctl._y:=1]
-	    572397 t.fifo_in1.fifo_element[0]._out_a_B : 1  [by t.fifo_in1.fifo_element[1].in.a:=0]
-	    572532 t.fifo_in1.fifo_element[1]._en : 1  [by t.fifo_in1.fifo_element[1].in.a:=0]
-----------------------------------------------------------------------------------------------------
-[2] 1 bit processed by the arbiter
-	    572532 t.out.a : 1
-	    591578 t.arb.ack_cell2._y : 0  [by t.out.a:=1]
-	    591819 t._out2.a : 1  [by t.arb.ack_cell2._y:=0]
-	    595778 t.fifo_in2.fifo_element[3]._out_a_B : 0  [by t._out2.a:=1]
-	    595790 t.fifo_in2.fifo_element[3].buf_func._y : 1  [by t.fifo_in2.fifo_element[3]._out_a_B:=0]
-	    599690 t._out2.r : 0  [by t.fifo_in2.fifo_element[3].buf_func._y:=1]
-	    599691 t.arb.arbiter._y2 : 1  [by t._out2.r:=0]
-	    599747 t.arb.arbiter._y1 : 0  [by t.arb.arbiter._y2:=1]
-	    600719 t.fifo_in2.fifo_element[3]._en : 1  [by t._out2.r:=0]
-	    644697 t.arb._y2_arb : 0  [by t.arb.arbiter._y2:=1]
-	    644698 t.arb.or_cell._y : 1  [by t.arb._y2_arb:=0]
-	    644735 t.out.r : 0  [by t.arb.or_cell._y:=1]
-	    644735 t.out.a : 0
-	    668110 t.arb.ack_cell2._y : 1  [by t.out.a:=0]
-	    668111 t._out2.a : 0  [by t.arb.ack_cell2._y:=1]
-	    669803 t.arb._y1_arb : 1  [by t._out2.a:=0]
-	    669816 t.arb.or_cell._y : 0  [by t.arb._y1_arb:=1]
-	    671675 t.fifo_in2.fifo_element[3]._out_a_B : 1  [by t._out2.a:=0]
-	    686800 t.out.r : 1  [by t.arb.or_cell._y:=0]
-----------------------------------------------------------------------------------------------------
-[3] 2 bit processed by the arbiter
-	    686800 t.out.a : 1
-	    686800 t.in2.r : 0
-	    686800 t.in1.r : 0
-	    686821 t.fifo_in1.fifo_element[0].inack_ctl._y : 1  [by t.in1.r:=0]
-	    686822 t.in1.a : 0  [by t.fifo_in1.fifo_element[0].inack_ctl._y:=1]
-	    686825 t.fifo_in2.fifo_element[0].inack_ctl._y : 1  [by t.in2.r:=0]
-	    686826 t.in2.a : 0  [by t.fifo_in2.fifo_element[0].inack_ctl._y:=1]
-	    686827 t.fifo_in2.fifo_element[0]._en : 1  [by t.in2.a:=0]
-	    687157 t.arb.ack_cell1._y : 0  [by t.out.a:=1]
-	    687318 t._out1.a : 1  [by t.arb.ack_cell1._y:=0]
-	    688355 t.fifo_in1.fifo_element[3]._out_a_B : 0  [by t._out1.a:=1]
-	    688360 t.fifo_in1.fifo_element[3].buf_func._y : 1  [by t.fifo_in1.fifo_element[3]._out_a_B:=0]
-	    688941 t._out1.r : 0  [by t.fifo_in1.fifo_element[3].buf_func._y:=1]
-	    688952 t.fifo_in1.fifo_element[3]._en : 1  [by t._out1.r:=0]
-	    689349 t.arb.arbiter._y1 : 1  [by t._out1.r:=0]
-	    690396 t.arb._y1_arb : 0  [by t.arb.arbiter._y1:=1]
-	    690410 t.arb.or_cell._y : 1  [by t.arb._y1_arb:=0]
-	    690428 t.out.r : 0  [by t.arb.or_cell._y:=1]
-	    696470 t.fifo_in1.fifo_element[0]._en : 1  [by t.in1.a:=0]
-	    696470 t.out.a : 0
-	    696470 t.in2.r : 1
-	    696470 t.in1.r : 1
-	    696474 t.arb.ack_cell1._y : 1  [by t.out.a:=0]
-	    696574 t.fifo_in2.fifo_element[0].buf_func._y : 0  [by t.in2.r:=1]
-	    697678 t._out1.a : 0  [by t.arb.ack_cell1._y:=1]
-	    697906 t.fifo_in1.fifo_element[3]._out_a_B : 1  [by t._out1.a:=0]
-	    705029 t.fifo_in2.fifo_element[1].in.r : 1  [by t.fifo_in2.fifo_element[0].buf_func._y:=0]
-	    705872 t.fifo_in2.fifo_element[1].buf_func._y : 0  [by t.fifo_in2.fifo_element[1].in.r:=1]
-	    705942 t.fifo_in2.fifo_element[2].in.r : 1  [by t.fifo_in2.fifo_element[1].buf_func._y:=0]
-	    705953 t.fifo_in2.fifo_element[1].inack_ctl._y : 0  [by t.fifo_in2.fifo_element[2].in.r:=1]
-	    705956 t.fifo_in2.fifo_element[1].in.a : 1  [by t.fifo_in2.fifo_element[1].inack_ctl._y:=0]
-	    706010 t.fifo_in2.fifo_element[1]._en : 0  [by t.fifo_in2.fifo_element[1].in.a:=1]
-	    706488 t.fifo_in2.fifo_element[0].inack_ctl._y : 0  [by t.fifo_in2.fifo_element[1].in.r:=1]
-	    707104 t.fifo_in2.fifo_element[0]._out_a_B : 0  [by t.fifo_in2.fifo_element[1].in.a:=1]
-	    707649 t.in2.a : 1  [by t.fifo_in2.fifo_element[0].inack_ctl._y:=0]
-	    716301 t.fifo_in2.fifo_element[0]._en : 0  [by t.in2.a:=1]
-	    716382 t.fifo_in2.fifo_element[0].buf_func._y : 1  [by t.fifo_in2.fifo_element[0]._en:=0]
-	    727459 t.fifo_in2.fifo_element[1].in.r : 0  [by t.fifo_in2.fifo_element[0].buf_func._y:=1]
-	    727914 t.fifo_in1.fifo_element[0].buf_func._y : 0  [by t.in1.r:=1]
-	    728006 t.fifo_in1.fifo_element[1].in.r : 1  [by t.fifo_in1.fifo_element[0].buf_func._y:=0]
-	    729750 t.fifo_in1.fifo_element[0].inack_ctl._y : 0  [by t.fifo_in1.fifo_element[1].in.r:=1]
-	    730363 t.in1.a : 1  [by t.fifo_in1.fifo_element[0].inack_ctl._y:=0]
-	    736317 t.fifo_in1.fifo_element[1].buf_func._y : 0  [by t.fifo_in1.fifo_element[1].in.r:=1]
-	    736362 t.fifo_in1.fifo_element[2].in.r : 1  [by t.fifo_in1.fifo_element[1].buf_func._y:=0]
-	    737359 t.fifo_in1.fifo_element[2].buf_func._y : 0  [by t.fifo_in1.fifo_element[2].in.r:=1]
-	    737884 t.fifo_in1.fifo_element[3].in.r : 1  [by t.fifo_in1.fifo_element[2].buf_func._y:=0]
-	    737936 t.fifo_in1.fifo_element[2].inack_ctl._y : 0  [by t.fifo_in1.fifo_element[3].in.r:=1]
-	    737943 t.fifo_in1.fifo_element[2].in.a : 1  [by t.fifo_in1.fifo_element[2].inack_ctl._y:=0]
-	    738011 t.fifo_in1.fifo_element[1].inack_ctl._y : 0  [by t.fifo_in1.fifo_element[2].in.r:=1]
-	    738013 t.fifo_in1.fifo_element[1].in.a : 1  [by t.fifo_in1.fifo_element[1].inack_ctl._y:=0]
-	    738146 t.fifo_in1.fifo_element[0]._out_a_B : 0  [by t.fifo_in1.fifo_element[1].in.a:=1]
-	    738367 t.fifo_in1.fifo_element[1]._en : 0  [by t.fifo_in1.fifo_element[1].in.a:=1]
-	    738784 t.fifo_in1.fifo_element[3].buf_func._y : 0  [by t.fifo_in1.fifo_element[3].in.r:=1]
-	    738785 t._out1.r : 1  [by t.fifo_in1.fifo_element[3].buf_func._y:=0]
-	    738789 t.arb.arbiter._y1 : 0  [by t._out1.r:=1]
-	    739331 t.fifo_in1.fifo_element[3].inack_ctl._y : 0  [by t._out1.r:=1]
-	    739332 t.fifo_in1.fifo_element[3].in.a : 1  [by t.fifo_in1.fifo_element[3].inack_ctl._y:=0]
-	    739411 t.fifo_in1.fifo_element[2]._out_a_B : 0  [by t.fifo_in1.fifo_element[3].in.a:=1]
-	    744385 t.fifo_in1.fifo_element[0]._en : 0  [by t.in1.a:=1]
-	    744410 t.fifo_in1.fifo_element[1]._out_a_B : 0  [by t.fifo_in1.fifo_element[2].in.a:=1]
-	    744498 t.fifo_in1.fifo_element[1].buf_func._y : 1  [by t.fifo_in1.fifo_element[1]._out_a_B:=0]
-	    745442 t.fifo_in2.fifo_element[1].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[1].in.r:=0]
-	    746818 t.fifo_in1.fifo_element[0].buf_func._y : 1  [by t.fifo_in1.fifo_element[0]._en:=0]
-	    746877 t.fifo_in1.fifo_element[1].in.r : 0  [by t.fifo_in1.fifo_element[0].buf_func._y:=1]
-	    746907 t.fifo_in1.fifo_element[1].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[1].in.r:=0]
-	    748374 t.fifo_in1.fifo_element[1].in.a : 0  [by t.fifo_in1.fifo_element[1].inack_ctl._y:=1]
-	    751710 t.fifo_in1.fifo_element[3]._en : 0  [by t.fifo_in1.fifo_element[3].in.a:=1]
-	    752280 t.fifo_in1.fifo_element[2].in.r : 0  [by t.fifo_in1.fifo_element[1].buf_func._y:=1]
-	    753555 t.fifo_in1.fifo_element[2]._en : 0  [by t.fifo_in1.fifo_element[2].in.a:=1]
-	    754240 t.fifo_in1.fifo_element[2].buf_func._y : 1  [by t.fifo_in1.fifo_element[2]._en:=0]
-	    754367 t.fifo_in1.fifo_element[3].in.r : 0  [by t.fifo_in1.fifo_element[2].buf_func._y:=1]
-	    754536 t.fifo_in1.fifo_element[3].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[3].in.r:=0]
-	    754579 t.fifo_in1.fifo_element[3].in.a : 0  [by t.fifo_in1.fifo_element[3].inack_ctl._y:=1]
-	    754591 t.fifo_in1.fifo_element[2]._out_a_B : 1  [by t.fifo_in1.fifo_element[3].in.a:=0]
-	    756364 t.fifo_in2.fifo_element[2].buf_func._y : 0  [by t.fifo_in2.fifo_element[2].in.r:=1]
-	    757643 t.fifo_in2.fifo_element[3].in.r : 1  [by t.fifo_in2.fifo_element[2].buf_func._y:=0]
-	    757646 t.fifo_in2.fifo_element[2].inack_ctl._y : 0  [by t.fifo_in2.fifo_element[3].in.r:=1]
-	    757684 t.fifo_in2.fifo_element[2].in.a : 1  [by t.fifo_in2.fifo_element[2].inack_ctl._y:=0]
-	    757685 t.fifo_in2.fifo_element[2]._en : 0  [by t.fifo_in2.fifo_element[2].in.a:=1]
-	    757876 t.fifo_in2.fifo_element[3].buf_func._y : 0  [by t.fifo_in2.fifo_element[3].in.r:=1]
-	    757968 t._out2.r : 1  [by t.fifo_in2.fifo_element[3].buf_func._y:=0]
-	    760695 t.fifo_in2.fifo_element[3].inack_ctl._y : 0  [by t._out2.r:=1]
-	    760697 t.fifo_in2.fifo_element[3].in.a : 1  [by t.fifo_in2.fifo_element[3].inack_ctl._y:=0]
-	    760698 t.fifo_in2.fifo_element[3]._en : 0  [by t.fifo_in2.fifo_element[3].in.a:=1]
-	    762198 t.fifo_in2.fifo_element[2]._out_a_B : 0  [by t.fifo_in2.fifo_element[3].in.a:=1]
-	    762200 t.fifo_in2.fifo_element[2].buf_func._y : 1  [by t.fifo_in2.fifo_element[2]._out_a_B:=0]
-	    762218 t.fifo_in2.fifo_element[3].in.r : 0  [by t.fifo_in2.fifo_element[2].buf_func._y:=1]
-	    762337 t.fifo_in2.fifo_element[3].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[3].in.r:=0]
-	    768057 t.fifo_in2.fifo_element[3].in.a : 0  [by t.fifo_in2.fifo_element[3].inack_ctl._y:=1]
-	    768065 t.fifo_in2.fifo_element[2]._out_a_B : 1  [by t.fifo_in2.fifo_element[3].in.a:=0]
-	    770270 t.fifo_in1.fifo_element[2].inack_ctl._y : 1  [by t.fifo_in1.fifo_element[2]._en:=0]
-	    770324 t.fifo_in1.fifo_element[2].in.a : 0  [by t.fifo_in1.fifo_element[2].inack_ctl._y:=1]
-	    770329 t.fifo_in1.fifo_element[1]._out_a_B : 1  [by t.fifo_in1.fifo_element[2].in.a:=0]
-	    770436 t.fifo_in2.fifo_element[1]._out_a_B : 0  [by t.fifo_in2.fifo_element[2].in.a:=1]
-	    771503 t.fifo_in2.fifo_element[1].buf_func._y : 1  [by t.fifo_in2.fifo_element[1]._out_a_B:=0]
-	    771504 t.fifo_in2.fifo_element[2].in.r : 0  [by t.fifo_in2.fifo_element[1].buf_func._y:=1]
-	    771642 t.fifo_in2.fifo_element[2].inack_ctl._y : 1  [by t.fifo_in2.fifo_element[2].in.r:=0]
-	    771643 t.fifo_in2.fifo_element[2].in.a : 0  [by t.fifo_in2.fifo_element[2].inack_ctl._y:=1]
-	    771664 t.fifo_in1.fifo_element[1]._en : 1  [by t.fifo_in1.fifo_element[2].in.r:=0]
-	    771707 t.fifo_in2.fifo_element[2]._en : 1  [by t.fifo_in2.fifo_element[2].in.a:=0]
-	    771766 t.fifo_in2.fifo_element[1]._out_a_B : 1  [by t.fifo_in2.fifo_element[2].in.a:=0]
-	    773769 t.fifo_in2.fifo_element[1].in.a : 0  [by t.fifo_in2.fifo_element[1].inack_ctl._y:=1]
-	    773771 t.fifo_in2.fifo_element[1]._en : 1  [by t.fifo_in2.fifo_element[1].in.a:=0]
-	    773806 t.fifo_in2.fifo_element[0]._out_a_B : 1  [by t.fifo_in2.fifo_element[1].in.a:=0]
-	    784352 t.arb._y1_arb : 1  [by t.arb.arbiter._y1:=0]
-	    784495 t.arb.or_cell._y : 0  [by t.arb._y1_arb:=1]
-	    784546 t.out.r : 1  [by t.arb.or_cell._y:=0]
-	    807878 t.fifo_in1.fifo_element[0]._out_a_B : 1  [by t.fifo_in1.fifo_element[1].in.a:=0]
-	    820862 t.fifo_in1.fifo_element[2]._en : 1  [by t.fifo_in1.fifo_element[2].in.a:=0]
-----------------------------------------------------------------------------------------------------
-[4] 3 bit processed by the arbiter
-	    820862 t.out.a : 1
-	    821304 t.arb.ack_cell1._y : 0  [by t.out.a:=1]
-	    821315 t._out1.a : 1  [by t.arb.ack_cell1._y:=0]
-	    821316 t.fifo_in1.fifo_element[3]._out_a_B : 0  [by t._out1.a:=1]
-	    821325 t.fifo_in1.fifo_element[3].buf_func._y : 1  [by t.fifo_in1.fifo_element[3]._out_a_B:=0]
-	    821350 t._out1.r : 0  [by t.fifo_in1.fifo_element[3].buf_func._y:=1]
-	    824871 t.fifo_in1.fifo_element[3]._en : 1  [by t._out1.r:=0]
-	    831603 t.arb.arbiter._y1 : 1  [by t._out1.r:=0]
-	    831748 t.arb.arbiter._y2 : 0  [by t.arb.arbiter._y1:=1]
-	    847771 t.arb._y1_arb : 0  [by t.arb.arbiter._y1:=1]
-	    848001 t.arb.or_cell._y : 1  [by t.arb._y1_arb:=0]
-	    848692 t.out.r : 0  [by t.arb.or_cell._y:=1]
-	    848692 t.out.a : 0
-	    848706 t.arb.ack_cell1._y : 1  [by t.out.a:=0]
-	    850249 t._out1.a : 0  [by t.arb.ack_cell1._y:=1]
-	    851860 t.arb._y2_arb : 1  [by t._out1.a:=0]
-	    851871 t.arb.or_cell._y : 0  [by t.arb._y2_arb:=1]
-	    851872 t.out.r : 1  [by t.arb.or_cell._y:=0]
-	    867761 t.fifo_in1.fifo_element[3]._out_a_B : 1  [by t._out1.a:=0]
-----------------------------------------------------------------------------------------------------
-[5] 4 bit processed by the arbiter

test/unit_tests/arbiter_handshake_adv/run/test.prs

@@ -1,606 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-"t.fifo_in2.reset_bufarray.buf1.a"->"t.fifo_in2.reset_bufarray.buf1._y"-
-~("t.fifo_in2.reset_bufarray.buf1.a")->"t.fifo_in2.reset_bufarray.buf1._y"+
-"t.fifo_in2.reset_bufarray.buf1._y"->"t.fifo_in2.reset_bufarray.buf1.y"-
-~("t.fifo_in2.reset_bufarray.buf1._y")->"t.fifo_in2.reset_bufarray.buf1.y"+
-= "t.fifo_in2.reset_bufarray.supply.vdd" "t.fifo_in2.reset_bufarray.buf1.vdd"
-= "t.fifo_in2.reset_bufarray.supply.vss" "t.fifo_in2.reset_bufarray.buf1.vss"
-= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.out[3]"
-= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.out[2]"
-= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.out[1]"
-= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.buf1.y"
-= "t.fifo_in2.reset_bufarray.in" "t.fifo_in2.reset_bufarray.buf1.a"
-"t.fifo_in2.reset_buf.a"->"t.fifo_in2.reset_buf._y"-
-~("t.fifo_in2.reset_buf.a")->"t.fifo_in2.reset_buf._y"+
-"t.fifo_in2.reset_buf._y"->"t.fifo_in2.reset_buf.y"-
-~("t.fifo_in2.reset_buf._y")->"t.fifo_in2.reset_buf.y"+
-= "t.fifo_in2.reset_B" "t.fifo_in2.reset_buf.a"
-= "t.fifo_in2.supply.vss" "t.fifo_in2.fifo_element[3].supply.vss"
-= "t.fifo_in2.supply.vdd" "t.fifo_in2.fifo_element[3].supply.vdd"
-= "t.fifo_in2.supply.vss" "t.fifo_in2.fifo_element[2].supply.vss"
-= "t.fifo_in2.supply.vdd" "t.fifo_in2.fifo_element[2].supply.vdd"
-= "t.fifo_in2.supply.vss" "t.fifo_in2.fifo_element[1].supply.vss"
-= "t.fifo_in2.supply.vdd" "t.fifo_in2.fifo_element[1].supply.vdd"
-= "t.fifo_in2.supply.vss" "t.fifo_in2.fifo_element[0].supply.vss"
-= "t.fifo_in2.supply.vdd" "t.fifo_in2.fifo_element[0].supply.vdd"
-= "t.fifo_in2.supply.vdd" "t.fifo_in2.reset_buf.vdd"
-= "t.fifo_in2.supply.vss" "t.fifo_in2.reset_buf.vss"
-= "t.fifo_in2._reset_BX" "t.fifo_in2.reset_bufarray.in"
-= "t.fifo_in2._reset_BX" "t.fifo_in2.reset_buf.y"
-"t.fifo_in2.fifo_element[0].reset_buf.a"->"t.fifo_in2.fifo_element[0].reset_buf._y"-
-~("t.fifo_in2.fifo_element[0].reset_buf.a")->"t.fifo_in2.fifo_element[0].reset_buf._y"+
-"t.fifo_in2.fifo_element[0].reset_buf._y"->"t.fifo_in2.fifo_element[0].reset_buf.y"-
-~("t.fifo_in2.fifo_element[0].reset_buf._y")->"t.fifo_in2.fifo_element[0].reset_buf.y"+
-"t.fifo_in2.fifo_element[0].inv_outa.a"->"t.fifo_in2.fifo_element[0].inv_outa.y"-
-~("t.fifo_in2.fifo_element[0].inv_outa.a")->"t.fifo_in2.fifo_element[0].inv_outa.y"+
-~"t.fifo_in2.fifo_element[0].inack_ctl.c1"&~"t.fifo_in2.fifo_element[0].inack_ctl.c2"|~"t.fifo_in2.fifo_element[0].inack_ctl.pr_B"->"t.fifo_in2.fifo_element[0].inack_ctl._y"+
-"t.fifo_in2.fifo_element[0].inack_ctl.c1"&"t.fifo_in2.fifo_element[0].inack_ctl.c2"&"t.fifo_in2.fifo_element[0].inack_ctl.n1"&"t.fifo_in2.fifo_element[0].inack_ctl.sr_B"->"t.fifo_in2.fifo_element[0].inack_ctl._y"-
-"t.fifo_in2.fifo_element[0].inack_ctl._y"->"t.fifo_in2.fifo_element[0].inack_ctl.y"-
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-"t.fifo_in2.fifo_element[3].buf_func.c1"&"t.fifo_in2.fifo_element[3].buf_func.c2"&"t.fifo_in2.fifo_element[3].buf_func.n1"&"t.fifo_in2.fifo_element[3].buf_func.sr_B"->"t.fifo_in2.fifo_element[3].buf_func._y"-
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-~("t.fifo_in2.fifo_element[3].buf_func._y")->"t.fifo_in2.fifo_element[3].buf_func.y"+
-= "t.fifo_in2.fifo_element[3].reset_B" "t.fifo_in2.fifo_element[3].reset_buf.a"
-= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].reset_buf.vdd"
-= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].buf_func.vdd"
-= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].inv_outa.vdd"
-= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].en_ctl.vdd"
-= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].inack_ctl.vdd"
-= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].reset_buf.vss"
-= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].buf_func.vss"
-= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].inv_outa.vss"
-= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].en_ctl.vss"
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-= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].buf_func.sr_B"
-= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].buf_func.pr_B"
-= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].inack_ctl.sr_B"
-= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].inack_ctl.pr_B"
-= "t.fifo_in2.fifo_element[3]._en" "t.fifo_in2.fifo_element[3].buf_func.c1"
-= "t.fifo_in2.fifo_element[3]._en" "t.fifo_in2.fifo_element[3].en_ctl.y"
-= "t.fifo_in2.fifo_element[3]._en" "t.fifo_in2.fifo_element[3].inack_ctl.c1"
-~"t.fifo_in2.fifo_element[3].en_ctl.p1"&~"t.fifo_in2.fifo_element[3].en_ctl.c1"->"t.fifo_in2.fifo_element[3].en_ctl.y"+
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-= "t.fifo_in2.fifo_element[3]._out_a_B" "t.fifo_in2.fifo_element[3].buf_func.c2"
-= "t.fifo_in2.fifo_element[3]._out_a_B" "t.fifo_in2.fifo_element[3].inv_outa.y"
-= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].in.r"
-= "t.fifo_in2.fifo_element[3].in.a" "t.fifo_in2.fifo_element[3].en_ctl.c1"
-= "t.fifo_in2.fifo_element[3].in.a" "t.fifo_in2.fifo_element[3].inack_ctl.y"
-= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].buf_func.n1"
-= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].inack_ctl.c2"
-= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].in.r"
-= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].out.r"
-= "t.fifo_in2.fifo_element[3].out.a" "t.fifo_in2.fifo_element[3].inv_outa.a"
-= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].buf_func.y"
-= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].en_ctl.p1"
-= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].inack_ctl.n1"
-= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].out.r"
-= "t.fifo_in2.fifo_element[3].in.a" "t.fifo_in2.fifo_element[2].out.a"
-= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[2].out.r"
-= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[2].out.d.d[0]"
-= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].in.r"
-= "t.fifo_in2.fifo_element[2].in.a" "t.fifo_in2.fifo_element[1].out.a"
-= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[1].out.r"
-= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[1].out.d.d[0]"
-= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[2].in.r"
-= "t.fifo_in2.fifo_element[1].in.a" "t.fifo_in2.fifo_element[0].out.a"
-= "t.fifo_in2.fifo_element[1].in.d.d[0]" "t.fifo_in2.fifo_element[0].out.r"
-= "t.fifo_in2.fifo_element[1].in.d.d[0]" "t.fifo_in2.fifo_element[0].out.d.d[0]"
-= "t.fifo_in2.fifo_element[1].in.d.d[0]" "t.fifo_in2.fifo_element[1].in.r"
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-= "t.fifo_in2._reset_BXX[1]" "t.fifo_in2.reset_bufarray.out[1]"
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-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.reset_bufarray.out[3]"
-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[2].reset_B"
-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2._reset_BXX[2]"
-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[1].reset_B"
-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2._reset_BXX[1]"
-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[0].reset_B"
-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2._reset_BXX[0]"
-= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[3].reset_B"
-= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.in.r"
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-= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.fifo_element[0].in.r"
-= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.fifo_element[0].in.d.d[0]"
-= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.in.r"
-= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.out.r"
-= "t.fifo_in2.out.a" "t.fifo_in2.fifo_element[3].out.a"
-= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.fifo_element[3].out.r"
-= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.fifo_element[3].out.d.d[0]"
-= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.out.r"
-= "Reset" "t.fifo_in2.reset_B"
-= "Vdd" "t.fifo_in2.supply.vdd"
-= "GND" "t.fifo_in2.supply.vss"
-= "t._out2.d.d[0]" "t._out2.r"
-= "t._out2.r" "t.arb.in2.r"
-= "t._out2.a" "t.arb.in2.a"
-= "t._out2.d.d[0]" "t.arb.in2.d.d[0]"
-= "t._out2.r" "t.fifo_in2.out.r"
-= "t._out2.a" "t.fifo_in2.out.a"
-= "t._out2.d.d[0]" "t.fifo_in2.out.d.d[0]"
-= "t._out2.d.d[0]" "t._out2.r"
-= "t._out1.d.d[0]" "t._out1.r"
-= "t._out1.r" "t.arb.in1.r"
-= "t._out1.a" "t.arb.in1.a"
-= "t._out1.d.d[0]" "t.arb.in1.d.d[0]"
-= "t._out1.r" "t.fifo_in1.out.r"
-= "t._out1.a" "t.fifo_in1.out.a"
-= "t._out1.d.d[0]" "t.fifo_in1.out.d.d[0]"
-= "t._out1.d.d[0]" "t._out1.r"
-= "t.in1.d.d[0]" "t.in1.r"
-= "t.in1.r" "t.fifo_in1.in.r"
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-= "t.in1.d.d[0]" "t.fifo_in1.in.d.d[0]"
-= "t.in1.d.d[0]" "t.in1.r"
-= "t.arb.in1.d.d[0]" "t.arb.in1.r"
-= "t.arb.in1.a" "t.arb.arbiter.d"
-= "t.arb.in1.a" "t.arb.ack_cell1.y"
-= "t.arb.in1.d.d[0]" "t.arb.arbiter.a"
-= "t.arb.in1.d.d[0]" "t.arb.in1.r"
-~"t.arb.ack_cell1.c1"&~"t.arb.ack_cell1.c2"->"t.arb.ack_cell1._y"+
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-"t.arb.ack_cell1._y"->"t.arb.ack_cell1.y"-
-~("t.arb.ack_cell1._y")->"t.arb.ack_cell1.y"+
-= "t.arb.in2.d.d[0]" "t.arb.in2.r"
-= "t.arb.in2.a" "t.arb.arbiter.c"
-= "t.arb.in2.a" "t.arb.ack_cell2.y"
-= "t.arb.in2.d.d[0]" "t.arb.arbiter.b"
-= "t.arb.in2.d.d[0]" "t.arb.in2.r"
-= "t.arb.supply.vdd" "t.arb.arbiter.vdd"
-= "t.arb.supply.vdd" "t.arb.or_cell.vdd"
-= "t.arb.supply.vdd" "t.arb.ack_cell2.vdd"
-= "t.arb.supply.vdd" "t.arb.ack_cell1.vdd"
-= "t.arb.supply.vss" "t.arb.arbiter.vss"
-= "t.arb.supply.vss" "t.arb.or_cell.vss"
-= "t.arb.supply.vss" "t.arb.ack_cell2.vss"
-= "t.arb.supply.vss" "t.arb.ack_cell1.vss"
-"t.arb.arbiter.a"&"t.arb.arbiter._y2"->"t.arb.arbiter._y1"-
-~"t.arb.arbiter.a"|~"t.arb.arbiter._y2"->"t.arb.arbiter._y1"+
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-~("t.arb.arbiter._y1"|"t.arb.arbiter.c")->"t.arb.arbiter.y1"+
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-~("t.arb.arbiter._y2"|"t.arb.arbiter.d")->"t.arb.arbiter.y2"+
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-= "t.arb._y1_arb" "t.arb.arbiter.y1"
-= "t.arb._y1_arb" "t.arb.or_cell.a"
-= "t.arb._y1_arb" "t.arb.ack_cell1.c2"
-~"t.arb.ack_cell2.c1"&~"t.arb.ack_cell2.c2"->"t.arb.ack_cell2._y"+
-"t.arb.ack_cell2.c1"&"t.arb.ack_cell2.c2"->"t.arb.ack_cell2._y"-
-"t.arb.ack_cell2._y"->"t.arb.ack_cell2.y"-
-~("t.arb.ack_cell2._y")->"t.arb.ack_cell2.y"+
-"t.arb.or_cell.a"|"t.arb.or_cell.b"->"t.arb.or_cell._y"-
-~("t.arb.or_cell.a"|"t.arb.or_cell.b")->"t.arb.or_cell._y"+
-"t.arb.or_cell._y"->"t.arb.or_cell.y"-
-~("t.arb.or_cell._y")->"t.arb.or_cell.y"+
-= "t.arb.out.d.d[0]" "t.arb.out.r"
-= "t.arb.out.a" "t.arb.ack_cell2.c1"
-= "t.arb.out.a" "t.arb.ack_cell1.c1"
-= "t.arb.out.d.d[0]" "t.arb.or_cell.y"
-= "t.arb.out.d.d[0]" "t.arb.out.r"
-= "t.arb._y2_arb" "t.arb.arbiter.y2"
-= "t.arb._y2_arb" "t.arb.or_cell.b"
-= "t.arb._y2_arb" "t.arb.ack_cell2.c2"
-= "Vdd" "t.arb.supply.vdd"
-= "GND" "t.arb.supply.vss"
-"t.fifo_in1.reset_bufarray.buf1.a"->"t.fifo_in1.reset_bufarray.buf1._y"-
-~("t.fifo_in1.reset_bufarray.buf1.a")->"t.fifo_in1.reset_bufarray.buf1._y"+
-"t.fifo_in1.reset_bufarray.buf1._y"->"t.fifo_in1.reset_bufarray.buf1.y"-
-~("t.fifo_in1.reset_bufarray.buf1._y")->"t.fifo_in1.reset_bufarray.buf1.y"+
-= "t.fifo_in1.reset_bufarray.supply.vdd" "t.fifo_in1.reset_bufarray.buf1.vdd"
-= "t.fifo_in1.reset_bufarray.supply.vss" "t.fifo_in1.reset_bufarray.buf1.vss"
-= "t.fifo_in1.reset_bufarray.out[0]" "t.fifo_in1.reset_bufarray.out[3]"
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-= "t.fifo_in1.reset_bufarray.out[0]" "t.fifo_in1.reset_bufarray.out[1]"
-= "t.fifo_in1.reset_bufarray.out[0]" "t.fifo_in1.reset_bufarray.buf1.y"
-= "t.fifo_in1.reset_bufarray.in" "t.fifo_in1.reset_bufarray.buf1.a"
-"t.fifo_in1.reset_buf.a"->"t.fifo_in1.reset_buf._y"-
-~("t.fifo_in1.reset_buf.a")->"t.fifo_in1.reset_buf._y"+
-"t.fifo_in1.reset_buf._y"->"t.fifo_in1.reset_buf.y"-
-~("t.fifo_in1.reset_buf._y")->"t.fifo_in1.reset_buf.y"+
-= "t.fifo_in1.reset_B" "t.fifo_in1.reset_buf.a"
-= "t.fifo_in1.supply.vss" "t.fifo_in1.fifo_element[3].supply.vss"
-= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[3].supply.vdd"
-= "t.fifo_in1.supply.vss" "t.fifo_in1.fifo_element[2].supply.vss"
-= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[2].supply.vdd"
-= "t.fifo_in1.supply.vss" "t.fifo_in1.fifo_element[1].supply.vss"
-= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[1].supply.vdd"
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-= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[0].supply.vdd"
-= "t.fifo_in1.supply.vdd" "t.fifo_in1.reset_buf.vdd"
-= "t.fifo_in1.supply.vss" "t.fifo_in1.reset_buf.vss"
-= "t.fifo_in1._reset_BX" "t.fifo_in1.reset_bufarray.in"
-= "t.fifo_in1._reset_BX" "t.fifo_in1.reset_buf.y"
-"t.fifo_in1.fifo_element[0].reset_buf.a"->"t.fifo_in1.fifo_element[0].reset_buf._y"-
-~("t.fifo_in1.fifo_element[0].reset_buf.a")->"t.fifo_in1.fifo_element[0].reset_buf._y"+
-"t.fifo_in1.fifo_element[0].reset_buf._y"->"t.fifo_in1.fifo_element[0].reset_buf.y"-
-~("t.fifo_in1.fifo_element[0].reset_buf._y")->"t.fifo_in1.fifo_element[0].reset_buf.y"+
-"t.fifo_in1.fifo_element[0].inv_outa.a"->"t.fifo_in1.fifo_element[0].inv_outa.y"-
-~("t.fifo_in1.fifo_element[0].inv_outa.a")->"t.fifo_in1.fifo_element[0].inv_outa.y"+
-~"t.fifo_in1.fifo_element[0].inack_ctl.c1"&~"t.fifo_in1.fifo_element[0].inack_ctl.c2"|~"t.fifo_in1.fifo_element[0].inack_ctl.pr_B"->"t.fifo_in1.fifo_element[0].inack_ctl._y"+
-"t.fifo_in1.fifo_element[0].inack_ctl.c1"&"t.fifo_in1.fifo_element[0].inack_ctl.c2"&"t.fifo_in1.fifo_element[0].inack_ctl.n1"&"t.fifo_in1.fifo_element[0].inack_ctl.sr_B"->"t.fifo_in1.fifo_element[0].inack_ctl._y"-
-"t.fifo_in1.fifo_element[0].inack_ctl._y"->"t.fifo_in1.fifo_element[0].inack_ctl.y"-
-~("t.fifo_in1.fifo_element[0].inack_ctl._y")->"t.fifo_in1.fifo_element[0].inack_ctl.y"+
-~"t.fifo_in1.fifo_element[0].buf_func.c1"&~"t.fifo_in1.fifo_element[0].buf_func.c2"|~"t.fifo_in1.fifo_element[0].buf_func.pr_B"->"t.fifo_in1.fifo_element[0].buf_func._y"+
-"t.fifo_in1.fifo_element[0].buf_func.c1"&"t.fifo_in1.fifo_element[0].buf_func.c2"&"t.fifo_in1.fifo_element[0].buf_func.n1"&"t.fifo_in1.fifo_element[0].buf_func.sr_B"->"t.fifo_in1.fifo_element[0].buf_func._y"-
-"t.fifo_in1.fifo_element[0].buf_func._y"->"t.fifo_in1.fifo_element[0].buf_func.y"-
-~("t.fifo_in1.fifo_element[0].buf_func._y")->"t.fifo_in1.fifo_element[0].buf_func.y"+
-= "t.fifo_in1.fifo_element[0].reset_B" "t.fifo_in1.fifo_element[0].reset_buf.a"
-= "t.fifo_in1.fifo_element[0].supply.vdd" "t.fifo_in1.fifo_element[0].reset_buf.vdd"
-= "t.fifo_in1.fifo_element[0].supply.vdd" "t.fifo_in1.fifo_element[0].buf_func.vdd"
-= "t.fifo_in1.fifo_element[0].supply.vdd" "t.fifo_in1.fifo_element[0].inv_outa.vdd"
-= "t.fifo_in1.fifo_element[0].supply.vdd" "t.fifo_in1.fifo_element[0].en_ctl.vdd"
-= "t.fifo_in1.fifo_element[0].supply.vdd" "t.fifo_in1.fifo_element[0].inack_ctl.vdd"
-= "t.fifo_in1.fifo_element[0].supply.vss" "t.fifo_in1.fifo_element[0].reset_buf.vss"
-= "t.fifo_in1.fifo_element[0].supply.vss" "t.fifo_in1.fifo_element[0].buf_func.vss"
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-= "t.fifo_in1.fifo_element[3].supply.vss" "t.fifo_in1.fifo_element[3].en_ctl.vss"
-= "t.fifo_in1.fifo_element[3].supply.vss" "t.fifo_in1.fifo_element[3].inack_ctl.vss"
-= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].reset_buf.y"
-= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].buf_func.sr_B"
-= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].buf_func.pr_B"
-= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].inack_ctl.sr_B"
-= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].inack_ctl.pr_B"
-= "t.fifo_in1.fifo_element[3]._en" "t.fifo_in1.fifo_element[3].buf_func.c1"
-= "t.fifo_in1.fifo_element[3]._en" "t.fifo_in1.fifo_element[3].en_ctl.y"
-= "t.fifo_in1.fifo_element[3]._en" "t.fifo_in1.fifo_element[3].inack_ctl.c1"
-~"t.fifo_in1.fifo_element[3].en_ctl.p1"&~"t.fifo_in1.fifo_element[3].en_ctl.c1"->"t.fifo_in1.fifo_element[3].en_ctl.y"+
-"t.fifo_in1.fifo_element[3].en_ctl.c1"->"t.fifo_in1.fifo_element[3].en_ctl.y"-
-= "t.fifo_in1.fifo_element[3]._out_a_B" "t.fifo_in1.fifo_element[3].buf_func.c2"
-= "t.fifo_in1.fifo_element[3]._out_a_B" "t.fifo_in1.fifo_element[3].inv_outa.y"
-= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].in.r"
-= "t.fifo_in1.fifo_element[3].in.a" "t.fifo_in1.fifo_element[3].en_ctl.c1"
-= "t.fifo_in1.fifo_element[3].in.a" "t.fifo_in1.fifo_element[3].inack_ctl.y"
-= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].buf_func.n1"
-= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].inack_ctl.c2"
-= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].in.r"
-= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].out.r"
-= "t.fifo_in1.fifo_element[3].out.a" "t.fifo_in1.fifo_element[3].inv_outa.a"
-= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].buf_func.y"
-= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].en_ctl.p1"
-= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].inack_ctl.n1"
-= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].out.r"
-= "t.fifo_in1.fifo_element[3].in.a" "t.fifo_in1.fifo_element[2].out.a"
-= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[2].out.r"
-= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[2].out.d.d[0]"
-= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].in.r"
-= "t.fifo_in1.fifo_element[2].in.a" "t.fifo_in1.fifo_element[1].out.a"
-= "t.fifo_in1.fifo_element[2].in.d.d[0]" "t.fifo_in1.fifo_element[1].out.r"
-= "t.fifo_in1.fifo_element[2].in.d.d[0]" "t.fifo_in1.fifo_element[1].out.d.d[0]"
-= "t.fifo_in1.fifo_element[2].in.d.d[0]" "t.fifo_in1.fifo_element[2].in.r"
-= "t.fifo_in1.fifo_element[1].in.a" "t.fifo_in1.fifo_element[0].out.a"
-= "t.fifo_in1.fifo_element[1].in.d.d[0]" "t.fifo_in1.fifo_element[0].out.r"
-= "t.fifo_in1.fifo_element[1].in.d.d[0]" "t.fifo_in1.fifo_element[0].out.d.d[0]"
-= "t.fifo_in1.fifo_element[1].in.d.d[0]" "t.fifo_in1.fifo_element[1].in.r"
-= "t.fifo_in1._reset_BXX[0]" "t.fifo_in1.reset_bufarray.out[0]"
-= "t.fifo_in1._reset_BXX[1]" "t.fifo_in1.reset_bufarray.out[1]"
-= "t.fifo_in1._reset_BXX[2]" "t.fifo_in1.reset_bufarray.out[2]"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.reset_bufarray.out[3]"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[2].reset_B"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1._reset_BXX[2]"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[1].reset_B"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1._reset_BXX[1]"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[0].reset_B"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1._reset_BXX[0]"
-= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[3].reset_B"
-= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.in.r"
-= "t.fifo_in1.in.a" "t.fifo_in1.fifo_element[0].in.a"
-= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.fifo_element[0].in.r"
-= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.fifo_element[0].in.d.d[0]"
-= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.in.r"
-= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.out.r"
-= "t.fifo_in1.out.a" "t.fifo_in1.fifo_element[3].out.a"
-= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.fifo_element[3].out.r"
-= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.fifo_element[3].out.d.d[0]"
-= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.out.r"
-= "Reset" "t.fifo_in1.reset_B"
-= "Vdd" "t.fifo_in1.supply.vdd"
-= "GND" "t.fifo_in1.supply.vss"
-= "t.out.d.d[0]" "t.out.r"
-= "t.out.r" "t.arb.out.r"
-= "t.out.a" "t.arb.out.a"
-= "t.out.d.d[0]" "t.arb.out.d.d[0]"
-= "t.out.d.d[0]" "t.out.r"
-= "t.in2.d.d[0]" "t.in2.r"
-= "t.in2.r" "t.fifo_in2.in.r"
-= "t.in2.a" "t.fifo_in2.in.a"
-= "t.in2.d.d[0]" "t.fifo_in2.in.d.d[0]"
-= "t.in2.d.d[0]" "t.in2.r"

test/unit_tests/arbiter_tree_simple_nosim/run/prsim.out

@@ -0,0 +1,98 @@
+my_tree.in[4].r my_tree.at_cell.tmp[6].r my_tree.at_cell.arbs[0].arbiter._y1 my_tree.in[2].a my_tree.at_cell.tmp[8].a my_tree.at_cell.arbs[0]._y1_arb my_tree.out.r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[2]._y2_arb my_tree.at_cell.arbs[3].ack_cell1._y my_tree.in[0].a my_tree.at_cell.tmp[6].a my_tree.in[4].a my_tree.at_cell.arbs[2].arbiter._y2 my_tree.in[1].a my_tree.out.a my_tree.at_cell.arbs[0].ack_cell1._y my_tree.in[0].r my_tree.at_cell.arbs[3].ack_cell2._y my_tree.in[3].r my_tree.at_cell.tmp[5].r my_tree.in[1].r my_tree.at_cell.arbs[0]._y2_arb my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1]._y1_arb my_tree.at_cell.arbs[1].ack_cell2._y my_tree.in[2].r my_tree.in[3].a my_tree.at_cell.tmp[8].r my_tree.at_cell.arbs[1]._y2_arb my_tree.at_cell.arbs[3]._y1_arb my_tree.at_cell.arbs[3].or_cell._y my_tree.at_cell.arbs[1].arbiter._y2 my_tree.at_cell.arbs[3].arbiter._y2 my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.arbs[3].arbiter._y1 my_tree.at_cell.arbs[0].ack_cell2._y my_tree.at_cell.arbs[3]._y2_arb my_tree.at_cell.arbs[2].ack_cell1._y my_tree.at_cell.arbs[1].or_cell._y my_tree.at_cell.arbs[2]._y1_arb my_tree.at_cell.arbs[1].arbiter._y1 my_tree.at_cell.arbs[0].or_cell._y my_tree.at_cell.arbs[0].arbiter._y2 my_tree.at_cell.arbs[2].or_cell._y my_tree.at_cell.arbs[2].arbiter._y1 
+	         1 my_tree.in[0].r : 0
+	         1 my_tree.out.a : 0
+	         1 my_tree.in[2].r : 0
+	         1 my_tree.in[4].r : 0
+	         1 my_tree.in[1].r : 0
+	         1 my_tree.in[3].r : 0
+	         3 my_tree.at_cell.arbs[3].arbiter._y2 : 1  [by my_tree.in[4].r:=0]
+	       117 my_tree.at_cell.arbs[3]._y2_arb : 0  [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
+	      1138 my_tree.at_cell.arbs[1].arbiter._y2 : 1  [by my_tree.in[3].r:=0]
+	      2864 my_tree.at_cell.arbs[1]._y2_arb : 0  [by my_tree.at_cell.arbs[1].arbiter._y2:=1]
+	      4754 my_tree.at_cell.arbs[0].arbiter._y2 : 1  [by my_tree.in[1].r:=0]
+	      4793 my_tree.at_cell.arbs[0]._y2_arb : 0  [by my_tree.at_cell.arbs[0].arbiter._y2:=1]
+	      7093 my_tree.at_cell.arbs[0].arbiter._y1 : 1  [by my_tree.in[0].r:=0]
+	      7108 my_tree.at_cell.arbs[0]._y1_arb : 0  [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
+	      7599 my_tree.at_cell.arbs[0].or_cell._y : 1  [by my_tree.at_cell.arbs[0]._y1_arb:=0]
+	      7612 my_tree.at_cell.tmp[5].r : 0  [by my_tree.at_cell.arbs[0].or_cell._y:=1]
+	      7652 my_tree.at_cell.arbs[2].arbiter._y1 : 1  [by my_tree.at_cell.tmp[5].r:=0]
+	      8067 my_tree.at_cell.arbs[2]._y1_arb : 0  [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
+	     10468 my_tree.at_cell.arbs[1].arbiter._y1 : 1  [by my_tree.in[2].r:=0]
+	     10488 my_tree.at_cell.arbs[1]._y1_arb : 0  [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
+	     16549 my_tree.at_cell.arbs[1].or_cell._y : 1  [by my_tree.at_cell.arbs[1]._y1_arb:=0]
+	     16596 my_tree.at_cell.tmp[6].r : 0  [by my_tree.at_cell.arbs[1].or_cell._y:=1]
+	     16612 my_tree.at_cell.arbs[2].arbiter._y2 : 1  [by my_tree.at_cell.tmp[6].r:=0]
+	     60710 my_tree.at_cell.arbs[2]._y2_arb : 0  [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
+	     65483 my_tree.at_cell.arbs[3].ack_cell2._y : 1  [by my_tree.at_cell.arbs[3]._y2_arb:=0]
+	     65487 my_tree.in[4].a : 0  [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
+	     74434 my_tree.at_cell.arbs[2].or_cell._y : 1  [by my_tree.at_cell.arbs[2]._y2_arb:=0]
+	     83563 my_tree.at_cell.tmp[8].r : 0  [by my_tree.at_cell.arbs[2].or_cell._y:=1]
+	     83578 my_tree.at_cell.arbs[3].arbiter._y1 : 1  [by my_tree.at_cell.tmp[8].r:=0]
+	    126826 my_tree.at_cell.arbs[3]._y1_arb : 0  [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
+	    126881 my_tree.at_cell.arbs[3].or_cell._y : 1  [by my_tree.at_cell.arbs[3]._y1_arb:=0]
+	    163757 my_tree.at_cell.arbs[3].ack_cell1._y : 1  [by my_tree.at_cell.arbs[3]._y1_arb:=0]
+	    178534 my_tree.out.r : 0  [by my_tree.at_cell.arbs[3].or_cell._y:=1]
+	    193537 my_tree.at_cell.tmp[8].a : 0  [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
+	    207386 my_tree.at_cell.arbs[2].ack_cell2._y : 1  [by my_tree.at_cell.tmp[8].a:=0]
+	    218349 my_tree.at_cell.arbs[2].ack_cell1._y : 1  [by my_tree.at_cell.tmp[8].a:=0]
+	    218771 my_tree.at_cell.tmp[5].a : 0  [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
+	    218772 my_tree.at_cell.arbs[0].ack_cell1._y : 1  [by my_tree.at_cell.tmp[5].a:=0]
+	    218773 my_tree.in[0].a : 0  [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
+	    221729 my_tree.at_cell.tmp[6].a : 0  [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
+	    222011 my_tree.at_cell.arbs[1].ack_cell1._y : 1  [by my_tree.at_cell.tmp[6].a:=0]
+	    222779 my_tree.in[2].a : 0  [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
+	    241934 my_tree.at_cell.arbs[1].ack_cell2._y : 1  [by my_tree.at_cell.tmp[6].a:=0]
+	    241937 my_tree.in[3].a : 0  [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
+	    267485 my_tree.at_cell.arbs[0].ack_cell2._y : 1  [by my_tree.at_cell.tmp[5].a:=0]
+	    289926 my_tree.in[1].a : 0  [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
+-------------------------------------------------
+[0] System initialized
+	    289926 Reset : 0
+	    290477 my_tree._reset_B : 1  [by Reset:=0]
+-------------------------------------------------
+[1] System reset completed
+	    290477 my_tree.in[0].r : 1
+	    290477 my_tree.in[4].r : 1
+	    290477 my_tree.in[2].r : 1
+	    291431 my_tree.at_cell.arbs[3].arbiter._y2 : 0  [by my_tree.in[4].r:=1]
+	    291548 my_tree.at_cell.arbs[0].arbiter._y1 : 0  [by my_tree.in[0].r:=1]
+	    291558 my_tree.at_cell.arbs[1].arbiter._y1 : 0  [by my_tree.in[2].r:=1]
+	    291576 my_tree.at_cell.arbs[1]._y1_arb : 1  [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
+	    292530 my_tree.at_cell.arbs[0]._y1_arb : 1  [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
+	    295589 my_tree.at_cell.arbs[1].or_cell._y : 0  [by my_tree.at_cell.arbs[1]._y1_arb:=1]
+	    296533 my_tree.at_cell.arbs[0].or_cell._y : 0  [by my_tree.at_cell.arbs[0]._y1_arb:=1]
+	    318117 my_tree.at_cell.tmp[5].r : 1  [by my_tree.at_cell.arbs[0].or_cell._y:=0]
+	    322877 my_tree.at_cell.arbs[2].arbiter._y1 : 0  [by my_tree.at_cell.tmp[5].r:=1]
+	    323379 my_tree.at_cell.arbs[2]._y1_arb : 1  [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
+	    323582 my_tree.at_cell.arbs[2].or_cell._y : 0  [by my_tree.at_cell.arbs[2]._y1_arb:=1]
+	    325436 my_tree.at_cell.tmp[8].r : 1  [by my_tree.at_cell.arbs[2].or_cell._y:=0]
+	    340490 my_tree.at_cell.tmp[6].r : 1  [by my_tree.at_cell.arbs[1].or_cell._y:=0]
+	    345901 my_tree.at_cell.arbs[3]._y2_arb : 1  [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
+	    346040 my_tree.at_cell.arbs[3].or_cell._y : 0  [by my_tree.at_cell.arbs[3]._y2_arb:=1]
+	    382386 my_tree.out.r : 1  [by my_tree.at_cell.arbs[3].or_cell._y:=0]
+	    382386 my_tree.out.a : 1
+	    382455 my_tree.at_cell.arbs[3].ack_cell2._y : 0  [by my_tree.out.a:=1]
+	    382466 my_tree.in[4].a : 1  [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
+-------------------------------------------------
+[2] Number 4 was chosen, move to the next one
+	    382466 my_tree.in[4].r : 0
+	    434252 my_tree.at_cell.arbs[3].arbiter._y2 : 1  [by my_tree.in[4].r:=0]
+	    434267 my_tree.at_cell.arbs[3]._y2_arb : 0  [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
+	    434268 my_tree.at_cell.arbs[3].or_cell._y : 1  [by my_tree.at_cell.arbs[3]._y2_arb:=0]
+	    434305 my_tree.out.r : 0  [by my_tree.at_cell.arbs[3].or_cell._y:=1]
+	    434456 my_tree.at_cell.arbs[3].arbiter._y1 : 0  [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
+	    434456 my_tree.out.a : 0
+	    435195 my_tree.at_cell.arbs[3].ack_cell2._y : 1  [by my_tree.out.a:=0]
+	    435307 my_tree.in[4].a : 0  [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
+	    482819 my_tree.at_cell.arbs[3]._y1_arb : 1  [by my_tree.in[4].a:=0]
+	    482859 my_tree.at_cell.arbs[3].or_cell._y : 0  [by my_tree.at_cell.arbs[3]._y1_arb:=1]
+	    483116 my_tree.out.r : 1  [by my_tree.at_cell.arbs[3].or_cell._y:=0]
+	    483116 my_tree.out.a : 1
+	    483203 my_tree.at_cell.arbs[3].ack_cell1._y : 0  [by my_tree.out.a:=1]
+	    483497 my_tree.at_cell.tmp[8].a : 1  [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
+	    483498 my_tree.at_cell.arbs[2].ack_cell1._y : 0  [by my_tree.at_cell.tmp[8].a:=1]
+	    485304 my_tree.at_cell.tmp[5].a : 1  [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
+	    487311 my_tree.at_cell.arbs[0].ack_cell1._y : 0  [by my_tree.at_cell.tmp[5].a:=1]
+	    488520 my_tree.in[0].a : 1  [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
+-------------------------------------------------
+[2] Number 0 was chosen, finish test

test/unit_tests/arbiter_tree_simple_nosim/run/test.prs

@@ -0,0 +1,325 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"Reset"->"my_tree._reset_B"-
+~("Reset")->"my_tree._reset_B"+
+= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
+= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].arbiter.d"
+= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].ack_cell1.y"
+= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.a"
+= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
+~"my_tree.at_cell.arbs[0].ack_cell1.c1"&~"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"+
+"my_tree.at_cell.arbs[0].ack_cell1.c1"&"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"-
+"my_tree.at_cell.arbs[0].ack_cell1._y"->"my_tree.at_cell.arbs[0].ack_cell1.y"-
+~("my_tree.at_cell.arbs[0].ack_cell1._y")->"my_tree.at_cell.arbs[0].ack_cell1.y"+
+= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
+= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].arbiter.c"
+= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].ack_cell2.y"
+= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.b"
+= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
+= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].arbiter.vdd"
+= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].or_cell.vdd"
+= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell2.vdd"
+= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell1.vdd"
+= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].arbiter.vss"
+= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].or_cell.vss"
+= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell2.vss"
+= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell1.vss"
+"my_tree.at_cell.arbs[0].arbiter.a"&"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"-
+~"my_tree.at_cell.arbs[0].arbiter.a"|~"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"+
+"my_tree.at_cell.arbs[0].arbiter.b"&"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"-
+~"my_tree.at_cell.arbs[0].arbiter.b"|~"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"+
+"my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c"->"my_tree.at_cell.arbs[0].arbiter.y1"-
+~("my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c")->"my_tree.at_cell.arbs[0].arbiter.y1"+
+"my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d"->"my_tree.at_cell.arbs[0].arbiter.y2"-
+~("my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d")->"my_tree.at_cell.arbs[0].arbiter.y2"+
+mk_excllo("my_tree.at_cell.arbs[0].arbiter._y1","my_tree.at_cell.arbs[0].arbiter._y2")
+= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].arbiter.y1"
+= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].or_cell.a"
+= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].ack_cell1.c2"
+~"my_tree.at_cell.arbs[0].ack_cell2.c1"&~"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"+
+"my_tree.at_cell.arbs[0].ack_cell2.c1"&"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"-
+"my_tree.at_cell.arbs[0].ack_cell2._y"->"my_tree.at_cell.arbs[0].ack_cell2.y"-
+~("my_tree.at_cell.arbs[0].ack_cell2._y")->"my_tree.at_cell.arbs[0].ack_cell2.y"+
+"my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b"->"my_tree.at_cell.arbs[0].or_cell._y"-
+~("my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b")->"my_tree.at_cell.arbs[0].or_cell._y"+
+"my_tree.at_cell.arbs[0].or_cell._y"->"my_tree.at_cell.arbs[0].or_cell.y"-
+~("my_tree.at_cell.arbs[0].or_cell._y")->"my_tree.at_cell.arbs[0].or_cell.y"+
+= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
+= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell2.c1"
+= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell1.c1"
+= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].or_cell.y"
+= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
+= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].arbiter.y2"
+= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].or_cell.b"
+= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].ack_cell2.c2"
+= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
+= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].arbiter.d"
+= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].ack_cell1.y"
+= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.a"
+= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
+~"my_tree.at_cell.arbs[1].ack_cell1.c1"&~"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"+
+"my_tree.at_cell.arbs[1].ack_cell1.c1"&"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"-
+"my_tree.at_cell.arbs[1].ack_cell1._y"->"my_tree.at_cell.arbs[1].ack_cell1.y"-
+~("my_tree.at_cell.arbs[1].ack_cell1._y")->"my_tree.at_cell.arbs[1].ack_cell1.y"+
+= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
+= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].arbiter.c"
+= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].ack_cell2.y"
+= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.b"
+= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
+= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].arbiter.vdd"
+= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].or_cell.vdd"
+= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell2.vdd"
+= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell1.vdd"
+= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].arbiter.vss"
+= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].or_cell.vss"
+= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell2.vss"
+= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell1.vss"
+"my_tree.at_cell.arbs[1].arbiter.a"&"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"-
+~"my_tree.at_cell.arbs[1].arbiter.a"|~"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"+
+"my_tree.at_cell.arbs[1].arbiter.b"&"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"-
+~"my_tree.at_cell.arbs[1].arbiter.b"|~"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"+
+"my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c"->"my_tree.at_cell.arbs[1].arbiter.y1"-
+~("my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c")->"my_tree.at_cell.arbs[1].arbiter.y1"+
+"my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d"->"my_tree.at_cell.arbs[1].arbiter.y2"-
+~("my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d")->"my_tree.at_cell.arbs[1].arbiter.y2"+
+mk_excllo("my_tree.at_cell.arbs[1].arbiter._y1","my_tree.at_cell.arbs[1].arbiter._y2")
+= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].arbiter.y1"
+= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].or_cell.a"
+= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].ack_cell1.c2"
+~"my_tree.at_cell.arbs[1].ack_cell2.c1"&~"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"+
+"my_tree.at_cell.arbs[1].ack_cell2.c1"&"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"-
+"my_tree.at_cell.arbs[1].ack_cell2._y"->"my_tree.at_cell.arbs[1].ack_cell2.y"-
+~("my_tree.at_cell.arbs[1].ack_cell2._y")->"my_tree.at_cell.arbs[1].ack_cell2.y"+
+"my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b"->"my_tree.at_cell.arbs[1].or_cell._y"-
+~("my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b")->"my_tree.at_cell.arbs[1].or_cell._y"+
+"my_tree.at_cell.arbs[1].or_cell._y"->"my_tree.at_cell.arbs[1].or_cell.y"-
+~("my_tree.at_cell.arbs[1].or_cell._y")->"my_tree.at_cell.arbs[1].or_cell.y"+
+= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
+= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell2.c1"
+= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell1.c1"
+= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].or_cell.y"
+= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
+= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].arbiter.y2"
+= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].or_cell.b"
+= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].ack_cell2.c2"
+= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
+= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].arbiter.d"
+= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].ack_cell1.y"
+= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.a"
+= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
+~"my_tree.at_cell.arbs[2].ack_cell1.c1"&~"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"+
+"my_tree.at_cell.arbs[2].ack_cell1.c1"&"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"-
+"my_tree.at_cell.arbs[2].ack_cell1._y"->"my_tree.at_cell.arbs[2].ack_cell1.y"-
+~("my_tree.at_cell.arbs[2].ack_cell1._y")->"my_tree.at_cell.arbs[2].ack_cell1.y"+
+= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
+= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].arbiter.c"
+= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].ack_cell2.y"
+= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.b"
+= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
+= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].arbiter.vdd"
+= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].or_cell.vdd"
+= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell2.vdd"
+= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell1.vdd"
+= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].arbiter.vss"
+= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].or_cell.vss"
+= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell2.vss"
+= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell1.vss"
+"my_tree.at_cell.arbs[2].arbiter.a"&"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"-
+~"my_tree.at_cell.arbs[2].arbiter.a"|~"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"+
+"my_tree.at_cell.arbs[2].arbiter.b"&"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"-
+~"my_tree.at_cell.arbs[2].arbiter.b"|~"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"+
+"my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c"->"my_tree.at_cell.arbs[2].arbiter.y1"-
+~("my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c")->"my_tree.at_cell.arbs[2].arbiter.y1"+
+"my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d"->"my_tree.at_cell.arbs[2].arbiter.y2"-
+~("my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d")->"my_tree.at_cell.arbs[2].arbiter.y2"+
+mk_excllo("my_tree.at_cell.arbs[2].arbiter._y1","my_tree.at_cell.arbs[2].arbiter._y2")
+= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].arbiter.y1"
+= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].or_cell.a"
+= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].ack_cell1.c2"
+~"my_tree.at_cell.arbs[2].ack_cell2.c1"&~"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"+
+"my_tree.at_cell.arbs[2].ack_cell2.c1"&"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"-
+"my_tree.at_cell.arbs[2].ack_cell2._y"->"my_tree.at_cell.arbs[2].ack_cell2.y"-
+~("my_tree.at_cell.arbs[2].ack_cell2._y")->"my_tree.at_cell.arbs[2].ack_cell2.y"+
+"my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b"->"my_tree.at_cell.arbs[2].or_cell._y"-
+~("my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b")->"my_tree.at_cell.arbs[2].or_cell._y"+
+"my_tree.at_cell.arbs[2].or_cell._y"->"my_tree.at_cell.arbs[2].or_cell.y"-
+~("my_tree.at_cell.arbs[2].or_cell._y")->"my_tree.at_cell.arbs[2].or_cell.y"+
+= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
+= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell2.c1"
+= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell1.c1"
+= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].or_cell.y"
+= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
+= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].arbiter.y2"
+= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].or_cell.b"
+= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].ack_cell2.c2"
+= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
+= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].arbiter.d"
+= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].ack_cell1.y"
+= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.a"
+= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
+~"my_tree.at_cell.arbs[3].ack_cell1.c1"&~"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"+
+"my_tree.at_cell.arbs[3].ack_cell1.c1"&"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"-
+"my_tree.at_cell.arbs[3].ack_cell1._y"->"my_tree.at_cell.arbs[3].ack_cell1.y"-
+~("my_tree.at_cell.arbs[3].ack_cell1._y")->"my_tree.at_cell.arbs[3].ack_cell1.y"+
+= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
+= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].arbiter.c"
+= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].ack_cell2.y"
+= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.b"
+= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
+= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].arbiter.vdd"
+= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].or_cell.vdd"
+= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell2.vdd"
+= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell1.vdd"
+= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].arbiter.vss"
+= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].or_cell.vss"
+= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell2.vss"
+= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell1.vss"
+"my_tree.at_cell.arbs[3].arbiter.a"&"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"-
+~"my_tree.at_cell.arbs[3].arbiter.a"|~"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"+
+"my_tree.at_cell.arbs[3].arbiter.b"&"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"-
+~"my_tree.at_cell.arbs[3].arbiter.b"|~"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"+
+"my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c"->"my_tree.at_cell.arbs[3].arbiter.y1"-
+~("my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c")->"my_tree.at_cell.arbs[3].arbiter.y1"+
+"my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d"->"my_tree.at_cell.arbs[3].arbiter.y2"-
+~("my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d")->"my_tree.at_cell.arbs[3].arbiter.y2"+
+mk_excllo("my_tree.at_cell.arbs[3].arbiter._y1","my_tree.at_cell.arbs[3].arbiter._y2")
+= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].arbiter.y1"
+= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].or_cell.a"
+= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].ack_cell1.c2"
+~"my_tree.at_cell.arbs[3].ack_cell2.c1"&~"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"+
+"my_tree.at_cell.arbs[3].ack_cell2.c1"&"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"-
+"my_tree.at_cell.arbs[3].ack_cell2._y"->"my_tree.at_cell.arbs[3].ack_cell2.y"-
+~("my_tree.at_cell.arbs[3].ack_cell2._y")->"my_tree.at_cell.arbs[3].ack_cell2.y"+
+"my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b"->"my_tree.at_cell.arbs[3].or_cell._y"-
+~("my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b")->"my_tree.at_cell.arbs[3].or_cell._y"+
+"my_tree.at_cell.arbs[3].or_cell._y"->"my_tree.at_cell.arbs[3].or_cell.y"-
+~("my_tree.at_cell.arbs[3].or_cell._y")->"my_tree.at_cell.arbs[3].or_cell.y"+
+= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
+= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell2.c1"
+= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell1.c1"
+= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].or_cell.y"
+= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
+= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].arbiter.y2"
+= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].or_cell.b"
+= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].ack_cell2.c2"
+= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
+= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
+= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
+= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[2].in1.r"
+= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[2].in1.a"
+= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[2].in1.d.d[0]"
+= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[0].out.r"
+= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[0].out.a"
+= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[0].out.d.d[0]"
+= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[2].in2.r"
+= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[2].in2.a"
+= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[2].in2.d.d[0]"
+= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[1].out.r"
+= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[1].out.a"
+= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[1].out.d.d[0]"
+= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[3].in1.r"
+= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[3].in1.a"
+= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[3].in1.d.d[0]"
+= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[2].out.r"
+= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[2].out.a"
+= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[2].out.d.d[0]"
+= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
+= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
+= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
+= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[3].supply.vss"
+= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[3].supply.vdd"
+= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[2].supply.vss"
+= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[2].supply.vdd"
+= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[1].supply.vss"
+= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[1].supply.vdd"
+= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[0].supply.vss"
+= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[0].supply.vdd"
+= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
+= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
+= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
+= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
+= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
+= "my_tree.at_cell.in[0].r" "my_tree.at_cell.arbs[0].in1.r"
+= "my_tree.at_cell.in[0].a" "my_tree.at_cell.arbs[0].in1.a"
+= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.arbs[0].in1.d.d[0]"
+= "my_tree.at_cell.in[0].r" "my_tree.at_cell.tmp[0].r"
+= "my_tree.at_cell.in[0].a" "my_tree.at_cell.tmp[0].a"
+= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.tmp[0].d.d[0]"
+= "my_tree.at_cell.in[1].r" "my_tree.at_cell.arbs[0].in2.r"
+= "my_tree.at_cell.in[1].a" "my_tree.at_cell.arbs[0].in2.a"
+= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.arbs[0].in2.d.d[0]"
+= "my_tree.at_cell.in[1].r" "my_tree.at_cell.tmp[1].r"
+= "my_tree.at_cell.in[1].a" "my_tree.at_cell.tmp[1].a"
+= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.tmp[1].d.d[0]"
+= "my_tree.at_cell.in[2].r" "my_tree.at_cell.arbs[1].in1.r"
+= "my_tree.at_cell.in[2].a" "my_tree.at_cell.arbs[1].in1.a"
+= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.arbs[1].in1.d.d[0]"
+= "my_tree.at_cell.in[2].r" "my_tree.at_cell.tmp[2].r"
+= "my_tree.at_cell.in[2].a" "my_tree.at_cell.tmp[2].a"
+= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.tmp[2].d.d[0]"
+= "my_tree.at_cell.in[3].r" "my_tree.at_cell.arbs[1].in2.r"
+= "my_tree.at_cell.in[3].a" "my_tree.at_cell.arbs[1].in2.a"
+= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.arbs[1].in2.d.d[0]"
+= "my_tree.at_cell.in[3].r" "my_tree.at_cell.tmp[3].r"
+= "my_tree.at_cell.in[3].a" "my_tree.at_cell.tmp[3].a"
+= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.tmp[3].d.d[0]"
+= "my_tree.at_cell.in[4].r" "my_tree.at_cell.arbs[3].in2.r"
+= "my_tree.at_cell.in[4].a" "my_tree.at_cell.arbs[3].in2.a"
+= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.arbs[3].in2.d.d[0]"
+= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[9].r"
+= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[9].a"
+= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[9].d.d[0]"
+= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[7].r"
+= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[7].a"
+= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[7].d.d[0]"
+= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[4].r"
+= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[4].a"
+= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[4].d.d[0]"
+= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
+= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
+= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
+= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
+= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
+= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
+= "my_tree.at_cell.out.r" "my_tree.at_cell.arbs[3].out.r"
+= "my_tree.at_cell.out.a" "my_tree.at_cell.arbs[3].out.a"
+= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.arbs[3].out.d.d[0]"
+= "my_tree.at_cell.out.r" "my_tree.at_cell.tmp[10].r"
+= "my_tree.at_cell.out.a" "my_tree.at_cell.tmp[10].a"
+= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.tmp[10].d.d[0]"
+= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
+= "my_tree._supply.vss" "my_tree.at_cell.supply.vss"
+= "my_tree._supply.vdd" "my_tree.at_cell.supply.vdd"
+= "Vdd" "my_tree._supply.vdd"
+= "GND" "my_tree._supply.vss"
+= "my_tree.out.d.d[0]" "my_tree.out.r"
+= "my_tree.out.r" "my_tree.at_cell.out.r"
+= "my_tree.out.a" "my_tree.at_cell.out.a"
+= "my_tree.out.d.d[0]" "my_tree.at_cell.out.d.d[0]"
+= "my_tree.out.d.d[0]" "my_tree.out.r"
+= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"
+= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
+= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
+= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
+= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
+= "my_tree.in[0].r" "my_tree.at_cell.in[0].r"
+= "my_tree.in[1].r" "my_tree.at_cell.in[1].r"
+= "my_tree.in[2].r" "my_tree.at_cell.in[2].r"
+= "my_tree.in[3].r" "my_tree.at_cell.in[3].r"
+= "my_tree.in[4].r" "my_tree.at_cell.in[4].r"
+= "my_tree.in[0].a" "my_tree.at_cell.in[0].a"
+= "my_tree.in[1].a" "my_tree.at_cell.in[1].a"
+= "my_tree.in[2].a" "my_tree.at_cell.in[2].a"
+= "my_tree.in[3].a" "my_tree.at_cell.in[3].a"
+= "my_tree.in[4].a" "my_tree.at_cell.in[4].a"
+= "my_tree.in[0].d.d[0]" "my_tree.at_cell.in[0].d.d[0]"
+= "my_tree.in[1].d.d[0]" "my_tree.at_cell.in[1].d.d[0]"
+= "my_tree.in[2].d.d[0]" "my_tree.at_cell.in[2].d.d[0]"
+= "my_tree.in[3].d.d[0]" "my_tree.at_cell.in[3].d.d[0]"
+= "my_tree.in[4].d.d[0]" "my_tree.at_cell.in[4].d.d[0]"
+= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
+= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
+= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
+= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
+= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"

test/unit_tests/arbiter_tree_simple_nosim/test.act

@@ -0,0 +1,55 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/coders.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+
+defproc arbiter_treee (a1of1 in[5]; a1of1 out)
+{
+    //Low active Reset
+    bool _reset_B;
+    prs {
+        Reset => _reset_B-
+    }
+
+    power _supply;
+    _supply.vdd = Vdd;
+    _supply.vss = GND;
+    arbtree<5> at_cell(.in=in, .out = out);
+
+
+
+    at_cell.supply = _supply;
+    
+}
+
+arbiter_treee my_tree;

test/unit_tests/arbiter_tree_simple_nosim/test.prsim

@@ -0,0 +1,52 @@
+
+watchall
+set my_tree.in[0].r 0
+set my_tree.in[1].r 0
+set my_tree.in[2].r 0
+set my_tree.in[3].r 0
+set my_tree.in[4].r 0
+set my_tree.out.a 0
+
+cycle
+
+assert my_tree.in[0].a 0
+assert my_tree.in[1].a 0
+assert my_tree.in[2].a 0
+assert my_tree.in[3].a 0
+assert my_tree.in[4].a 0
+assert my_tree.out.r 0
+
+system "echo '-------------------------------------------------'"
+system "echo '[0] System initialized'"
+
+set Reset 0
+cycle
+system "echo '-------------------------------------------------'"
+system "echo '[1] System reset completed'"
+
+set my_tree.in[0].r 1
+set my_tree.in[2].r 1
+set my_tree.in[4].r 1
+
+cycle
+
+assert my_tree.out.r 1
+set my_tree.out.a 1
+cycle
+
+assert my_tree.in[4].a 1
+set my_tree.in[4].r 0
+system "echo '-------------------------------------------------'"
+system "echo '[2] Number 4 was chosen, move to the next one'"
+cycle
+assert my_tree.out.r 0
+set my_tree.out.a 0
+cycle
+assert my_tree.in[4].a 0
+assert my_tree.out.r 1
+set my_tree.out.a 1
+cycle
+assert my_tree.in[0].a 1
+system "echo '-------------------------------------------------'"
+system "echo '[2] Number 0 was chosen, finish test'"
+

test/unit_tests/arbiter_tree_test/run/prsim.out

@@ -0,0 +1,232 @@
+my_tree.in[1].r my_tree.at_cell.tmp[8].a my_tree.in[3].r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[3].ack_cell1._y my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B my_tree._in[1].a my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B my_tree._in[3].a my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B my_tree._in[2].a my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1].ack_cell2._y my_tree._in[4].a my_tree.out.a my_tree._in[0].a my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.tmp[6].a my_tree.in[2].r my_tree.in[4].r my_tree.at_cell.arbs[2].ack_cell1._y my_tree.in[0].r my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B my_tree.at_cell.arbs[0].ack_cell1._y my_tree.at_cell.arbs[3].ack_cell2._y my_tree.at_cell.arbs[0].ack_cell2._y 
+	    217204 my_tree.in[0].r : 0
+	    217204 my_tree.out.a : 0
+	    217204 my_tree.in[4].r : 0
+	    217204 my_tree.in[2].r : 0
+	    217204 my_tree.in[1].r : 0
+	    217204 my_tree.in[3].r : 0
+	    217205 my_tree.at_cell.arbs[3].ack_cell2._y : 1  [by my_tree.out.a:=0]
+	    217216 my_tree._in[4].a : 0  [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
+	    217586 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1  [by my_tree._in[4].a:=0]
+	    217752 my_tree.at_cell.arbs[3].ack_cell1._y : 1  [by my_tree.out.a:=0]
+	    217819 my_tree.at_cell.tmp[8].a : 0  [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
+	    217835 my_tree.at_cell.arbs[2].ack_cell1._y : 1  [by my_tree.at_cell.tmp[8].a:=0]
+	    220460 my_tree.at_cell.arbs[2].ack_cell2._y : 1  [by my_tree.at_cell.tmp[8].a:=0]
+	    220988 my_tree.at_cell.tmp[6].a : 0  [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
+	    222397 my_tree.at_cell.tmp[5].a : 0  [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
+	    223423 my_tree.at_cell.arbs[1].ack_cell2._y : 1  [by my_tree.at_cell.tmp[6].a:=0]
+	    223425 my_tree._in[3].a : 0  [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
+	    235438 my_tree.at_cell.arbs[0].ack_cell1._y : 1  [by my_tree.at_cell.tmp[5].a:=0]
+	    235441 my_tree._in[0].a : 0  [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
+	    235470 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1  [by my_tree._in[0].a:=0]
+	    246322 my_tree.at_cell.arbs[0].ack_cell2._y : 1  [by my_tree.at_cell.tmp[5].a:=0]
+	    246639 my_tree._in[1].a : 0  [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
+	    247868 my_tree.at_cell.arbs[1].ack_cell1._y : 1  [by my_tree.at_cell.tmp[6].a:=0]
+	    248021 my_tree._in[2].a : 0  [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
+	    248065 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1  [by my_tree._in[2].a:=0]
+	    248240 my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B : 1  [by my_tree._in[1].a:=0]
+	    284383 my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B : 1  [by my_tree._in[3].a:=0]
+-------------------------------------------------
+[0] System initialized
+	    284383 Reset : 0
+	    287144 my_tree._reset_B : 1  [by Reset:=0]
+	    287145 my_tree.fifo_to_tree[3].reset_buf._y : 0  [by my_tree._reset_B:=1]
+	    287145 my_tree.fifo_to_tree[0].reset_buf._y : 0  [by my_tree._reset_B:=1]
+	    287166 my_tree.fifo_to_tree[1].reset_buf._y : 0  [by my_tree._reset_B:=1]
+	    287325 my_tree.fifo_to_tree[1]._reset_BX : 1  [by my_tree.fifo_to_tree[1].reset_buf._y:=0]
+	    287361 my_tree.fifo_to_tree[2].reset_buf._y : 0  [by my_tree._reset_B:=1]
+	    288648 my_tree.fifo_to_tree[2]._reset_BX : 1  [by my_tree.fifo_to_tree[2].reset_buf._y:=0]
+	    288726 my_tree.fifo_to_tree[3]._reset_BX : 1  [by my_tree.fifo_to_tree[3].reset_buf._y:=0]
+	    288871 my_tree.fifo_to_tree[3].reset_bufarray.buf1._y : 0  [by my_tree.fifo_to_tree[3]._reset_BX:=1]
+	    290880 my_tree.fifo_to_tree[2].reset_bufarray.buf1._y : 0  [by my_tree.fifo_to_tree[2]._reset_BX:=1]
+	    291703 my_tree.fifo_to_tree[3]._reset_BXX[0] : 1  [by my_tree.fifo_to_tree[3].reset_bufarray.buf1._y:=0]
+	    291704 my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y : 0  [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
+	    291866 my_tree.fifo_to_tree[3].fifo_element[0]._reset_BX : 1  [by my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y:=0]
+	    296490 my_tree.fifo_to_tree[0]._reset_BX : 1  [by my_tree.fifo_to_tree[0].reset_buf._y:=0]
+	    297234 my_tree.fifo_to_tree[2]._reset_BXX[0] : 1  [by my_tree.fifo_to_tree[2].reset_bufarray.buf1._y:=0]
+	    297241 my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y : 0  [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
+	    297248 my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y : 0  [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
+	    297401 my_tree.fifo_to_tree[2].fifo_element[1]._reset_BX : 1  [by my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y:=0]
+	    300827 my_tree.fifo_to_tree[4].reset_buf._y : 0  [by my_tree._reset_B:=1]
+	    300828 my_tree.fifo_to_tree[4]._reset_BX : 1  [by my_tree.fifo_to_tree[4].reset_buf._y:=0]
+	    300829 my_tree.fifo_to_tree[4].reset_bufarray.buf1._y : 0  [by my_tree.fifo_to_tree[4]._reset_BX:=1]
+	    300830 my_tree.fifo_to_tree[4]._reset_BXX[0] : 1  [by my_tree.fifo_to_tree[4].reset_bufarray.buf1._y:=0]
+	    301017 my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y : 0  [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
+	    301018 my_tree.fifo_to_tree[4].fifo_element[1]._reset_BX : 1  [by my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y:=0]
+	    303073 my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y : 0  [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
+	    303859 my_tree.fifo_to_tree[0].reset_bufarray.buf1._y : 0  [by my_tree.fifo_to_tree[0]._reset_BX:=1]
+	    307001 my_tree.fifo_to_tree[1].reset_bufarray.buf1._y : 0  [by my_tree.fifo_to_tree[1]._reset_BX:=1]
+	    307002 my_tree.fifo_to_tree[1]._reset_BXX[0] : 1  [by my_tree.fifo_to_tree[1].reset_bufarray.buf1._y:=0]
+	    307007 my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y : 0  [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
+	    307255 my_tree.fifo_to_tree[4].fifo_element[0]._reset_BX : 1  [by my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y:=0]
+	    307855 my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y : 0  [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
+	    307856 my_tree.fifo_to_tree[1].fifo_element[0]._reset_BX : 1  [by my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y:=0]
+	    307898 my_tree.fifo_to_tree[1].fifo_element[1]._reset_BX : 1  [by my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y:=0]
+	    318805 my_tree.fifo_to_tree[2].fifo_element[0]._reset_BX : 1  [by my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y:=0]
+	    330987 my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y : 0  [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
+	    331004 my_tree.fifo_to_tree[3].fifo_element[1]._reset_BX : 1  [by my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y:=0]
+	    338641 my_tree.fifo_to_tree[0]._reset_BXX[0] : 1  [by my_tree.fifo_to_tree[0].reset_bufarray.buf1._y:=0]
+	    341214 my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y : 0  [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
+	    341217 my_tree.fifo_to_tree[0].fifo_element[0]._reset_BX : 1  [by my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y:=0]
+	    347002 my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y : 0  [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
+	    347943 my_tree.fifo_to_tree[0].fifo_element[1]._reset_BX : 1  [by my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y:=0]
+-------------------------------------------------
+[1] System reset completed
+	    347943 my_tree.in[0].r : 1
+	    347943 my_tree.in[4].r : 1
+	    347943 my_tree.in[2].r : 1
+	    347944 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 0  [by my_tree.in[4].r:=1]
+	    347985 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 0  [by my_tree.in[2].r:=1]
+	    350761 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 1  [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=0]
+	    350856 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 0  [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
+	    350864 my_tree._in[4].r : 1  [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=0]
+	    350898 my_tree.at_cell.arbs[3].arbiter._y2 : 0  [by my_tree._in[4].r:=1]
+	    351096 my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y : 0  [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
+	    351100 my_tree.in[4].a : 1  [by my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y:=0]
+	    351816 my_tree.at_cell.arbs[3]._y2_arb : 1  [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
+	    354214 my_tree.at_cell.arbs[3].or_cell._y : 0  [by my_tree.at_cell.arbs[3]._y2_arb:=1]
+	    357429 my_tree.out.r : 1  [by my_tree.at_cell.arbs[3].or_cell._y:=0]
+	    361718 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 1  [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=0]
+	    361766 my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y : 0  [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
+	    361769 my_tree.in[2].a : 1  [by my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y:=0]
+	    361947 my_tree.fifo_to_tree[2].fifo_element[0]._en : 0  [by my_tree.in[2].a:=1]
+	    364751 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 0  [by my_tree._in[4].r:=1]
+	    385728 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 1  [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=0]
+	    391679 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 0  [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
+	    397478 my_tree.fifo_to_tree[4].fifo_element[0]._en : 0  [by my_tree.in[4].a:=1]
+	    397627 my_tree.fifo_to_tree[4].fifo_element[1]._en : 0  [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
+	    406905 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 0  [by my_tree.in[0].r:=1]
+	    407732 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 1  [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=0]
+	    407905 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 0  [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
+	    407906 my_tree._in[0].r : 1  [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=0]
+	    407910 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 0  [by my_tree._in[0].r:=1]
+	    407916 my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y : 0  [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
+	    407979 my_tree.at_cell.arbs[0].arbiter._y1 : 0  [by my_tree._in[0].r:=1]
+	    408012 my_tree.in[0].a : 1  [by my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y:=0]
+	    408013 my_tree.fifo_to_tree[0].fifo_element[0]._en : 0  [by my_tree.in[0].a:=1]
+	    408115 my_tree.at_cell.arbs[0]._y1_arb : 1  [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
+	    408837 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 0  [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
+	    409078 my_tree._in[2].r : 1  [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=0]
+	    409090 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 0  [by my_tree._in[2].r:=1]
+	    412990 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 1  [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=0]
+	    412991 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 0  [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
+	    413037 my_tree.at_cell.arbs[1].arbiter._y1 : 0  [by my_tree._in[2].r:=1]
+	    413047 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 1  [by my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B:=0]
+	    413048 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 0  [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=1]
+	    414019 my_tree.fifo_to_tree[2].fifo_element[1]._en : 0  [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
+	    414056 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 1  [by my_tree.fifo_to_tree[2].fifo_element[1]._en:=0]
+	    427161 my_tree.at_cell.arbs[0].or_cell._y : 0  [by my_tree.at_cell.arbs[0]._y1_arb:=1]
+	    427162 my_tree.at_cell.tmp[5].r : 1  [by my_tree.at_cell.arbs[0].or_cell._y:=0]
+	    430726 my_tree.at_cell.arbs[2].arbiter._y1 : 0  [by my_tree.at_cell.tmp[5].r:=1]
+	    432418 my_tree.at_cell.arbs[2]._y1_arb : 1  [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
+	    432431 my_tree.at_cell.arbs[2].or_cell._y : 0  [by my_tree.at_cell.arbs[2]._y1_arb:=1]
+	    436963 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 1  [by my_tree.fifo_to_tree[4].fifo_element[0]._en:=0]
+	    437320 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 0  [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=1]
+	    437345 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 1  [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=0]
+	    437366 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 0  [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=1]
+	    437367 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 1  [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=0]
+	    437431 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 0  [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=1]
+	    445198 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 1  [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=0]
+	    445199 my_tree.fifo_to_tree[0].fifo_element[1]._en : 0  [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
+	    445199 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 0  [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
+	    445360 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 1  [by my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B:=0]
+	    446397 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 0  [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=1]
+	    446402 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 1  [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=0]
+	    446983 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 0  [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=1]
+	    447079 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 1  [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=0]
+	    447391 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 1  [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=0]
+	    449415 my_tree.at_cell.tmp[8].r : 1  [by my_tree.at_cell.arbs[2].or_cell._y:=0]
+	    458043 my_tree.at_cell.arbs[1]._y1_arb : 1  [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
+	    458054 my_tree.at_cell.arbs[1].or_cell._y : 0  [by my_tree.at_cell.arbs[1]._y1_arb:=1]
+	    459101 my_tree.at_cell.tmp[6].r : 1  [by my_tree.at_cell.arbs[1].or_cell._y:=0]
+	    459101 my_tree.out.a : 1
+	    459115 my_tree.at_cell.arbs[3].ack_cell2._y : 0  [by my_tree.out.a:=1]
+	    459133 my_tree._in[4].a : 1  [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
+	    459137 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 0  [by my_tree._in[4].a:=1]
+	    459241 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 1  [by my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B:=0]
+	    490685 my_tree._in[4].r : 0  [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=1]
+	    491889 my_tree.at_cell.arbs[3].arbiter._y2 : 1  [by my_tree._in[4].r:=0]
+	    492117 my_tree.at_cell.arbs[3].arbiter._y1 : 0  [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
+	    492732 my_tree.at_cell.arbs[3]._y2_arb : 0  [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
+	    494191 my_tree.at_cell.arbs[3].or_cell._y : 1  [by my_tree.at_cell.arbs[3]._y2_arb:=0]
+	    494261 my_tree.out.r : 0  [by my_tree.at_cell.arbs[3].or_cell._y:=1]
+	    499140 my_tree.fifo_to_tree[4].fifo_element[1]._en : 1  [by my_tree._in[4].r:=0]
+	    499140 my_tree.out.a : 0
+	    549562 my_tree.at_cell.arbs[3].ack_cell2._y : 1  [by my_tree.out.a:=0]
+	    549573 my_tree._in[4].a : 0  [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
+	    549576 my_tree.at_cell.arbs[3]._y1_arb : 1  [by my_tree._in[4].a:=0]
+	    549627 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1  [by my_tree._in[4].a:=0]
+	    550724 my_tree.at_cell.arbs[3].or_cell._y : 0  [by my_tree.at_cell.arbs[3]._y1_arb:=1]
+	    551885 my_tree.out.r : 1  [by my_tree.at_cell.arbs[3].or_cell._y:=0]
+	    551885 my_tree.out.a : 1
+	    560537 my_tree.at_cell.arbs[3].ack_cell1._y : 0  [by my_tree.out.a:=1]
+	    560618 my_tree.at_cell.tmp[8].a : 1  [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
+	    571695 my_tree.at_cell.arbs[2].ack_cell1._y : 0  [by my_tree.at_cell.tmp[8].a:=1]
+	    589678 my_tree.at_cell.tmp[5].a : 1  [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
+	    589770 my_tree.at_cell.arbs[0].ack_cell1._y : 0  [by my_tree.at_cell.tmp[5].a:=1]
+	    598081 my_tree._in[0].a : 1  [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
+	    599825 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 0  [by my_tree._in[0].a:=1]
+	    600438 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 1  [by my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B:=0]
+	    614460 my_tree._in[0].r : 0  [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=1]
+	    614505 my_tree.at_cell.arbs[0].arbiter._y1 : 1  [by my_tree._in[0].r:=0]
+	    615457 my_tree.fifo_to_tree[0].fifo_element[1]._en : 1  [by my_tree._in[0].r:=0]
+	    616154 my_tree.at_cell.arbs[0]._y1_arb : 0  [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
+	    616679 my_tree.at_cell.arbs[0].or_cell._y : 1  [by my_tree.at_cell.arbs[0]._y1_arb:=0]
+	    617579 my_tree.at_cell.tmp[5].r : 0  [by my_tree.at_cell.arbs[0].or_cell._y:=1]
+	    617631 my_tree.at_cell.arbs[2].arbiter._y1 : 1  [by my_tree.at_cell.tmp[5].r:=0]
+	    617638 my_tree.at_cell.arbs[2].arbiter._y2 : 0  [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
+	    633243 my_tree.at_cell.arbs[2]._y1_arb : 0  [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
+	    639710 my_tree.at_cell.arbs[2].or_cell._y : 1  [by my_tree.at_cell.arbs[2]._y1_arb:=0]
+	    639712 my_tree.at_cell.tmp[8].r : 0  [by my_tree.at_cell.arbs[2].or_cell._y:=1]
+	    640066 my_tree.at_cell.arbs[3].arbiter._y1 : 1  [by my_tree.at_cell.tmp[8].r:=0]
+	    640199 my_tree.at_cell.arbs[3]._y1_arb : 0  [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
+	    640200 my_tree.at_cell.arbs[3].or_cell._y : 1  [by my_tree.at_cell.arbs[3]._y1_arb:=0]
+	    640204 my_tree.out.r : 0  [by my_tree.at_cell.arbs[3].or_cell._y:=1]
+	    640204 my_tree.out.a : 0
+	    640750 my_tree.at_cell.arbs[3].ack_cell1._y : 1  [by my_tree.out.a:=0]
+	    686313 my_tree.at_cell.tmp[8].a : 0  [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
+	    686314 my_tree.at_cell.arbs[2].ack_cell1._y : 1  [by my_tree.at_cell.tmp[8].a:=0]
+	    698692 my_tree.at_cell.tmp[5].a : 0  [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
+	    698771 my_tree.at_cell.arbs[2]._y2_arb : 1  [by my_tree.at_cell.tmp[5].a:=0]
+	    698859 my_tree.at_cell.arbs[2].or_cell._y : 0  [by my_tree.at_cell.arbs[2]._y2_arb:=1]
+	    701125 my_tree.at_cell.arbs[0].ack_cell1._y : 1  [by my_tree.at_cell.tmp[5].a:=0]
+	    706641 my_tree.at_cell.tmp[8].r : 1  [by my_tree.at_cell.arbs[2].or_cell._y:=0]
+	    706700 my_tree.at_cell.arbs[3].arbiter._y1 : 0  [by my_tree.at_cell.tmp[8].r:=1]
+	    706730 my_tree.at_cell.arbs[3]._y1_arb : 1  [by my_tree.at_cell.arbs[3].arbiter._y1:=0]
+	    708197 my_tree.at_cell.arbs[3].or_cell._y : 0  [by my_tree.at_cell.arbs[3]._y1_arb:=1]
+	    729452 my_tree._in[0].a : 0  [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
+	    748836 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1  [by my_tree._in[0].a:=0]
+	    767701 my_tree.out.r : 1  [by my_tree.at_cell.arbs[3].or_cell._y:=0]
+	    767701 my_tree.out.a : 1
+	    768386 my_tree.at_cell.arbs[3].ack_cell1._y : 0  [by my_tree.out.a:=1]
+	    785101 my_tree.at_cell.tmp[8].a : 1  [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
+	    785228 my_tree.at_cell.arbs[2].ack_cell2._y : 0  [by my_tree.at_cell.tmp[8].a:=1]
+	    785397 my_tree.at_cell.tmp[6].a : 1  [by my_tree.at_cell.arbs[2].ack_cell2._y:=0]
+	    785440 my_tree.at_cell.arbs[1].ack_cell1._y : 0  [by my_tree.at_cell.tmp[6].a:=1]
+	    785452 my_tree._in[2].a : 1  [by my_tree.at_cell.arbs[1].ack_cell1._y:=0]
+	    786731 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 0  [by my_tree._in[2].a:=1]
+	    786964 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 1  [by my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B:=0]
+	    786967 my_tree._in[2].r : 0  [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=1]
+	    786968 my_tree.fifo_to_tree[2].fifo_element[1]._en : 1  [by my_tree._in[2].r:=0]
+	    787005 my_tree.at_cell.arbs[1].arbiter._y1 : 1  [by my_tree._in[2].r:=0]
+	    799757 my_tree.at_cell.arbs[1]._y1_arb : 0  [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
+	    799849 my_tree.at_cell.arbs[1].or_cell._y : 1  [by my_tree.at_cell.arbs[1]._y1_arb:=0]
+	    802576 my_tree.at_cell.tmp[6].r : 0  [by my_tree.at_cell.arbs[1].or_cell._y:=1]
+	    802578 my_tree.at_cell.arbs[2].arbiter._y2 : 1  [by my_tree.at_cell.tmp[6].r:=0]
+	    802579 my_tree.at_cell.arbs[2]._y2_arb : 0  [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
+	    804080 my_tree.at_cell.arbs[2].or_cell._y : 1  [by my_tree.at_cell.arbs[2]._y2_arb:=0]
+	    804082 my_tree.at_cell.tmp[8].r : 0  [by my_tree.at_cell.arbs[2].or_cell._y:=1]
+	    804100 my_tree.at_cell.arbs[3].arbiter._y1 : 1  [by my_tree.at_cell.tmp[8].r:=0]
+	    804219 my_tree.at_cell.arbs[3]._y1_arb : 0  [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
+	    809939 my_tree.at_cell.arbs[3].or_cell._y : 1  [by my_tree.at_cell.arbs[3]._y1_arb:=0]
+	    809947 my_tree.out.r : 0  [by my_tree.at_cell.arbs[3].or_cell._y:=1]
+	    809947 my_tree.out.a : 0
+	    810001 my_tree.at_cell.arbs[3].ack_cell1._y : 1  [by my_tree.out.a:=0]
+	    860539 my_tree.at_cell.tmp[8].a : 0  [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
+	    860544 my_tree.at_cell.arbs[2].ack_cell2._y : 1  [by my_tree.at_cell.tmp[8].a:=0]
+	    861611 my_tree.at_cell.tmp[6].a : 0  [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
+	    861612 my_tree.at_cell.arbs[1].ack_cell1._y : 1  [by my_tree.at_cell.tmp[6].a:=0]
+	    861750 my_tree._in[2].a : 0  [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
+	    861751 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1  [by my_tree._in[2].a:=0]
+-------------------------------------------------
+[3] Sent three inputs, received 3 outputs

test/unit_tests/arbiter_tree_test/test.act

@@ -0,0 +1,64 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/coders.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+
+defproc arbiter_treee (a1of1 in[5]; a1of1 out)
+{
+    //Low active Reset
+    bool _reset_B;
+    prs {
+        Reset => _reset_B-
+    }
+    a1of1 _in[5];
+    power _supply;
+    _supply.vdd = Vdd;
+    _supply.vss = GND;
+
+    fifo_t<2> fifo_to_tree[5];
+    (i:5:
+        fifo_to_tree[i].in = in[i];
+        fifo_to_tree[i].out = _in[i];
+        fifo_to_tree[i].supply = _supply;
+        fifo_to_tree[i].reset_B = _reset_B;
+    )
+
+    arbtree<5> at_cell(.in=_in, .out = out);
+
+
+
+    at_cell.supply = _supply;
+    
+}
+
+arbiter_treee my_tree;

test/unit_tests/arbiter_tree_test/test.prsim

@@ -0,0 +1,63 @@
+
+watchall
+set my_tree.in[0].r 0
+set my_tree.in[1].r 0
+set my_tree.in[2].r 0
+set my_tree.in[3].r 0
+set my_tree.in[4].r 0
+set my_tree.out.a 0
+
+cycle
+
+assert my_tree.in[0].a 0
+assert my_tree.in[1].a 0
+assert my_tree.in[2].a 0
+assert my_tree.in[3].a 0
+assert my_tree.in[4].a 0
+assert my_tree.out.r 0
+
+system "echo '-------------------------------------------------'"
+system "echo '[0] System initialized'"
+
+set Reset 0
+cycle
+system "echo '-------------------------------------------------'"
+system "echo '[1] System reset completed'"
+
+set my_tree.in[0].r 1
+set my_tree.in[2].r 1
+set my_tree.in[4].r 1
+
+cycle
+
+assert my_tree.out.r 1
+set my_tree.out.a 1
+cycle
+
+assert my_tree.out.r 0
+set my_tree.out.a 0
+
+cycle
+
+assert my_tree.out.r 1
+set my_tree.out.a 1
+cycle
+
+assert my_tree.out.r 0
+set my_tree.out.a 0
+
+cycle
+
+assert my_tree.out.r 1
+set my_tree.out.a 1
+cycle
+
+assert my_tree.out.r 0
+set my_tree.out.a 0
+
+cycle
+
+
+system "echo '-------------------------------------------------'"
+system "echo '[3] Sent three inputs, received 3 outputs'"
+

test/unit_tests/async_instantiate/run/prsim.out

@@ -1 +0,0 @@
-cell27._y cell25.c3 cell18._y cell14._y cell27.pr_B cell21.y cell23.c3 cell10._y cell30.p3 cell20.c1 cell10.n1 cell30._y cell12.sr_B cell8.c1 cell16.c2 cell2.p1 cell28.c2 cell5.c1 cell21._y cell19.c2 cell6.p2 cell9.pr_B cell9.p3 cell4.p1 cell28.sr_B cell11.pr_B cell26.c4 cell9.n2 cell27.c2 cell12.c2 cell28.pr_B cell21.pr_B cell22.pr_B cell11.c2 cell13.y cell9.n1 cell1.n1 cell12.c1 cell28.c4 cell1.n2 cell22.sr_B cell26.y cell11.n2 cell13.n4 cell15.rs_B cell6.c1 cell28._y cell2.n2 cell10.pr_B cell16.y cell16.c1 cell11.sr_B cell15._y cell2.pr_B cell11._y cell20.y cell21.c2 cell22.c1 cell27.sr_B cell4.y cell10.n4 cell23.pr_B cell2.sr_B cell6.p1 cell9.p4 cell23._y cell11.c1 cell9.sr_B cell9.c1 cell27.y cell29.c3 cell12.n1 cell1.sr_B cell29.sr_B cell13.n3 cell13.n2 cell11.n4 cell15.n2 cell15.rp_B cell2.y cell3.n1 cell15.c2 cell26.c3 cell24.c2 cell17._y cell28.c1 cell6.n1 cell14.n1 cell31.n1 cell21.c3 cell27.c3 cell19.sr_B cell26._y cell7._y cell20.c2 cell10.n2 cell9.p2 cell14.rs_B cell31.y cell13.pr_B cell31.p1 cell30.n2 cell18.sr_B cell10.y cell6.y cell24.sr_B cell14.n2 cell30.n1 cell22.y cell10.sr_B cell10.n3 cell13.c2 cell13.n1 cell24.y cell12.pr_B cell29.pr_B cell24.c1 cell16.n1 cell24.pr_B cell28.c3 cell17.c2 cell11.n3 cell16.rs_B cell4._y cell14.c1 cell8.p2 cell14.c2 cell8.p1 cell15.n1 cell15.y cell23.c2 cell18.c1 cell7.p2 cell9.y cell7.y cell29.c1 cell30.p1 cell12.n3 cell11.n1 cell26.pr_B cell29.y cell22._y cell13.c1 cell18.y cell7.c1 cell19.y cell27.c4 cell25.c1 cell21.c1 cell30.y cell1.y cell26.c1 cell17.c1 cell2.n1 cell25.y cell5.y cell30.p4 cell31.p3 cell25.c2 cell3.p1 cell9.p5 cell9.p1 cell26.sr_B cell19.c1 cell8.y cell23.c1 cell18.c2 cell7.p1 cell22.c2 cell23.y cell14.rp_B cell30.p2 cell29.c4 cell23.sr_B cell1.c1 cell26.c2 cell3.y cell10.c1 cell16.n2 cell21.sr_B cell24.c3 cell31.p4 cell1.pr_B cell12.n2 cell31.p2 cell11.y cell12.n4 cell12._y cell18.pr_B cell10.c2 cell2.c1 cell5.p1 cell31.n2 cell13.sr_B cell12.y cell27.c1 cell1._y cell14.y cell16.rp_B cell15.c1 cell4.c1 cell29.c2 cell17.y cell19.pr_B cell3.c1 cell22.c3 cell28.y cell1.p1 

test/unit_tests/async_instantiate/run/test.prs

@@ -1,96 +0,0 @@
-~"cell26.c1"&~"cell26.c2"&~"cell26.c3"&~"cell26.c4"|~"cell26.pr_B"->"cell26._y"+
-"cell26.c1"&"cell26.c2"&"cell26.c3"&"cell26.c4"&"cell26.sr_B"->"cell26._y"-
-"cell26._y"->"cell26.y"-
-~("cell26._y")->"cell26.y"+
-~"cell16.c1"&~"cell16.c2"|~"cell16.rp_B"->"cell16.y"+
-"cell16.c1"&"cell16.c2"&"cell16.n1"&"cell16.n2"&"cell16.rs_B"->"cell16.y"-
-~"cell8.p1"&~"cell8.p2"&~"cell8.c1"->"cell8.y"+
-"cell8.c1"->"cell8.y"-
-~"cell22.c1"&~"cell22.c2"&~"cell22.c3"|~"cell22.pr_B"->"cell22._y"+
-"cell22.c1"&"cell22.c2"&"cell22.c3"&"cell22.sr_B"->"cell22._y"-
-"cell22._y"->"cell22.y"-
-~("cell22._y")->"cell22.y"+
-~"cell19.c1"&~"cell19.c2"|~"cell19.pr_B"->"cell19.y"+
-"cell19.c1"&"cell19.c2"&"cell19.sr_B"->"cell19.y"-
-~"cell12.c1"&~"cell12.c2"|~"cell12.pr_B"->"cell12._y"+
-"cell12.c1"&"cell12.c2"&("cell12.n1"&"cell12.n2"|"cell12.n3"&"cell12.n4")&"cell12.sr_B"->"cell12._y"-
-"cell12._y"->"cell12.y"-
-~("cell12._y")->"cell12.y"+
-~"cell30.p1"&~"cell30.p2"&~"cell30.p3"&~"cell30.p4"->"cell30._y"+
-"cell30.n1"|"cell30.n2"->"cell30._y"-
-"cell30._y"->"cell30.y"-
-~("cell30._y")->"cell30.y"+
-~"cell17.c1"&~"cell17.c2"->"cell17._y"+
-"cell17.c1"&"cell17.c2"->"cell17._y"-
-"cell17._y"->"cell17.y"-
-~("cell17._y")->"cell17.y"+
-~"cell14.c1"&~"cell14.c2"|~"cell14.rp_B"->"cell14._y"+
-"cell14.c1"&"cell14.c2"&"cell14.n1"&"cell14.n2"&"cell14.rs_B"->"cell14._y"-
-"cell14._y"->"cell14.y"-
-~("cell14._y")->"cell14.y"+
-~"cell7.p1"&~"cell7.p2"&~"cell7.c1"->"cell7._y"-
-"cell7.c1"->"cell7._y"+
-"cell7._y"->"cell7.y"-
-~("cell7._y")->"cell7.y"+
-~"cell1.p1"&~"cell1.c1"|~"cell1.pr_B"->"cell1._y"+
-"cell1.c1"&"cell1.n1"&"cell1.n2"&"cell1.sr_B"->"cell1._y"-
-"cell1._y"->"cell1.y"-
-~("cell1._y")->"cell1.y"+
-~"cell21.c1"&~"cell21.c2"&~"cell21.c3"|~"cell21.pr_B"->"cell21._y"+
-"cell21.c1"&"cell21.c2"&"cell21.c3"&"cell21.sr_B"->"cell21._y"-
-"cell21._y"->"cell21.y"-
-~("cell21._y")->"cell21.y"+
-~"cell18.c1"&~"cell18.c2"|~"cell18.pr_B"->"cell18._y"+
-"cell18.c1"&"cell18.c2"&"cell18.sr_B"->"cell18._y"-
-"cell18._y"->"cell18.y"-
-~("cell18._y")->"cell18.y"+
-~"cell15.c1"&~"cell15.c2"|~"cell15.rp_B"->"cell15._y"+
-"cell15.c1"&"cell15.c2"&"cell15.n1"&"cell15.n2"&"cell15.rs_B"->"cell15._y"-
-"cell15._y"->"cell15.y"-
-~("cell15._y")->"cell15.y"+
-~"cell13.c1"&~"cell13.c2"|~"cell13.pr_B"->"cell13.y"+
-"cell13.c1"&"cell13.c2"&("cell13.n1"&"cell13.n2"|"cell13.n3"&"cell13.n4")&"cell13.sr_B"->"cell13.y"-
-~"cell11.c1"&~"cell11.c2"|~"cell11.pr_B"->"cell11._y"+
-"cell11.c1"&"cell11.c2"&("cell11.n1"&"cell11.n2"|"cell11.n3"&"cell11.n4")&"cell11.sr_B"->"cell11._y"-
-"cell11._y"->"cell11.y"-
-~("cell11._y")->"cell11.y"+
-~"cell28.c1"&~"cell28.c2"&~"cell28.c3"&~"cell28.c4"|~"cell28.pr_B"->"cell28._y"+
-"cell28.c1"&"cell28.c2"&"cell28.c3"&"cell28.c4"&"cell28.sr_B"->"cell28._y"-
-"cell28._y"->"cell28.y"-
-~("cell28._y")->"cell28.y"+
-~"cell24.c1"&~"cell24.c2"&~"cell24.c3"|~"cell24.pr_B"->"cell24.y"+
-"cell24.c1"&"cell24.c2"&"cell24.c3"&"cell24.sr_B"->"cell24.y"-
-~"cell23.c1"&~"cell23.c2"&~"cell23.c3"|~"cell23.pr_B"->"cell23._y"+
-"cell23.c1"&"cell23.c2"&"cell23.c3"&"cell23.sr_B"->"cell23._y"-
-"cell23._y"->"cell23.y"-
-~("cell23._y")->"cell23.y"+
-~"cell10.c1"&~"cell10.c2"|~"cell10.pr_B"->"cell10._y"+
-"cell10.c1"&"cell10.c2"&("cell10.n1"&"cell10.n2"|"cell10.n3"&"cell10.n4")&"cell10.sr_B"->"cell10._y"-
-"cell10._y"->"cell10.y"-
-~("cell10._y")->"cell10.y"+
-~"cell3.p1"&~"cell3.c1"->"cell3.y"+
-"cell3.c1"&"cell3.n1"->"cell3.y"-
-~"cell29.c1"&~"cell29.c2"&~"cell29.c3"&~"cell29.c4"|~"cell29.pr_B"->"cell29.y"+
-"cell29.c1"&"cell29.c2"&"cell29.c3"&"cell29.c4"&"cell29.sr_B"->"cell29.y"-
-~"cell25.c1"&~"cell25.c2"&~"cell25.c3"->"cell25.y"+
-"cell25.c1"&"cell25.c2"&"cell25.c3"->"cell25.y"-
-~"cell5.p1"&~"cell5.c1"->"cell5.y"+
-"cell5.c1"->"cell5.y"-
-~"cell4.p1"&~"cell4.c1"->"cell4._y"-
-"cell4.c1"->"cell4._y"+
-"cell4._y"->"cell4.y"-
-~("cell4._y")->"cell4.y"+
-~"cell31.p1"&~"cell31.p2"&~"cell31.p3"&~"cell31.p4"->"cell31.y"+
-"cell31.n1"|"cell31.n2"->"cell31.y"-
-~"cell27.c1"&~"cell27.c2"&~"cell27.c3"&~"cell27.c4"|~"cell27.pr_B"->"cell27._y"+
-"cell27.c1"&"cell27.c2"&"cell27.c3"&"cell27.c4"&"cell27.sr_B"->"cell27._y"-
-"cell27._y"->"cell27.y"-
-~("cell27._y")->"cell27.y"+
-~"cell20.c1"&~"cell20.c2"->"cell20.y"+
-"cell20.c1"&"cell20.c2"->"cell20.y"-
-~"cell9.p1"&~"cell9.p2"&~"cell9.p3"&~"cell9.c1"|~"cell9.p4"&~"cell9.p5"&~"cell9.c1"|~"cell9.pr_B"->"cell9.y"+
-"cell9.c1"&"cell9.n1"&"cell9.n2"&"cell9.sr_B"->"cell9.y"-
-~"cell6.p1"&~"cell6.p2"&~"cell6.c1"->"cell6.y"+
-"cell6.c1"&"cell6.n1"->"cell6.y"-
-~"cell2.p1"&~"cell2.c1"|~"cell2.pr_B"->"cell2.y"-
-"cell2.c1"&"cell2.n1"&"cell2.n2"&"cell2.sr_B"->"cell2.y"+

test/unit_tests/async_instantiate/test.act

@@ -31,17 +31,17 @@ A_1C1P2N_RB_X1 cell1;
 A_1C1P2N_R_X1 cell2;
 A_1C1P_1N_X1 cell3;
 A_1C1P_B cell4;
-A_1C1P cell5;
+A_1C1P_X1 cell5;
 A_1C2P1N_X1 cell6;
 A_1C2P_B_X1 cell7;
-A_1C2P cell8;
+A_1C2P_X1 cell8;
 A_1C3P2P2N_R_X1 cell9;
 A_2C2N2N_RB_X1 cell10;
 A_2C2N2N_RB_X2 cell11;
 A_2C2N2N_RB_X4 cell12;
 A_2C2N2N_R_X1 cell13;
-A_2C2N_R_B_X2 cell14;
-A_2C2N_R_B_X4 cell15;
+A_2C2N_RB_X2 cell14;
+A_2C2N_RB_X4 cell15;
 A_2C2N_R_X1 cell16;
 A_2C_B_X1 cell17;
 A_2C_RB_X1 cell18;

test/unit_tests/bd-fifo-register-fifo-bd/test.act

@@ -0,0 +1,64 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/interfaces.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]; bool? dly_cfg2[2]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    bd2qdi<9,4,2> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .dly_cfg2 = dly_cfg2, .reset_B = _reset_B, .supply = supply);
+
+    fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);
+
+    // Make a register array with 3 bit address (-> 8 registers), 
+    // each register holding 5 bits.
+    register_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
+        .reset_B = _reset_B, .supply = supply);
+
+    fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);
+
+    qdi2bd<8,4> _qdi2bd(.in = fifo_post.out, .out = out, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_reg_fifo_3x5x8 b;

test/unit_tests/bd-fifo-register-fifo-bd/test.prsim

@@ -0,0 +1,78 @@
+watchall
+
+set-bd-channel-neutral "b.in" 9
+# set b.in.r 0
+set b.out.a 0
+
+set b.dly_cfg[0] 1
+set b.dly_cfg[1] 1
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
+
+set b.dly_cfg2[0] 1
+set b.dly_cfg2[1] 1
+
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert-bd-channel-neutral "b.out" 8
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-bd-data-valid "b.in" 9 256
+cycle
+set b.in.r 1
+cycle
+assert b.in.a 1
+# assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+# assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 01100=12 to reg0'"
+set-bd-data-valid "b.in" 9 352
+cycle
+set b.in.r 1
+cycle
+assert b.in.a 1
+# assert b.in.v 1
+assert-var-int "b.data[0]" 5 12
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+# assert b.in.v 0
+assert-var-int "b.data[0]" 5 12
+
+system "echo '[] Reading register 0'"
+set-bd-data-valid "b.in" 9 0
+cycle
+set b.in.r 1
+cycle
+assert-bd-channel-valid "b.out" 8 96
+assert b.out.r 1
+# assert b.in.v 1
+assert b.in.a 1
+
+set b.out.a 1
+cycle
+assert-bd-channel-neutral "b.out" 8
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-bd-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+set b.out.a 0
+cycle

test/unit_tests/bd2qdi_5/test.act

@@ -0,0 +1,45 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ *  It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/interfaces.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc bd2qdi_5(bd<5> in; avMx1of2<5> out; bool? dly_cfg[4]; bool? dly_cfg2[2])
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+  bd2qdi<5,4,2> b(.in = in, .out = out, .reset_B = _reset_B, .dly_cfg = dly_cfg, .dly_cfg2 = dly_cfg2);
+  b.supply.vdd = Vdd;
+  b.supply.vss = GND; 
+}
+
+bd2qdi_5 b;

test/unit_tests/bd2qdi_5/test.prsim

@@ -0,0 +1,140 @@
+watchall
+
+set b.out.a 0
+set b.out.v 0
+set b.in.r 0
+
+set b.dly_cfg[0] 1
+set b.dly_cfg[1] 1
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
+
+set b.dly_cfg2[0] 1
+set b.dly_cfg2[1] 1
+
+set b.in.d[0] 1
+set b.in.d[1] 0
+set b.in.d[2] 0
+set b.in.d[3] 1
+set b.in.d[4] 0
+
+set Reset 0
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+status X
+assert-qdi-channel-neutral "b.out" 5
+assert b.in.a 0
+
+
+system "echo '[] Reset finished, setting data'"
+set b.in.d[0] 0
+set b.in.d[1] 1
+set b.in.d[2] 1
+set b.in.d[3] 0
+set b.in.d[4] 1
+cycle
+
+system "echo '[] Reset finished, setting req 1'"
+set b.in.r 1
+cycle
+assert-qdi-channel-valid "b.out" 5 22
+
+system "echo '[] Receiving val out'"
+set b.out.v 1
+# set b.out.a 1
+cycle
+assert-qdi-channel-valid "b.out" 5 22
+assert b.in.a 1
+
+system "echo '[] Changing some input data'"
+set b.in.d[0] 1
+set b.in.d[1] 1
+set b.in.d[2] 1
+cycle
+system "echo '[] Removing req'"
+set b.in.r 0
+system "echo '[] Changing more data'"
+set b.in.d[3] 0
+set b.in.d[4] 0
+cycle
+assert-qdi-channel-valid "b.out" 5 22
+
+system "echo '[] Receiving ack out'"
+set b.out.a 1
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+set b.out.v 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Set ack out 0'"
+set b.out.a 0
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+assert b.in.a 0
+
+
+
+
+
+
+
+
+
+
+system "echo '[] Again!!! setting data'"
+
+
+set b.in.d[0] 0
+set b.in.d[1] 0
+set b.in.d[2] 0
+set b.in.d[3] 0
+set b.in.d[4] 0
+cycle
+
+system "echo '[] Again!!! setting req 1'"
+set b.in.r 1
+cycle
+assert-qdi-channel-valid "b.out" 5 0
+
+system "echo '[] Receiving val out'"
+set b.out.v 1
+# set b.out.a 1
+cycle
+assert-qdi-channel-valid "b.out" 5 0
+assert b.in.a 1
+
+system "echo '[] Changing some input data'"
+set b.in.d[0] 1
+set b.in.d[1] 1
+set b.in.d[2] 1
+cycle
+system "echo '[] Removing req'"
+set b.in.r 0
+system "echo '[] Changing more data'"
+set b.in.d[3] 0
+set b.in.d[4] 0
+cycle
+assert-qdi-channel-valid "b.out" 5 0
+
+system "echo '[] Receiving ack out'"
+set b.out.a 1
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+set b.out.v 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Set ack out 0'"
+set b.out.a 0
+cycle
+assert-qdi-channel-neutral "b.out" 5 
+assert b.in.a 0

test/unit_tests/buf_15.v

@@ -0,0 +1,685 @@
+//
+// Verilog module for: BUF_X6<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: sigbuf<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
+   input in;
+   output \out[0] ;
+
+// -- signals ---
+   wire in;
+   reg \out[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6  (.y(\out[0] ), .a(in));
+endmodule
+
+//
+// Verilog module for: A_3C_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   wire sr_B;
+   wire pr_B;
+   wire c3;
+   wire c1;
+   reg _y;
+   reg y;
+   wire c2;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg _y;
+   wire a;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: INV_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
+   output y;
+   input c1;
+   input c2;
+
+// -- signals ---
+   reg y;
+   reg _y;
+   wire c2;
+   wire c1;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_3C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+
+// -- signals ---
+   reg _y;
+   reg y;
+   wire c3;
+   wire c1;
+   wire c2;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: ctree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
+   input \in[0] ;
+   input \in[1] ;
+   input \in[2] ;
+   input \in[3] ;
+   input \in[4] ;
+   input \in[5] ;
+   input \in[6] ;
+   input \in[7] ;
+   input \in[8] ;
+   input \in[9] ;
+   input \in[10] ;
+   input \in[11] ;
+   input \in[12] ;
+   input \in[13] ;
+   input \in[14] ;
+   output out;
+
+// -- signals ---
+   wire \in[4] ;
+   wire \in[11] ;
+   wire \in[12] ;
+   reg \tmp[21] ;
+   wire \in[3] ;
+   reg out;
+   reg \tmp[23] ;
+   wire \in[6] ;
+   wire \in[0] ;
+   reg \tmp[18] ;
+   wire \in[10] ;
+   reg \tmp[15] ;
+   reg \tmp[16] ;
+   wire \in[13] ;
+   wire \in[1] ;
+   wire \in[9] ;
+   wire \in[2] ;
+   wire \in[5] ;
+   reg \tmp[24] ;
+   wire \in[14] ;
+   reg \tmp[19] ;
+   wire \in[7] ;
+   reg \tmp[22] ;
+   reg \tmp[20] ;
+   wire \in[8] ;
+   reg \tmp[17] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0]  (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1]  (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2]  (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3]  (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4]  (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5]  (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6]  (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7]  (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0]  (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1]  (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2]  (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
+endmodule
+
+//
+// Verilog module for: OR2_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
+   output y;
+   input a;
+   input b;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+   wire b;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: vtree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
+   input \in.d[0].d[0] ;
+   input \in.d[0].d[1] ;
+   input \in.d[1].d[0] ;
+   input \in.d[1].d[1] ;
+   input \in.d[2].d[0] ;
+   input \in.d[2].d[1] ;
+   input \in.d[3].d[0] ;
+   input \in.d[3].d[1] ;
+   input \in.d[4].d[0] ;
+   input \in.d[4].d[1] ;
+   input \in.d[5].d[0] ;
+   input \in.d[5].d[1] ;
+   input \in.d[6].d[0] ;
+   input \in.d[6].d[1] ;
+   input \in.d[7].d[0] ;
+   input \in.d[7].d[1] ;
+   input \in.d[8].d[0] ;
+   input \in.d[8].d[1] ;
+   input \in.d[9].d[0] ;
+   input \in.d[9].d[1] ;
+   input \in.d[10].d[0] ;
+   input \in.d[10].d[1] ;
+   input \in.d[11].d[0] ;
+   input \in.d[11].d[1] ;
+   input \in.d[12].d[0] ;
+   input \in.d[12].d[1] ;
+   input \in.d[13].d[0] ;
+   input \in.d[13].d[1] ;
+   input \in.d[14].d[0] ;
+   input \in.d[14].d[1] ;
+   output out;
+
+// -- signals ---
+   reg \ct.in[14] ;
+   reg \ct.in[13] ;
+   wire \in.d[7].d[0] ;
+   wire \in.d[1].d[0] ;
+   wire \in.d[0].d[0] ;
+   reg \ct.in[4] ;
+   reg out;
+   wire \in.d[10].d[0] ;
+   wire \in.d[4].d[1] ;
+   reg \ct.in[3] ;
+   wire \in.d[9].d[1] ;
+   wire \in.d[1].d[1] ;
+   wire \in.d[2].d[0] ;
+   wire \in.d[10].d[1] ;
+   reg \ct.in[8] ;
+   wire \in.d[12].d[0] ;
+   wire \in.d[5].d[0] ;
+   wire \in.d[4].d[0] ;
+   reg \ct.in[10] ;
+   reg \ct.in[0] ;
+   wire \in.d[11].d[0] ;
+   wire \in.d[7].d[1] ;
+   wire \in.d[3].d[1] ;
+   reg \ct.in[11] ;
+   reg \ct.in[2] ;
+   reg \ct.in[9] ;
+   wire \in.d[13].d[0] ;
+   wire \in.d[14].d[1] ;
+   wire \in.d[11].d[1] ;
+   wire \in.d[13].d[1] ;
+   wire \in.d[0].d[1] ;
+   reg \ct.in[1] ;
+   wire \in.d[14].d[0] ;
+   wire \in.d[12].d[1] ;
+   wire \in.d[9].d[0] ;
+   wire \in.d[2].d[1] ;
+   reg \ct.in[5] ;
+   wire \in.d[5].d[1] ;
+   reg \ct.in[12] ;
+   reg \ct.in[6] ;
+   wire \in.d[3].d[0] ;
+   wire \in.d[8].d[0] ;
+   wire \in.d[8].d[1] ;
+   reg \ct.in[7] ;
+   wire \in.d[6].d[0] ;
+   wire \in.d[6].d[1] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct  (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0]  (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1]  (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2]  (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3]  (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4]  (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5]  (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6]  (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7]  (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8]  (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9]  (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10]  (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11]  (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12]  (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13]  (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14]  (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
+endmodule
+
+//
+// Verilog module for: A_1C1P_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
+   output y;
+   input c1;
+   input p1;
+
+// -- signals ---
+   reg y;
+   wire c1;
+   wire p1;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C1N_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input n1;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   reg y;
+   wire pr_B;
+   wire c2;
+   wire n1;
+   wire c1;
+   reg _y;
+   wire sr_B;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: buffer<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+   input reset_B;
+
+// -- signals ---
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[5].d[1] ;
+   reg \_en_X_f[0] ;
+   wire \in.d.d[14].d[0] ;
+   wire \in.d.d[12].d[1] ;
+   reg \out.d.d[12].d[1] ;
+   wire \in.d.d[5].d[0] ;
+   reg \out.d.d[11].d[0] ;
+   reg \out.d.d[7].d[0] ;
+   reg _reset_BX;
+   reg \_reset_BXX[0] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[10].d[1] ;
+   wire \in.d.d[2].d[0] ;
+   wire \out.a ;
+   reg \out.d.d[0].d[0] ;
+   wire \in.d.d[0].d[0] ;
+   reg \out.d.d[10].d[1] ;
+   wire \in.d.d[11].d[0] ;
+   wire \in.d.d[7].d[1] ;
+   wire \in.d.d[3].d[1] ;
+   reg _in_v;
+   reg \in.v ;
+   reg _out_a_B;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[9].d[0] ;
+   wire \in.d.d[4].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   wire \in.d.d[1].d[1] ;
+   wire \in.d.d[12].d[0] ;
+   wire \in.d.d[1].d[0] ;
+   reg \_out_a_BX_f[0] ;
+   reg \out.d.d[3].d[1] ;
+   reg \out.d.d[0].d[1] ;
+   reg \out.d.d[2].d[1] ;
+   reg \out.d.d[4].d[1] ;
+   wire reset_B;
+   wire \in.d.d[8].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   wire \in.d.d[5].d[1] ;
+   reg \out.d.d[9].d[0] ;
+   reg \out.d.d[7].d[1] ;
+   reg \_out_a_BX_t[0] ;
+   wire \in.d.d[10].d[0] ;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[7].d[0] ;
+   wire \in.d.d[13].d[1] ;
+   wire \out.v ;
+   reg \out.d.d[2].d[0] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[11].d[1] ;
+   wire \in.d.d[6].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   wire \in.d.d[3].d[0] ;
+   reg _en;
+   reg \out.d.d[13].d[0] ;
+   reg \out.d.d[5].d[0] ;
+   reg \in.a ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[4].d[0] ;
+   wire \in.d.d[8].d[1] ;
+   reg \out.d.d[13].d[1] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[14].d[1] ;
+   wire \in.d.d[2].d[1] ;
+   reg \out.d.d[6].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   reg \out.d.d[1].d[1] ;
+   reg \_en_X_t[0] ;
+   wire \in.d.d[0].d[1] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t  (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl  (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray  (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf  (.y(\in.v ), .a(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv  (.y(_out_a_B), .a(\out.a ));
+_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc  (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f  (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl  (.y(_en), .c1(\in.a ), .p1(\out.v ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf  (.y(_reset_BX), .a(reset_B));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f  (.in(_en), .\out[0] (\_en_X_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t  (.in(_en), .\out[0] (\_en_X_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0]  (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1]  (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2]  (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3]  (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4]  (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5]  (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6]  (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7]  (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8]  (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9]  (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10]  (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11]  (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12]  (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13]  (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14]  (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0]  (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1]  (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2]  (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3]  (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4]  (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5]  (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6]  (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7]  (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8]  (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9]  (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10]  (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11]  (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12]  (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13]  (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14]  (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+endmodule
+
+//
+// Verilog module for: buffer_15<>
+//
+module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+
+// -- signals ---
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[10].d[0] ;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[10].d[1] ;
+   wire \in.d.d[4].d[0] ;
+   reg \out.d.d[10].d[1] ;
+   wire \in.d.d[13].d[0] ;
+   reg \out.d.d[13].d[0] ;
+   reg \out.d.d[9].d[1] ;
+   wire \in.d.d[2].d[1] ;
+   reg \out.d.d[2].d[0] ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[5].d[0] ;
+   reg \in.a ;
+   reg _reset_B;
+   wire \out.v ;
+   wire \out.a ;
+   reg \out.d.d[4].d[0] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[11].d[0] ;
+   wire \in.d.d[2].d[0] ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[13].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   reg \out.d.d[7].d[1] ;
+   wire \in.d.d[12].d[1] ;
+   wire \in.d.d[6].d[1] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[1].d[0] ;
+   reg \out.d.d[14].d[1] ;
+   reg \out.d.d[8].d[0] ;
+   wire \in.d.d[13].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   wire \in.d.d[8].d[1] ;
+   reg \out.d.d[4].d[1] ;
+   wire \in.d.d[14].d[0] ;
+   wire \in.d.d[5].d[1] ;
+   wire \in.d.d[1].d[1] ;
+   wire \in.d.d[9].d[0] ;
+   wire \in.d.d[14].d[1] ;
+   reg \out.d.d[11].d[0] ;
+   reg \out.d.d[6].d[1] ;
+   wire \in.d.d[12].d[0] ;
+   wire \in.d.d[7].d[1] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[5].d[0] ;
+   reg \out.d.d[1].d[1] ;
+   reg \in.v ;
+   wire \in.d.d[0].d[1] ;
+   wire \in.d.d[0].d[0] ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[3].d[1] ;
+   wire \in.d.d[6].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   wire \in.d.d[3].d[1] ;
+   reg \out.d.d[12].d[1] ;
+   wire \in.d.d[4].d[1] ;
+   reg \out.d.d[9].d[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test  (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
+endmodule
+

test/unit_tests/buf_15/run/prsim.out

@@ -1,5 +0,0 @@
-t.buffer_test._en t.buffer_test._out_a_BX_f[0] t.buffer_test._out_a_BX_t[0] t.buffer_test.f_buf_func[0].n1 t.buffer_test.t_buf_func[7].n1 t.buffer_test.t_buf_func[12].n1 t.buffer_test.f_buf_func[8].n1 t.buffer_test.t_buf_func[10].n1 t.buffer_test._en_X_t[0] t.buffer_test.t_buf_func[3].n1 t.buffer_test.f_buf_func[5].n1 t.out.a t.buffer_test.t_buf_func[11].n1 t.buffer_test.vc.tmp[8] t.buffer_test.f_buf_func[4].n1 t.buffer_test.vc.tmp[0] t.buffer_test.vc.tmp[22] t.buffer_test.f_buf_func[6].n1 t.buffer_test.t_buf_func[2].n1 t.buffer_test.t_buf_func[9].n1 t.buffer_test.f_buf_func[13].n1 t.buffer_test.vc.tmp[18] t.buffer_test.t_buf_func[14].n1 t.buffer_test.vc.tmp[5] t.buffer_test.f_buf_func[7].n1 t.buffer_test.f_buf_func[12].n1 t.buffer_test.t_buf_func[4].n1 t.buffer_test._en_X_f[0] t.buffer_test.vc.tmp[10] t.buffer_test.f_buf_func[14].n1 t.buffer_test.out_a_B_buf_t.buf6._y t.buffer_test.vc.tmp[19] t.buffer_test.t_buf_func[8].n1 t.buffer_test.f_buf_func[9].n1 t.buffer_test.f_buf_func[2].n1 t.buffer_test.vc.tmp[16] t.buffer_test.t_buf_func[1].n1 t.buffer_test.f_buf_func[10].n1 t.buffer_test.vc.tmp[2] t.buffer_test.vc.tmp[14] t.buffer_test.vc.tmp[12] t.buffer_test.vc.tmp[1] t.buffer_test._out_a_B t.buffer_test.f_buf_func[1].n1 t.buffer_test.vc.tmp[4] t.buffer_test.out_a_B_buf_f.buf6._y t.buffer_test.vc.tmp[15] t.buffer_test.vc.tmp[11] t.buffer_test.vc.tmp[13] t.in.v t.buffer_test.vc.OR2_tf[0]._y t.buffer_test.vc.tmp[6] t.buffer_test.vc.tmp[9] t.buffer_test.vc.tmp[24] t.buffer_test.vc.tmp[23] t.buffer_test.vc.OR2_tf[14]._y t.buffer_test._in_v t.buffer_test.t_buf_func[0].n1 t.buffer_test.vc.OR2_tf[4]._y t.buffer_test.t_buf_func[5].n1 t.buffer_test.t_buf_func[6].n1 t.buffer_test.t_buf_func[13].n1 t.buffer_test.f_buf_func[3].n1 t.buffer_test.vc.tmp[7] t.buffer_test.vc.C2Els[0]._y t.buffer_test.vc.OR2_tf[5]._y t.buffer_test.vc.tmp[20] t.buffer_test.en_buf_f.buf6._y t.out.v t.buffer_test.vc.OR2_tf[10]._y t.buffer_test.vc.OR2_tf[8]._y t.buffer_test.vc.OR2_tf[3]._y t.buffer_test.vc.C2Els[7]._y t.buffer_test.vc.C2Els[1]._y t.buffer_test.vc.OR2_tf[6]._y t.buffer_test.vc.C3Els[0]._y t.buffer_test.vc.C2Els[3]._y t.buffer_test.f_buf_func[11].n1 t.buffer_test.vc.tmp[21] t.buffer_test.vc.OR2_tf[11]._y t.buffer_test.in_v_buf._y t.buffer_test.vc.OR2_tf[12]._y t.buffer_test.vc.C2Els[2]._y t.buffer_test.vc.tmp[17] t.buffer_test.vc.tmp[3] t.buffer_test.vc.OR2_tf[2]._y t.buffer_test.vc.OR2_tf[7]._y t.buffer_test.vc.OR2_tf[1]._y t.buffer_test.vc.C3Els[1]._y t.buffer_test.vc.C2Els[4]._y t.buffer_test.vc.OR2_tf[13]._y t.buffer_test.vc.C2Els[6]._y t.buffer_test.vc.OR2_tf[9]._y t.buffer_test.en_buf_t.buf6._y t.buffer_test.vc.C3Els[2]._y t.buffer_test.vc.C2Els[5]._y 
-yo man
-reset completed
-
-Finished

test/unit_tests/buf_15_friendly2.v

@@ -0,0 +1,571 @@
+//
+// Verilog module for: BUF_X6<>
+//
+
+
+//
+// Verilog module for: sigbuf<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] , vdd, vss); 
+   input vdd;
+   input vss;
+   input in;
+   output \out[0] ;
+
+// -- signals ---
+   wire in;
+   reg \out[0] ;
+
+// --- instances
+BUF_X6 \buf6  (.y(\out[0] ), .a(in), .vdd(vdd), .vss(vss));
+endmodule
+
+//
+// Verilog module for: A_3C_RB_X4<>
+//
+
+
+//
+// Verilog module for: BUF_X4<>
+//
+
+
+//
+// Verilog module for: INV_X1<>
+//
+
+
+//
+// Verilog module for: A_2C_B_X1<>
+//
+
+
+//
+// Verilog module for: A_3C_B_X1<>
+//
+
+
+//
+// Verilog module for: ctree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input \in[0] ;
+   input \in[1] ;
+   input \in[2] ;
+   input \in[3] ;
+   input \in[4] ;
+   input \in[5] ;
+   input \in[6] ;
+   input \in[7] ;
+   input \in[8] ;
+   input \in[9] ;
+   input \in[10] ;
+   input \in[11] ;
+   input \in[12] ;
+   input \in[13] ;
+   input \in[14] ;
+   output out;
+
+// -- signals ---
+   wire \in[4] ;
+   wire \in[11] ;
+   wire \in[12] ;
+   reg \tmp[21] ;
+   wire \in[3] ;
+   reg out;
+   reg \tmp[23] ;
+   wire \in[6] ;
+   wire \in[0] ;
+   reg \tmp[18] ;
+   wire \in[10] ;
+   reg \tmp[15] ;
+   reg \tmp[16] ;
+   wire \in[13] ;
+   wire \in[1] ;
+   wire \in[9] ;
+   wire \in[2] ;
+   wire \in[5] ;
+   reg \tmp[24] ;
+   wire \in[14] ;
+   reg \tmp[19] ;
+   wire \in[7] ;
+   reg \tmp[22] ;
+   reg \tmp[20] ;
+   wire \in[8] ;
+   reg \tmp[17] ;
+
+// --- instances
+A_2C_B_X1 \C2Els[0]  (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 \C2Els[1]  (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 \C2Els[2]  (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 \C2Els[3]  (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 \C2Els[4]  (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 \C2Els[5]  (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 \C2Els[6]  (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 \C2Els[7]  (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 \C3Els[0]  (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 \C3Els[1]  (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 \C3Els[2]  (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ), .vdd(vdd), .vss(vss));
+endmodule
+
+//
+// Verilog module for: OR2_X1<>
+//
+
+
+//
+// Verilog module for: vtree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input \in.d[0].d[0] ;
+   input \in.d[0].d[1] ;
+   input \in.d[1].d[0] ;
+   input \in.d[1].d[1] ;
+   input \in.d[2].d[0] ;
+   input \in.d[2].d[1] ;
+   input \in.d[3].d[0] ;
+   input \in.d[3].d[1] ;
+   input \in.d[4].d[0] ;
+   input \in.d[4].d[1] ;
+   input \in.d[5].d[0] ;
+   input \in.d[5].d[1] ;
+   input \in.d[6].d[0] ;
+   input \in.d[6].d[1] ;
+   input \in.d[7].d[0] ;
+   input \in.d[7].d[1] ;
+   input \in.d[8].d[0] ;
+   input \in.d[8].d[1] ;
+   input \in.d[9].d[0] ;
+   input \in.d[9].d[1] ;
+   input \in.d[10].d[0] ;
+   input \in.d[10].d[1] ;
+   input \in.d[11].d[0] ;
+   input \in.d[11].d[1] ;
+   input \in.d[12].d[0] ;
+   input \in.d[12].d[1] ;
+   input \in.d[13].d[0] ;
+   input \in.d[13].d[1] ;
+   input \in.d[14].d[0] ;
+   input \in.d[14].d[1] ;
+   output out;
+
+// -- signals ---
+   reg \ct.in[14] ;
+   reg \ct.in[13] ;
+   wire \in.d[7].d[0] ;
+   wire \in.d[1].d[0] ;
+   wire \in.d[0].d[0] ;
+   reg \ct.in[4] ;
+   reg out;
+   wire \in.d[10].d[0] ;
+   wire \in.d[4].d[1] ;
+   reg \ct.in[3] ;
+   wire \in.d[9].d[1] ;
+   wire \in.d[1].d[1] ;
+   wire \in.d[2].d[0] ;
+   wire \in.d[10].d[1] ;
+   reg \ct.in[8] ;
+   wire \in.d[12].d[0] ;
+   wire \in.d[5].d[0] ;
+   wire \in.d[4].d[0] ;
+   reg \ct.in[10] ;
+   reg \ct.in[0] ;
+   wire \in.d[11].d[0] ;
+   wire \in.d[7].d[1] ;
+   wire \in.d[3].d[1] ;
+   reg \ct.in[11] ;
+   reg \ct.in[2] ;
+   reg \ct.in[9] ;
+   wire \in.d[13].d[0] ;
+   wire \in.d[14].d[1] ;
+   wire \in.d[11].d[1] ;
+   wire \in.d[13].d[1] ;
+   wire \in.d[0].d[1] ;
+   reg \ct.in[1] ;
+   wire \in.d[14].d[0] ;
+   wire \in.d[12].d[1] ;
+   wire \in.d[9].d[0] ;
+   wire \in.d[2].d[1] ;
+   reg \ct.in[5] ;
+   wire \in.d[5].d[1] ;
+   reg \ct.in[12] ;
+   reg \ct.in[6] ;
+   wire \in.d[3].d[0] ;
+   wire \in.d[8].d[0] ;
+   wire \in.d[8].d[1] ;
+   reg \ct.in[7] ;
+   wire \in.d[6].d[0] ;
+   wire \in.d[6].d[1] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct  (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[0]  (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[1]  (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[2]  (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[3]  (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[4]  (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[5]  (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[6]  (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[7]  (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[8]  (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[9]  (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[10]  (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[11]  (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[12]  (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[13]  (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ), .vdd(vdd), .vss(vss));
+OR2_X1 \OR2_tf[14]  (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ), .vdd(vdd), .vss(vss));
+endmodule
+
+//
+// Verilog module for: A_1C1P_X1<>
+//
+
+
+//
+// Verilog module for: BUF_X1<>
+//
+
+
+//
+// Verilog module for: A_2C1N_RB_X4<>
+//
+
+
+//
+// Verilog module for: buffer<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B, vdd, vss); 
+   input vdd;
+   input vss;
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+   input reset_B;
+
+// -- signals ---
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[5].d[1] ;
+   reg \_en_X_f[0] ;
+   wire \in.d.d[14].d[0] ;
+   wire \in.d.d[12].d[1] ;
+   reg \out.d.d[12].d[1] ;
+   wire \in.d.d[5].d[0] ;
+   reg \out.d.d[11].d[0] ;
+   reg \out.d.d[7].d[0] ;
+   reg _reset_BX;
+   reg \_reset_BXX[0] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[10].d[1] ;
+   wire \in.d.d[2].d[0] ;
+   wire \out.a ;
+   reg \out.d.d[0].d[0] ;
+   wire \in.d.d[0].d[0] ;
+   reg \out.d.d[10].d[1] ;
+   wire \in.d.d[11].d[0] ;
+   wire \in.d.d[7].d[1] ;
+   wire \in.d.d[3].d[1] ;
+   reg _in_v;
+   reg \in.v ;
+   reg _out_a_B;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[9].d[0] ;
+   wire \in.d.d[4].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   wire \in.d.d[1].d[1] ;
+   wire \in.d.d[12].d[0] ;
+   wire \in.d.d[1].d[0] ;
+   reg \_out_a_BX_f[0] ;
+   reg \out.d.d[3].d[1] ;
+   reg \out.d.d[0].d[1] ;
+   reg \out.d.d[2].d[1] ;
+   reg \out.d.d[4].d[1] ;
+   wire reset_B;
+   wire \in.d.d[8].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   wire \in.d.d[5].d[1] ;
+   reg \out.d.d[9].d[0] ;
+   reg \out.d.d[7].d[1] ;
+   reg \_out_a_BX_t[0] ;
+   wire \in.d.d[10].d[0] ;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[7].d[0] ;
+   wire \in.d.d[13].d[1] ;
+   wire \out.v ;
+   reg \out.d.d[2].d[0] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[11].d[1] ;
+   wire \in.d.d[6].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   wire \in.d.d[3].d[0] ;
+   reg _en;
+   reg \out.d.d[13].d[0] ;
+   reg \out.d.d[5].d[0] ;
+   reg \in.a ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[4].d[0] ;
+   wire \in.d.d[8].d[1] ;
+   reg \out.d.d[13].d[1] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[14].d[1] ;
+   wire \in.d.d[2].d[1] ;
+   reg \out.d.d[6].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   reg \out.d.d[1].d[1] ;
+   reg \_en_X_t[0] ;
+   wire \in.d.d[0].d[1] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t  (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ), .vdd(vdd), .vss(vss));
+A_3C_RB_X4 \inack_ctl  (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray  (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+BUF_X4 \in_v_buf  (.y(\in.v ), .a(_in_v), .vdd(vdd), .vss(vss));
+INV_X1 \out_a_inv  (.y(_out_a_B), .a(\out.a ), .vdd(vdd), .vss(vss));
+_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc  (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v), .vdd(vdd), .vss(vss));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f  (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ), .vdd(vdd), .vss(vss));
+A_1C1P_X1 \en_ctl  (.y(_en), .c1(\in.a ), .p1(\out.v ), .vdd(vdd), .vss(vss));
+BUF_X1 \reset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f  (.in(_en), .\out[0] (\_en_X_f[0] ), .vdd(vdd), .vss(vss));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t  (.in(_en), .\out[0] (\_en_X_t[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[0]  (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[1]  (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[2]  (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[3]  (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[4]  (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[5]  (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[6]  (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[7]  (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[8]  (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[9]  (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[10]  (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[11]  (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[12]  (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[13]  (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \t_buf_func[14]  (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[0]  (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[1]  (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[2]  (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[3]  (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[4]  (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[5]  (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[6]  (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[7]  (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[8]  (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[9]  (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[10]  (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[11]  (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[12]  (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[13]  (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X4 \f_buf_func[14]  (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
+endmodule
+
+//
+// Verilog module for: buffer_15<>
+//
+module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , vdd, vss); 
+   input vdd;
+   input vss;
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+
+// -- signals ---
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[10].d[0] ;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[10].d[1] ;
+   wire \in.d.d[4].d[0] ;
+   reg \out.d.d[10].d[1] ;
+   wire \in.d.d[13].d[0] ;
+   reg \out.d.d[13].d[0] ;
+   reg \out.d.d[9].d[1] ;
+   wire \in.d.d[2].d[1] ;
+   reg \out.d.d[2].d[0] ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[5].d[0] ;
+   reg \in.a ;
+   reg _reset_B;
+   wire \out.v ;
+   wire \out.a ;
+   reg \out.d.d[4].d[0] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[11].d[0] ;
+   wire \in.d.d[2].d[0] ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[13].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   reg \out.d.d[7].d[1] ;
+   wire \in.d.d[12].d[1] ;
+   wire \in.d.d[6].d[1] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[1].d[0] ;
+   reg \out.d.d[14].d[1] ;
+   reg \out.d.d[8].d[0] ;
+   wire \in.d.d[13].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   wire \in.d.d[8].d[1] ;
+   reg \out.d.d[4].d[1] ;
+   wire \in.d.d[14].d[0] ;
+   wire \in.d.d[5].d[1] ;
+   wire \in.d.d[1].d[1] ;
+   wire \in.d.d[9].d[0] ;
+   wire \in.d.d[14].d[1] ;
+   reg \out.d.d[11].d[0] ;
+   reg \out.d.d[6].d[1] ;
+   wire \in.d.d[12].d[0] ;
+   wire \in.d.d[7].d[1] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[5].d[0] ;
+   reg \out.d.d[1].d[1] ;
+   reg \in.v ;
+   wire \in.d.d[0].d[1] ;
+   wire \in.d.d[0].d[0] ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[3].d[1] ;
+   wire \in.d.d[6].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   wire \in.d.d[3].d[1] ;
+   reg \out.d.d[12].d[1] ;
+   wire \in.d.d[4].d[1] ;
+   reg \out.d.d[9].d[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test  (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
+endmodule
+

test/unit_tests/buf_s_5/run/prsim.out

@@ -1,173 +0,0 @@
-b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.vc.tmp[0] b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.tmp[2] b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.OR2_tf[2]._y b.b.en_buf_f.buf2._y b.b.vc.tmp[5] b.b.en_buf_t.buf2._y b.b._en b.b.vc.tmp[4] b.b.vc.C3Els[0]._y b.b.vc.OR2_tf[4]._y b.out.a b.b._in_v b.b.vc.tmp[6] b.b.vc.tmp[3] b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.vc.C2Els[0]._y b.b.out_a_B_buf_f.buf2._y b.b.vc.OR2_tf[3]._y 
-	     84120 b.b.f_buf_func[0].n1 : 0
-	     84120 b.b.f_buf_func[4].y : 1
-	     84120 b.b.t_buf_func[4].y : 1
-	     84120 b.b.f_buf_func[1].n1 : 0
-	     84120 b.b.f_buf_func[3].n1 : 0
-	     84120 b.b.f_buf_func[3].y : 1
-	     84120 b.b.t_buf_func[3].y : 1
-	     84120 b.b.f_buf_func[0].y : 1
-	     84120 b.b.t_buf_func[0].y : 1
-	     84120 b.b.t_buf_func[2].n1 : 0
-	     84120 Reset : 0
-	     84120 b.b.f_buf_func[2].y : 1
-	     84120 b.out.v : 0
-	     84120 b.b.t_buf_func[0].n1 : 0
-	     84120 b.b.f_buf_func[2].n1 : 0
-	     84120 b.out.a : 0
-	     84120 b.b.t_buf_func[4].n1 : 0
-	     84120 b.b.t_buf_func[1].n1 : 0
-	     84120 b.b.f_buf_func[4].n1 : 0
-	     84120 b.b.t_buf_func[2].y : 1
-	     84120 b.b.t_buf_func[3].n1 : 0
-	     84120 b.b.f_buf_func[1].y : 1
-	     84120 b.b.t_buf_func[1].y : 1
-	     84121 b.b.f_buf_func[2].y : 0
-	     84121 b.b._en : 1  [by b.out.v:=0]
-	     84123 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
-	     84141 b.b.vc.tmp[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
-	     84402 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
-	     84542 b.b.t_buf_func[0].y : 0
-	     84671 b.b.t_buf_func[2].y : 0
-	     84888 b.b._out_a_B : 1  [by b.out.a:=0]
-	     85074 b.b.f_buf_func[1].y : 0
-	     85103 b.b.en_buf_t.buf2._y : 0  [by b.b._en:=1]
-	     85191 b.b.vc.OR2_tf[3]._y : 1  [by b.b.t_buf_func[3].n1:=0]
-	     85201 b.b.t_buf_func[1].y : 0
-	     88415 b.b.vc.tmp[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
-	     88891 b.b.out_a_B_buf_t.buf2._y : 0  [by b.b._out_a_B:=1]
-	     89393 b.b._out_a_BX_f[0] : 1  [by b.b.out_a_B_buf_t.buf2._y:=0]
-	     89951 b.b.vc.tmp[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
-	     97969 b.b.f_buf_func[3].y : 0
-	     98463 b.b.f_buf_func[0].y : 0
-	    104325 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
-	    104528 b.b.vc.tmp[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
-	    106382 b.b.vc.C2Els[0]._y : 1  [by b.b.vc.tmp[0]:=0]
-	    106521 b.b.vc.tmp[5] : 0  [by b.b.vc.C2Els[0]._y:=1]
-	    106561 b.b.vc.OR2_tf[4]._y : 1  [by b.b.f_buf_func[4].n1:=0]
-	    106687 b.b._en_X_t[0] : 1  [by b.b.en_buf_t.buf2._y:=0]
-	    108932 b.b.t_buf_func[3].y : 0
-	    113900 b.b.t_buf_func[4].y : 0
-	    129789 b.b.out_a_B_buf_f.buf2._y : 0  [by b.b._out_a_B:=1]
-	    129858 b.b._out_a_BX_t[0] : 1  [by b.b.out_a_B_buf_f.buf2._y:=0]
-	    132834 b._reset_B : 1  [by Reset:=0]
-	    132845 b.b.reset_buf._y : 0  [by b._reset_B:=1]
-	    135773 b.b.f_buf_func[4].y : 0
-	    138591 b.b.en_buf_f.buf2._y : 0  [by b.b._en:=1]
-	    138795 b.b._en_X_f[0] : 1  [by b.b.en_buf_f.buf2._y:=0]
-	    142907 b.b.vc.tmp[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
-	    142922 b.b.vc.C3Els[0]._y : 1  [by b.b.vc.tmp[4]:=0]
-	    142923 b.b.vc.tmp[6] : 0  [by b.b.vc.C3Els[0]._y:=1]
-	    142960 b.b.vc.C2Els[1]._y : 1  [by b.b.vc.tmp[6]:=0]
-	    143699 b.b._in_v : 0  [by b.b.vc.C2Els[1]._y:=1]
-	    143811 b.b.in_v_buf4._y : 1  [by b.b._in_v:=0]
-	    184631 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
-	    184671 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
-	    184928 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]
-	    191323 b.in.v : 0  [by b.b.in_v_buf4._y:=1]
-	    191410 b.b.in_v_bufN.buf2._y : 1  [by b.in.v:=0]
-	    191704 b.b._in_vX[0] : 0  [by b.b.in_v_bufN.buf2._y:=1]
-[] set Reset 1
-	    191704 Reset : 1
-	    191705 b._reset_B : 0  [by Reset:=1]
-	    193511 b.b.reset_buf._y : 1  [by b._reset_B:=0]
-	    195518 b.b._reset_BX : 0  [by b.b.reset_buf._y:=1]
-	    196727 b.b.reset_bufarray.buf2._y : 1  [by b.b._reset_BX:=0]
-	    197317 b.b._reset_BXX[0] : 0  [by b.b.reset_bufarray.buf2._y:=1]
-[] set Reset 0
-	    197317 Reset : 0
-	    197495 b._reset_B : 1  [by Reset:=0]
-	    198298 b.b.reset_buf._y : 0  [by b._reset_B:=1]
-	    198462 b.b._reset_BX : 1  [by b.b.reset_buf._y:=0]
-	    200657 b.b.reset_bufarray.buf2._y : 0  [by b.b._reset_BX:=1]
-	    200679 b.b._reset_BXX[0] : 1  [by b.b.reset_bufarray.buf2._y:=0]
-[] Reset finished, setting some inputs.
-
-	    200679 b.b.t_buf_func[0].n1 : 1
-	    200679 b.b.f_buf_func[3].n1 : 1
-	    200679 b.b.f_buf_func[2].n1 : 1
-	    200679 b.b.t_buf_func[1].n1 : 1
-	    200812 b.b.vc.OR2_tf[2]._y : 0  [by b.b.f_buf_func[2].n1:=1]
-	    201171 b.b.vc.tmp[2] : 1  [by b.b.vc.OR2_tf[2]._y:=0]
-	    201526 b.b.vc.OR2_tf[0]._y : 0  [by b.b.t_buf_func[0].n1:=1]
-	    215642 b.b.vc.tmp[0] : 1  [by b.b.vc.OR2_tf[0]._y:=0]
-	    216341 b.b.vc.OR2_tf[1]._y : 0  [by b.b.t_buf_func[1].n1:=1]
-	    216562 b.b.vc.tmp[1] : 1  [by b.b.vc.OR2_tf[1]._y:=0]
-	    216569 b.b.vc.C2Els[0]._y : 0  [by b.b.vc.tmp[1]:=1]
-	    216599 b.b.vc.tmp[5] : 1  [by b.b.vc.C2Els[0]._y:=0]
-	    230807 b.b.vc.OR2_tf[3]._y : 0  [by b.b.f_buf_func[3].n1:=1]
-	    237520 b.b.vc.tmp[3] : 1  [by b.b.vc.OR2_tf[3]._y:=0]
-[] Setting final input
-	    237520 b.b.t_buf_func[4].n1 : 1
-	    294981 b.b.vc.OR2_tf[4]._y : 0  [by b.b.t_buf_func[4].n1:=1]
-	    295072 b.b.vc.tmp[4] : 1  [by b.b.vc.OR2_tf[4]._y:=0]
-	    297261 b.b.vc.C3Els[0]._y : 0  [by b.b.vc.tmp[4]:=1]
-	    297268 b.b.vc.tmp[6] : 1  [by b.b.vc.C3Els[0]._y:=0]
-	    300055 b.b.vc.C2Els[1]._y : 0  [by b.b.vc.tmp[6]:=1]
-	    300161 b.b._in_v : 1  [by b.b.vc.C2Els[1]._y:=0]
-	    300239 b.b.in_v_buf4._y : 0  [by b.b._in_v:=1]
-	    300514 b.in.v : 1  [by b.b.in_v_buf4._y:=0]
-	    319510 b.b.in_v_bufN.buf2._y : 0  [by b.in.v:=1]
-	    319965 b.b._in_vX[0] : 1  [by b.b.in_v_bufN.buf2._y:=0]
-	    319977 b.b.t_buf_func[0]._y : 0  [by b.b._in_vX[0]:=1]
-	    319977 b.b.t_buf_func[4]._y : 0  [by b.b._in_vX[0]:=1]
-	    320369 b.b.t_buf_func[1]._y : 0  [by b.b._in_vX[0]:=1]
-	    320371 b.b.t_buf_func[1].y : 1  [by b.b.t_buf_func[1]._y:=0]
-	    322876 b.b.t_buf_func[0].y : 1  [by b.b.t_buf_func[0]._y:=0]
-	    324241 b.b.f_buf_func[3]._y : 0  [by b.b._in_vX[0]:=1]
-	    324272 b.b.t_buf_func[4].y : 1  [by b.b.t_buf_func[4]._y:=0]
-	    325881 b.b.f_buf_func[2]._y : 0  [by b.b._in_vX[0]:=1]
-	    327130 b.b.f_buf_func[2].y : 1  [by b.b.f_buf_func[2]._y:=0]
-	    328776 b.b.f_buf_func[3].y : 1  [by b.b.f_buf_func[3]._y:=0]
-[] Receiving out val
-	    328776 b.out.v : 1
-	    332275 b.b.inack_ctl._y : 0  [by b.out.v:=1]
-	    332441 b.in.a : 1  [by b.b.inack_ctl._y:=0]
-	    332516 b.b._en : 0  [by b.in.a:=1]
-	    332654 b.b.en_buf_t.buf2._y : 1  [by b.b._en:=0]
-	    332861 b.b.en_buf_f.buf2._y : 1  [by b.b._en:=0]
-	    332863 b.b._en_X_f[0] : 0  [by b.b.en_buf_f.buf2._y:=1]
-	    337917 b.b._en_X_t[0] : 0  [by b.b.en_buf_t.buf2._y:=1]
-[] Removing input
-	    337917 b.b.t_buf_func[0].n1 : 0
-	    337917 b.b.t_buf_func[4].n1 : 0
-	    337917 b.b.f_buf_func[2].n1 : 0
-	    337917 b.b.t_buf_func[1].n1 : 0
-	    337917 b.b.f_buf_func[3].n1 : 0
-	    337918 b.b.vc.OR2_tf[4]._y : 1  [by b.b.t_buf_func[4].n1:=0]
-	    337928 b.b.vc.OR2_tf[1]._y : 1  [by b.b.t_buf_func[1].n1:=0]
-	    337985 b.b.vc.tmp[4] : 0  [by b.b.vc.OR2_tf[4]._y:=1]
-	    338287 b.b.vc.OR2_tf[3]._y : 1  [by b.b.f_buf_func[3].n1:=0]
-	    338303 b.b.vc.tmp[3] : 0  [by b.b.vc.OR2_tf[3]._y:=1]
-	    338465 b.b.vc.OR2_tf[2]._y : 1  [by b.b.f_buf_func[2].n1:=0]
-	    340569 b.b.vc.tmp[1] : 0  [by b.b.vc.OR2_tf[1]._y:=1]
-	    343027 b.b.vc.tmp[2] : 0  [by b.b.vc.OR2_tf[2]._y:=1]
-	    343555 b.b.vc.C3Els[0]._y : 1  [by b.b.vc.tmp[2]:=0]
-	    345990 b.b.vc.tmp[6] : 0  [by b.b.vc.C3Els[0]._y:=1]
-	    381834 b.b.vc.OR2_tf[0]._y : 1  [by b.b.t_buf_func[0].n1:=0]
-	    408714 b.b.vc.tmp[0] : 0  [by b.b.vc.OR2_tf[0]._y:=1]
-	    432639 b.b.vc.C2Els[0]._y : 1  [by b.b.vc.tmp[0]:=0]
-	    445680 b.b.vc.tmp[5] : 0  [by b.b.vc.C2Els[0]._y:=1]
-	    445682 b.b.vc.C2Els[1]._y : 1  [by b.b.vc.tmp[5]:=0]
-	    506640 b.b._in_v : 0  [by b.b.vc.C2Els[1]._y:=1]
-	    506643 b.b.in_v_buf4._y : 1  [by b.b._in_v:=0]
-	    506672 b.in.v : 0  [by b.b.in_v_buf4._y:=1]
-	    506989 b.b.in_v_bufN.buf2._y : 1  [by b.in.v:=0]
-	    508590 b.b._in_vX[0] : 0  [by b.b.in_v_bufN.buf2._y:=1]
-[] Receiving out ack
-	    508590 b.out.a : 1
-	    508743 b.b._out_a_B : 0  [by b.out.a:=1]
-	    508787 b.b.out_a_B_buf_t.buf2._y : 1  [by b.b._out_a_B:=0]
-	    511504 b.b.out_a_B_buf_f.buf2._y : 1  [by b.b._out_a_B:=0]
-	    511505 b.b._out_a_BX_t[0] : 0  [by b.b.out_a_B_buf_f.buf2._y:=1]
-	    511506 b.b.t_buf_func[4]._y : 1  [by b.b._out_a_BX_t[0]:=0]
-	    511527 b.b.t_buf_func[1]._y : 1  [by b.b._out_a_BX_t[0]:=0]
-	    511722 b.b.t_buf_func[0]._y : 1  [by b.b._out_a_BX_t[0]:=0]
-	    511881 b.b.t_buf_func[0].y : 0  [by b.b.t_buf_func[0]._y:=1]
-	    513087 b.b.t_buf_func[4].y : 0  [by b.b.t_buf_func[4]._y:=1]
-	    520872 b.b.t_buf_func[1].y : 0  [by b.b.t_buf_func[1]._y:=1]
-	    522470 b.b._out_a_BX_f[0] : 0  [by b.b.out_a_B_buf_t.buf2._y:=1]
-	    523757 b.b.f_buf_func[3]._y : 1  [by b.b._out_a_BX_f[0]:=0]
-	    525989 b.b.f_buf_func[3].y : 0  [by b.b.f_buf_func[3]._y:=1]
-	    542146 b.b.f_buf_func[2]._y : 1  [by b.b._out_a_BX_f[0]:=0]
-	    542291 b.b.f_buf_func[2].y : 0  [by b.b.f_buf_func[2]._y:=1]

test/unit_tests/buf_s_5/run/test.prs

@@ -1,646 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-"Reset"->"b._reset_B"-
-~("Reset")->"b._reset_B"+
-"b.b.out_a_B_buf_t.buf2.a"->"b.b.out_a_B_buf_t.buf2._y"-
-~("b.b.out_a_B_buf_t.buf2.a")->"b.b.out_a_B_buf_t.buf2._y"+
-"b.b.out_a_B_buf_t.buf2._y"->"b.b.out_a_B_buf_t.buf2.y"-
-~("b.b.out_a_B_buf_t.buf2._y")->"b.b.out_a_B_buf_t.buf2.y"+
-= "b.b.out_a_B_buf_t.supply.vdd" "b.b.out_a_B_buf_t.buf2.vdd"
-= "b.b.out_a_B_buf_t.supply.vss" "b.b.out_a_B_buf_t.buf2.vss"
-= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[4]"
-= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[3]"
-= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[2]"
-= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[1]"
-= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.buf2.y"
-= "b.b.out_a_B_buf_t.in" "b.b.out_a_B_buf_t.buf2.a"
-= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
-= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
-= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
-= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
-= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
-= "b.b._en_X_f[0]" "b.b.f_buf_func[4].c1"
-= "b.b._en_X_f[0]" "b.b.f_buf_func[3].c1"
-= "b.b._en_X_f[0]" "b.b.f_buf_func[2].c1"
-= "b.b._en_X_f[0]" "b.b.f_buf_func[1].c1"
-= "b.b._en_X_f[0]" "b.b.f_buf_func[0].c1"
-= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
-= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
-= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
-= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
-~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"&~"b.b.inack_ctl.c3"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl._y"+
-"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.c3"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl._y"-
-"b.b.inack_ctl._y"->"b.b.inack_ctl.y"-
-~("b.b.inack_ctl._y")->"b.b.inack_ctl.y"+
-"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
-~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
-"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
-~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
-= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
-= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
-= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
-= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
-= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
-= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
-= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
-= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
-"b.b.in_v_buf4.a"->"b.b.in_v_buf4._y"-
-~("b.b.in_v_buf4.a")->"b.b.in_v_buf4._y"+
-"b.b.in_v_buf4._y"->"b.b.in_v_buf4.y"-
-~("b.b.in_v_buf4._y")->"b.b.in_v_buf4.y"+
-"b.b.out_a_inv.a"->"b.b.out_a_inv.y"-
-~("b.b.out_a_inv.a")->"b.b.out_a_inv.y"+
-= "b.b._out_a_BX_f[0]" "b.b.out_a_B_buf_t.out[0]"
-= "b.b._out_a_BX_f[1]" "b.b.out_a_B_buf_t.out[1]"
-= "b.b._out_a_BX_f[2]" "b.b.out_a_B_buf_t.out[2]"
-= "b.b._out_a_BX_f[3]" "b.b.out_a_B_buf_t.out[3]"
-= "b.b._out_a_BX_f[4]" "b.b.out_a_B_buf_t.out[4]"
-= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[4].c2"
-= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[3].c2"
-= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[2].c2"
-= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[1].c2"
-= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[0].c2"
-= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[4]"
-= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[3]"
-= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[2]"
-= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[1]"
-= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
-= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
-= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
-= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
-= "b.b.supply.vss" "b.b.in_v_bufN.supply.vss"
-= "b.b.supply.vdd" "b.b.in_v_bufN.supply.vdd"
-= "b.b.supply.vss" "b.b.vc.supply.vss"
-= "b.b.supply.vdd" "b.b.vc.supply.vdd"
-= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
-= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
-= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
-= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
-= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
-= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
-= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
-= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
-= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
-= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
-= "b.b.supply.vdd" "b.b.in_v_buf4.vdd"
-= "b.b.supply.vdd" "b.b.reset_buf.vdd"
-= "b.b.supply.vdd" "b.b.en_ctl.vdd"
-= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
-= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
-= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
-= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
-= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
-= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
-= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
-= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
-= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
-= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
-= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
-= "b.b.supply.vss" "b.b.in_v_buf4.vss"
-= "b.b.supply.vss" "b.b.reset_buf.vss"
-= "b.b.supply.vss" "b.b.en_ctl.vss"
-= "b.b.supply.vss" "b.b.inack_ctl.vss"
-~"b.b.vc.C2Els[0].c1"&~"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"+
-"b.b.vc.C2Els[0].c1"&"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"-
-"b.b.vc.C2Els[0]._y"->"b.b.vc.C2Els[0].y"-
-~("b.b.vc.C2Els[0]._y")->"b.b.vc.C2Els[0].y"+
-~"b.b.vc.C2Els[1].c1"&~"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"+
-"b.b.vc.C2Els[1].c1"&"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"-
-"b.b.vc.C2Els[1]._y"->"b.b.vc.C2Els[1].y"-
-~("b.b.vc.C2Els[1]._y")->"b.b.vc.C2Els[1].y"+
-~"b.b.vc.C3Els[0].c1"&~"b.b.vc.C3Els[0].c2"&~"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"+
-"b.b.vc.C3Els[0].c1"&"b.b.vc.C3Els[0].c2"&"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"-
-"b.b.vc.C3Els[0]._y"->"b.b.vc.C3Els[0].y"-
-~("b.b.vc.C3Els[0]._y")->"b.b.vc.C3Els[0].y"+
-"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
-~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
-"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
-~("b.b.vc.OR2_tf[0]._y")->"b.b.vc.OR2_tf[0].y"+
-"b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b"->"b.b.vc.OR2_tf[1]._y"-
-~("b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b")->"b.b.vc.OR2_tf[1]._y"+
-"b.b.vc.OR2_tf[1]._y"->"b.b.vc.OR2_tf[1].y"-
-~("b.b.vc.OR2_tf[1]._y")->"b.b.vc.OR2_tf[1].y"+
-"b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b"->"b.b.vc.OR2_tf[2]._y"-
-~("b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b")->"b.b.vc.OR2_tf[2]._y"+
-"b.b.vc.OR2_tf[2]._y"->"b.b.vc.OR2_tf[2].y"-
-~("b.b.vc.OR2_tf[2]._y")->"b.b.vc.OR2_tf[2].y"+
-"b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b"->"b.b.vc.OR2_tf[3]._y"-
-~("b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b")->"b.b.vc.OR2_tf[3]._y"+
-"b.b.vc.OR2_tf[3]._y"->"b.b.vc.OR2_tf[3].y"-
-~("b.b.vc.OR2_tf[3]._y")->"b.b.vc.OR2_tf[3].y"+
-"b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b"->"b.b.vc.OR2_tf[4]._y"-
-~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
-"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
-~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
-= "b.b.vc.tmp[0]" "b.b.vc.C2Els[0].c1"
-= "b.b.vc.tmp[0]" "b.b.vc.OR2_tf[0].y"
-= "b.b.vc.tmp[1]" "b.b.vc.C2Els[0].c2"
-= "b.b.vc.tmp[1]" "b.b.vc.OR2_tf[1].y"
-= "b.b.vc.tmp[2]" "b.b.vc.C3Els[0].c1"
-= "b.b.vc.tmp[2]" "b.b.vc.OR2_tf[2].y"
-= "b.b.vc.tmp[3]" "b.b.vc.C3Els[0].c2"
-= "b.b.vc.tmp[3]" "b.b.vc.OR2_tf[3].y"
-= "b.b.vc.tmp[4]" "b.b.vc.C3Els[0].c3"
-= "b.b.vc.tmp[4]" "b.b.vc.OR2_tf[4].y"
-= "b.b.vc.tmp[5]" "b.b.vc.C2Els[1].c1"
-= "b.b.vc.tmp[5]" "b.b.vc.C2Els[0].y"
-= "b.b.vc.tmp[6]" "b.b.vc.C2Els[1].c2"
-= "b.b.vc.tmp[6]" "b.b.vc.C3Els[0].y"
-= "b.b.vc.supply.vdd" "b.b.vc.C3Els[0].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.C2Els[1].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.C2Els[0].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
-= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
-= "b.b.vc.supply.vss" "b.b.vc.C3Els[0].vss"
-= "b.b.vc.supply.vss" "b.b.vc.C2Els[1].vss"
-= "b.b.vc.supply.vss" "b.b.vc.C2Els[0].vss"
-= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
-= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
-= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
-= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
-= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
-= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
-= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
-= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
-= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
-= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
-= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
-= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
-= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
-= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
-= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
-= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
-= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
-= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
-= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
-= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
-= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
-= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
-= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
-= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
-= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
-= "b.b.vc.in.d[4].d[0]" "b.b.vc.OR2_tf[4].b"
-= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
-= "b.b.vc.in.d[4].d[1]" "b.b.vc.OR2_tf[4].a"
-= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
-= "b.b.vc.in.d[3].d[0]" "b.b.vc.OR2_tf[3].b"
-= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
-= "b.b.vc.in.d[3].d[1]" "b.b.vc.OR2_tf[3].a"
-= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
-= "b.b.vc.in.d[2].d[0]" "b.b.vc.OR2_tf[2].b"
-= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
-= "b.b.vc.in.d[2].d[1]" "b.b.vc.OR2_tf[2].a"
-= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
-= "b.b.vc.in.d[1].d[0]" "b.b.vc.OR2_tf[1].b"
-= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
-= "b.b.vc.in.d[1].d[1]" "b.b.vc.OR2_tf[1].a"
-= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
-= "b.b.vc.in.d[0].d[0]" "b.b.vc.OR2_tf[0].b"
-= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
-= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
-= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
-= "b.b.vc.out" "b.b.vc.C2Els[1].y"
-= "b.b.vc.out" "b.b.vc.tmp[7]"
-"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
-~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
-"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
-~("b.b.out_a_B_buf_f.buf2._y")->"b.b.out_a_B_buf_f.buf2.y"+
-= "b.b.out_a_B_buf_f.supply.vdd" "b.b.out_a_B_buf_f.buf2.vdd"
-= "b.b.out_a_B_buf_f.supply.vss" "b.b.out_a_B_buf_f.buf2.vss"
-= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[4]"
-= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[3]"
-= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[2]"
-= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[1]"
-= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.buf2.y"
-= "b.b.out_a_B_buf_f.in" "b.b.out_a_B_buf_f.buf2.a"
-= "b.b._en" "b.b.en_buf_f.in"
-= "b.b._en" "b.b.en_buf_t.in"
-= "b.b._en" "b.b.en_ctl.y"
-= "b.b._en" "b.b.inack_ctl.c1"
-~"b.b.en_ctl.p1"&~"b.b.en_ctl.c1"->"b.b.en_ctl.y"+
-"b.b.en_ctl.c1"->"b.b.en_ctl.y"-
-= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
-= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
-= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
-= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
-= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
-= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
-= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
-= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
-= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
-= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
-= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
-= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
-= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
-= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
-= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
-= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
-= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
-= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
-= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
-= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
-= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
-= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
-= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
-= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
-= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
-= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
-= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
-= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
-= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
-= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
-= "b.b.out.a" "b.b.out_a_inv.a"
-= "b.b.out.v" "b.b.en_ctl.p1"
-= "b.b.out.v" "b.b.inack_ctl.c3"
-= "b.b.out.d.d[4].d[0]" "b.b.f_buf_func[4].y"
-= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
-= "b.b.out.d.d[4].d[1]" "b.b.t_buf_func[4].y"
-= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
-= "b.b.out.d.d[3].d[0]" "b.b.f_buf_func[3].y"
-= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
-= "b.b.out.d.d[3].d[1]" "b.b.t_buf_func[3].y"
-= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
-= "b.b.out.d.d[2].d[0]" "b.b.f_buf_func[2].y"
-= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
-= "b.b.out.d.d[2].d[1]" "b.b.t_buf_func[2].y"
-= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
-= "b.b.out.d.d[1].d[0]" "b.b.f_buf_func[1].y"
-= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
-= "b.b.out.d.d[1].d[1]" "b.b.t_buf_func[1].y"
-= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
-= "b.b.out.d.d[0].d[0]" "b.b.f_buf_func[0].y"
-= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
-= "b.b.out.d.d[0].d[1]" "b.b.t_buf_func[0].y"
-= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
-= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
-= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
-= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
-= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
-= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
-= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
-= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
-= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
-= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
-= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
-= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
-= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
-= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
-= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
-= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
-= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
-= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
-= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
-= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
-= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
-= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
-= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
-= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
-= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
-= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
-= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
-= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
-= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
-= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
-= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
-= "b.b.in.d.d[0].f" "b.b.vc.in.d[0].f"
-= "b.b.in.d.d[0].t" "b.b.vc.in.d[0].t"
-= "b.b.in.d.d[0].d[0]" "b.b.vc.in.d[0].d[0]"
-= "b.b.in.d.d[0].d[1]" "b.b.vc.in.d[0].d[1]"
-= "b.b.in.d.d[1].f" "b.b.vc.in.d[1].f"
-= "b.b.in.d.d[1].t" "b.b.vc.in.d[1].t"
-= "b.b.in.d.d[1].d[0]" "b.b.vc.in.d[1].d[0]"
-= "b.b.in.d.d[1].d[1]" "b.b.vc.in.d[1].d[1]"
-= "b.b.in.d.d[2].f" "b.b.vc.in.d[2].f"
-= "b.b.in.d.d[2].t" "b.b.vc.in.d[2].t"
-= "b.b.in.d.d[2].d[0]" "b.b.vc.in.d[2].d[0]"
-= "b.b.in.d.d[2].d[1]" "b.b.vc.in.d[2].d[1]"
-= "b.b.in.d.d[3].f" "b.b.vc.in.d[3].f"
-= "b.b.in.d.d[3].t" "b.b.vc.in.d[3].t"
-= "b.b.in.d.d[3].d[0]" "b.b.vc.in.d[3].d[0]"
-= "b.b.in.d.d[3].d[1]" "b.b.vc.in.d[3].d[1]"
-= "b.b.in.d.d[4].f" "b.b.vc.in.d[4].f"
-= "b.b.in.d.d[4].t" "b.b.vc.in.d[4].t"
-= "b.b.in.d.d[4].d[0]" "b.b.vc.in.d[4].d[0]"
-= "b.b.in.d.d[4].d[1]" "b.b.vc.in.d[4].d[1]"
-= "b.b.in.a" "b.b.en_ctl.c1"
-= "b.b.in.a" "b.b.inack_ctl.y"
-= "b.b.in.v" "b.b.in_v_bufN.in"
-= "b.b.in.v" "b.b.in_v_buf4.y"
-= "b.b.in.v" "b.b.inack_ctl.c2"
-= "b.b.in.d.d[4].d[0]" "b.b.f_buf_func[4].n1"
-= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
-= "b.b.in.d.d[4].d[1]" "b.b.t_buf_func[4].n1"
-= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
-= "b.b.in.d.d[3].d[0]" "b.b.f_buf_func[3].n1"
-= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
-= "b.b.in.d.d[3].d[1]" "b.b.t_buf_func[3].n1"
-= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
-= "b.b.in.d.d[2].d[0]" "b.b.f_buf_func[2].n1"
-= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
-= "b.b.in.d.d[2].d[1]" "b.b.t_buf_func[2].n1"
-= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
-= "b.b.in.d.d[1].d[0]" "b.b.f_buf_func[1].n1"
-= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
-= "b.b.in.d.d[1].d[1]" "b.b.t_buf_func[1].n1"
-= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
-= "b.b.in.d.d[0].d[0]" "b.b.f_buf_func[0].n1"
-= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
-= "b.b.in.d.d[0].d[1]" "b.b.t_buf_func[0].n1"
-= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
-"b.b.reset_buf.a"->"b.b.reset_buf._y"-
-~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
-"b.b.reset_buf._y"->"b.b.reset_buf.y"-
-~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
-= "b.b._in_v" "b.b.in_v_buf4.a"
-= "b.b._in_v" "b.b.vc.out"
-= "b.b._out_a_BX_t[0]" "b.b.out_a_B_buf_f.out[0]"
-= "b.b._out_a_BX_t[1]" "b.b.out_a_B_buf_f.out[1]"
-= "b.b._out_a_BX_t[2]" "b.b.out_a_B_buf_f.out[2]"
-= "b.b._out_a_BX_t[3]" "b.b.out_a_B_buf_f.out[3]"
-= "b.b._out_a_BX_t[4]" "b.b.out_a_B_buf_f.out[4]"
-= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[4].c2"
-= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[3].c2"
-= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[2].c2"
-= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[1].c2"
-= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[0].c2"
-= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[4]"
-= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[3]"
-= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[2]"
-= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[1]"
-= "b.b._reset_BX" "b.b.reset_bufarray.in"
-= "b.b._reset_BX" "b.b.reset_buf.y"
-= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
-= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
-= "b.b.reset_B" "b.b.reset_buf.a"
-"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
-~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
-"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
-~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
-= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
-= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
-= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
-= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
-= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
-= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
-= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
-= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
-"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
-~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
-"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
-~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
-= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
-= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
-= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
-= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
-= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
-= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
-= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
-= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
-= "b.b._out_a_B" "b.b.out_a_B_buf_t.in"
-= "b.b._out_a_B" "b.b.out_a_B_buf_f.in"
-= "b.b._out_a_B" "b.b.out_a_inv.y"
-= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
-= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
-= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
-= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
-= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].sr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].pr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].sr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].pr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].sr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].pr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].sr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].pr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
-= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].sr_B"
-= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].pr_B"
-= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
-= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
-= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
-= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
-= "b.b._in_vX[0]" "b.b.in_v_bufN.out[0]"
-= "b.b._in_vX[1]" "b.b.in_v_bufN.out[1]"
-= "b.b._in_vX[2]" "b.b.in_v_bufN.out[2]"
-= "b.b._in_vX[3]" "b.b.in_v_bufN.out[3]"
-= "b.b._in_vX[4]" "b.b.in_v_bufN.out[4]"
-= "b.b._in_vX[0]" "b.b.t_buf_func[4].n2"
-= "b.b._in_vX[0]" "b.b.f_buf_func[4].n2"
-= "b.b._in_vX[0]" "b.b.t_buf_func[3].n2"
-= "b.b._in_vX[0]" "b.b.f_buf_func[3].n2"
-= "b.b._in_vX[0]" "b.b.t_buf_func[2].n2"
-= "b.b._in_vX[0]" "b.b.f_buf_func[2].n2"
-= "b.b._in_vX[0]" "b.b.t_buf_func[1].n2"
-= "b.b._in_vX[0]" "b.b.f_buf_func[1].n2"
-= "b.b._in_vX[0]" "b.b.t_buf_func[0].n2"
-= "b.b._in_vX[0]" "b.b.f_buf_func[0].n2"
-= "b.b._in_vX[0]" "b.b._in_vX[4]"
-= "b.b._in_vX[0]" "b.b._in_vX[3]"
-= "b.b._in_vX[0]" "b.b._in_vX[2]"
-= "b.b._in_vX[0]" "b.b._in_vX[1]"
-"b.b.in_v_bufN.buf2.a"->"b.b.in_v_bufN.buf2._y"-
-~("b.b.in_v_bufN.buf2.a")->"b.b.in_v_bufN.buf2._y"+
-"b.b.in_v_bufN.buf2._y"->"b.b.in_v_bufN.buf2.y"-
-~("b.b.in_v_bufN.buf2._y")->"b.b.in_v_bufN.buf2.y"+
-= "b.b.in_v_bufN.supply.vdd" "b.b.in_v_bufN.buf2.vdd"
-= "b.b.in_v_bufN.supply.vss" "b.b.in_v_bufN.buf2.vss"
-= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[4]"
-= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[3]"
-= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[2]"
-= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[1]"
-= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.buf2.y"
-= "b.b.in_v_bufN.in" "b.b.in_v_bufN.buf2.a"
-~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].c2"|~"b.b.t_buf_func[0].pr_B"->"b.b.t_buf_func[0]._y"+
-"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].c2"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"&"b.b.t_buf_func[0].sr_B"->"b.b.t_buf_func[0]._y"-
-"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
-~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
-~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].c2"|~"b.b.t_buf_func[1].pr_B"->"b.b.t_buf_func[1]._y"+
-"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].c2"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"&"b.b.t_buf_func[1].sr_B"->"b.b.t_buf_func[1]._y"-
-"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
-~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
-~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].c2"|~"b.b.t_buf_func[2].pr_B"->"b.b.t_buf_func[2]._y"+
-"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].c2"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"&"b.b.t_buf_func[2].sr_B"->"b.b.t_buf_func[2]._y"-
-"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
-~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
-~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].c2"|~"b.b.t_buf_func[3].pr_B"->"b.b.t_buf_func[3]._y"+
-"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].c2"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"&"b.b.t_buf_func[3].sr_B"->"b.b.t_buf_func[3]._y"-
-"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
-~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
-~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].c2"|~"b.b.t_buf_func[4].pr_B"->"b.b.t_buf_func[4]._y"+
-"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].c2"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"&"b.b.t_buf_func[4].sr_B"->"b.b.t_buf_func[4]._y"-
-"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
-~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
-~"b.b.f_buf_func[0].c1"&~"b.b.f_buf_func[0].c2"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
-"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].c2"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
-"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
-~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
-~"b.b.f_buf_func[1].c1"&~"b.b.f_buf_func[1].c2"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
-"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].c2"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
-"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
-~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
-~"b.b.f_buf_func[2].c1"&~"b.b.f_buf_func[2].c2"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
-"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].c2"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
-"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
-~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
-~"b.b.f_buf_func[3].c1"&~"b.b.f_buf_func[3].c2"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
-"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].c2"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
-"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
-~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
-~"b.b.f_buf_func[4].c1"&~"b.b.f_buf_func[4].c2"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
-"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].c2"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
-"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
-~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
-= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
-= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
-= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
-= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
-= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
-= "b.b._en_X_t[0]" "b.b.t_buf_func[4].c1"
-= "b.b._en_X_t[0]" "b.b.t_buf_func[3].c1"
-= "b.b._en_X_t[0]" "b.b.t_buf_func[2].c1"
-= "b.b._en_X_t[0]" "b.b.t_buf_func[1].c1"
-= "b.b._en_X_t[0]" "b.b.t_buf_func[0].c1"
-= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
-= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
-= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
-= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
-= "Vdd" "b.b.supply.vdd"
-= "GND" "b.b.supply.vss"
-= "b._reset_B" "b.b.reset_B"
-= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
-= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
-= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
-= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
-= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
-= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
-= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
-= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
-= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
-= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
-= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
-= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
-= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
-= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
-= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
-= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
-= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
-= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
-= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
-= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
-= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
-= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
-= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
-= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
-= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
-= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
-= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
-= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
-= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
-= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
-= "b.out.v" "b.b.out.v"
-= "b.out.a" "b.b.out.a"
-= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
-= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
-= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
-= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
-= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
-= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
-= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
-= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
-= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
-= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
-= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
-= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
-= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
-= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
-= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
-= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
-= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
-= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
-= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
-= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
-= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
-= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
-= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
-= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
-= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
-= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
-= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
-= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
-= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
-= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
-= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
-= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
-= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
-= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
-= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
-= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
-= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
-= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
-= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
-= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
-= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
-= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
-= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
-= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
-= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
-= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
-= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
-= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
-= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
-= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
-= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
-= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
-= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
-= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
-= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
-= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
-= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
-= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
-= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
-= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
-= "b.in.v" "b.b.in.v"
-= "b.in.a" "b.b.in.a"
-= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
-= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
-= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
-= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
-= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
-= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
-= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
-= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
-= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
-= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
-= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
-= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
-= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
-= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
-= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
-= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
-= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
-= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
-= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
-= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
-= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
-= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
-= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
-= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
-= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
-= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
-= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
-= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
-= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
-= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

test/unit_tests/buff.v

@@ -0,0 +1,685 @@
+//
+// Verilog module for: BUF_X6<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   wire a;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: sigbuf<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
+   input in;
+   output \out[0] ;
+
+// -- signals ---
+   reg \out[0] ;
+   wire in;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6  (.y(\out[0] ), .a(in));
+endmodule
+
+//
+// Verilog module for: A_3C_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   wire pr_B;
+   wire c3;
+   wire c1;
+   wire sr_B;
+   wire c2;
+   reg _y;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: INV_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
+   output y;
+   input c1;
+   input c2;
+
+// -- signals ---
+   wire c2;
+   wire c1;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_3C_B_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
+   output y;
+   input c1;
+   input c2;
+   input c3;
+
+// -- signals ---
+   wire c1;
+   reg y;
+   reg _y;
+   wire c3;
+   wire c2;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: ctree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
+   input \in[0] ;
+   input \in[1] ;
+   input \in[2] ;
+   input \in[3] ;
+   input \in[4] ;
+   input \in[5] ;
+   input \in[6] ;
+   input \in[7] ;
+   input \in[8] ;
+   input \in[9] ;
+   input \in[10] ;
+   input \in[11] ;
+   input \in[12] ;
+   input \in[13] ;
+   input \in[14] ;
+   output out;
+
+// -- signals ---
+   wire \in[9] ;
+   wire \in[11] ;
+   reg \tmp[18] ;
+   reg \tmp[16] ;
+   reg \tmp[24] ;
+   wire \in[0] ;
+   reg \tmp[22] ;
+   reg out;
+   wire \in[7] ;
+   reg \tmp[23] ;
+   wire \in[4] ;
+   wire \in[3] ;
+   wire \in[12] ;
+   reg \tmp[20] ;
+   wire \in[2] ;
+   reg \tmp[19] ;
+   wire \in[14] ;
+   wire \in[6] ;
+   wire \in[10] ;
+   wire \in[5] ;
+   wire \in[8] ;
+   wire \in[13] ;
+   wire \in[1] ;
+   reg \tmp[21] ;
+   reg \tmp[17] ;
+   reg \tmp[15] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0]  (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1]  (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2]  (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3]  (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4]  (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5]  (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6]  (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7]  (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0]  (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1]  (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2]  (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
+endmodule
+
+//
+// Verilog module for: OR2_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
+   output y;
+   input a;
+   input b;
+
+// -- signals ---
+   wire a;
+   wire b;
+   reg y;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: vtree<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
+   input \in.d[0].d[0] ;
+   input \in.d[0].d[1] ;
+   input \in.d[1].d[0] ;
+   input \in.d[1].d[1] ;
+   input \in.d[2].d[0] ;
+   input \in.d[2].d[1] ;
+   input \in.d[3].d[0] ;
+   input \in.d[3].d[1] ;
+   input \in.d[4].d[0] ;
+   input \in.d[4].d[1] ;
+   input \in.d[5].d[0] ;
+   input \in.d[5].d[1] ;
+   input \in.d[6].d[0] ;
+   input \in.d[6].d[1] ;
+   input \in.d[7].d[0] ;
+   input \in.d[7].d[1] ;
+   input \in.d[8].d[0] ;
+   input \in.d[8].d[1] ;
+   input \in.d[9].d[0] ;
+   input \in.d[9].d[1] ;
+   input \in.d[10].d[0] ;
+   input \in.d[10].d[1] ;
+   input \in.d[11].d[0] ;
+   input \in.d[11].d[1] ;
+   input \in.d[12].d[0] ;
+   input \in.d[12].d[1] ;
+   input \in.d[13].d[0] ;
+   input \in.d[13].d[1] ;
+   input \in.d[14].d[0] ;
+   input \in.d[14].d[1] ;
+   output out;
+
+// -- signals ---
+   wire \in.d[2].d[1] ;
+   wire \in.d[14].d[1] ;
+   reg \ct.in[8] ;
+   wire \in.d[10].d[1] ;
+   wire \in.d[7].d[1] ;
+   reg \ct.in[14] ;
+   wire \in.d[3].d[0] ;
+   reg \ct.in[0] ;
+   wire \in.d[8].d[1] ;
+   wire \in.d[6].d[1] ;
+   reg out;
+   wire \in.d[14].d[0] ;
+   wire \in.d[6].d[0] ;
+   wire \in.d[10].d[0] ;
+   wire \in.d[5].d[1] ;
+   wire \in.d[7].d[0] ;
+   wire \in.d[3].d[1] ;
+   wire \in.d[2].d[0] ;
+   reg \ct.in[6] ;
+   reg \ct.in[4] ;
+   wire \in.d[5].d[0] ;
+   wire \in.d[1].d[1] ;
+   wire \in.d[0].d[1] ;
+   reg \ct.in[5] ;
+   reg \ct.in[1] ;
+   wire \in.d[9].d[0] ;
+   wire \in.d[0].d[0] ;
+   wire \in.d[4].d[1] ;
+   reg \ct.in[12] ;
+   wire \in.d[12].d[1] ;
+   wire \in.d[8].d[0] ;
+   reg \ct.in[2] ;
+   wire \in.d[13].d[0] ;
+   wire \in.d[4].d[0] ;
+   wire \in.d[12].d[0] ;
+   wire \in.d[11].d[0] ;
+   wire \in.d[13].d[1] ;
+   reg \ct.in[9] ;
+   reg \ct.in[3] ;
+   reg \ct.in[11] ;
+   wire \in.d[1].d[0] ;
+   reg \ct.in[7] ;
+   wire \in.d[11].d[1] ;
+   wire \in.d[9].d[1] ;
+   reg \ct.in[10] ;
+   reg \ct.in[13] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct  (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0]  (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1]  (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2]  (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3]  (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4]  (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5]  (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6]  (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7]  (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8]  (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9]  (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10]  (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11]  (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12]  (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13]  (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14]  (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
+endmodule
+
+//
+// Verilog module for: A_1C1P_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
+   output y;
+   input c1;
+   input p1;
+
+// -- signals ---
+   wire c1;
+   wire p1;
+   reg y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: BUF_X1<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
+   output y;
+   input a;
+
+// -- signals ---
+   reg y;
+   wire a;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: A_2C1N_RB_X4<>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
+   output y;
+   input c1;
+   input c2;
+   input n1;
+   input pr_B;
+   input sr_B;
+
+// -- signals ---
+   reg y;
+   wire n1;
+   wire sr_B;
+   wire pr_B;
+   wire c2;
+   wire c1;
+   reg _y;
+
+// --- instances
+endmodule
+
+//
+// Verilog module for: buffer<15>
+//
+module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+   input reset_B;
+
+// -- signals ---
+   wire \in.d.d[9].d[0] ;
+   reg _out_a_B;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   wire \in.d.d[14].d[0] ;
+   wire \in.d.d[10].d[1] ;
+   reg \out.d.d[14].d[1] ;
+   wire \in.d.d[8].d[1] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[3].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[5].d[0] ;
+   wire \out.v ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[1].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[4].d[1] ;
+   reg _reset_BX;
+   reg \in.v ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   reg \out.d.d[5].d[0] ;
+   reg \out.d.d[10].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   reg \out.d.d[7].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[5].d[1] ;
+   reg _en;
+   reg \_out_a_BX_f[0] ;
+   reg \out.d.d[9].d[0] ;
+   wire \in.d.d[13].d[1] ;
+   reg \out.d.d[11].d[0] ;
+   wire \in.d.d[12].d[0] ;
+   wire \in.d.d[11].d[0] ;
+   wire \in.d.d[1].d[1] ;
+   wire \in.d.d[1].d[0] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[4].d[1] ;
+   reg _in_v;
+   reg \out.d.d[13].d[0] ;
+   reg \out.d.d[2].d[0] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[2].d[1] ;
+   reg \in.a ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[3].d[1] ;
+   reg \_out_a_BX_t[0] ;
+   wire \in.d.d[2].d[0] ;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[0].d[0] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \_en_X_t[0] ;
+   wire \in.d.d[10].d[0] ;
+   wire \out.a ;
+   reg \out.d.d[12].d[1] ;
+   wire reset_B;
+   wire \in.d.d[7].d[1] ;
+   wire \in.d.d[6].d[1] ;
+   wire \in.d.d[12].d[1] ;
+   wire \in.d.d[0].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   reg \_reset_BXX[0] ;
+   reg \out.d.d[4].d[0] ;
+   reg \out.d.d[13].d[1] ;
+   reg \_en_X_f[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t  (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl  (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray  (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf  (.y(\in.v ), .a(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv  (.y(_out_a_B), .a(\out.a ));
+_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc  (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f  (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl  (.y(_en), .c1(\in.a ), .p1(\out.v ));
+_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf  (.y(_reset_BX), .a(reset_B));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f  (.in(_en), .\out[0] (\_en_X_f[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t  (.in(_en), .\out[0] (\_en_X_t[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0]  (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1]  (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2]  (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3]  (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4]  (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5]  (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6]  (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7]  (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8]  (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9]  (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10]  (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11]  (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12]  (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13]  (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14]  (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0]  (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1]  (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2]  (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3]  (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4]  (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5]  (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6]  (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7]  (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8]  (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9]  (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10]  (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11]  (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12]  (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13]  (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14]  (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
+endmodule
+
+//
+// Verilog module for: buffer_15<>
+//
+module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
+   input \in.d.d[0].d[0] ;
+   input \in.d.d[0].d[1] ;
+   input \in.d.d[1].d[0] ;
+   input \in.d.d[1].d[1] ;
+   input \in.d.d[2].d[0] ;
+   input \in.d.d[2].d[1] ;
+   input \in.d.d[3].d[0] ;
+   input \in.d.d[3].d[1] ;
+   input \in.d.d[4].d[0] ;
+   input \in.d.d[4].d[1] ;
+   input \in.d.d[5].d[0] ;
+   input \in.d.d[5].d[1] ;
+   input \in.d.d[6].d[0] ;
+   input \in.d.d[6].d[1] ;
+   input \in.d.d[7].d[0] ;
+   input \in.d.d[7].d[1] ;
+   input \in.d.d[8].d[0] ;
+   input \in.d.d[8].d[1] ;
+   input \in.d.d[9].d[0] ;
+   input \in.d.d[9].d[1] ;
+   input \in.d.d[10].d[0] ;
+   input \in.d.d[10].d[1] ;
+   input \in.d.d[11].d[0] ;
+   input \in.d.d[11].d[1] ;
+   input \in.d.d[12].d[0] ;
+   input \in.d.d[12].d[1] ;
+   input \in.d.d[13].d[0] ;
+   input \in.d.d[13].d[1] ;
+   input \in.d.d[14].d[0] ;
+   input \in.d.d[14].d[1] ;
+   output \in.a ;
+   output \in.v ;
+   output \out.d.d[0].d[0] ;
+   output \out.d.d[0].d[1] ;
+   output \out.d.d[1].d[0] ;
+   output \out.d.d[1].d[1] ;
+   output \out.d.d[2].d[0] ;
+   output \out.d.d[2].d[1] ;
+   output \out.d.d[3].d[0] ;
+   output \out.d.d[3].d[1] ;
+   output \out.d.d[4].d[0] ;
+   output \out.d.d[4].d[1] ;
+   output \out.d.d[5].d[0] ;
+   output \out.d.d[5].d[1] ;
+   output \out.d.d[6].d[0] ;
+   output \out.d.d[6].d[1] ;
+   output \out.d.d[7].d[0] ;
+   output \out.d.d[7].d[1] ;
+   output \out.d.d[8].d[0] ;
+   output \out.d.d[8].d[1] ;
+   output \out.d.d[9].d[0] ;
+   output \out.d.d[9].d[1] ;
+   output \out.d.d[10].d[0] ;
+   output \out.d.d[10].d[1] ;
+   output \out.d.d[11].d[0] ;
+   output \out.d.d[11].d[1] ;
+   output \out.d.d[12].d[0] ;
+   output \out.d.d[12].d[1] ;
+   output \out.d.d[13].d[0] ;
+   output \out.d.d[13].d[1] ;
+   output \out.d.d[14].d[0] ;
+   output \out.d.d[14].d[1] ;
+   input \out.a ;
+   input \out.v ;
+
+// -- signals ---
+   reg \out.d.d[2].d[0] ;
+   reg \out.d.d[14].d[1] ;
+   reg \out.d.d[4].d[0] ;
+   reg \out.d.d[0].d[1] ;
+   wire \in.d.d[8].d[1] ;
+   wire \in.d.d[7].d[0] ;
+   wire \in.d.d[1].d[0] ;
+   reg _reset_B;
+   reg \out.d.d[6].d[1] ;
+   reg \out.d.d[5].d[0] ;
+   reg \out.d.d[11].d[1] ;
+   reg \out.d.d[6].d[0] ;
+   reg \out.d.d[12].d[0] ;
+   wire \in.d.d[2].d[1] ;
+   wire \in.d.d[14].d[1] ;
+   wire \in.d.d[13].d[0] ;
+   wire \in.d.d[5].d[0] ;
+   wire \in.d.d[4].d[0] ;
+   reg \out.d.d[5].d[1] ;
+   reg \out.d.d[3].d[0] ;
+   wire \in.d.d[10].d[0] ;
+   wire \in.d.d[3].d[1] ;
+   wire \in.d.d[11].d[0] ;
+   reg \out.d.d[0].d[0] ;
+   reg \out.d.d[2].d[1] ;
+   wire \in.d.d[9].d[0] ;
+   wire \in.d.d[2].d[0] ;
+   wire \in.d.d[6].d[0] ;
+   wire \in.d.d[4].d[1] ;
+   wire \in.d.d[1].d[1] ;
+   reg \out.d.d[13].d[1] ;
+   reg \out.d.d[1].d[1] ;
+   reg \out.d.d[10].d[1] ;
+   wire \in.d.d[11].d[1] ;
+   wire \in.d.d[5].d[1] ;
+   reg \out.d.d[9].d[1] ;
+   wire \in.d.d[3].d[0] ;
+   wire \in.d.d[0].d[1] ;
+   wire \out.v ;
+   wire \in.d.d[12].d[0] ;
+   reg \out.d.d[3].d[1] ;
+   reg \out.d.d[7].d[1] ;
+   reg \out.d.d[14].d[0] ;
+   reg \out.d.d[11].d[0] ;
+   reg \out.d.d[4].d[1] ;
+   wire \in.d.d[9].d[1] ;
+   wire \in.d.d[7].d[1] ;
+   wire \out.a ;
+   reg \in.a ;
+   wire \in.d.d[13].d[1] ;
+   wire \in.d.d[10].d[1] ;
+   reg \out.d.d[12].d[1] ;
+   reg \out.d.d[10].d[0] ;
+   reg \out.d.d[1].d[0] ;
+   wire \in.d.d[6].d[1] ;
+   reg \in.v ;
+   wire \in.d.d[14].d[0] ;
+   reg \out.d.d[13].d[0] ;
+   wire \in.d.d[12].d[1] ;
+   reg \out.d.d[8].d[1] ;
+   reg \out.d.d[8].d[0] ;
+   reg \out.d.d[7].d[0] ;
+   reg \out.d.d[9].d[0] ;
+   wire \in.d.d[8].d[0] ;
+   wire \in.d.d[0].d[0] ;
+
+// --- instances
+_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test  (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
+endmodule
+

test/unit_tests/decoder_2d_dly_8_16/test.act

@@ -0,0 +1,47 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc decoder_2d_dly_8_16(avMx1of2<3+4> in; bool? outx[8], outy[16], dly_cfg[4])
+
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+  decoder_2d_dly<3,4,8,16,4> b(.in = in, .outx = outx, .outy = outy, .dly_cfg = dly_cfg);
+  b.supply.vdd = Vdd;
+  b.supply.vss = GND; 
+  b.reset_B = _reset_B;
+}
+
+decoder_2d_dly_8_16 b;

test/unit_tests/decoder_2d_dly_8_16/test.prsim

@@ -0,0 +1,59 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 7
+set b.b.addr_buf.out.a 0
+set Reset 0
+
+# Set delay config lines
+set b.dly_cfg[0] 1
+set b.dly_cfg[1] 1
+set b.dly_cfg[2] 1
+set b.dly_cfg[3] 1
+
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+
+system "echo '[] Sending packet in'"
+set-qdi-channel-valid "b.in" 7 127
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+
+# system "echo '[]' Setting ack from DLY high"
+# set b.b.addr_buf.out.a 1
+cycle
+
+assert b.outx[0] 0
+assert b.outx[1] 0
+assert b.outx[2] 0
+assert b.outx[3] 0
+assert b.outx[4] 0
+assert b.outx[5] 0
+assert b.outx[6] 0
+assert b.outx[7] 0
+
+assert b.outy[0] 0
+assert b.outy[1] 0
+assert b.outy[2] 0
+assert b.outy[3] 0
+assert b.outy[4] 0
+assert b.outy[5] 0
+assert b.outy[6] 0
+assert b.outy[7] 0
+assert b.outy[8] 0
+assert b.outy[9] 0
+assert b.outy[10] 0
+assert b.outy[11] 0
+assert b.outy[12] 0
+assert b.outy[13] 0
+assert b.outy[14] 0
+assert b.outy[15] 0

test/unit_tests/decoder_2d_dly_and_2_4/test.act

@@ -0,0 +1,52 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc decoder_2d_dly_and_2_4(avMx1of2<1+2> in; bool? out[2*4], dly_cfg[4])
+
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+  decoder_2d_dly<1,2,2,4,4> de(.in = in, .dly_cfg = dly_cfg);
+  de.supply.vdd = Vdd;
+  de.supply.vss = GND; 
+  de.reset_B = _reset_B;
+
+  and_grid<2,4> ag(.inx = de.outx, .iny = de.outy, .out = out);
+  ag.supply.vdd = Vdd;
+  ag.supply.vss = GND;
+
+}
+
+decoder_2d_dly_and_2_4 t;

test/unit_tests/decoder_2d_dly_and_2_4/test.prsim

@@ -0,0 +1,57 @@
+watchall
+
+set-qdi-channel-neutral "t.in" 3
+set Reset 0
+
+# Set delay config lines
+set t.dly_cfg[0] 1
+set t.dly_cfg[1] 1
+set t.dly_cfg[2] 1
+set t.dly_cfg[3] 1
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+
+system "echo '[] Sending packet in'"
+set-qdi-channel-valid "t.in" 3 7
+cycle
+assert t.in.a 1
+assert t.in.v 1
+
+
+# system "echo '[]' Setting ack from DLY high"
+# set b.b.addr_buf.out.a 1
+# cycle
+
+# assert b.outx[0] 0
+# assert b.outx[1] 0
+# assert b.outx[2] 0
+# assert b.outx[3] 0
+# assert b.outx[4] 0
+# assert b.outx[5] 0
+# assert b.outx[6] 0
+# assert b.outx[7] 0
+
+# assert b.outy[0] 0
+# assert b.outy[1] 0
+# assert b.outy[2] 0
+# assert b.outy[3] 0
+# assert b.outy[4] 0
+# assert b.outy[5] 0
+# assert b.outy[6] 0
+# assert b.outy[7] 0
+# assert b.outy[8] 0
+# assert b.outy[9] 0
+# assert b.outy[10] 0
+# assert b.outy[11] 0
+# assert b.outy[12] 0
+# assert b.outy[13] 0
+# assert b.outy[14] 0
+# assert b.outy[15] 0

test/unit_tests/decoder_2d_hs/test.act

@@ -0,0 +1,73 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc decoder_2d_hs_2x4 (avMx1of2<3> in; a1of1 out[8]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    decoder_2d_hs<1,2,2,4> decoder(.in = in, .out = out,
+        .reset_B = _reset_B, .supply = supply);
+
+    // model the synapse as having automatic pulldown of ack.
+    INV_X1 synapses[8];
+    PULLDOWN_X4 synapses2[8];
+    (i:8:
+        synapses[i].a = decoder.out[i].r;
+        synapses2[i].a = synapses[i].y; 
+        synapses2[i].y = decoder.out[i].a;
+
+        synapses[i].vss = supply.vss;
+        synapses[i].vdd = supply.vdd;
+        synapses2[i].vss = supply.vss;
+        synapses2[i].vdd = supply.vdd;
+
+    )
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+decoder_2d_hs_2x4 e; 

test/unit_tests/decoder_2d_hs/test.prsim

@@ -0,0 +1,153 @@
+watchall
+
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+
+set-qdi-channel-neutral "e.in" 3
+set Reset 1
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+system "echo '[] Sending in a 7 packet'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+

test/unit_tests/decoder_2d_hybrid/test.act

@@ -0,0 +1,104 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en, ack_disable){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .dly_cfg = dly_cfg, .hs_en = hs_en, .ack_disable = ack_disable,
+        .reset_B = _reset_B, .supply = supply);
+
+    // Dummy synapses to perform the handshaking.
+    // They consist of a grid of ANDs and pulldowns, and have the "synapses" exposed,\
+    // which would be the pulse extenders (which we thus short here)
+
+
+    decoder_2d_synapse_hs<2,4> syn_hs(.in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
+        .out_ackB_decoder = decoder.in_ackB_decoder,
+        .to_pu = decoder.to_pu,
+        .synapses = out,
+        .supply = supply);
+
+
+
+    // (i:8: syn_hs.synapses[i].a = syn_hs.synapses[i].r;)
+
+    // // model the synapse as having automatic pulldown of ack.
+    // INV_X1 synapses[8];
+    // AND2_X1 req_and2s[8];
+
+    // pint index;
+
+    // PULLDOWN_X4 synapses2[8];
+    // (i:4:
+    //     (j:2:
+    //         index = i + 4*j;
+
+    //         req_and2s[index].a = decoder.out_req_x[index];
+    //         req_and2s[index].b = decoder.out_req_y[index];
+
+    //         // synapses[index].a = decoder.out[index].r;
+    //         synapses[index].a = req_and2s[index].y;
+    //         synapses2[index].a = synapses[index].y; 
+    //         synapses2[index].y = decoder.out[index].a;
+
+    //         synapses[index].vss = supply.vss;
+    //         synapses[index].vdd = supply.vdd;
+    //         synapses2[index].vss = supply.vss;
+    //         synapses2[index].vdd = supply.vdd;            
+    //         req_and2s[index].vss = supply.vss;
+    //         req_and2s[index].vdd = supply.vdd;
+
+    //     )
+        
+    // )
+
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+decoder_2d_hybrid_2x4 e; 

test/unit_tests/decoder_2d_hybrid/test.prsim

@@ -0,0 +1,342 @@
+watchall
+
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+cycle
+set e.dly_cfg[0] 0
+set e.dly_cfg[1] 0
+set e.dly_cfg[2] 0
+set e.dly_cfg[3] 0
+
+set e.hs_en 1
+
+set e.ack_disable 0
+
+set-qdi-channel-neutral "e.in" 3
+set Reset 1
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+system "echo '[] Sending in a 7 packet'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+cycle
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+cycle
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [1] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input, enabling delays'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+system "echo '[] Enabling delays'"
+cycle
+set e.dly_cfg[0] 1
+set e.dly_cfg[1] 1
+set e.dly_cfg[2] 1
+set e.dly_cfg[3] 1
+
+system "echo '[] Sending in a 7 packet, with delays'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+cycle
+
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+cycle
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [1] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input, disabling handshaking'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+set e.hs_en 0
+cycle
+
+system "echo '[] Sending in a 0, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 0
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in a 7, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+system "echo '[] Sending in a 5, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+

test/unit_tests/delayprog_4/run/prsim.out

@@ -1,134 +0,0 @@
-t.s[2] t.dp.dly[2].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.a t.s[0] t.dp.and2[2]._y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[11].y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[9].a t.dp.dly[1].y t.dp.dly[1].a t.dp.dly[4].a t.y t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[10].a t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[8].a t.dp.dly[0].a t.dp.dly[7].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.mu2[1]._s t.dp.dly[11].a t.dp.dly[14].a t.dp.dly[13].a t.dp.dly[13]._y t.dp.dly[7].y t.dp.dly[8]._y t.dp.mu2[2]._y t.dp.dly[3].y t.dp.dly[14].y t.dp.dly[0].y t.dp.dly[3]._y t.dp.dly[13].y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[10].y t.dp.dly[9].y t.dp.dly[4]._y t.dp.dly[12].y t.dp.dly[8].y t.dp.mu2[1]._y t.dp.dly[12].a t.dp.dly[10]._y 
-0
-	         0 t.a : 0
-	         0 t.s[3] : 1
-	         0 t.s[1] : 1
-	         0 t.s[0] : 1
-	         0 t.s[2] : 1
-	         1 t.dp.and2[0]._y : 1  [by t.a:=0]
-	         2 t.dp.mu2[0]._s : 0  [by t.s[0]:=1]
-	      1138 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
-	      1252 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
-	      4753 t.dp.mu2[2]._s : 0  [by t.s[2]:=1]
-	      7092 t.dp.mu2[3]._s : 0  [by t.s[3]:=1]
-	     10467 t.dp.mu2[1]._s : 0  [by t.s[1]:=1]
-	     66618 t.dp.dly[0].y : 0  [by t.dp.dly[0]._y:=1]
-	     68344 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
-	     68383 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	     68398 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
-	     68889 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
-	     68902 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
-	     68942 t.dp.dly[1].y : 0  [by t.dp.dly[1]._y:=1]
-	     69357 t.dp.mu2[1]._y : 1  [by t.dp.dly[1].y:=0]
-	     69377 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	     75438 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
-	     75485 t.dp.dly[2].a : 0  [by t.dp.and2[2]._y:=1]
-	     75501 t.dp.dly[2]._y : 1  [by t.dp.dly[2].a:=0]
-	    119599 t.dp.dly[2].y : 0  [by t.dp.dly[2]._y:=1]
-	    133323 t.dp.dly[3]._y : 1  [by t.dp.dly[2].y:=0]
-	    133327 t.dp.dly[3].y : 0  [by t.dp.dly[3]._y:=1]
-	    142456 t.dp.mu2[2]._y : 1  [by t.dp.dly[3].y:=0]
-	    142471 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    185719 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
-	    222650 t.dp.dly[4].a : 0  [by t.dp.and2[3]._y:=1]
-	    222705 t.dp.dly[4]._y : 1  [by t.dp.dly[4].a:=0]
-	    274358 t.dp.dly[4].y : 0  [by t.dp.dly[4]._y:=1]
-	    304138 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
-	    317987 t.dp.dly[5].y : 0  [by t.dp.dly[5]._y:=1]
-	    342799 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
-	    357142 t.dp.dly[6].y : 0  [by t.dp.dly[6]._y:=1]
-	    357564 t.dp.mu2[3]._y : 1  [by t.dp.dly[6].y:=0]
-	    406278 t.y : 0  [by t.dp.mu2[3]._y:=1]
-[] setting high
-	    406278 t.a : 1
-	    406279 t.dp.and2[0]._y : 0  [by t.a:=1]
-	    406280 t.dp.dly[0].a : 1  [by t.dp.and2[0]._y:=0]
-	    426485 t.dp.dly[0]._y : 0  [by t.dp.dly[0].a:=1]
-	    426767 t.dp.dly[0].y : 1  [by t.dp.dly[0]._y:=0]
-	    427535 t.dp.mu2[0]._y : 0  [by t.dp.dly[0].y:=1]
-	    427538 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
-	    449979 t.dp.and2[1]._y : 0  [by t.dp._a[1]:=1]
-	    450530 t.dp.dly[1].a : 1  [by t.dp.and2[1]._y:=0]
-	    451601 t.dp.dly[1]._y : 0  [by t.dp.dly[1].a:=1]
-	    452555 t.dp.dly[1].y : 1  [by t.dp.dly[1]._y:=0]
-	    453636 t.dp.mu2[1]._y : 0  [by t.dp.dly[1].y:=1]
-	    508106 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
-	    509088 t.dp.and2[2]._y : 0  [by t.dp._a[2]:=1]
-	    509106 t.dp.dly[2].a : 1  [by t.dp.and2[2]._y:=0]
-	    513119 t.dp.dly[2]._y : 0  [by t.dp.dly[2].a:=1]
-	    517122 t.dp.dly[2].y : 1  [by t.dp.dly[2]._y:=0]
-	    562023 t.dp.dly[3]._y : 0  [by t.dp.dly[2].y:=1]
-	    583607 t.dp.dly[3].y : 1  [by t.dp.dly[3]._y:=0]
-	    588367 t.dp.mu2[2]._y : 0  [by t.dp.dly[3].y:=1]
-	    588869 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
-	    589072 t.dp.and2[3]._y : 0  [by t.dp._a[3]:=1]
-	    590926 t.dp.dly[4].a : 1  [by t.dp.and2[3]._y:=0]
-	    591065 t.dp.dly[4]._y : 0  [by t.dp.dly[4].a:=1]
-	    627411 t.dp.dly[4].y : 1  [by t.dp.dly[4]._y:=0]
-	    627480 t.dp.dly[5]._y : 0  [by t.dp.dly[4].y:=1]
-	    627491 t.dp.dly[5].y : 1  [by t.dp.dly[5]._y:=0]
-	    679277 t.dp.dly[6]._y : 0  [by t.dp.dly[5].y:=1]
-	    679481 t.dp.dly[6].y : 1  [by t.dp.dly[6]._y:=0]
-	    679496 t.dp.mu2[3]._y : 0  [by t.dp.dly[6].y:=1]
-	    679497 t.y : 1  [by t.dp.mu2[3]._y:=0]
-[] setting low
-	    679497 t.a : 0
-	    679534 t.dp.and2[0]._y : 1  [by t.a:=0]
-	    680273 t.dp.dly[0].a : 0  [by t.dp.and2[0]._y:=1]
-	    680385 t.dp.dly[0]._y : 1  [by t.dp.dly[0].a:=0]
-	    727897 t.dp.dly[0].y : 0  [by t.dp.dly[0]._y:=1]
-	    727937 t.dp.mu2[0]._y : 1  [by t.dp.dly[0].y:=0]
-	    728194 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	    728281 t.dp.and2[1]._y : 1  [by t.dp._a[1]:=0]
-	    728575 t.dp.dly[1].a : 0  [by t.dp.and2[1]._y:=1]
-	    728576 t.dp.dly[1]._y : 1  [by t.dp.dly[1].a:=0]
-	    730382 t.dp.dly[1].y : 0  [by t.dp.dly[1]._y:=1]
-	    732389 t.dp.mu2[1]._y : 1  [by t.dp.dly[1].y:=0]
-	    733598 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	    734188 t.dp.and2[2]._y : 1  [by t.dp._a[2]:=0]
-	    734366 t.dp.dly[2].a : 0  [by t.dp.and2[2]._y:=1]
-	    735169 t.dp.dly[2]._y : 1  [by t.dp.dly[2].a:=0]
-	    735333 t.dp.dly[2].y : 0  [by t.dp.dly[2]._y:=1]
-	    737528 t.dp.dly[3]._y : 1  [by t.dp.dly[2].y:=0]
-	    737550 t.dp.dly[3].y : 0  [by t.dp.dly[3]._y:=1]
-	    738397 t.dp.mu2[2]._y : 1  [by t.dp.dly[3].y:=0]
-	    768525 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    768658 t.dp.and2[3]._y : 1  [by t.dp._a[3]:=0]
-	    784320 t.dp.dly[4].a : 0  [by t.dp.and2[3]._y:=1]
-	    784679 t.dp.dly[4]._y : 1  [by t.dp.dly[4].a:=0]
-	    798795 t.dp.dly[4].y : 0  [by t.dp.dly[4]._y:=1]
-	    799016 t.dp.dly[5]._y : 1  [by t.dp.dly[4].y:=0]
-	    799023 t.dp.dly[5].y : 0  [by t.dp.dly[5]._y:=1]
-	    799053 t.dp.dly[6]._y : 1  [by t.dp.dly[5].y:=0]
-	    805766 t.dp.dly[6].y : 0  [by t.dp.dly[6]._y:=1]
-	    863227 t.dp.mu2[3]._y : 1  [by t.dp.dly[6].y:=0]
-	    863318 t.y : 0  [by t.dp.mu2[3]._y:=1]
-[] setting configs low
-	    863318 t.s[0] : 0
-	    863318 t.s[3] : 0
-	    863318 t.s[2] : 0
-	    863318 t.s[1] : 0
-	    863325 t.dp.mu2[3]._s : 1  [by t.s[3]:=0]
-	    863424 t.dp.mu2[1]._s : 1  [by t.s[1]:=0]
-	    865507 t.dp.mu2[0]._s : 1  [by t.s[0]:=0]
-	    866105 t.dp.mu2[2]._s : 1  [by t.s[2]:=0]
-[] setting high
-	    866105 t.a : 1
-	    866183 t.dp.mu2[0]._y : 0  [by t.a:=1]
-	    866458 t.dp._a[1] : 1  [by t.dp.mu2[0]._y:=0]
-	    885454 t.dp.mu2[1]._y : 0  [by t.dp._a[1]:=1]
-	    885909 t.dp._a[2] : 1  [by t.dp.mu2[1]._y:=0]
-	    885921 t.dp.mu2[2]._y : 0  [by t.dp._a[2]:=1]
-	    886325 t.dp._a[3] : 1  [by t.dp.mu2[2]._y:=0]
-	    886337 t.dp.mu2[3]._y : 0  [by t.dp._a[3]:=1]
-	    892253 t.y : 1  [by t.dp.mu2[3]._y:=0]
-[] setting low
-	    892253 t.a : 0
-	    896529 t.dp.mu2[0]._y : 1  [by t.a:=0]
-	    899428 t.dp._a[1] : 0  [by t.dp.mu2[0]._y:=1]
-	    903723 t.dp.mu2[1]._y : 1  [by t.dp._a[1]:=0]
-	    903725 t.dp._a[2] : 0  [by t.dp.mu2[1]._y:=1]
-	    908260 t.dp.mu2[2]._y : 1  [by t.dp._a[2]:=0]
-	    909509 t.dp._a[3] : 0  [by t.dp.mu2[2]._y:=1]
-	    913008 t.dp.mu2[3]._y : 1  [by t.dp._a[3]:=0]
-	    913174 t.y : 0  [by t.dp.mu2[3]._y:=1]

test/unit_tests/delayprog_4/run/test.prs

@@ -1,190 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-= "t.y" "t.dp.y"
-= "t.a" "t.dp.a"
-= "t.dp.a" "t.dp.mu2[0].a"
-= "t.dp.a" "t.dp.and2[0].a"
-= "t.dp.a" "t.dp._a[0]"
-"t.dp.and2[0].a"&"t.dp.and2[0].b"->"t.dp.and2[0]._y"-
-~("t.dp.and2[0].a"&"t.dp.and2[0].b")->"t.dp.and2[0]._y"+
-"t.dp.and2[0]._y"->"t.dp.and2[0].y"-
-~("t.dp.and2[0]._y")->"t.dp.and2[0].y"+
-"t.dp.and2[1].a"&"t.dp.and2[1].b"->"t.dp.and2[1]._y"-
-~("t.dp.and2[1].a"&"t.dp.and2[1].b")->"t.dp.and2[1]._y"+
-"t.dp.and2[1]._y"->"t.dp.and2[1].y"-
-~("t.dp.and2[1]._y")->"t.dp.and2[1].y"+
-"t.dp.and2[2].a"&"t.dp.and2[2].b"->"t.dp.and2[2]._y"-
-~("t.dp.and2[2].a"&"t.dp.and2[2].b")->"t.dp.and2[2]._y"+
-"t.dp.and2[2]._y"->"t.dp.and2[2].y"-
-~("t.dp.and2[2]._y")->"t.dp.and2[2].y"+
-"t.dp.and2[3].a"&"t.dp.and2[3].b"->"t.dp.and2[3]._y"-
-~("t.dp.and2[3].a"&"t.dp.and2[3].b")->"t.dp.and2[3]._y"+
-"t.dp.and2[3]._y"->"t.dp.and2[3].y"-
-~("t.dp.and2[3]._y")->"t.dp.and2[3].y"+
-= "t.dp.s[0]" "t.dp.mu2[0].s"
-= "t.dp.s[0]" "t.dp.and2[0].b"
-= "t.dp.s[1]" "t.dp.mu2[1].s"
-= "t.dp.s[1]" "t.dp.and2[1].b"
-= "t.dp.s[2]" "t.dp.mu2[2].s"
-= "t.dp.s[2]" "t.dp.and2[2].b"
-= "t.dp.s[3]" "t.dp.mu2[3].s"
-= "t.dp.s[3]" "t.dp.and2[3].b"
-= "t.dp.supply.vdd" "t.dp.dly[14].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[13].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[12].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[11].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[10].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[9].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[8].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[7].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[6].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[5].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[4].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[3].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[2].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[1].vdd"
-= "t.dp.supply.vdd" "t.dp.dly[0].vdd"
-= "t.dp.supply.vdd" "t.dp.mu2[3].vdd"
-= "t.dp.supply.vdd" "t.dp.mu2[2].vdd"
-= "t.dp.supply.vdd" "t.dp.mu2[1].vdd"
-= "t.dp.supply.vdd" "t.dp.mu2[0].vdd"
-= "t.dp.supply.vdd" "t.dp.and2[3].vdd"
-= "t.dp.supply.vdd" "t.dp.and2[2].vdd"
-= "t.dp.supply.vdd" "t.dp.and2[1].vdd"
-= "t.dp.supply.vdd" "t.dp.and2[0].vdd"
-= "t.dp.supply.vss" "t.dp.dly[14].vss"
-= "t.dp.supply.vss" "t.dp.dly[13].vss"
-= "t.dp.supply.vss" "t.dp.dly[12].vss"
-= "t.dp.supply.vss" "t.dp.dly[11].vss"
-= "t.dp.supply.vss" "t.dp.dly[10].vss"
-= "t.dp.supply.vss" "t.dp.dly[9].vss"
-= "t.dp.supply.vss" "t.dp.dly[8].vss"
-= "t.dp.supply.vss" "t.dp.dly[7].vss"
-= "t.dp.supply.vss" "t.dp.dly[6].vss"
-= "t.dp.supply.vss" "t.dp.dly[5].vss"
-= "t.dp.supply.vss" "t.dp.dly[4].vss"
-= "t.dp.supply.vss" "t.dp.dly[3].vss"
-= "t.dp.supply.vss" "t.dp.dly[2].vss"
-= "t.dp.supply.vss" "t.dp.dly[1].vss"
-= "t.dp.supply.vss" "t.dp.dly[0].vss"
-= "t.dp.supply.vss" "t.dp.mu2[3].vss"
-= "t.dp.supply.vss" "t.dp.mu2[2].vss"
-= "t.dp.supply.vss" "t.dp.mu2[1].vss"
-= "t.dp.supply.vss" "t.dp.mu2[0].vss"
-= "t.dp.supply.vss" "t.dp.and2[3].vss"
-= "t.dp.supply.vss" "t.dp.and2[2].vss"
-= "t.dp.supply.vss" "t.dp.and2[1].vss"
-= "t.dp.supply.vss" "t.dp.and2[0].vss"
-"t.dp.mu2[0].s"->"t.dp.mu2[0]._s"-
-~("t.dp.mu2[0].s")->"t.dp.mu2[0]._s"+
-~"t.dp.mu2[0].a"&~"t.dp.mu2[0].s"|~"t.dp.mu2[0].b"&~"t.dp.mu2[0]._s"->"t.dp.mu2[0]._y"+
-"t.dp.mu2[0].a"&"t.dp.mu2[0]._s"|"t.dp.mu2[0].b"&"t.dp.mu2[0].s"->"t.dp.mu2[0]._y"-
-"t.dp.mu2[0]._y"->"t.dp.mu2[0].y"-
-~("t.dp.mu2[0]._y")->"t.dp.mu2[0].y"+
-"t.dp.mu2[1].s"->"t.dp.mu2[1]._s"-
-~("t.dp.mu2[1].s")->"t.dp.mu2[1]._s"+
-~"t.dp.mu2[1].a"&~"t.dp.mu2[1].s"|~"t.dp.mu2[1].b"&~"t.dp.mu2[1]._s"->"t.dp.mu2[1]._y"+
-"t.dp.mu2[1].a"&"t.dp.mu2[1]._s"|"t.dp.mu2[1].b"&"t.dp.mu2[1].s"->"t.dp.mu2[1]._y"-
-"t.dp.mu2[1]._y"->"t.dp.mu2[1].y"-
-~("t.dp.mu2[1]._y")->"t.dp.mu2[1].y"+
-"t.dp.mu2[2].s"->"t.dp.mu2[2]._s"-
-~("t.dp.mu2[2].s")->"t.dp.mu2[2]._s"+
-~"t.dp.mu2[2].a"&~"t.dp.mu2[2].s"|~"t.dp.mu2[2].b"&~"t.dp.mu2[2]._s"->"t.dp.mu2[2]._y"+
-"t.dp.mu2[2].a"&"t.dp.mu2[2]._s"|"t.dp.mu2[2].b"&"t.dp.mu2[2].s"->"t.dp.mu2[2]._y"-
-"t.dp.mu2[2]._y"->"t.dp.mu2[2].y"-
-~("t.dp.mu2[2]._y")->"t.dp.mu2[2].y"+
-"t.dp.mu2[3].s"->"t.dp.mu2[3]._s"-
-~("t.dp.mu2[3].s")->"t.dp.mu2[3]._s"+
-~"t.dp.mu2[3].a"&~"t.dp.mu2[3].s"|~"t.dp.mu2[3].b"&~"t.dp.mu2[3]._s"->"t.dp.mu2[3]._y"+
-"t.dp.mu2[3].a"&"t.dp.mu2[3]._s"|"t.dp.mu2[3].b"&"t.dp.mu2[3].s"->"t.dp.mu2[3]._y"-
-"t.dp.mu2[3]._y"->"t.dp.mu2[3].y"-
-~("t.dp.mu2[3]._y")->"t.dp.mu2[3].y"+
-"t.dp.dly[0].a"->"t.dp.dly[0]._y"-
-~("t.dp.dly[0].a")->"t.dp.dly[0]._y"+
-"t.dp.dly[0]._y"->"t.dp.dly[0].y"-
-~("t.dp.dly[0]._y")->"t.dp.dly[0].y"+
-"t.dp.dly[1].a"->"t.dp.dly[1]._y"-
-~("t.dp.dly[1].a")->"t.dp.dly[1]._y"+
-"t.dp.dly[1]._y"->"t.dp.dly[1].y"-
-~("t.dp.dly[1]._y")->"t.dp.dly[1].y"+
-"t.dp.dly[2].a"->"t.dp.dly[2]._y"-
-~("t.dp.dly[2].a")->"t.dp.dly[2]._y"+
-"t.dp.dly[2]._y"->"t.dp.dly[2].y"-
-~("t.dp.dly[2]._y")->"t.dp.dly[2].y"+
-"t.dp.dly[3].a"->"t.dp.dly[3]._y"-
-~("t.dp.dly[3].a")->"t.dp.dly[3]._y"+
-"t.dp.dly[3]._y"->"t.dp.dly[3].y"-
-~("t.dp.dly[3]._y")->"t.dp.dly[3].y"+
-"t.dp.dly[4].a"->"t.dp.dly[4]._y"-
-~("t.dp.dly[4].a")->"t.dp.dly[4]._y"+
-"t.dp.dly[4]._y"->"t.dp.dly[4].y"-
-~("t.dp.dly[4]._y")->"t.dp.dly[4].y"+
-"t.dp.dly[5].a"->"t.dp.dly[5]._y"-
-~("t.dp.dly[5].a")->"t.dp.dly[5]._y"+
-"t.dp.dly[5]._y"->"t.dp.dly[5].y"-
-~("t.dp.dly[5]._y")->"t.dp.dly[5].y"+
-"t.dp.dly[6].a"->"t.dp.dly[6]._y"-
-~("t.dp.dly[6].a")->"t.dp.dly[6]._y"+
-"t.dp.dly[6]._y"->"t.dp.dly[6].y"-
-~("t.dp.dly[6]._y")->"t.dp.dly[6].y"+
-"t.dp.dly[7].a"->"t.dp.dly[7]._y"-
-~("t.dp.dly[7].a")->"t.dp.dly[7]._y"+
-"t.dp.dly[7]._y"->"t.dp.dly[7].y"-
-~("t.dp.dly[7]._y")->"t.dp.dly[7].y"+
-"t.dp.dly[8].a"->"t.dp.dly[8]._y"-
-~("t.dp.dly[8].a")->"t.dp.dly[8]._y"+
-"t.dp.dly[8]._y"->"t.dp.dly[8].y"-
-~("t.dp.dly[8]._y")->"t.dp.dly[8].y"+
-"t.dp.dly[9].a"->"t.dp.dly[9]._y"-
-~("t.dp.dly[9].a")->"t.dp.dly[9]._y"+
-"t.dp.dly[9]._y"->"t.dp.dly[9].y"-
-~("t.dp.dly[9]._y")->"t.dp.dly[9].y"+
-"t.dp.dly[10].a"->"t.dp.dly[10]._y"-
-~("t.dp.dly[10].a")->"t.dp.dly[10]._y"+
-"t.dp.dly[10]._y"->"t.dp.dly[10].y"-
-~("t.dp.dly[10]._y")->"t.dp.dly[10].y"+
-"t.dp.dly[11].a"->"t.dp.dly[11]._y"-
-~("t.dp.dly[11].a")->"t.dp.dly[11]._y"+
-"t.dp.dly[11]._y"->"t.dp.dly[11].y"-
-~("t.dp.dly[11]._y")->"t.dp.dly[11].y"+
-"t.dp.dly[12].a"->"t.dp.dly[12]._y"-
-~("t.dp.dly[12].a")->"t.dp.dly[12]._y"+
-"t.dp.dly[12]._y"->"t.dp.dly[12].y"-
-~("t.dp.dly[12]._y")->"t.dp.dly[12].y"+
-"t.dp.dly[13].a"->"t.dp.dly[13]._y"-
-~("t.dp.dly[13].a")->"t.dp.dly[13]._y"+
-"t.dp.dly[13]._y"->"t.dp.dly[13].y"-
-~("t.dp.dly[13]._y")->"t.dp.dly[13].y"+
-"t.dp.dly[14].a"->"t.dp.dly[14]._y"-
-~("t.dp.dly[14].a")->"t.dp.dly[14]._y"+
-"t.dp.dly[14]._y"->"t.dp.dly[14].y"-
-~("t.dp.dly[14]._y")->"t.dp.dly[14].y"+
-= "t.dp.dly[6].y" "t.dp.mu2[3].b"
-= "t.dp.dly[6].a" "t.dp.dly[5].y"
-= "t.dp.dly[5].a" "t.dp.dly[4].y"
-= "t.dp.dly[4].a" "t.dp.and2[3].y"
-= "t.dp.dly[3].y" "t.dp.mu2[2].b"
-= "t.dp.dly[3].a" "t.dp.dly[2].y"
-= "t.dp.dly[2].a" "t.dp.and2[2].y"
-= "t.dp.dly[1].y" "t.dp.mu2[1].b"
-= "t.dp.dly[1].a" "t.dp.and2[1].y"
-= "t.dp.dly[0].y" "t.dp.mu2[0].b"
-= "t.dp.dly[0].a" "t.dp.and2[0].y"
-= "t.dp._a[1]" "t.dp.mu2[1].a"
-= "t.dp._a[1]" "t.dp.and2[1].a"
-= "t.dp._a[1]" "t.dp.mu2[0].y"
-= "t.dp._a[2]" "t.dp.mu2[2].a"
-= "t.dp._a[2]" "t.dp.and2[2].a"
-= "t.dp._a[2]" "t.dp.mu2[1].y"
-= "t.dp._a[3]" "t.dp.mu2[3].a"
-= "t.dp._a[3]" "t.dp.and2[3].a"
-= "t.dp._a[3]" "t.dp.mu2[2].y"
-= "t.dp.y" "t.dp.mu2[3].y"
-= "t.dp.y" "t.dp._a[4]"
-= "Vdd" "t.dp.supply.vdd"
-= "GND" "t.dp.supply.vss"
-= "t.s[0]" "t.dp.s[0]"
-= "t.s[1]" "t.dp.s[1]"
-= "t.s[2]" "t.dp.s[2]"
-= "t.s[3]" "t.dp.s[3]"

test/unit_tests/delayprog_4/test.act

@@ -31,8 +31,8 @@ import globals;
 
 open tmpl::dataflow_neuro;
 
-defproc delayprog_4 (bool? s[4], a; bool! y){
-    delayprog<4> dp(.a=a, .y=y, .s = s);
+defproc delayprog_4 (bool? s[4], in; bool! out){
+    delayprog<4> dp(.in=in, .out=out, .s = s);
     dp.supply.vss = GND;
     dp.supply.vdd = Vdd;
 

test/unit_tests/delayprog_4/test.prsim

@@ -2,7 +2,7 @@ watchall
 
 system "echo '0'"
 
-set t.a  0
+set t.in  0
 set t.s[0] 1
 set t.s[1] 1
 set t.s[2] 1
@@ -11,17 +11,17 @@ set t.s[3] 1
 cycle
 mode run
 
-assert t.y 0
+# assert t.out 0
 
 system "echo '[] setting high'"
-set t.a  1
+set t.in  1
 cycle
-assert t.y 1
+assert t.out 1
 
 system "echo '[] setting low'"
-set t.a  0
+set t.in  0
 cycle
-assert t.y 0
+assert t.out 0
 
 system "echo '[] setting configs low'"
 set t.s[0] 0
@@ -29,14 +29,14 @@ set t.s[1] 0
 set t.s[2] 0
 set t.s[3] 0
 cycle
-assert t.y 0
+assert t.out 0
 
 system "echo '[] setting high'"
-set t.a  1
+set t.in  1
 cycle
-assert t.y 1
+assert t.out 1
 
 system "echo '[] setting low'"
-set t.a  0
+set t.in  0
 cycle
-assert t.y 0
+assert t.out 0

test/unit_tests/demux_7/run/prsim.out

@@ -1,330 +0,0 @@
-my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.tmp[9] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux.vc.tmp[7] my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.C2Els[1]._y my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.tmp[6] my_demux.my_demux.vc.tmp[1] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.C2Els[0]._y my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux.vc.tmp[8] my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_c_v_ my_demux.out2.v my_demux.my_demux._in_v my_demux.my_demux.vc.tmp[4] my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.tmp[0] my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.my_demux.vc.tmp[5] my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux._out_v my_demux.my_demux.vc.C3Els[0]._y my_demux.in.v my_demux.my_demux.vc.C3Els[1]._y my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.tmp[3] my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.vc.tmp[2] my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y 
-	    119199 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
-	    119199 my_demux.my_demux.c_buf_f.in : 0
-	    119199 my_demux.my_demux.c_buf_t.in : 0
-	    119199 my_demux.my_demux.out1_f_buf_func[1].n1 : 0
-	    119199 my_demux.my_demux.out1_f_buf_func[3].n1 : 0
-	    119199 my_demux.out1.a : 0
-	    119199 my_demux.out2.v : 0
-	    119199 my_demux.my_demux.out1_t_buf_func[6].n1 : 0
-	    119199 my_demux.out2.a : 0
-	    119199 my_demux.out1.v : 0
-	    119199 my_demux.my_demux.out1_t_buf_func[2].n1 : 0
-	    119199 my_demux.my_demux.out1_f_buf_func[6].n1 : 0
-	    119199 my_demux.my_demux.out1_t_buf_func[5].n1 : 0
-	    119199 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	    119199 my_demux.my_demux.out1_f_buf_func[2].n1 : 0
-	    119199 my_demux.my_demux.out1_f_buf_func[5].n1 : 0
-	    119199 my_demux.my_demux.out1_t_buf_func[4].n1 : 0
-	    119199 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	    119199 my_demux.my_demux.out1_f_buf_func[4].n1 : 0
-	    119199 my_demux.my_demux.out1_t_buf_func[3].n1 : 0
-	    119200 my_demux.my_demux.c_buf_f.buf2._y : 1  [by my_demux.my_demux.c_buf_f.in:=0]
-	    119200 my_demux.my_demux.vc.OR2_tf[5]._y : 1  [by my_demux.my_demux.out1_f_buf_func[5].n1:=0]
-	    119236 my_demux.my_demux.c_buf_t.buf2._y : 1  [by my_demux.my_demux.c_buf_t.in:=0]
-	    119239 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
-	    119286 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    119311 my_demux.my_demux._out1_a_B : 1  [by my_demux.out1.a:=0]
-	    119333 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    119378 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
-	    119403 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    119456 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_f_buf_func[6].n1:=0]
-	    119493 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_f_buf_func[2].n1:=0]
-	    119536 my_demux.my_demux._en : 1  [by my_demux.my_demux._out_v:=0]
-	    119543 my_demux.my_demux.out2_en_buf_t.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    119566 my_demux.my_demux.out1_en_buf_f.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    119757 my_demux.my_demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    119790 my_demux.my_demux._c_f_buf[0] : 0  [by my_demux.my_demux.c_buf_f.buf2._y:=1]
-	    119848 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf2._y:=0]
-	    119852 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
-	    119938 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.c_buf_t.in:=0]
-	    120039 my_demux.my_demux._c_t_buf[0] : 0  [by my_demux.my_demux.c_buf_t.buf2._y:=1]
-	    120158 my_demux.my_demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    120165 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
-	    120408 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
-	    121005 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    121111 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    121206 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
-	    121284 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
-	    121481 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    121756 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[0]:=0]
-	    122127 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    123195 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
-	    123650 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[3]:=0]
-	    123662 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
-	    126256 my_demux.my_demux._en2_X_t[0] : 1  [by my_demux.my_demux.out2_en_buf_t.buf2._y:=0]
-	    133652 my_demux.my_demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    134056 my_demux.my_demux._en2_X_f[0] : 1  [by my_demux.my_demux.out2_en_buf_f.buf2._y:=0]
-	    135118 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    135130 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
-	    140752 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    141046 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    145322 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[9]:=0]
-	    148221 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
-	    148223 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._in_v:=0]
-	    149461 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
-	    152516 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    152758 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    153765 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-	    166711 my_demux.my_demux._out2_a_B : 1  [by my_demux.out2.a:=0]
-	    166877 my_demux.my_demux.out2_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out2_a_B:=1]
-	    166952 my_demux.my_demux._out2_a_BX_t[0] : 1  [by my_demux.my_demux.out2_a_B_buf_f.buf2._y:=0]
-	    170210 my_demux.my_demux.out2_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux._out2_a_B:=1]
-	    170555 my_demux.my_demux._out2_a_BX_f[0] : 1  [by my_demux.my_demux.out2_a_B_buf_t.buf2._y:=0]
-	    177027 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf2._y:=0]
-System initialized
-	    177027 Reset : 0
-	    177165 my_demux._reset_B : 1  [by Reset:=0]
-	    182428 my_demux.my_demux.reset_buf._y : 0  [by my_demux._reset_B:=1]
-	    182430 my_demux.my_demux._reset_BX : 1  [by my_demux.my_demux.reset_buf._y:=0]
-	    226347 my_demux.my_demux.reset_bufarray.buf4._y : 0  [by my_demux.my_demux._reset_BX:=1]
-	    226348 my_demux.my_demux._reset_BXX[0] : 1  [by my_demux.my_demux.reset_bufarray.buf4._y:=0]
-System reset completed
-
-Output neutral checked
-	    226348 my_demux.my_demux.c_buf_t.in : 1
-	    226348 my_demux.my_demux.out1_t_buf_func[6].n1 : 1
-	    226348 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
-	    226348 my_demux.my_demux.out1_t_buf_func[5].n1 : 1
-	    226348 my_demux.my_demux.out1_t_buf_func[4].n1 : 1
-	    226348 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
-	    226348 my_demux.my_demux.out1_t_buf_func[3].n1 : 1
-	    226348 my_demux.my_demux.out1_t_buf_func[2].n1 : 1
-	    226359 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.c_buf_t.in:=1]
-	    226364 my_demux.my_demux.vc.OR2_tf[4]._y : 0  [by my_demux.my_demux.out1_t_buf_func[4].n1:=1]
-	    226415 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
-	    226718 my_demux.my_demux.vc.OR2_tf[6]._y : 0  [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
-	    226720 my_demux.my_demux.vc.tmp[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
-	    226876 my_demux.my_demux.vc.OR2_tf[3]._y : 0  [by my_demux.my_demux.out1_t_buf_func[3].n1:=1]
-	    226896 my_demux.my_demux.c_buf_t.buf2._y : 0  [by my_demux.my_demux.c_buf_t.in:=1]
-	    226899 my_demux.my_demux._c_t_buf[0] : 1  [by my_demux.my_demux.c_buf_t.buf2._y:=0]
-	    226928 my_demux.my_demux.out1_t_buf_func[0]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
-	    226929 my_demux.my_demux.out1_t_buf_func[0].y : 1  [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
-	    226943 my_demux.my_demux.out1_t_buf_func[4]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
-	    227052 my_demux.my_demux.out1_t_buf_func[3]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
-	    227074 my_demux.my_demux.out1_t_buf_func[3].y : 1  [by my_demux.my_demux.out1_t_buf_func[3]._y:=0]
-	    227160 my_demux.my_demux.out1_t_buf_func[4].y : 1  [by my_demux.my_demux.out1_t_buf_func[4]._y:=0]
-	    227216 my_demux.my_demux.out1_t_buf_func[1]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
-	    227217 my_demux.my_demux.out1_t_buf_func[1].y : 1  [by my_demux.my_demux.out1_t_buf_func[1]._y:=0]
-	    228500 my_demux.my_demux.out1_t_buf_func[2]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
-	    228783 my_demux.my_demux.vc.OR2_tf[2]._y : 0  [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
-	    228989 my_demux.my_demux.vc.OR2_tf[5]._y : 0  [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
-	    229148 my_demux.my_demux.vc.tmp[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
-	    229660 my_demux.my_demux.out1_t_buf_func[5]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
-	    230081 my_demux.my_demux.out1_t_buf_func[2].y : 1  [by my_demux.my_demux.out1_t_buf_func[2]._y:=0]
-	    230910 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    232197 my_demux.my_demux.vc.tmp[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    238128 my_demux.my_demux.vc.tmp[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
-	    239456 my_demux.my_demux.vc.tmp[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
-	    240582 my_demux.my_demux.out1_t_buf_func[6]._y : 0  [by my_demux.my_demux._c_t_buf[0]:=1]
-	    240727 my_demux.my_demux.out1_t_buf_func[6].y : 1  [by my_demux.my_demux.out1_t_buf_func[6]._y:=0]
-	    241688 my_demux.my_demux.vc.C2Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[1]:=1]
-	    244520 my_demux.my_demux.vc.tmp[7] : 1  [by my_demux.my_demux.vc.C2Els[0]._y:=0]
-	    249336 my_demux.my_demux.out1_t_buf_func[5].y : 1  [by my_demux.my_demux.out1_t_buf_func[5]._y:=0]
-	    250289 my_demux.my_demux.vc.tmp[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
-	    253239 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    256643 my_demux.my_demux.vc.C3Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[4]:=1]
-	    256644 my_demux.my_demux.vc.tmp[9] : 1  [by my_demux.my_demux.vc.C3Els[0]._y:=0]
-	    287834 my_demux.my_demux.vc.tmp[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
-	    327118 my_demux.my_demux.vc.C2Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[3]:=1]
-	    327280 my_demux.my_demux.vc.tmp[8] : 1  [by my_demux.my_demux.vc.C2Els[1]._y:=0]
-	    334649 my_demux.my_demux.vc.C3Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[8]:=1]
-	    334663 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.C3Els[1]._y:=0]
-	    334670 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    334823 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    334824 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
-	    356227 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
-	    356227 my_demux.out1.v : 1
-	    356228 my_demux.my_demux.out_or._y : 0  [by my_demux.out1.v:=1]
-	    356229 my_demux.my_demux._out_v : 1  [by my_demux.my_demux.out_or._y:=0]
-	    358472 my_demux.my_demux.inack_ctl._y : 0  [by my_demux.my_demux._out_v:=1]
-	    358659 my_demux.in.a : 1  [by my_demux.my_demux.inack_ctl._y:=0]
-	    358660 my_demux.my_demux._en : 0  [by my_demux.in.a:=1]
-	    358661 my_demux.my_demux.out2_en_buf_t.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    358666 my_demux.my_demux._en2_X_t[0] : 0  [by my_demux.my_demux.out2_en_buf_t.buf2._y:=1]
-	    359513 my_demux.my_demux.out1_en_buf_f.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    360404 my_demux.my_demux._en1_X_f[0] : 0  [by my_demux.my_demux.out1_en_buf_f.buf2._y:=1]
-	    362842 my_demux.my_demux.out2_en_buf_f.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    362843 my_demux.my_demux._en2_X_f[0] : 0  [by my_demux.my_demux.out2_en_buf_f.buf2._y:=1]
-	    393442 my_demux.my_demux.out1_en_buf_t.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    393459 my_demux.my_demux._en1_X_t[0] : 0  [by my_demux.my_demux.out1_en_buf_t.buf2._y:=1]
-	    393459 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	    393459 my_demux.my_demux.out1_t_buf_func[6].n1 : 0
-	    393459 my_demux.my_demux.out1_t_buf_func[2].n1 : 0
-	    393459 my_demux.my_demux.out1_t_buf_func[5].n1 : 0
-	    393459 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	    393459 my_demux.my_demux.out1_t_buf_func[4].n1 : 0
-	    393459 my_demux.my_demux.out1_t_buf_func[3].n1 : 0
-	    393460 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_t_buf_func[4].n1:=0]
-	    393462 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
-	    393501 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
-	    393596 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
-	    394400 my_demux.my_demux.vc.OR2_tf[5]._y : 1  [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
-	    394735 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
-	    396032 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    396040 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    396277 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
-	    401820 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
-	    401854 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    407195 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
-	    408113 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[2]:=0]
-	    408117 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
-	    415741 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
-	    452421 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    454819 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    458034 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[1]:=0]
-	    462119 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    505153 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    505201 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[7]:=0]
-	    505204 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
-	    505382 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    526359 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-First Cond Checked
-	    526359 my_demux.out1.a : 1
-	    538258 my_demux.my_demux._out1_a_B : 0  [by my_demux.out1.a:=1]
-	    544209 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 1  [by my_demux.my_demux._out1_a_B:=0]
-	    545036 my_demux.my_demux._out1_a_BX_t[0] : 0  [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=1]
-	    545037 my_demux.my_demux.out1_t_buf_func[2]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    545040 my_demux.my_demux.out1_t_buf_func[4]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    545041 my_demux.my_demux.out1_t_buf_func[4].y : 0  [by my_demux.my_demux.out1_t_buf_func[4]._y:=1]
-	    545109 my_demux.my_demux.out1_t_buf_func[3]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    545132 my_demux.my_demux.out1_t_buf_func[6]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    545173 my_demux.my_demux.out1_t_buf_func[2].y : 0  [by my_demux.my_demux.out1_t_buf_func[2]._y:=1]
-	    545209 my_demux.my_demux.out1_t_buf_func[0]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    545220 my_demux.my_demux.out1_t_buf_func[1]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    545232 my_demux.my_demux.out1_t_buf_func[1].y : 0  [by my_demux.my_demux.out1_t_buf_func[1]._y:=1]
-	    545373 my_demux.my_demux.out1_t_buf_func[6].y : 0  [by my_demux.my_demux.out1_t_buf_func[6]._y:=1]
-	    549168 my_demux.my_demux.out1_t_buf_func[0].y : 0  [by my_demux.my_demux.out1_t_buf_func[0]._y:=1]
-	    564155 my_demux.my_demux.out1_t_buf_func[3].y : 0  [by my_demux.my_demux.out1_t_buf_func[3]._y:=1]
-	    577743 my_demux.my_demux.out1_a_B_buf_t.buf2._y : 1  [by my_demux.my_demux._out1_a_B:=0]
-	    581643 my_demux.my_demux._out1_a_BX_f[0] : 0  [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=1]
-	    582324 my_demux.my_demux.out1_t_buf_func[5]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    583353 my_demux.my_demux.out1_t_buf_func[5].y : 0  [by my_demux.my_demux.out1_t_buf_func[5]._y:=1]
-System reset completed
-
-Output neutral checked
-	    583353 my_demux.my_demux.c_buf_t.in : 0
-	    583353 my_demux.out1.v : 0
-	    583353 my_demux.out1.a : 0
-	    583354 my_demux.my_demux.c_buf_t.buf2._y : 1  [by my_demux.my_demux.c_buf_t.in:=0]
-	    583354 my_demux.my_demux._out1_a_B : 1  [by my_demux.out1.a:=0]
-	    583355 my_demux.my_demux.out1_a_B_buf_t.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    583391 my_demux.my_demux._c_t_buf[0] : 0  [by my_demux.my_demux.c_buf_t.buf2._y:=1]
-	    583409 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.c_buf_t.in:=0]
-	    585101 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    585114 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._c_v:=0]
-	    586919 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
-	    602098 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    606729 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    607086 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
-	    628359 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
-	    628384 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    628405 my_demux.my_demux.inack_ctl._y : 1  [by my_demux.my_demux._out_v:=0]
-	    628406 my_demux.in.a : 0  [by my_demux.my_demux.inack_ctl._y:=1]
-	    638054 my_demux.my_demux._en : 1  [by my_demux.in.a:=0]
-	    638055 my_demux.my_demux.out2_en_buf_f.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    638055 my_demux.my_demux.out1_en_buf_t.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    638060 my_demux.my_demux._en2_X_f[0] : 1  [by my_demux.my_demux.out2_en_buf_f.buf2._y:=0]
-	    638215 my_demux.my_demux.out2_en_buf_t.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    638623 my_demux.my_demux._en2_X_t[0] : 1  [by my_demux.my_demux.out2_en_buf_t.buf2._y:=0]
-	    638636 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf2._y:=0]
-	    639091 my_demux.my_demux.out1_en_buf_f.buf2._y : 0  [by my_demux.my_demux._en:=1]
-	    639102 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf2._y:=0]
-	    639102 my_demux.my_demux.c_buf_f.in : 1
-	    639102 my_demux.my_demux.out1_t_buf_func[6].n1 : 1
-	    639102 my_demux.my_demux.out1_f_buf_func[1].n1 : 1
-	    639102 my_demux.my_demux.out1_t_buf_func[5].n1 : 1
-	    639102 my_demux.my_demux.out1_f_buf_func[4].n1 : 1
-	    639102 my_demux.my_demux.out1_f_buf_func[0].n1 : 1
-	    639102 my_demux.my_demux.out1_f_buf_func[3].n1 : 1
-	    639102 my_demux.my_demux.out1_t_buf_func[2].n1 : 1
-	    639106 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_f_buf_func[1].n1:=1]
-	    639116 my_demux.my_demux.c_buf_f.buf2._y : 0  [by my_demux.my_demux.c_buf_f.in:=1]
-	    639120 my_demux.my_demux.vc.OR2_tf[6]._y : 0  [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
-	    639190 my_demux.my_demux.vc.tmp[6] : 1  [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
-	    639206 my_demux.my_demux.vc.OR2_tf[5]._y : 0  [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
-	    639330 my_demux.my_demux.vc.OR2_tf[2]._y : 0  [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
-	    639341 my_demux.my_demux.vc.tmp[2] : 1  [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
-	    639949 my_demux.my_demux.vc.tmp[1] : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
-	    640149 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.c_buf_f.in:=1]
-	    640152 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    640306 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_f_buf_func[0].n1:=1]
-	    640360 my_demux.my_demux.vc.tmp[0] : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    640575 my_demux.my_demux._c_f_buf[0] : 1  [by my_demux.my_demux.c_buf_f.buf2._y:=0]
-	    640656 my_demux.my_demux.out2_t_buf_func[6]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
-	    640667 my_demux.my_demux.out2_f_buf_func[3]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
-	    641280 my_demux.my_demux.out2_f_buf_func[3].y : 1  [by my_demux.my_demux.out2_f_buf_func[3]._y:=0]
-	    641508 my_demux.my_demux.vc.C2Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[0]:=1]
-	    641736 my_demux.my_demux.out2_t_buf_func[2]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
-	    641781 my_demux.my_demux.out2_t_buf_func[2].y : 1  [by my_demux.my_demux.out2_t_buf_func[2]._y:=0]
-	    642400 my_demux.my_demux.out2_t_buf_func[6].y : 1  [by my_demux.my_demux.out2_t_buf_func[6]._y:=0]
-	    647557 my_demux.my_demux.vc.OR2_tf[3]._y : 0  [by my_demux.my_demux.out1_f_buf_func[3].n1:=1]
-	    648554 my_demux.my_demux.vc.tmp[3] : 1  [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
-	    648886 my_demux.my_demux.out2_f_buf_func[4]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
-	    649227 my_demux.my_demux.out2_t_buf_func[5]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
-	    649411 my_demux.my_demux.out2_f_buf_func[4].y : 1  [by my_demux.my_demux.out2_f_buf_func[4]._y:=0]
-	    650127 my_demux.my_demux.out2_t_buf_func[5].y : 1  [by my_demux.my_demux.out2_t_buf_func[5]._y:=0]
-	    650203 my_demux.my_demux.vc.C2Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[3]:=1]
-	    650255 my_demux.my_demux.vc.tmp[8] : 1  [by my_demux.my_demux.vc.C2Els[1]._y:=0]
-	    651652 my_demux.my_demux.out2_f_buf_func[0]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
-	    651659 my_demux.my_demux.out2_f_buf_func[0].y : 1  [by my_demux.my_demux.out2_f_buf_func[0]._y:=0]
-	    655530 my_demux.my_demux.vc.tmp[7] : 1  [by my_demux.my_demux.vc.C2Els[0]._y:=0]
-	    658558 my_demux.my_demux.out2_f_buf_func[1]._y : 0  [by my_demux.my_demux._c_f_buf[0]:=1]
-	    670546 my_demux.my_demux.vc.OR2_tf[4]._y : 0  [by my_demux.my_demux.out1_f_buf_func[4].n1:=1]
-	    674170 my_demux.my_demux.out2_f_buf_func[1].y : 1  [by my_demux.my_demux.out2_f_buf_func[1]._y:=0]
-	    677013 my_demux.my_demux.vc.tmp[4] : 1  [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
-	    689628 my_demux.my_demux.vc.tmp[5] : 1  [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
-	    689630 my_demux.my_demux.vc.C3Els[0]._y : 0  [by my_demux.my_demux.vc.tmp[5]:=1]
-	    689984 my_demux.my_demux.vc.tmp[9] : 1  [by my_demux.my_demux.vc.C3Els[0]._y:=0]
-	    690117 my_demux.my_demux.vc.C3Els[1]._y : 0  [by my_demux.my_demux.vc.tmp[9]:=1]
-	    690118 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.C3Els[1]._y:=0]
-	    690122 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    690664 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    690665 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
-	    735685 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
-	    735685 my_demux.out2.v : 1
-	    748063 my_demux.my_demux.out_or._y : 0  [by my_demux.out2.v:=1]
-	    748142 my_demux.my_demux._out_v : 1  [by my_demux.my_demux.out_or._y:=0]
-	    750575 my_demux.my_demux.inack_ctl._y : 0  [by my_demux.my_demux._out_v:=1]
-	    750663 my_demux.in.a : 1  [by my_demux.my_demux.inack_ctl._y:=0]
-	    758445 my_demux.my_demux._en : 0  [by my_demux.in.a:=1]
-	    758475 my_demux.my_demux.out2_en_buf_t.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    758504 my_demux.my_demux.out1_en_buf_t.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    759912 my_demux.my_demux.out1_en_buf_f.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    760597 my_demux.my_demux._en1_X_f[0] : 0  [by my_demux.my_demux.out1_en_buf_f.buf2._y:=1]
-	    777888 my_demux.my_demux._en1_X_t[0] : 0  [by my_demux.my_demux.out1_en_buf_t.buf2._y:=1]
-	    786772 my_demux.my_demux.out2_en_buf_f.buf2._y : 1  [by my_demux.my_demux._en:=0]
-	    803487 my_demux.my_demux._en2_X_f[0] : 0  [by my_demux.my_demux.out2_en_buf_f.buf2._y:=1]
-	    817979 my_demux.my_demux._en2_X_t[0] : 0  [by my_demux.my_demux.out2_en_buf_t.buf2._y:=1]
-	    817979 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
-	    817979 my_demux.my_demux.out1_t_buf_func[6].n1 : 0
-	    817979 my_demux.my_demux.out1_t_buf_func[2].n1 : 0
-	    817979 my_demux.my_demux.out1_t_buf_func[5].n1 : 0
-	    817979 my_demux.my_demux.out1_f_buf_func[1].n1 : 0
-	    817979 my_demux.my_demux.out1_f_buf_func[4].n1 : 0
-	    817979 my_demux.my_demux.out1_f_buf_func[3].n1 : 0
-	    817982 my_demux.my_demux.vc.OR2_tf[3]._y : 1  [by my_demux.my_demux.out1_f_buf_func[3].n1:=0]
-	    817991 my_demux.my_demux.vc.OR2_tf[5]._y : 1  [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
-	    817992 my_demux.my_demux.vc.tmp[5] : 0  [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
-	    818020 my_demux.my_demux.vc.tmp[3] : 0  [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
-	    818022 my_demux.my_demux.vc.OR2_tf[2]._y : 1  [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
-	    818106 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_f_buf_func[0].n1:=0]
-	    818148 my_demux.my_demux.vc.OR2_tf[6]._y : 1  [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
-	    818198 my_demux.my_demux.vc.tmp[0] : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    818212 my_demux.my_demux.vc.OR2_tf[4]._y : 1  [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
-	    818214 my_demux.my_demux.vc.tmp[4] : 0  [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
-	    819258 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_f_buf_func[1].n1:=0]
-	    819259 my_demux.my_demux.vc.tmp[1] : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    820760 my_demux.my_demux.vc.C2Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[1]:=0]
-	    820762 my_demux.my_demux.vc.tmp[7] : 0  [by my_demux.my_demux.vc.C2Els[0]._y:=1]
-	    820875 my_demux.my_demux.vc.tmp[6] : 0  [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
-	    820893 my_demux.my_demux.vc.C3Els[0]._y : 1  [by my_demux.my_demux.vc.tmp[6]:=0]
-	    821012 my_demux.my_demux.vc.tmp[9] : 0  [by my_demux.my_demux.vc.C3Els[0]._y:=1]
-	    830774 my_demux.my_demux.vc.tmp[2] : 0  [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
-	    836494 my_demux.my_demux.vc.C2Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[2]:=0]
-	    836502 my_demux.my_demux.vc.tmp[8] : 0  [by my_demux.my_demux.vc.C2Els[1]._y:=1]
-	    836556 my_demux.my_demux.vc.C3Els[1]._y : 1  [by my_demux.my_demux.vc.tmp[8]:=0]
-	    887094 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.C3Els[1]._y:=1]
-	    887099 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    888166 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-Second Cond Checked

test/unit_tests/demux_7/test.prsim

@@ -18,18 +18,21 @@ mode run
 assert-qdi-channel-neutral "my_demux.out1" 7
 assert-qdi-channel-neutral "my_demux.out2" 7
 assert-qdi-channel-neutral "my_demux.in" 7
+assert my_demux.cond.v 0
 cycle
 
 system "echo 'Output neutral checked'"
 
-set my_demux.cond.d.d[0].t 1
-set my_demux.cond.d.d[0].f 0
+set my_demux.cond.d.d[0].t 0
+set my_demux.cond.d.d[0].f 1
 set-qdi-channel-valid "my_demux.in" 7 127
 cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
+assert my_demux.cond.v 1
 
 assert-qdi-channel-valid "my_demux.out1" 7 127
+assert-qdi-channel-neutral "my_demux.out2" 7
 set my_demux.out1.v 1
 cycle
 assert my_demux.in.a 1
@@ -62,12 +65,13 @@ set my_demux.out2.a 0
 set my_demux.out2.v 0
 cycle
 
-set my_demux.cond.d.d[0].t 0
-set my_demux.cond.d.d[0].f 1
+set my_demux.cond.d.d[0].t 1
+set my_demux.cond.d.d[0].f 0
 set-qdi-channel-valid "my_demux.in" 7 100
 cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
+assert my_demux.cond.v 1
 
 assert-qdi-channel-valid "my_demux.out2" 7 100
 set my_demux.out2.v 1

test/unit_tests/demux_bit_7/test.act

@@ -0,0 +1,49 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+
+defproc demux_bit_7 (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
+
+    demux_bit<7,0> my_demux(.in=in, .out1=out1,.out2 = out2);
+    //Low active Reset 
+    bool _reset_B; 
+    prs {
+    	Reset => _reset_B-
+    }
+    my_demux.supply.vss = GND;
+    my_demux.supply.vdd = Vdd;
+    my_demux.reset_B = _reset_B;
+    
+}
+
+demux_bit_7 my_demux;

test/unit_tests/demux_bit_7/test.prsim

@@ -0,0 +1,77 @@
+watchall
+set-qdi-channel-neutral "my_demux.in" 8
+set my_demux.out1.a 0
+set my_demux.out1.v 0
+set my_demux.out2.a 0
+set my_demux.out2.v 0
+set my_demux.in.d.d[0].t 0
+set my_demux.in.d.d[0].f 0
+cycle
+system "echo 'System initialized'"
+
+set Reset 0
+cycle
+system "echo 'System reset completed'"
+status X
+mode run
+
+assert-qdi-channel-neutral "my_demux.out1" 7
+assert-qdi-channel-neutral "my_demux.out2" 7
+assert-qdi-channel-neutral "my_demux.in" 8
+cycle
+
+system "echo 'Output neutral checked'"
+
+set-qdi-channel-valid "my_demux.in" 8 254
+cycle
+assert my_demux.in.v 1
+assert my_demux.in.a 0
+
+assert-qdi-channel-valid "my_demux.out1" 7 127
+assert-qdi-channel-neutral "my_demux.out2" 7
+set my_demux.out1.v 1
+cycle
+assert my_demux.in.a 1
+set-qdi-channel-neutral "my_demux.in" 8
+cycle
+set my_demux.out1.a 1
+
+
+system "echo 'First Cond Checked'"
+
+
+set Reset 0
+cycle
+system "echo 'System reset completed'"
+status X
+mode run
+
+assert-qdi-channel-neutral "my_demux.out1" 7
+assert-qdi-channel-neutral "my_demux.out2" 7
+assert-qdi-channel-neutral "my_demux.in" 8
+cycle
+
+system "echo 'Output neutral checked'"
+
+set my_demux.out1.a 0
+set my_demux.out1.v 0
+set my_demux.out2.a 0
+set my_demux.out2.v 0
+cycle
+
+set-qdi-channel-valid "my_demux.in" 8 101
+cycle
+assert my_demux.in.v 1
+assert my_demux.in.a 0
+
+assert-qdi-channel-valid "my_demux.out2" 7 50
+set my_demux.out2.v 1
+cycle
+assert my_demux.in.a 1
+set-qdi-channel-neutral "my_demux.in" 7
+cycle
+
+
+system "echo 'Second Cond Checked'"
+
+

test/unit_tests/demux_td_2/run/prsim.out

@@ -1,197 +0,0 @@
-my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_en_buf_t.buf1._y my_demux.my_demux.token_a_out my_demux.my_demux._out_v my_demux.my_demux._in_v my_demux.my_demux._c_d_buf[0] my_demux.my_demux._en my_demux.my_demux.vc.OR2_tf[1].y my_demux.my_demux.cond_inv_f my_demux.my_demux._out1_a_B my_demux.my_demux.invout_f.a my_demux.my_demux._out1_a_BX_t[0] my_demux.in.v my_demux.my_demux._c_v my_demux.my_demux.invout_t.a my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.v my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.cond_inv_t my_demux.out1.a my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out_or._y my_demux.my_demux._en1_X_t[0] my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[0].y my_demux.token.a my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux._in_c_v_ my_demux.my_demux.c_buf_tk_inv._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_f.buf1._y my_demux.my_demux.c_buf_d_inv.buf1._y my_demux.my_demux._c_tk_buf my_demux.my_demux.vc.myctree.C2Els[0]._y my_demux.my_demux.out1_a_B_buf_f.buf1._y my_demux.my_demux.c_el._y my_demux.my_demux.out1_a_B_buf_t.buf1._y 
-	     83058 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
-	     83058 my_demux.my_demux.invout_f.a : 0
-	     83058 my_demux.my_demux.invout_t.a : 0
-	     83058 my_demux.my_demux.out1_f_buf_func[1].n1 : 0
-	     83058 my_demux.token.a : 0
-	     83058 my_demux.out1.v : 0
-	     83058 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	     83058 my_demux.out1.a : 0
-	     83058 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	     83062 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.invout_t.a:=0]
-	     83073 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
-	     83113 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	     92187 my_demux.my_demux.token_a_out : 1  [by my_demux.token.a:=0]
-	     96782 my_demux.my_demux.cond_inv_t : 1  [by my_demux.my_demux.invout_t.a:=0]
-	     96962 my_demux.my_demux.vc.OR2_tf[1].y : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    112853 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    119989 my_demux.my_demux._out1_a_B : 1  [by my_demux.out1.a:=0]
-	    120411 my_demux.my_demux.out1_a_B_buf_f.buf1._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    120412 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf1._y:=0]
-	    121594 my_demux.my_demux.c_buf_tk_inv._y : 0  [by my_demux.my_demux.cond_inv_t:=1]
-	    121595 my_demux.my_demux._c_tk_buf : 1  [by my_demux.my_demux.c_buf_tk_inv._y:=0]
-	    126306 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    127156 my_demux.my_demux.cond_inv_f : 1  [by my_demux.my_demux.invout_f.a:=0]
-	    127196 my_demux.my_demux._en : 1  [by my_demux.my_demux._out_v:=0]
-	    127199 my_demux.my_demux.out1_en_buf_f.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    127438 my_demux.my_demux.c_buf_d_inv.buf1._y : 0  [by my_demux.my_demux.cond_inv_f:=1]
-	    127964 my_demux.my_demux.out1_en_buf_t.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    127989 my_demux.my_demux._c_d_buf[0] : 1  [by my_demux.my_demux.c_buf_d_inv.buf1._y:=0]
-	    129035 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
-	    134715 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    146511 my_demux.my_demux.vc.OR2_tf[0].y : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    147465 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1  [by my_demux.my_demux.vc.OR2_tf[0].y:=0]
-	    148546 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
-	    149528 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._in_v:=0]
-	    149546 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    149640 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
-	    168703 my_demux.my_demux.out1_a_B_buf_t.buf1._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    172716 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=0]
-	    203016 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    207019 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-System initialized
-	    207019 Reset : 0
-	    251920 my_demux._reset_B : 1  [by Reset:=0]
-	    273504 my_demux.my_demux.reset_buf._y : 0  [by my_demux._reset_B:=1]
-	    278264 my_demux.my_demux._reset_BX : 1  [by my_demux.my_demux.reset_buf._y:=0]
-	    278467 my_demux.my_demux.reset_buf_token._y : 0  [by my_demux.my_demux._reset_BX:=1]
-	    278766 my_demux.my_demux.reset_bufarray.buf1._y : 0  [by my_demux.my_demux._reset_BX:=1]
-	    278905 my_demux.my_demux._reset_BXX[0] : 1  [by my_demux.my_demux.reset_bufarray.buf1._y:=0]
-	    280321 my_demux.my_demux._reset_BXt : 1  [by my_demux.my_demux.reset_buf_token._y:=0]
-System reset completed
-
-Output neutral checked
-	    280321 my_demux.my_demux.invout_t.a : 1
-	    280321 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
-	    280321 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
-	    280332 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
-	    280333 my_demux.my_demux.vc.OR2_tf[1].y : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
-	    280336 my_demux.my_demux.out1_t_buf_func[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    280373 my_demux.my_demux.out1_t_buf_func[0].y : 1  [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
-	    280390 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.invout_t.a:=1]
-	    280525 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    280637 my_demux.my_demux.vc.OR2_tf[0].y : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    281129 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    316667 my_demux.my_demux.cond_inv_t : 0  [by my_demux.my_demux.invout_t.a:=1]
-	    316707 my_demux.my_demux.c_buf_tk_inv._y : 1  [by my_demux.my_demux.cond_inv_t:=0]
-	    316964 my_demux.my_demux._c_tk_buf : 0  [by my_demux.my_demux.c_buf_tk_inv._y:=1]
-	    328149 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0  [by my_demux.my_demux.vc.OR2_tf[0].y:=1]
-	    328236 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
-	    328237 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    328530 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    330043 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
-	    330537 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
-	    332107 my_demux.my_demux.out1_t_buf_func[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
-	    333316 my_demux.my_demux.out1_t_buf_func[1].y : 1  [by my_demux.my_demux.out1_t_buf_func[1]._y:=0]
-	    333316 my_demux.out1.v : 1
-	    333906 my_demux.my_demux.out_or._y : 0  [by my_demux.out1.v:=1]
-	    334084 my_demux.my_demux._out_v : 1  [by my_demux.my_demux.out_or._y:=0]
-	    334887 my_demux.my_demux.inack_ctl._y : 0  [by my_demux.my_demux._out_v:=1]
-	    335051 my_demux.in.a : 1  [by my_demux.my_demux.inack_ctl._y:=0]
-	    337246 my_demux.my_demux._en : 0  [by my_demux.in.a:=1]
-	    337268 my_demux.my_demux.out1_en_buf_t.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    338093 my_demux.my_demux.out1_en_buf_f.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    338226 my_demux.my_demux._en1_X_f[0] : 0  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=1]
-	    367396 my_demux.my_demux._en1_X_t[0] : 0  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=1]
-	    367396 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	    367396 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	    367755 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    381871 my_demux.my_demux.vc.OR2_tf[1].y : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    383058 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    383279 my_demux.my_demux.vc.OR2_tf[0].y : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    383286 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1  [by my_demux.my_demux.vc.OR2_tf[0].y:=0]
-	    383316 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
-	    390029 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    447490 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-	    447490 my_demux.out1.a : 1
-	    447581 my_demux.my_demux._out1_a_B : 0  [by my_demux.out1.a:=1]
-	    447588 my_demux.my_demux.out1_a_B_buf_t.buf1._y : 1  [by my_demux.my_demux._out1_a_B:=0]
-	    449770 my_demux.my_demux.out1_a_B_buf_f.buf1._y : 1  [by my_demux.my_demux._out1_a_B:=0]
-	    449876 my_demux.my_demux._out1_a_BX_t[0] : 0  [by my_demux.my_demux.out1_a_B_buf_f.buf1._y:=1]
-	    449954 my_demux.my_demux.out1_t_buf_func[0]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    450151 my_demux.my_demux.out1_t_buf_func[1]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    450375 my_demux.my_demux._out1_a_BX_f[0] : 0  [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=1]
-	    450606 my_demux.my_demux.out1_t_buf_func[1].y : 0  [by my_demux.my_demux.out1_t_buf_func[1]._y:=1]
-	    468950 my_demux.my_demux.out1_t_buf_func[0].y : 0  [by my_demux.my_demux.out1_t_buf_func[0]._y:=1]
-First Cond Checked
-	    468950 my_demux.my_demux.invout_t.a : 0
-	    468950 my_demux.out1.v : 0
-	    468950 my_demux.out1.a : 0
-	    468962 my_demux.my_demux.cond_inv_t : 1  [by my_demux.my_demux.invout_t.a:=0]
-	    468962 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
-	    469354 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.invout_t.a:=0]
-	    471861 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    473238 my_demux.my_demux.c_buf_tk_inv._y : 0  [by my_demux.my_demux.cond_inv_t:=1]
-	    473240 my_demux.my_demux._c_tk_buf : 1  [by my_demux.my_demux.c_buf_tk_inv._y:=0]
-	    473649 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    474866 my_demux.my_demux._out1_a_B : 1  [by my_demux.out1.a:=0]
-	    476115 my_demux.my_demux.out1_a_B_buf_f.buf1._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    476281 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf1._y:=0]
-	    478184 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._c_v:=0]
-	    478259 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    478365 my_demux.my_demux.out1_a_B_buf_t.buf1._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    478503 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=0]
-	    478604 my_demux.my_demux.inack_ctl._y : 1  [by my_demux.my_demux._in_c_v_:=0]
-	    483867 my_demux.in.a : 0  [by my_demux.my_demux.inack_ctl._y:=1]
-	    483869 my_demux.my_demux._en : 1  [by my_demux.in.a:=0]
-	    483870 my_demux.my_demux.out1_en_buf_f.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    484418 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
-	    527786 my_demux.my_demux.out1_en_buf_t.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    527797 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
-System initialized
-	    527797 my_demux.my_demux.invout_f.a : 1
-	    527797 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
-	    527797 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
-	    527813 my_demux.my_demux.out1_t_buf_func[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
-	    527864 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.invout_f.a:=1]
-	    528167 my_demux.my_demux.cond_inv_f : 0  [by my_demux.my_demux.invout_f.a:=1]
-	    528325 my_demux.my_demux.out1_t_buf_func[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    530248 my_demux.my_demux.out1_t_buf_func[1].y : 1  [by my_demux.my_demux.out1_t_buf_func[1]._y:=0]
-	    530438 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
-	    530440 my_demux.my_demux.vc.OR2_tf[1].y : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
-	    532359 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    541366 my_demux.my_demux.out1_t_buf_func[0].y : 1  [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
-	    552092 my_demux.my_demux.c_buf_d_inv.buf1._y : 1  [by my_demux.my_demux.cond_inv_f:=0]
-	    552095 my_demux.my_demux._c_d_buf[0] : 0  [by my_demux.my_demux.c_buf_d_inv.buf1._y:=1]
-	    554744 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    593317 my_demux.my_demux.vc.OR2_tf[0].y : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    593346 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0  [by my_demux.my_demux.vc.OR2_tf[0].y:=1]
-	    593663 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
-	    593707 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    593816 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    595264 my_demux.my_demux.token_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    595265 my_demux.token.r : 1  [by my_demux.my_demux.token_buf._y:=0]
-	    595482 my_demux.my_demux.out_or._y : 0  [by my_demux.token.r:=1]
-	    595504 my_demux.my_demux._out_v : 1  [by my_demux.my_demux.out_or._y:=0]
-	    596468 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
-	    596469 my_demux.my_demux.inack_ctl._y : 0  [by my_demux.my_demux._in_c_v_:=1]
-	    598050 my_demux.in.a : 1  [by my_demux.my_demux.inack_ctl._y:=0]
-	    607395 my_demux.my_demux._en : 0  [by my_demux.in.a:=1]
-	    607499 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
-	    607554 my_demux.my_demux.out1_en_buf_t.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    608841 my_demux.my_demux._en1_X_t[0] : 0  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=1]
-	    627071 my_demux.my_demux.out1_en_buf_f.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    629303 my_demux.my_demux._en1_X_f[0] : 0  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=1]
-	    629303 my_demux.token.a : 1
-	    629448 my_demux.my_demux.token_a_out : 0  [by my_demux.token.a:=1]
-	    632280 my_demux.my_demux.token_buf._y : 1  [by my_demux.my_demux.token_a_out:=0]
-	    638634 my_demux.token.r : 0  [by my_demux.my_demux.token_buf._y:=1]
-	    638635 my_demux.my_demux.out_or._y : 1  [by my_demux.token.r:=0]
-	    677919 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    677919 my_demux.token.a : 0
-	    677919 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	    677919 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	    677933 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    677940 my_demux.my_demux.vc.OR2_tf[0].y : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    678081 my_demux.my_demux.token_a_out : 1  [by my_demux.token.a:=0]
-	    685288 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    685448 my_demux.my_demux.vc.OR2_tf[1].y : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    707005 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1  [by my_demux.my_demux.vc.OR2_tf[1].y:=0]
-	    707006 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
-	    707007 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    707008 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-	    707008 my_demux.my_demux.invout_f.a : 0
-	    707195 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.invout_f.a:=0]
-	    707196 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    709251 my_demux.my_demux.cond_inv_f : 1  [by my_demux.my_demux.invout_f.a:=0]
-	    711378 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._c_v:=0]
-	    711379 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    712232 my_demux.my_demux.inack_ctl._y : 1  [by my_demux.my_demux._in_c_v_:=0]
-	    712237 my_demux.in.a : 0  [by my_demux.my_demux.inack_ctl._y:=1]
-	    713128 my_demux.my_demux._en : 1  [by my_demux.in.a:=0]
-	    713129 my_demux.my_demux.out1_en_buf_t.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    713145 my_demux.my_demux.out1_en_buf_f.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    715702 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
-	    721506 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
-	    744033 my_demux.my_demux.c_buf_d_inv.buf1._y : 0  [by my_demux.my_demux.cond_inv_f:=1]
-	    744036 my_demux.my_demux._c_d_buf[0] : 1  [by my_demux.my_demux.c_buf_d_inv.buf1._y:=0]

test/unit_tests/demux_td_2/run/test.prs

@@ -1,420 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-"Reset"->"my_demux._reset_B"-
-~("Reset")->"my_demux._reset_B"+
-= "my_demux._reset_B" "my_demux.my_demux.reset_B"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.cond.v" "my_demux.my_demux.cond.v"
-= "my_demux.cond.a" "my_demux.my_demux.cond.a"
-= "my_demux.cond.d.d[0].f" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].t" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].d[0]"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].d[1]"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-= "my_demux.out1.v" "my_demux.my_demux.out1.v"
-= "my_demux.out1.a" "my_demux.my_demux.out1.a"
-= "my_demux.out1.d.d[0].f" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].t" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].d[0]"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].d[1]"
-= "my_demux.out1.d.d[1].f" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].t" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].d[0]"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].d[1]"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-~"my_demux.my_demux.token_buf.c1"&~"my_demux.my_demux.token_buf.c2"|~"my_demux.my_demux.token_buf.pr_B"->"my_demux.my_demux.token_buf._y"+
-"my_demux.my_demux.token_buf.c1"&"my_demux.my_demux.token_buf.c2"&"my_demux.my_demux.token_buf.n1"&"my_demux.my_demux.token_buf.n2"&"my_demux.my_demux.token_buf.sr_B"->"my_demux.my_demux.token_buf._y"-
-"my_demux.my_demux.token_buf._y"->"my_demux.my_demux.token_buf.y"-
-~("my_demux.my_demux.token_buf._y")->"my_demux.my_demux.token_buf.y"+
-"my_demux.my_demux.out1_a_B_buf_f.buf1.a"->"my_demux.my_demux.out1_a_B_buf_f.buf1._y"-
-~("my_demux.my_demux.out1_a_B_buf_f.buf1.a")->"my_demux.my_demux.out1_a_B_buf_f.buf1._y"+
-"my_demux.my_demux.out1_a_B_buf_f.buf1._y"->"my_demux.my_demux.out1_a_B_buf_f.buf1.y"-
-~("my_demux.my_demux.out1_a_B_buf_f.buf1._y")->"my_demux.my_demux.out1_a_B_buf_f.buf1.y"+
-= "my_demux.my_demux.out1_a_B_buf_f.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.buf1.vdd"
-= "my_demux.my_demux.out1_a_B_buf_f.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.buf1.vss"
-= "my_demux.my_demux.out1_a_B_buf_f.out[0]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
-= "my_demux.my_demux.out1_a_B_buf_f.out[0]" "my_demux.my_demux.out1_a_B_buf_f.buf1.y"
-= "my_demux.my_demux.out1_a_B_buf_f.in" "my_demux.my_demux.out1_a_B_buf_f.buf1.a"
-~"my_demux.my_demux.inack_ctl.c1"&~"my_demux.my_demux.inack_ctl.c2"&~"my_demux.my_demux.inack_ctl.c3"|~"my_demux.my_demux.inack_ctl.pr_B"->"my_demux.my_demux.inack_ctl._y"+
-"my_demux.my_demux.inack_ctl.c1"&"my_demux.my_demux.inack_ctl.c2"&"my_demux.my_demux.inack_ctl.c3"&"my_demux.my_demux.inack_ctl.sr_B"->"my_demux.my_demux.inack_ctl._y"-
-"my_demux.my_demux.inack_ctl._y"->"my_demux.my_demux.inack_ctl.y"-
-~("my_demux.my_demux.inack_ctl._y")->"my_demux.my_demux.inack_ctl.y"+
-"my_demux.my_demux.reset_bufarray.buf1.a"->"my_demux.my_demux.reset_bufarray.buf1._y"-
-~("my_demux.my_demux.reset_bufarray.buf1.a")->"my_demux.my_demux.reset_bufarray.buf1._y"+
-"my_demux.my_demux.reset_bufarray.buf1._y"->"my_demux.my_demux.reset_bufarray.buf1.y"-
-~("my_demux.my_demux.reset_bufarray.buf1._y")->"my_demux.my_demux.reset_bufarray.buf1.y"+
-= "my_demux.my_demux.reset_bufarray.supply.vdd" "my_demux.my_demux.reset_bufarray.buf1.vdd"
-= "my_demux.my_demux.reset_bufarray.supply.vss" "my_demux.my_demux.reset_bufarray.buf1.vss"
-= "my_demux.my_demux.reset_bufarray.out[0]" "my_demux.my_demux.reset_bufarray.out[1]"
-= "my_demux.my_demux.reset_bufarray.out[0]" "my_demux.my_demux.reset_bufarray.buf1.y"
-= "my_demux.my_demux.reset_bufarray.in" "my_demux.my_demux.reset_bufarray.buf1.a"
-= "my_demux.my_demux._c_v" "my_demux.my_demux.c_el.c1"
-= "my_demux.my_demux._c_v" "my_demux.my_demux.c_f_c_t_or.y"
-"my_demux.my_demux.reset_buf_token.a"->"my_demux.my_demux.reset_buf_token._y"-
-~("my_demux.my_demux.reset_buf_token.a")->"my_demux.my_demux.reset_buf_token._y"+
-"my_demux.my_demux.reset_buf_token._y"->"my_demux.my_demux.reset_buf_token.y"-
-~("my_demux.my_demux.reset_buf_token._y")->"my_demux.my_demux.reset_buf_token.y"+
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.c_buf_d_inv.out[0]"
-= "my_demux.my_demux._c_d_buf[1]" "my_demux.my_demux.c_buf_d_inv.out[1]"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_t_buf_func[1].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_f_buf_func[1].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_t_buf_func[0].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_f_buf_func[0].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux._c_d_buf[1]"
-"my_demux.my_demux.invout_t.a"->"my_demux.my_demux.invout_t.y"-
-~("my_demux.my_demux.invout_t.a")->"my_demux.my_demux.invout_t.y"+
-= "my_demux.my_demux._en" "my_demux.my_demux.token_buf.c1"
-= "my_demux.my_demux._en" "my_demux.my_demux.out1_en_buf_f.in"
-= "my_demux.my_demux._en" "my_demux.my_demux.out1_en_buf_t.in"
-= "my_demux.my_demux._en" "my_demux.my_demux.en_ctl.y"
-= "my_demux.my_demux._en" "my_demux.my_demux.inack_ctl.c1"
-"my_demux.my_demux.c_buf_tk_inv.a"->"my_demux.my_demux.c_buf_tk_inv._y"-
-~("my_demux.my_demux.c_buf_tk_inv.a")->"my_demux.my_demux.c_buf_tk_inv._y"+
-"my_demux.my_demux.c_buf_tk_inv._y"->"my_demux.my_demux.c_buf_tk_inv.y"-
-~("my_demux.my_demux.c_buf_tk_inv._y")->"my_demux.my_demux.c_buf_tk_inv.y"+
-= "my_demux.my_demux.token_a_out" "my_demux.my_demux.token_buf.c2"
-= "my_demux.my_demux.token_a_out" "my_demux.my_demux.outt_a_inv.y"
-= "my_demux.my_demux._out1_a_B" "my_demux.my_demux.out1_a_B_buf_t.in"
-= "my_demux.my_demux._out1_a_B" "my_demux.my_demux.out1_a_B_buf_f.in"
-= "my_demux.my_demux._out1_a_B" "my_demux.my_demux.out1_a_inv.y"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.my_demux.in.d.d[0].f" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.in.d.d[0].t" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].d[0]"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].d[1]"
-= "my_demux.my_demux.in.d.d[1].f" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.in.d.d[1].t" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].d[0]"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].d[1]"
-= "my_demux.my_demux.in.a" "my_demux.my_demux.en_ctl.c1"
-= "my_demux.my_demux.in.a" "my_demux.my_demux.inack_ctl.y"
-= "my_demux.my_demux.in.v" "my_demux.my_demux.in_v_buf.y"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.out1_f_buf_func[1].n1"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.out1_t_buf_func[1].n1"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.out1_f_buf_func[0].n1"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.out1_t_buf_func[0].n1"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-"my_demux.my_demux.out1_en_buf_t.buf1.a"->"my_demux.my_demux.out1_en_buf_t.buf1._y"-
-~("my_demux.my_demux.out1_en_buf_t.buf1.a")->"my_demux.my_demux.out1_en_buf_t.buf1._y"+
-"my_demux.my_demux.out1_en_buf_t.buf1._y"->"my_demux.my_demux.out1_en_buf_t.buf1.y"-
-~("my_demux.my_demux.out1_en_buf_t.buf1._y")->"my_demux.my_demux.out1_en_buf_t.buf1.y"+
-= "my_demux.my_demux.out1_en_buf_t.supply.vdd" "my_demux.my_demux.out1_en_buf_t.buf1.vdd"
-= "my_demux.my_demux.out1_en_buf_t.supply.vss" "my_demux.my_demux.out1_en_buf_t.buf1.vss"
-= "my_demux.my_demux.out1_en_buf_t.out[0]" "my_demux.my_demux.out1_en_buf_t.out[1]"
-= "my_demux.my_demux.out1_en_buf_t.out[0]" "my_demux.my_demux.out1_en_buf_t.buf1.y"
-= "my_demux.my_demux.out1_en_buf_t.in" "my_demux.my_demux.out1_en_buf_t.buf1.a"
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_a_B_buf_f.out[0]"
-= "my_demux.my_demux._out1_a_BX_t[1]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_t_buf_func[1].c2"
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_t_buf_func[0].c2"
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux._out1_a_BX_t[1]"
-"my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b"->"my_demux.my_demux.out_or._y"-
-~("my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b")->"my_demux.my_demux.out_or._y"+
-"my_demux.my_demux.out_or._y"->"my_demux.my_demux.out_or.y"-
-~("my_demux.my_demux.out_or._y")->"my_demux.my_demux.out_or.y"+
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.c_el.y"
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.inack_ctl.c2"
-"my_demux.my_demux.reset_buf.a"->"my_demux.my_demux.reset_buf._y"-
-~("my_demux.my_demux.reset_buf.a")->"my_demux.my_demux.reset_buf._y"+
-"my_demux.my_demux.reset_buf._y"->"my_demux.my_demux.reset_buf.y"-
-~("my_demux.my_demux.reset_buf._y")->"my_demux.my_demux.reset_buf.y"+
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.reset_bufarray.in"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.reset_buf_token.a"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.reset_buf.y"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.inack_ctl.sr_B"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.inack_ctl.pr_B"
-= "my_demux.my_demux.reset_B" "my_demux.my_demux.reset_buf.a"
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux.out1_en_buf_f.out[0]"
-= "my_demux.my_demux._en1_X_f[1]" "my_demux.my_demux.out1_en_buf_f.out[1]"
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux.out1_f_buf_func[1].c1"
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux.out1_f_buf_func[0].c1"
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux._en1_X_f[1]"
-= "my_demux.my_demux._out_v" "my_demux.my_demux.en_ctl.p1"
-= "my_demux.my_demux._out_v" "my_demux.my_demux.inack_ctl.c3"
-= "my_demux.my_demux._out_v" "my_demux.my_demux.out_or.y"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.reset_bufarray.out[0]"
-= "my_demux.my_demux._reset_BXX[1]" "my_demux.my_demux.reset_bufarray.out[1]"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[1].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[1].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[1].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[1].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[0].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[0].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[0].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[0].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux._reset_BXX[1]"
-"my_demux.my_demux.out1_en_buf_f.buf1.a"->"my_demux.my_demux.out1_en_buf_f.buf1._y"-
-~("my_demux.my_demux.out1_en_buf_f.buf1.a")->"my_demux.my_demux.out1_en_buf_f.buf1._y"+
-"my_demux.my_demux.out1_en_buf_f.buf1._y"->"my_demux.my_demux.out1_en_buf_f.buf1.y"-
-~("my_demux.my_demux.out1_en_buf_f.buf1._y")->"my_demux.my_demux.out1_en_buf_f.buf1.y"+
-= "my_demux.my_demux.out1_en_buf_f.supply.vdd" "my_demux.my_demux.out1_en_buf_f.buf1.vdd"
-= "my_demux.my_demux.out1_en_buf_f.supply.vss" "my_demux.my_demux.out1_en_buf_f.buf1.vss"
-= "my_demux.my_demux.out1_en_buf_f.out[0]" "my_demux.my_demux.out1_en_buf_f.out[1]"
-= "my_demux.my_demux.out1_en_buf_f.out[0]" "my_demux.my_demux.out1_en_buf_f.buf1.y"
-= "my_demux.my_demux.out1_en_buf_f.in" "my_demux.my_demux.out1_en_buf_f.buf1.a"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux.out1_a_B_buf_t.out[0]"
-= "my_demux.my_demux._out1_a_BX_f[1]" "my_demux.my_demux.out1_a_B_buf_t.out[1]"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux.out1_f_buf_func[1].c2"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux.out1_f_buf_func[0].c2"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux._out1_a_BX_f[1]"
-~"my_demux.my_demux.c_el.c1"&~"my_demux.my_demux.c_el.c2"->"my_demux.my_demux.c_el._y"+
-"my_demux.my_demux.c_el.c1"&"my_demux.my_demux.c_el.c2"->"my_demux.my_demux.c_el._y"-
-"my_demux.my_demux.c_el._y"->"my_demux.my_demux.c_el.y"-
-~("my_demux.my_demux.c_el._y")->"my_demux.my_demux.c_el.y"+
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux.out1_en_buf_t.out[0]"
-= "my_demux.my_demux._en1_X_t[1]" "my_demux.my_demux.out1_en_buf_t.out[1]"
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux.out1_t_buf_func[1].c1"
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux.out1_t_buf_func[0].c1"
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux._en1_X_t[1]"
-"my_demux.my_demux.in_v_buf.a"->"my_demux.my_demux.in_v_buf._y"-
-~("my_demux.my_demux.in_v_buf.a")->"my_demux.my_demux.in_v_buf._y"+
-"my_demux.my_demux.in_v_buf._y"->"my_demux.my_demux.in_v_buf.y"-
-~("my_demux.my_demux.in_v_buf._y")->"my_demux.my_demux.in_v_buf.y"+
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.my_demux.out1.a" "my_demux.my_demux.out1_a_inv.a"
-= "my_demux.my_demux.out1.v" "my_demux.my_demux.out_or.a"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1_f_buf_func[1].y"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1_t_buf_func[1].y"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1_f_buf_func[0].y"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1_t_buf_func[0].y"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-"my_demux.my_demux.c_f_c_t_or.a"|"my_demux.my_demux.c_f_c_t_or.b"->"my_demux.my_demux.c_f_c_t_or._y"-
-~("my_demux.my_demux.c_f_c_t_or.a"|"my_demux.my_demux.c_f_c_t_or.b")->"my_demux.my_demux.c_f_c_t_or._y"+
-"my_demux.my_demux.c_f_c_t_or._y"->"my_demux.my_demux.c_f_c_t_or.y"-
-~("my_demux.my_demux.c_f_c_t_or._y")->"my_demux.my_demux.c_f_c_t_or.y"+
-"my_demux.my_demux.out1_a_inv.a"->"my_demux.my_demux.out1_a_inv.y"-
-~("my_demux.my_demux.out1_a_inv.a")->"my_demux.my_demux.out1_a_inv.y"+
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token.r"
-= "my_demux.my_demux.token.a" "my_demux.my_demux.outt_a_inv.a"
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token_buf.y"
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.out_or.b"
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token.r"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.token_buf.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[1].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[1].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[0].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[0].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.in_v_buf.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_el.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_f.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.invout_t.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_f_c_t_or.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_buf_token.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_buf.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.en_ctl.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.inack_ctl.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out_or.vdd"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.token_buf.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[1].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[1].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[0].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[0].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.in_v_buf.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_el.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_f.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.invout_t.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_f_c_t_or.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_buf_token.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_buf.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.en_ctl.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.inack_ctl.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
-"my_demux.my_demux.invout_f.a"->"my_demux.my_demux.invout_f.y"-
-~("my_demux.my_demux.invout_f.a")->"my_demux.my_demux.invout_f.y"+
-~"my_demux.my_demux.vc.myctree.C2Els[0].c1"&~"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"+
-"my_demux.my_demux.vc.myctree.C2Els[0].c1"&"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"-
-"my_demux.my_demux.vc.myctree.C2Els[0]._y"->"my_demux.my_demux.vc.myctree.C2Els[0].y"-
-~("my_demux.my_demux.vc.myctree.C2Els[0]._y")->"my_demux.my_demux.vc.myctree.C2Els[0].y"+
-= "my_demux.my_demux.vc.myctree.supply.vdd" "my_demux.my_demux.vc.myctree.C2Els[0].vdd"
-= "my_demux.my_demux.vc.myctree.supply.vss" "my_demux.my_demux.vc.myctree.C2Els[0].vss"
-= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.C2Els[0].c1"
-= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.tmp[0]"
-= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.C2Els[0].c2"
-= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.tmp[1]"
-= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.C2Els[0].y"
-= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.tmp[2]"
-"my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
-~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
-"my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
-~("my_demux.my_demux.vc.OR2_tf[0]._y")->"my_demux.my_demux.vc.OR2_tf[0].y"+
-"my_demux.my_demux.vc.OR2_tf[1].a"|"my_demux.my_demux.vc.OR2_tf[1].b"->"my_demux.my_demux.vc.OR2_tf[1]._y"-
-~("my_demux.my_demux.vc.OR2_tf[1].a"|"my_demux.my_demux.vc.OR2_tf[1].b")->"my_demux.my_demux.vc.OR2_tf[1]._y"+
-"my_demux.my_demux.vc.OR2_tf[1]._y"->"my_demux.my_demux.vc.OR2_tf[1].y"-
-~("my_demux.my_demux.vc.OR2_tf[1]._y")->"my_demux.my_demux.vc.OR2_tf[1].y"+
-= "my_demux.my_demux.vc.OR2_tf[1].y" "my_demux.my_demux.vc.myctree.in[1]"
-= "my_demux.my_demux.vc.OR2_tf[0].y" "my_demux.my_demux.vc.myctree.in[0]"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.myctree.supply.vss"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.myctree.supply.vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
-= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.myctree.out"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.OR2_tf[1].b"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.OR2_tf[1].a"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.OR2_tf[0].b"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.OR2_tf[0].a"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-"my_demux.my_demux.out1_a_B_buf_t.buf1.a"->"my_demux.my_demux.out1_a_B_buf_t.buf1._y"-
-~("my_demux.my_demux.out1_a_B_buf_t.buf1.a")->"my_demux.my_demux.out1_a_B_buf_t.buf1._y"+
-"my_demux.my_demux.out1_a_B_buf_t.buf1._y"->"my_demux.my_demux.out1_a_B_buf_t.buf1.y"-
-~("my_demux.my_demux.out1_a_B_buf_t.buf1._y")->"my_demux.my_demux.out1_a_B_buf_t.buf1.y"+
-= "my_demux.my_demux.out1_a_B_buf_t.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.buf1.vdd"
-= "my_demux.my_demux.out1_a_B_buf_t.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.buf1.vss"
-= "my_demux.my_demux.out1_a_B_buf_t.out[0]" "my_demux.my_demux.out1_a_B_buf_t.out[1]"
-= "my_demux.my_demux.out1_a_B_buf_t.out[0]" "my_demux.my_demux.out1_a_B_buf_t.buf1.y"
-= "my_demux.my_demux.out1_a_B_buf_t.in" "my_demux.my_demux.out1_a_B_buf_t.buf1.a"
-~"my_demux.my_demux.en_ctl.p1"&~"my_demux.my_demux.en_ctl.c1"->"my_demux.my_demux.en_ctl.y"+
-"my_demux.my_demux.en_ctl.c1"->"my_demux.my_demux.en_ctl.y"-
-= "my_demux.my_demux._reset_BXt" "my_demux.my_demux.token_buf.sr_B"
-= "my_demux.my_demux._reset_BXt" "my_demux.my_demux.token_buf.pr_B"
-= "my_demux.my_demux._reset_BXt" "my_demux.my_demux.reset_buf_token.y"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.invout_f.a"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_f_c_t_or.b"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.invout_t.a"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.c_f_c_t_or.a"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-~"my_demux.my_demux.out1_f_buf_func[0].c1"&~"my_demux.my_demux.out1_f_buf_func[0].c2"|~"my_demux.my_demux.out1_f_buf_func[0].pr_B"->"my_demux.my_demux.out1_f_buf_func[0]._y"+
-"my_demux.my_demux.out1_f_buf_func[0].c1"&"my_demux.my_demux.out1_f_buf_func[0].c2"&"my_demux.my_demux.out1_f_buf_func[0].n1"&"my_demux.my_demux.out1_f_buf_func[0].n2"&"my_demux.my_demux.out1_f_buf_func[0].sr_B"->"my_demux.my_demux.out1_f_buf_func[0]._y"-
-"my_demux.my_demux.out1_f_buf_func[0]._y"->"my_demux.my_demux.out1_f_buf_func[0].y"-
-~("my_demux.my_demux.out1_f_buf_func[0]._y")->"my_demux.my_demux.out1_f_buf_func[0].y"+
-~"my_demux.my_demux.out1_f_buf_func[1].c1"&~"my_demux.my_demux.out1_f_buf_func[1].c2"|~"my_demux.my_demux.out1_f_buf_func[1].pr_B"->"my_demux.my_demux.out1_f_buf_func[1]._y"+
-"my_demux.my_demux.out1_f_buf_func[1].c1"&"my_demux.my_demux.out1_f_buf_func[1].c2"&"my_demux.my_demux.out1_f_buf_func[1].n1"&"my_demux.my_demux.out1_f_buf_func[1].n2"&"my_demux.my_demux.out1_f_buf_func[1].sr_B"->"my_demux.my_demux.out1_f_buf_func[1]._y"-
-"my_demux.my_demux.out1_f_buf_func[1]._y"->"my_demux.my_demux.out1_f_buf_func[1].y"-
-~("my_demux.my_demux.out1_f_buf_func[1]._y")->"my_demux.my_demux.out1_f_buf_func[1].y"+
-= "my_demux.my_demux._in_v" "my_demux.my_demux.token_buf.n2"
-= "my_demux.my_demux._in_v" "my_demux.my_demux.in_v_buf.a"
-= "my_demux.my_demux._in_v" "my_demux.my_demux.c_el.c2"
-= "my_demux.my_demux._in_v" "my_demux.my_demux.vc.out"
-~"my_demux.my_demux.out1_t_buf_func[0].c1"&~"my_demux.my_demux.out1_t_buf_func[0].c2"|~"my_demux.my_demux.out1_t_buf_func[0].pr_B"->"my_demux.my_demux.out1_t_buf_func[0]._y"+
-"my_demux.my_demux.out1_t_buf_func[0].c1"&"my_demux.my_demux.out1_t_buf_func[0].c2"&"my_demux.my_demux.out1_t_buf_func[0].n1"&"my_demux.my_demux.out1_t_buf_func[0].n2"&"my_demux.my_demux.out1_t_buf_func[0].sr_B"->"my_demux.my_demux.out1_t_buf_func[0]._y"-
-"my_demux.my_demux.out1_t_buf_func[0]._y"->"my_demux.my_demux.out1_t_buf_func[0].y"-
-~("my_demux.my_demux.out1_t_buf_func[0]._y")->"my_demux.my_demux.out1_t_buf_func[0].y"+
-~"my_demux.my_demux.out1_t_buf_func[1].c1"&~"my_demux.my_demux.out1_t_buf_func[1].c2"|~"my_demux.my_demux.out1_t_buf_func[1].pr_B"->"my_demux.my_demux.out1_t_buf_func[1]._y"+
-"my_demux.my_demux.out1_t_buf_func[1].c1"&"my_demux.my_demux.out1_t_buf_func[1].c2"&"my_demux.my_demux.out1_t_buf_func[1].n1"&"my_demux.my_demux.out1_t_buf_func[1].n2"&"my_demux.my_demux.out1_t_buf_func[1].sr_B"->"my_demux.my_demux.out1_t_buf_func[1]._y"-
-"my_demux.my_demux.out1_t_buf_func[1]._y"->"my_demux.my_demux.out1_t_buf_func[1].y"-
-~("my_demux.my_demux.out1_t_buf_func[1]._y")->"my_demux.my_demux.out1_t_buf_func[1].y"+
-= "my_demux.my_demux.cond_inv_f" "my_demux.my_demux.c_buf_d_inv.in"
-= "my_demux.my_demux.cond_inv_f" "my_demux.my_demux.invout_f.y"
-"my_demux.my_demux.outt_a_inv.a"->"my_demux.my_demux.outt_a_inv.y"-
-~("my_demux.my_demux.outt_a_inv.a")->"my_demux.my_demux.outt_a_inv.y"+
-= "my_demux.my_demux.cond_inv_t" "my_demux.my_demux.c_buf_tk_inv.a"
-= "my_demux.my_demux.cond_inv_t" "my_demux.my_demux.invout_t.y"
-"my_demux.my_demux.c_buf_d_inv.buf1.a"->"my_demux.my_demux.c_buf_d_inv.buf1._y"-
-~("my_demux.my_demux.c_buf_d_inv.buf1.a")->"my_demux.my_demux.c_buf_d_inv.buf1._y"+
-"my_demux.my_demux.c_buf_d_inv.buf1._y"->"my_demux.my_demux.c_buf_d_inv.buf1.y"-
-~("my_demux.my_demux.c_buf_d_inv.buf1._y")->"my_demux.my_demux.c_buf_d_inv.buf1.y"+
-= "my_demux.my_demux.c_buf_d_inv.supply.vdd" "my_demux.my_demux.c_buf_d_inv.buf1.vdd"
-= "my_demux.my_demux.c_buf_d_inv.supply.vss" "my_demux.my_demux.c_buf_d_inv.buf1.vss"
-= "my_demux.my_demux.c_buf_d_inv.out[0]" "my_demux.my_demux.c_buf_d_inv.out[1]"
-= "my_demux.my_demux.c_buf_d_inv.out[0]" "my_demux.my_demux.c_buf_d_inv.buf1.y"
-= "my_demux.my_demux.c_buf_d_inv.in" "my_demux.my_demux.c_buf_d_inv.buf1.a"
-= "my_demux.my_demux._c_tk_buf" "my_demux.my_demux.token_buf.n1"
-= "my_demux.my_demux._c_tk_buf" "my_demux.my_demux.c_buf_tk_inv.y"
-= "Vdd" "my_demux.my_demux.supply.vdd"
-= "GND" "my_demux.my_demux.supply.vss"
-= "my_demux.token.d.d[0]" "my_demux.token.r"
-= "my_demux.token.r" "my_demux.my_demux.token.r"
-= "my_demux.token.a" "my_demux.my_demux.token.a"
-= "my_demux.token.d.d[0]" "my_demux.my_demux.token.d.d[0]"
-= "my_demux.token.d.d[0]" "my_demux.token.r"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"
-= "my_demux.in.v" "my_demux.my_demux.in.v"
-= "my_demux.in.a" "my_demux.my_demux.in.a"
-= "my_demux.in.d.d[0].f" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].t" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].d[0]"
-= "my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].d[1]"
-= "my_demux.in.d.d[1].f" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].t" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].d[0]"
-= "my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].d[1]"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"

test/unit_tests/demux_td_2/test.act

@@ -32,9 +32,9 @@ import globals;
 open tmpl::dataflow_neuro;
 
 
-defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out1; a1of1 token; avMx1of2<1> cond){
+defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out; a1of1 token; avMx1of2<1> cond){
 
-    demux_td<2, false> my_demux(.in=in, .out1=out1,.token = token, .cond = cond);
+    demux_td<2, false> my_demux(.in=in, .out=out,.token = token, .cond = cond);
     //Low active Reset 
     bool _reset_B; 
     prs {

test/unit_tests/demux_td_2/test.prsim

@@ -1,25 +1,25 @@
 watchall
 set-qdi-channel-neutral "my_demux.in" 2
-set my_demux.out1.a 0
-set my_demux.out1.v 0
+set my_demux.out.a 0
+set my_demux.out.v 0
 set my_demux.token.a 0
 set my_demux.token.r 0
 set my_demux.cond.d.d[0].t 0
 set my_demux.cond.d.d[0].f 0
 cycle
-system "echo 'System initialized'"
+system "echo '[]System initialized'"
 
 set Reset 0
 cycle
-system "echo 'System reset completed'"
+system "echo '[]System reset completed'"
 status X
 mode run
 
-assert-qdi-channel-neutral "my_demux.out1" 2
+assert-qdi-channel-neutral "my_demux.out" 2
 assert-qdi-channel-neutral "my_demux.in" 2
 cycle
 
-system "echo 'Output neutral checked'"
+system "echo '[]Output neutral checked'"
 
 set my_demux.cond.d.d[0].t 1
 set my_demux.cond.d.d[0].f 0
@@ -28,35 +28,35 @@ cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
 
-assert-qdi-channel-valid "my_demux.out1" 2 3
+assert-qdi-channel-valid "my_demux.out" 2 3
 assert my_demux.token.a 0
-set my_demux.out1.v 1
+set my_demux.out.v 1
 cycle
 
 assert my_demux.in.a 1
 set-qdi-channel-neutral "my_demux.in" 2
 cycle
 
-set my_demux.out1.a 1
+set my_demux.out.a 1
 cycle
 
-set my_demux.out1.v 0
+set my_demux.out.v 0
 
 assert my_demux.in.a 1
 set-qdi-channel-neutral "my_demux.in" 2
 
 
-system "echo 'First Cond Checked'"
+system "echo '[]First Cond Checked'"
 
-set my_demux.out1.a 0
-set my_demux.out1.v 0
+set my_demux.out.a 0
+set my_demux.out.v 0
 set my_demux.token.a 0
 set my_demux.token.r 0
 set my_demux.cond.d.d[0].t 0
 set my_demux.cond.d.d[0].f 0
 cycle
 
-system "echo 'System initialized'"
+system "echo '[]System initialized'"
 
 set my_demux.cond.d.d[0].t 0
 set my_demux.cond.d.d[0].f 1

test/unit_tests/demux_td_2_SIGN/run/prsim.out

@@ -1,181 +0,0 @@
-my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._c_tk_buf my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux._c_d_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_en_buf_t.buf1._y my_demux.my_demux.token_a_out my_demux.my_demux._out_v my_demux.my_demux._in_v my_demux.my_demux._en my_demux.my_demux.vc.OR2_tf[1].y my_demux.my_demux._out1_a_B my_demux.my_demux.c_buf_d.in my_demux.my_demux._out1_a_BX_t[0] my_demux.in.v my_demux.my_demux._c_v my_demux.my_demux.c_buf_tk.a my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.v my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.out1.a my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out_or._y my_demux.my_demux._en1_X_t[0] my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.c_buf_d.buf1._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[0].y my_demux.token.a my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux._in_c_v_ my_demux.my_demux.c_buf_tk._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_f.buf1._y my_demux.my_demux.vc.myctree.C2Els[0]._y my_demux.my_demux.out1_a_B_buf_f.buf1._y my_demux.my_demux.c_el._y my_demux.my_demux.out1_a_B_buf_t.buf1._y 
-	     83058 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
-	     83058 my_demux.my_demux.c_buf_d.in : 0
-	     83058 my_demux.my_demux.c_buf_tk.a : 0
-	     83058 my_demux.my_demux.out1_f_buf_func[1].n1 : 0
-	     83058 my_demux.token.a : 0
-	     83058 my_demux.out1.v : 0
-	     83058 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	     83058 my_demux.out1.a : 0
-	     83058 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	     83062 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.c_buf_tk.a:=0]
-	     83073 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
-	     83113 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	     92187 my_demux.my_demux.token_a_out : 1  [by my_demux.token.a:=0]
-	     96782 my_demux.my_demux.c_buf_tk._y : 1  [by my_demux.my_demux.c_buf_tk.a:=0]
-	     96962 my_demux.my_demux.vc.OR2_tf[1].y : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    112853 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    119989 my_demux.my_demux._out1_a_B : 1  [by my_demux.out1.a:=0]
-	    120411 my_demux.my_demux.out1_a_B_buf_f.buf1._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    120412 my_demux.my_demux._out1_a_BX_t[0] : 1  [by my_demux.my_demux.out1_a_B_buf_f.buf1._y:=0]
-	    121594 my_demux.my_demux._c_tk_buf : 0  [by my_demux.my_demux.c_buf_tk._y:=1]
-	    126306 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    126307 my_demux.my_demux.vc.OR2_tf[0].y : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    127156 my_demux.my_demux.c_buf_d.buf1._y : 1  [by my_demux.my_demux.c_buf_d.in:=0]
-	    127196 my_demux.my_demux._en : 1  [by my_demux.my_demux._out_v:=0]
-	    127199 my_demux.my_demux.out1_en_buf_f.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    127438 my_demux.my_demux._c_d_buf[0] : 0  [by my_demux.my_demux.c_buf_d.buf1._y:=1]
-	    127964 my_demux.my_demux.out1_en_buf_t.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    128515 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
-	    134715 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    146512 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1  [by my_demux.my_demux.vc.OR2_tf[0].y:=0]
-	    147583 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
-	    148537 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    148664 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._in_v:=0]
-	    149640 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
-	    149646 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    168703 my_demux.my_demux.out1_a_B_buf_t.buf1._y : 0  [by my_demux.my_demux._out1_a_B:=1]
-	    168721 my_demux.my_demux._out1_a_BX_f[0] : 1  [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=0]
-	    203007 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-System initialized
-	    203007 Reset : 0
-	    207020 my_demux._reset_B : 1  [by Reset:=0]
-	    211023 my_demux.my_demux.reset_buf._y : 0  [by my_demux._reset_B:=1]
-	    255924 my_demux.my_demux._reset_BX : 1  [by my_demux.my_demux.reset_buf._y:=0]
-	    260684 my_demux.my_demux.reset_buf_token._y : 0  [by my_demux.my_demux._reset_BX:=1]
-	    261186 my_demux.my_demux._reset_BXt : 1  [by my_demux.my_demux.reset_buf_token._y:=0]
-	    277508 my_demux.my_demux.reset_bufarray.buf1._y : 0  [by my_demux.my_demux._reset_BX:=1]
-	    277711 my_demux.my_demux._reset_BXX[0] : 1  [by my_demux.my_demux.reset_bufarray.buf1._y:=0]
-System reset completed
-
-Output neutral checked
-	    277711 my_demux.my_demux.c_buf_d.in : 1
-	    277711 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
-	    277711 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
-	    277780 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    277791 my_demux.my_demux.vc.OR2_tf[0].y : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    277850 my_demux.my_demux.c_buf_d.buf1._y : 0  [by my_demux.my_demux.c_buf_d.in:=1]
-	    279565 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.c_buf_d.in:=1]
-	    279769 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    314057 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
-	    314072 my_demux.my_demux.vc.OR2_tf[1].y : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
-	    314073 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0  [by my_demux.my_demux.vc.OR2_tf[1].y:=1]
-	    314110 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
-	    314222 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    314849 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    314889 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
-	    329636 my_demux.my_demux._c_d_buf[0] : 1  [by my_demux.my_demux.c_buf_d.buf1._y:=0]
-	    329723 my_demux.my_demux.out1_t_buf_func[1]._y : 0  [by my_demux.my_demux._c_d_buf[0]:=1]
-	    329893 my_demux.my_demux.out1_t_buf_func[0]._y : 0  [by my_demux.my_demux._c_d_buf[0]:=1]
-	    329894 my_demux.my_demux.out1_t_buf_func[0].y : 1  [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
-	    330017 my_demux.my_demux.out1_t_buf_func[1].y : 1  [by my_demux.my_demux.out1_t_buf_func[1]._y:=0]
-	    361734 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
-	    361734 my_demux.out1.v : 1
-	    363540 my_demux.my_demux.out_or._y : 0  [by my_demux.out1.v:=1]
-	    365547 my_demux.my_demux._out_v : 1  [by my_demux.my_demux.out_or._y:=0]
-	    366756 my_demux.my_demux.inack_ctl._y : 0  [by my_demux.my_demux._out_v:=1]
-	    367346 my_demux.in.a : 1  [by my_demux.my_demux.inack_ctl._y:=0]
-	    367524 my_demux.my_demux._en : 0  [by my_demux.in.a:=1]
-	    367688 my_demux.my_demux.out1_en_buf_f.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    368327 my_demux.my_demux.out1_en_buf_t.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    368349 my_demux.my_demux._en1_X_t[0] : 0  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=1]
-	    369883 my_demux.my_demux._en1_X_f[0] : 0  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=1]
-	    369883 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	    369883 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	    370730 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    370863 my_demux.my_demux.vc.OR2_tf[0].y : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    400011 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    415673 my_demux.my_demux.vc.OR2_tf[1].y : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    416032 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1  [by my_demux.my_demux.vc.OR2_tf[1].y:=0]
-	    430148 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
-	    430369 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    430376 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-First Cond Checked
-	    430376 my_demux.out1.a : 1
-	    430376 my_demux.my_demux.c_buf_d.in : 0
-	    430376 my_demux.out1.v : 0
-	    430406 my_demux.my_demux._out1_a_B : 0  [by my_demux.out1.a:=1]
-	    430413 my_demux.my_demux.out1_a_B_buf_t.buf1._y : 1  [by my_demux.my_demux._out1_a_B:=0]
-	    430467 my_demux.my_demux.out_or._y : 1  [by my_demux.out1.v:=0]
-	    430573 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    432595 my_demux.my_demux.out1_a_B_buf_f.buf1._y : 1  [by my_demux.my_demux._out1_a_B:=0]
-	    432673 my_demux.my_demux._out1_a_BX_t[0] : 0  [by my_demux.my_demux.out1_a_B_buf_f.buf1._y:=1]
-	    432948 my_demux.my_demux.out1_t_buf_func[0]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    433200 my_demux.my_demux._out1_a_BX_f[0] : 0  [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=1]
-	    433403 my_demux.my_demux.out1_t_buf_func[0].y : 0  [by my_demux.my_demux.out1_t_buf_func[0]._y:=1]
-	    437089 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.c_buf_d.in:=0]
-	    437101 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    437505 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._c_v:=0]
-	    437517 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    443433 my_demux.my_demux.inack_ctl._y : 1  [by my_demux.my_demux._in_c_v_:=0]
-	    447709 my_demux.in.a : 0  [by my_demux.my_demux.inack_ctl._y:=1]
-	    450608 my_demux.my_demux._en : 1  [by my_demux.in.a:=0]
-	    450610 my_demux.my_demux.out1_en_buf_f.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    451669 my_demux.my_demux.out1_t_buf_func[1]._y : 1  [by my_demux.my_demux._out1_a_BX_t[0]:=0]
-	    452918 my_demux.my_demux.out1_t_buf_func[1].y : 0  [by my_demux.my_demux.out1_t_buf_func[1]._y:=1]
-	    454903 my_demux.my_demux.out1_en_buf_t.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    455145 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
-	    458402 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
-	    487837 my_demux.my_demux.c_buf_d.buf1._y : 1  [by my_demux.my_demux.c_buf_d.in:=0]
-	    488003 my_demux.my_demux._c_d_buf[0] : 0  [by my_demux.my_demux.c_buf_d.buf1._y:=1]
-System initialized
-	    488003 my_demux.my_demux.c_buf_tk.a : 1
-	    488003 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
-	    488003 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
-	    488078 my_demux.my_demux.c_buf_tk._y : 0  [by my_demux.my_demux.c_buf_tk.a:=1]
-	    488080 my_demux.my_demux._c_tk_buf : 1  [by my_demux.my_demux.c_buf_tk._y:=0]
-	    488141 my_demux.my_demux.vc.OR2_tf[1]._y : 0  [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
-	    488348 my_demux.my_demux.c_f_c_t_or._y : 0  [by my_demux.my_demux.c_buf_tk.a:=1]
-	    488349 my_demux.my_demux._c_v : 1  [by my_demux.my_demux.c_f_c_t_or._y:=0]
-	    493266 my_demux.my_demux.vc.OR2_tf[0]._y : 0  [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
-	    493814 my_demux.my_demux.vc.OR2_tf[0].y : 1  [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
-	    532058 my_demux.my_demux.vc.OR2_tf[1].y : 1  [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
-	    532069 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0  [by my_demux.my_demux.vc.OR2_tf[1].y:=1]
-	    532439 my_demux.my_demux._in_v : 1  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
-	    532455 my_demux.my_demux.c_el._y : 0  [by my_demux.my_demux._in_v:=1]
-	    532506 my_demux.my_demux.token_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    533034 my_demux.token.r : 1  [by my_demux.my_demux.token_buf._y:=0]
-	    535080 my_demux.my_demux.in_v_buf._y : 0  [by my_demux.my_demux._in_v:=1]
-	    535469 my_demux.my_demux.out_or._y : 0  [by my_demux.token.r:=1]
-	    537017 my_demux.my_demux._in_c_v_ : 1  [by my_demux.my_demux.c_el._y:=0]
-	    559394 my_demux.my_demux._out_v : 1  [by my_demux.my_demux.out_or._y:=0]
-	    561960 my_demux.in.v : 1  [by my_demux.my_demux.in_v_buf._y:=0]
-	    572435 my_demux.my_demux.inack_ctl._y : 0  [by my_demux.my_demux._out_v:=1]
-	    572437 my_demux.in.a : 1  [by my_demux.my_demux.inack_ctl._y:=0]
-	    633395 my_demux.my_demux._en : 0  [by my_demux.in.a:=1]
-	    633398 my_demux.my_demux.out1_en_buf_t.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    633424 my_demux.my_demux.out1_en_buf_f.buf1._y : 1  [by my_demux.my_demux._en:=0]
-	    633715 my_demux.my_demux._en1_X_t[0] : 0  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=1]
-	    635025 my_demux.my_demux._en1_X_f[0] : 0  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=1]
-	    635025 my_demux.token.a : 1
-	    635178 my_demux.my_demux.token_a_out : 0  [by my_demux.token.a:=1]
-	    635222 my_demux.my_demux.token_buf._y : 1  [by my_demux.my_demux.token_a_out:=0]
-	    637983 my_demux.token.r : 0  [by my_demux.my_demux.token_buf._y:=1]
-	    651666 my_demux.my_demux.out_or._y : 1  [by my_demux.token.r:=0]
-	    651667 my_demux.my_demux._out_v : 0  [by my_demux.my_demux.out_or._y:=1]
-	    651667 my_demux.token.a : 0
-	    651667 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
-	    651667 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
-	    651668 my_demux.my_demux.vc.OR2_tf[0]._y : 1  [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
-	    651689 my_demux.my_demux.vc.OR2_tf[1]._y : 1  [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
-	    651884 my_demux.my_demux.token_a_out : 1  [by my_demux.token.a:=0]
-	    653249 my_demux.my_demux.vc.OR2_tf[0].y : 0  [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
-	    661034 my_demux.my_demux.vc.OR2_tf[1].y : 0  [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
-	    661193 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1  [by my_demux.my_demux.vc.OR2_tf[1].y:=0]
-	    680869 my_demux.my_demux._in_v : 0  [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
-	    682156 my_demux.my_demux.in_v_buf._y : 1  [by my_demux.my_demux._in_v:=0]
-	    684388 my_demux.in.v : 0  [by my_demux.my_demux.in_v_buf._y:=1]
-	    684388 my_demux.my_demux.c_buf_tk.a : 0
-	    684533 my_demux.my_demux.c_buf_tk._y : 1  [by my_demux.my_demux.c_buf_tk.a:=0]
-	    687220 my_demux.my_demux.c_f_c_t_or._y : 1  [by my_demux.my_demux.c_buf_tk.a:=0]
-	    687221 my_demux.my_demux._c_v : 0  [by my_demux.my_demux.c_f_c_t_or._y:=1]
-	    690887 my_demux.my_demux._c_tk_buf : 0  [by my_demux.my_demux.c_buf_tk._y:=1]
-	    726505 my_demux.my_demux.c_el._y : 1  [by my_demux.my_demux._c_v:=0]
-	    726667 my_demux.my_demux._in_c_v_ : 0  [by my_demux.my_demux.c_el._y:=1]
-	    734036 my_demux.my_demux.inack_ctl._y : 1  [by my_demux.my_demux._in_c_v_:=0]
-	    734050 my_demux.in.a : 0  [by my_demux.my_demux.inack_ctl._y:=1]
-	    734057 my_demux.my_demux._en : 1  [by my_demux.in.a:=0]
-	    734217 my_demux.my_demux.out1_en_buf_t.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    734218 my_demux.my_demux._en1_X_t[0] : 1  [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
-	    755614 my_demux.my_demux.out1_en_buf_f.buf1._y : 0  [by my_demux.my_demux._en:=1]
-	    755615 my_demux.my_demux._en1_X_f[0] : 1  [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]

test/unit_tests/demux_td_2_SIGN/run/test.prs

@@ -1,408 +0,0 @@
-= "GND" "GND"
-= "Vdd" "Vdd"
-= "Reset" "Reset"
-"Reset"->"my_demux._reset_B"-
-~("Reset")->"my_demux._reset_B"+
-= "my_demux._reset_B" "my_demux.my_demux.reset_B"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.cond.v" "my_demux.my_demux.cond.v"
-= "my_demux.cond.a" "my_demux.my_demux.cond.a"
-= "my_demux.cond.d.d[0].f" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].t" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].d[0]"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].d[1]"
-= "my_demux.cond.d.d[0].d[0]" "my_demux.cond.d.d[0].f"
-= "my_demux.cond.d.d[0].d[1]" "my_demux.cond.d.d[0].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-= "my_demux.out1.v" "my_demux.my_demux.out1.v"
-= "my_demux.out1.a" "my_demux.my_demux.out1.a"
-= "my_demux.out1.d.d[0].f" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].t" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].d[0]"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].d[1]"
-= "my_demux.out1.d.d[1].f" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].t" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].d[0]"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].d[1]"
-= "my_demux.out1.d.d[1].d[0]" "my_demux.out1.d.d[1].f"
-= "my_demux.out1.d.d[1].d[1]" "my_demux.out1.d.d[1].t"
-= "my_demux.out1.d.d[0].d[0]" "my_demux.out1.d.d[0].f"
-= "my_demux.out1.d.d[0].d[1]" "my_demux.out1.d.d[0].t"
-~"my_demux.my_demux.token_buf.c1"&~"my_demux.my_demux.token_buf.c2"|~"my_demux.my_demux.token_buf.pr_B"->"my_demux.my_demux.token_buf._y"+
-"my_demux.my_demux.token_buf.c1"&"my_demux.my_demux.token_buf.c2"&"my_demux.my_demux.token_buf.n1"&"my_demux.my_demux.token_buf.n2"&"my_demux.my_demux.token_buf.sr_B"->"my_demux.my_demux.token_buf._y"-
-"my_demux.my_demux.token_buf._y"->"my_demux.my_demux.token_buf.y"-
-~("my_demux.my_demux.token_buf._y")->"my_demux.my_demux.token_buf.y"+
-"my_demux.my_demux.out1_a_B_buf_f.buf1.a"->"my_demux.my_demux.out1_a_B_buf_f.buf1._y"-
-~("my_demux.my_demux.out1_a_B_buf_f.buf1.a")->"my_demux.my_demux.out1_a_B_buf_f.buf1._y"+
-"my_demux.my_demux.out1_a_B_buf_f.buf1._y"->"my_demux.my_demux.out1_a_B_buf_f.buf1.y"-
-~("my_demux.my_demux.out1_a_B_buf_f.buf1._y")->"my_demux.my_demux.out1_a_B_buf_f.buf1.y"+
-= "my_demux.my_demux.out1_a_B_buf_f.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.buf1.vdd"
-= "my_demux.my_demux.out1_a_B_buf_f.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.buf1.vss"
-= "my_demux.my_demux.out1_a_B_buf_f.out[0]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
-= "my_demux.my_demux.out1_a_B_buf_f.out[0]" "my_demux.my_demux.out1_a_B_buf_f.buf1.y"
-= "my_demux.my_demux.out1_a_B_buf_f.in" "my_demux.my_demux.out1_a_B_buf_f.buf1.a"
-~"my_demux.my_demux.inack_ctl.c1"&~"my_demux.my_demux.inack_ctl.c2"&~"my_demux.my_demux.inack_ctl.c3"|~"my_demux.my_demux.inack_ctl.pr_B"->"my_demux.my_demux.inack_ctl._y"+
-"my_demux.my_demux.inack_ctl.c1"&"my_demux.my_demux.inack_ctl.c2"&"my_demux.my_demux.inack_ctl.c3"&"my_demux.my_demux.inack_ctl.sr_B"->"my_demux.my_demux.inack_ctl._y"-
-"my_demux.my_demux.inack_ctl._y"->"my_demux.my_demux.inack_ctl.y"-
-~("my_demux.my_demux.inack_ctl._y")->"my_demux.my_demux.inack_ctl.y"+
-"my_demux.my_demux.reset_bufarray.buf1.a"->"my_demux.my_demux.reset_bufarray.buf1._y"-
-~("my_demux.my_demux.reset_bufarray.buf1.a")->"my_demux.my_demux.reset_bufarray.buf1._y"+
-"my_demux.my_demux.reset_bufarray.buf1._y"->"my_demux.my_demux.reset_bufarray.buf1.y"-
-~("my_demux.my_demux.reset_bufarray.buf1._y")->"my_demux.my_demux.reset_bufarray.buf1.y"+
-= "my_demux.my_demux.reset_bufarray.supply.vdd" "my_demux.my_demux.reset_bufarray.buf1.vdd"
-= "my_demux.my_demux.reset_bufarray.supply.vss" "my_demux.my_demux.reset_bufarray.buf1.vss"
-= "my_demux.my_demux.reset_bufarray.out[0]" "my_demux.my_demux.reset_bufarray.out[1]"
-= "my_demux.my_demux.reset_bufarray.out[0]" "my_demux.my_demux.reset_bufarray.buf1.y"
-= "my_demux.my_demux.reset_bufarray.in" "my_demux.my_demux.reset_bufarray.buf1.a"
-= "my_demux.my_demux._c_v" "my_demux.my_demux.c_el.c1"
-= "my_demux.my_demux._c_v" "my_demux.my_demux.c_f_c_t_or.y"
-"my_demux.my_demux.reset_buf_token.a"->"my_demux.my_demux.reset_buf_token._y"-
-~("my_demux.my_demux.reset_buf_token.a")->"my_demux.my_demux.reset_buf_token._y"+
-"my_demux.my_demux.reset_buf_token._y"->"my_demux.my_demux.reset_buf_token.y"-
-~("my_demux.my_demux.reset_buf_token._y")->"my_demux.my_demux.reset_buf_token.y"+
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.c_buf_d.out[0]"
-= "my_demux.my_demux._c_d_buf[1]" "my_demux.my_demux.c_buf_d.out[1]"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_t_buf_func[1].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_f_buf_func[1].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_t_buf_func[0].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux.out1_f_buf_func[0].n2"
-= "my_demux.my_demux._c_d_buf[0]" "my_demux.my_demux._c_d_buf[1]"
-= "my_demux.my_demux._en" "my_demux.my_demux.token_buf.c1"
-= "my_demux.my_demux._en" "my_demux.my_demux.out1_en_buf_f.in"
-= "my_demux.my_demux._en" "my_demux.my_demux.out1_en_buf_t.in"
-= "my_demux.my_demux._en" "my_demux.my_demux.en_ctl.y"
-= "my_demux.my_demux._en" "my_demux.my_demux.inack_ctl.c1"
-= "my_demux.my_demux.token_a_out" "my_demux.my_demux.token_buf.c2"
-= "my_demux.my_demux.token_a_out" "my_demux.my_demux.outt_a_inv.y"
-= "my_demux.my_demux._out1_a_B" "my_demux.my_demux.out1_a_B_buf_t.in"
-= "my_demux.my_demux._out1_a_B" "my_demux.my_demux.out1_a_B_buf_f.in"
-= "my_demux.my_demux._out1_a_B" "my_demux.my_demux.out1_a_inv.y"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.my_demux.in.d.d[0].f" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.in.d.d[0].t" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].d[0]"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].d[1]"
-= "my_demux.my_demux.in.d.d[1].f" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.in.d.d[1].t" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].d[0]"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].d[1]"
-= "my_demux.my_demux.in.a" "my_demux.my_demux.en_ctl.c1"
-= "my_demux.my_demux.in.a" "my_demux.my_demux.inack_ctl.y"
-= "my_demux.my_demux.in.v" "my_demux.my_demux.in_v_buf.y"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.out1_f_buf_func[1].n1"
-= "my_demux.my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.out1_t_buf_func[1].n1"
-= "my_demux.my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.out1_f_buf_func[0].n1"
-= "my_demux.my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.out1_t_buf_func[0].n1"
-= "my_demux.my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].t"
-"my_demux.my_demux.out1_en_buf_t.buf1.a"->"my_demux.my_demux.out1_en_buf_t.buf1._y"-
-~("my_demux.my_demux.out1_en_buf_t.buf1.a")->"my_demux.my_demux.out1_en_buf_t.buf1._y"+
-"my_demux.my_demux.out1_en_buf_t.buf1._y"->"my_demux.my_demux.out1_en_buf_t.buf1.y"-
-~("my_demux.my_demux.out1_en_buf_t.buf1._y")->"my_demux.my_demux.out1_en_buf_t.buf1.y"+
-= "my_demux.my_demux.out1_en_buf_t.supply.vdd" "my_demux.my_demux.out1_en_buf_t.buf1.vdd"
-= "my_demux.my_demux.out1_en_buf_t.supply.vss" "my_demux.my_demux.out1_en_buf_t.buf1.vss"
-= "my_demux.my_demux.out1_en_buf_t.out[0]" "my_demux.my_demux.out1_en_buf_t.out[1]"
-= "my_demux.my_demux.out1_en_buf_t.out[0]" "my_demux.my_demux.out1_en_buf_t.buf1.y"
-= "my_demux.my_demux.out1_en_buf_t.in" "my_demux.my_demux.out1_en_buf_t.buf1.a"
-"my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b"->"my_demux.my_demux.out_or._y"-
-~("my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b")->"my_demux.my_demux.out_or._y"+
-"my_demux.my_demux.out_or._y"->"my_demux.my_demux.out_or.y"-
-~("my_demux.my_demux.out_or._y")->"my_demux.my_demux.out_or.y"+
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.c_el.y"
-= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.inack_ctl.c2"
-"my_demux.my_demux.reset_buf.a"->"my_demux.my_demux.reset_buf._y"-
-~("my_demux.my_demux.reset_buf.a")->"my_demux.my_demux.reset_buf._y"+
-"my_demux.my_demux.reset_buf._y"->"my_demux.my_demux.reset_buf.y"-
-~("my_demux.my_demux.reset_buf._y")->"my_demux.my_demux.reset_buf.y"+
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_a_B_buf_f.out[0]"
-= "my_demux.my_demux._out1_a_BX_t[1]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_t_buf_func[1].c2"
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_t_buf_func[0].c2"
-= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux._out1_a_BX_t[1]"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.reset_bufarray.in"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.reset_buf_token.a"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.reset_buf.y"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.inack_ctl.sr_B"
-= "my_demux.my_demux._reset_BX" "my_demux.my_demux.inack_ctl.pr_B"
-= "my_demux.my_demux.reset_B" "my_demux.my_demux.reset_buf.a"
-"my_demux.my_demux.c_buf_tk.a"->"my_demux.my_demux.c_buf_tk._y"-
-~("my_demux.my_demux.c_buf_tk.a")->"my_demux.my_demux.c_buf_tk._y"+
-"my_demux.my_demux.c_buf_tk._y"->"my_demux.my_demux.c_buf_tk.y"-
-~("my_demux.my_demux.c_buf_tk._y")->"my_demux.my_demux.c_buf_tk.y"+
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux.out1_en_buf_f.out[0]"
-= "my_demux.my_demux._en1_X_f[1]" "my_demux.my_demux.out1_en_buf_f.out[1]"
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux.out1_f_buf_func[1].c1"
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux.out1_f_buf_func[0].c1"
-= "my_demux.my_demux._en1_X_f[0]" "my_demux.my_demux._en1_X_f[1]"
-= "my_demux.my_demux._out_v" "my_demux.my_demux.en_ctl.p1"
-= "my_demux.my_demux._out_v" "my_demux.my_demux.inack_ctl.c3"
-= "my_demux.my_demux._out_v" "my_demux.my_demux.out_or.y"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.reset_bufarray.out[0]"
-= "my_demux.my_demux._reset_BXX[1]" "my_demux.my_demux.reset_bufarray.out[1]"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[1].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[1].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[1].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[1].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[0].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_f_buf_func[0].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[0].sr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux.out1_t_buf_func[0].pr_B"
-= "my_demux.my_demux._reset_BXX[0]" "my_demux.my_demux._reset_BXX[1]"
-"my_demux.my_demux.out1_en_buf_f.buf1.a"->"my_demux.my_demux.out1_en_buf_f.buf1._y"-
-~("my_demux.my_demux.out1_en_buf_f.buf1.a")->"my_demux.my_demux.out1_en_buf_f.buf1._y"+
-"my_demux.my_demux.out1_en_buf_f.buf1._y"->"my_demux.my_demux.out1_en_buf_f.buf1.y"-
-~("my_demux.my_demux.out1_en_buf_f.buf1._y")->"my_demux.my_demux.out1_en_buf_f.buf1.y"+
-= "my_demux.my_demux.out1_en_buf_f.supply.vdd" "my_demux.my_demux.out1_en_buf_f.buf1.vdd"
-= "my_demux.my_demux.out1_en_buf_f.supply.vss" "my_demux.my_demux.out1_en_buf_f.buf1.vss"
-= "my_demux.my_demux.out1_en_buf_f.out[0]" "my_demux.my_demux.out1_en_buf_f.out[1]"
-= "my_demux.my_demux.out1_en_buf_f.out[0]" "my_demux.my_demux.out1_en_buf_f.buf1.y"
-= "my_demux.my_demux.out1_en_buf_f.in" "my_demux.my_demux.out1_en_buf_f.buf1.a"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux.out1_a_B_buf_t.out[0]"
-= "my_demux.my_demux._out1_a_BX_f[1]" "my_demux.my_demux.out1_a_B_buf_t.out[1]"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux.out1_f_buf_func[1].c2"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux.out1_f_buf_func[0].c2"
-= "my_demux.my_demux._out1_a_BX_f[0]" "my_demux.my_demux._out1_a_BX_f[1]"
-~"my_demux.my_demux.c_el.c1"&~"my_demux.my_demux.c_el.c2"->"my_demux.my_demux.c_el._y"+
-"my_demux.my_demux.c_el.c1"&"my_demux.my_demux.c_el.c2"->"my_demux.my_demux.c_el._y"-
-"my_demux.my_demux.c_el._y"->"my_demux.my_demux.c_el.y"-
-~("my_demux.my_demux.c_el._y")->"my_demux.my_demux.c_el.y"+
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux.out1_en_buf_t.out[0]"
-= "my_demux.my_demux._en1_X_t[1]" "my_demux.my_demux.out1_en_buf_t.out[1]"
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux.out1_t_buf_func[1].c1"
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux.out1_t_buf_func[0].c1"
-= "my_demux.my_demux._en1_X_t[0]" "my_demux.my_demux._en1_X_t[1]"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-= "my_demux.my_demux.out1.a" "my_demux.my_demux.out1_a_inv.a"
-= "my_demux.my_demux.out1.v" "my_demux.my_demux.out_or.a"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1_f_buf_func[1].y"
-= "my_demux.my_demux.out1.d.d[1].d[0]" "my_demux.my_demux.out1.d.d[1].f"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1_t_buf_func[1].y"
-= "my_demux.my_demux.out1.d.d[1].d[1]" "my_demux.my_demux.out1.d.d[1].t"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1_f_buf_func[0].y"
-= "my_demux.my_demux.out1.d.d[0].d[0]" "my_demux.my_demux.out1.d.d[0].f"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1_t_buf_func[0].y"
-= "my_demux.my_demux.out1.d.d[0].d[1]" "my_demux.my_demux.out1.d.d[0].t"
-"my_demux.my_demux.c_f_c_t_or.a"|"my_demux.my_demux.c_f_c_t_or.b"->"my_demux.my_demux.c_f_c_t_or._y"-
-~("my_demux.my_demux.c_f_c_t_or.a"|"my_demux.my_demux.c_f_c_t_or.b")->"my_demux.my_demux.c_f_c_t_or._y"+
-"my_demux.my_demux.c_f_c_t_or._y"->"my_demux.my_demux.c_f_c_t_or.y"-
-~("my_demux.my_demux.c_f_c_t_or._y")->"my_demux.my_demux.c_f_c_t_or.y"+
-"my_demux.my_demux.in_v_buf.a"->"my_demux.my_demux.in_v_buf._y"-
-~("my_demux.my_demux.in_v_buf.a")->"my_demux.my_demux.in_v_buf._y"+
-"my_demux.my_demux.in_v_buf._y"->"my_demux.my_demux.in_v_buf.y"-
-~("my_demux.my_demux.in_v_buf._y")->"my_demux.my_demux.in_v_buf.y"+
-"my_demux.my_demux.out1_a_inv.a"->"my_demux.my_demux.out1_a_inv.y"-
-~("my_demux.my_demux.out1_a_inv.a")->"my_demux.my_demux.out1_a_inv.y"+
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token.r"
-= "my_demux.my_demux.token.a" "my_demux.my_demux.outt_a_inv.a"
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token_buf.y"
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.out_or.b"
-= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token.r"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.token_buf.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[1].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[1].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[0].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[0].vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.in_v_buf.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_el.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_f_c_t_or.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_buf_token.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_buf.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.en_ctl.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.inack_ctl.vdd"
-= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out_or.vdd"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.token_buf.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[1].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[1].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_t_buf_func[0].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_f_buf_func[0].vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.in_v_buf.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_el.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_f_c_t_or.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_buf_token.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_buf.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.en_ctl.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.inack_ctl.vss"
-= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
-~"my_demux.my_demux.vc.myctree.C2Els[0].c1"&~"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"+
-"my_demux.my_demux.vc.myctree.C2Els[0].c1"&"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"-
-"my_demux.my_demux.vc.myctree.C2Els[0]._y"->"my_demux.my_demux.vc.myctree.C2Els[0].y"-
-~("my_demux.my_demux.vc.myctree.C2Els[0]._y")->"my_demux.my_demux.vc.myctree.C2Els[0].y"+
-= "my_demux.my_demux.vc.myctree.supply.vdd" "my_demux.my_demux.vc.myctree.C2Els[0].vdd"
-= "my_demux.my_demux.vc.myctree.supply.vss" "my_demux.my_demux.vc.myctree.C2Els[0].vss"
-= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.C2Els[0].c1"
-= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.tmp[0]"
-= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.C2Els[0].c2"
-= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.tmp[1]"
-= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.C2Els[0].y"
-= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.tmp[2]"
-"my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
-~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
-"my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
-~("my_demux.my_demux.vc.OR2_tf[0]._y")->"my_demux.my_demux.vc.OR2_tf[0].y"+
-"my_demux.my_demux.vc.OR2_tf[1].a"|"my_demux.my_demux.vc.OR2_tf[1].b"->"my_demux.my_demux.vc.OR2_tf[1]._y"-
-~("my_demux.my_demux.vc.OR2_tf[1].a"|"my_demux.my_demux.vc.OR2_tf[1].b")->"my_demux.my_demux.vc.OR2_tf[1]._y"+
-"my_demux.my_demux.vc.OR2_tf[1]._y"->"my_demux.my_demux.vc.OR2_tf[1].y"-
-~("my_demux.my_demux.vc.OR2_tf[1]._y")->"my_demux.my_demux.vc.OR2_tf[1].y"+
-= "my_demux.my_demux.vc.OR2_tf[1].y" "my_demux.my_demux.vc.myctree.in[1]"
-= "my_demux.my_demux.vc.OR2_tf[0].y" "my_demux.my_demux.vc.myctree.in[0]"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.myctree.supply.vss"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.myctree.supply.vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
-= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
-= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
-= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.myctree.out"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.OR2_tf[1].b"
-= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.OR2_tf[1].a"
-= "my_demux.my_demux.vc.in.d[1].d[1]" "my_demux.my_demux.vc.in.d[1].t"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.OR2_tf[0].b"
-= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.OR2_tf[0].a"
-= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
-"my_demux.my_demux.out1_a_B_buf_t.buf1.a"->"my_demux.my_demux.out1_a_B_buf_t.buf1._y"-
-~("my_demux.my_demux.out1_a_B_buf_t.buf1.a")->"my_demux.my_demux.out1_a_B_buf_t.buf1._y"+
-"my_demux.my_demux.out1_a_B_buf_t.buf1._y"->"my_demux.my_demux.out1_a_B_buf_t.buf1.y"-
-~("my_demux.my_demux.out1_a_B_buf_t.buf1._y")->"my_demux.my_demux.out1_a_B_buf_t.buf1.y"+
-= "my_demux.my_demux.out1_a_B_buf_t.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.buf1.vdd"
-= "my_demux.my_demux.out1_a_B_buf_t.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.buf1.vss"
-= "my_demux.my_demux.out1_a_B_buf_t.out[0]" "my_demux.my_demux.out1_a_B_buf_t.out[1]"
-= "my_demux.my_demux.out1_a_B_buf_t.out[0]" "my_demux.my_demux.out1_a_B_buf_t.buf1.y"
-= "my_demux.my_demux.out1_a_B_buf_t.in" "my_demux.my_demux.out1_a_B_buf_t.buf1.a"
-~"my_demux.my_demux.en_ctl.p1"&~"my_demux.my_demux.en_ctl.c1"->"my_demux.my_demux.en_ctl.y"+
-"my_demux.my_demux.en_ctl.c1"->"my_demux.my_demux.en_ctl.y"-
-= "my_demux.my_demux._reset_BXt" "my_demux.my_demux.token_buf.sr_B"
-= "my_demux.my_demux._reset_BXt" "my_demux.my_demux.token_buf.pr_B"
-= "my_demux.my_demux._reset_BXt" "my_demux.my_demux.reset_buf_token.y"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_buf_d.in"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_f_c_t_or.b"
-= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.c_buf_tk.a"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.c_f_c_t_or.a"
-= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
-~"my_demux.my_demux.out1_f_buf_func[0].c1"&~"my_demux.my_demux.out1_f_buf_func[0].c2"|~"my_demux.my_demux.out1_f_buf_func[0].pr_B"->"my_demux.my_demux.out1_f_buf_func[0]._y"+
-"my_demux.my_demux.out1_f_buf_func[0].c1"&"my_demux.my_demux.out1_f_buf_func[0].c2"&"my_demux.my_demux.out1_f_buf_func[0].n1"&"my_demux.my_demux.out1_f_buf_func[0].n2"&"my_demux.my_demux.out1_f_buf_func[0].sr_B"->"my_demux.my_demux.out1_f_buf_func[0]._y"-
-"my_demux.my_demux.out1_f_buf_func[0]._y"->"my_demux.my_demux.out1_f_buf_func[0].y"-
-~("my_demux.my_demux.out1_f_buf_func[0]._y")->"my_demux.my_demux.out1_f_buf_func[0].y"+
-~"my_demux.my_demux.out1_f_buf_func[1].c1"&~"my_demux.my_demux.out1_f_buf_func[1].c2"|~"my_demux.my_demux.out1_f_buf_func[1].pr_B"->"my_demux.my_demux.out1_f_buf_func[1]._y"+
-"my_demux.my_demux.out1_f_buf_func[1].c1"&"my_demux.my_demux.out1_f_buf_func[1].c2"&"my_demux.my_demux.out1_f_buf_func[1].n1"&"my_demux.my_demux.out1_f_buf_func[1].n2"&"my_demux.my_demux.out1_f_buf_func[1].sr_B"->"my_demux.my_demux.out1_f_buf_func[1]._y"-
-"my_demux.my_demux.out1_f_buf_func[1]._y"->"my_demux.my_demux.out1_f_buf_func[1].y"-
-~("my_demux.my_demux.out1_f_buf_func[1]._y")->"my_demux.my_demux.out1_f_buf_func[1].y"+
-= "my_demux.my_demux._in_v" "my_demux.my_demux.token_buf.n2"
-= "my_demux.my_demux._in_v" "my_demux.my_demux.in_v_buf.a"
-= "my_demux.my_demux._in_v" "my_demux.my_demux.c_el.c2"
-= "my_demux.my_demux._in_v" "my_demux.my_demux.vc.out"
-~"my_demux.my_demux.out1_t_buf_func[0].c1"&~"my_demux.my_demux.out1_t_buf_func[0].c2"|~"my_demux.my_demux.out1_t_buf_func[0].pr_B"->"my_demux.my_demux.out1_t_buf_func[0]._y"+
-"my_demux.my_demux.out1_t_buf_func[0].c1"&"my_demux.my_demux.out1_t_buf_func[0].c2"&"my_demux.my_demux.out1_t_buf_func[0].n1"&"my_demux.my_demux.out1_t_buf_func[0].n2"&"my_demux.my_demux.out1_t_buf_func[0].sr_B"->"my_demux.my_demux.out1_t_buf_func[0]._y"-
-"my_demux.my_demux.out1_t_buf_func[0]._y"->"my_demux.my_demux.out1_t_buf_func[0].y"-
-~("my_demux.my_demux.out1_t_buf_func[0]._y")->"my_demux.my_demux.out1_t_buf_func[0].y"+
-~"my_demux.my_demux.out1_t_buf_func[1].c1"&~"my_demux.my_demux.out1_t_buf_func[1].c2"|~"my_demux.my_demux.out1_t_buf_func[1].pr_B"->"my_demux.my_demux.out1_t_buf_func[1]._y"+
-"my_demux.my_demux.out1_t_buf_func[1].c1"&"my_demux.my_demux.out1_t_buf_func[1].c2"&"my_demux.my_demux.out1_t_buf_func[1].n1"&"my_demux.my_demux.out1_t_buf_func[1].n2"&"my_demux.my_demux.out1_t_buf_func[1].sr_B"->"my_demux.my_demux.out1_t_buf_func[1]._y"-
-"my_demux.my_demux.out1_t_buf_func[1]._y"->"my_demux.my_demux.out1_t_buf_func[1].y"-
-~("my_demux.my_demux.out1_t_buf_func[1]._y")->"my_demux.my_demux.out1_t_buf_func[1].y"+
-"my_demux.my_demux.c_buf_d.buf1.a"->"my_demux.my_demux.c_buf_d.buf1._y"-
-~("my_demux.my_demux.c_buf_d.buf1.a")->"my_demux.my_demux.c_buf_d.buf1._y"+
-"my_demux.my_demux.c_buf_d.buf1._y"->"my_demux.my_demux.c_buf_d.buf1.y"-
-~("my_demux.my_demux.c_buf_d.buf1._y")->"my_demux.my_demux.c_buf_d.buf1.y"+
-= "my_demux.my_demux.c_buf_d.supply.vdd" "my_demux.my_demux.c_buf_d.buf1.vdd"
-= "my_demux.my_demux.c_buf_d.supply.vss" "my_demux.my_demux.c_buf_d.buf1.vss"
-= "my_demux.my_demux.c_buf_d.out[0]" "my_demux.my_demux.c_buf_d.out[1]"
-= "my_demux.my_demux.c_buf_d.out[0]" "my_demux.my_demux.c_buf_d.buf1.y"
-= "my_demux.my_demux.c_buf_d.in" "my_demux.my_demux.c_buf_d.buf1.a"
-"my_demux.my_demux.outt_a_inv.a"->"my_demux.my_demux.outt_a_inv.y"-
-~("my_demux.my_demux.outt_a_inv.a")->"my_demux.my_demux.outt_a_inv.y"+
-= "my_demux.my_demux._c_tk_buf" "my_demux.my_demux.token_buf.n1"
-= "my_demux.my_demux._c_tk_buf" "my_demux.my_demux.c_buf_tk.y"
-= "Vdd" "my_demux.my_demux.supply.vdd"
-= "GND" "my_demux.my_demux.supply.vss"
-= "my_demux.token.d.d[0]" "my_demux.token.r"
-= "my_demux.token.r" "my_demux.my_demux.token.r"
-= "my_demux.token.a" "my_demux.my_demux.token.a"
-= "my_demux.token.d.d[0]" "my_demux.my_demux.token.d.d[0]"
-= "my_demux.token.d.d[0]" "my_demux.token.r"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"
-= "my_demux.in.v" "my_demux.my_demux.in.v"
-= "my_demux.in.a" "my_demux.my_demux.in.a"
-= "my_demux.in.d.d[0].f" "my_demux.my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].t" "my_demux.my_demux.in.d.d[0].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.my_demux.in.d.d[0].d[0]"
-= "my_demux.in.d.d[0].d[1]" "my_demux.my_demux.in.d.d[0].d[1]"
-= "my_demux.in.d.d[1].f" "my_demux.my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].t" "my_demux.my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[1].d[0]" "my_demux.my_demux.in.d.d[1].d[0]"
-= "my_demux.in.d.d[1].d[1]" "my_demux.my_demux.in.d.d[1].d[1]"
-= "my_demux.in.d.d[1].d[0]" "my_demux.in.d.d[1].f"
-= "my_demux.in.d.d[1].d[1]" "my_demux.in.d.d[1].t"
-= "my_demux.in.d.d[0].d[0]" "my_demux.in.d.d[0].f"
-= "my_demux.in.d.d[0].d[1]" "my_demux.in.d.d[0].t"

test/unit_tests/demux_td_2_SIGN/test.act

@@ -32,9 +32,9 @@ import globals;
 open tmpl::dataflow_neuro;
 
 
-defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out1; a1of1 token; avMx1of2<1> cond){
+defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out; a1of1 token; avMx1of2<1> cond){
 
-    demux_td<2, true> my_demux(.in=in, .out1=out1,.token = token, .cond = cond);
+    demux_td<2, true> my_demux(.in=in, .out=out,.token = token, .cond = cond);
     //Low active Reset 
     bool _reset_B; 
     prs {

test/unit_tests/demux_td_2_SIGN/test.prsim

@@ -1,7 +1,7 @@
 watchall
 set-qdi-channel-neutral "my_demux.in" 2
-set my_demux.out1.a 0
-set my_demux.out1.v 0
+set my_demux.out.a 0
+set my_demux.out.v 0
 set my_demux.token.a 0
 set my_demux.token.r 0
 set my_demux.cond.d.d[0].t 0
@@ -15,7 +15,7 @@ system "echo 'System reset completed'"
 status X
 mode run
 
-assert-qdi-channel-neutral "my_demux.out1" 2
+assert-qdi-channel-neutral "my_demux.out" 2
 assert-qdi-channel-neutral "my_demux.in" 2
 cycle
 
@@ -28,21 +28,26 @@ cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 0
 
-assert-qdi-channel-valid "my_demux.out1" 2 3
+assert-qdi-channel-valid "my_demux.out" 2 3
 assert my_demux.token.a 0
-set my_demux.out1.v 1
+assert my_demux.token.r 0
+set my_demux.out.v 1
 cycle
 
 assert my_demux.in.a 1
 set-qdi-channel-neutral "my_demux.in" 2
 cycle
-set my_demux.out1.a 1
-
+set my_demux.out.a 1
+cycle
+assert-qdi-channel-neutral "my_demux.out" 2
+set my_demux.out.a 0
+set my_demux.out.v 0
+cycle
 
 system "echo 'First Cond Checked'"
 
-set my_demux.out1.a 0
-set my_demux.out1.v 0
+set my_demux.out.a 0
+set my_demux.out.v 0
 set my_demux.token.a 0
 set my_demux.token.r 0
 set my_demux.cond.d.d[0].t 0
@@ -58,9 +63,9 @@ cycle
 assert my_demux.in.v 1
 assert my_demux.in.a 1
 assert my_demux.token.r 1
+assert-qdi-channel-neutral "my_demux.out" 2
 
 set my_demux.token.a 1
-set my_demux.out1.a 1
 cycle
 
 assert my_demux.token.r 0
@@ -75,6 +80,7 @@ set my_demux.cond.d.d[0].t 0
 set my_demux.cond.d.d[0].f 0
 cycle
 
+assert my_demux.cond.v 0
 assert my_demux.in.a 0
 
 

test/unit_tests/dropper_static/test.act

@@ -0,0 +1,52 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc dropper_static_7 (avMx1of2<7> in; avMx1of2<7> out; bool? drop){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    dropper_static<7, true> b(.in = in, .out = out, .cond = drop, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+dropper_static_7 b;

test/unit_tests/dropper_static/test.prsim

@@ -0,0 +1,73 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 7
+set b.out.a 0
+set b.out.v 0
+set b.drop 0
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+status X
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 45
+cycle
+assert-qdi-channel-valid "b.out" 7 45
+assert b.in.v 1
+cycle
+set b.out.a 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+set b.out.a 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 37
+cycle
+assert-qdi-channel-valid "b.out" 7 37
+assert b.in.v 1
+cycle
+set b.out.a 1
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+set b.out.a 0
+cycle
+assert b.in.a 0
+
+system "echo '[] Enabling drop'"
+set b.drop 1
+cycle
+system "echo '[] Sending in valid data'"
+set-qdi-channel-valid "b.in" 7 45
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 1
+assert b.in.a 1
+
+system "echo '[] Removing data'"
+set-qdi-channel-neutral "b.in" 7
+cycle
+assert-qdi-channel-neutral "b.out" 7
+assert b.in.v 0
+assert b.in.a 0

test/unit_tests/encoder1d_7/test.act

@@ -0,0 +1,54 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc encoder1d_simple_test(a1of1 in[7]; avMx1of2<3> out){
+    power supply;
+    supply.vss = GND;
+    supply.vdd = Vdd; 
+
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    
+    encoder1d_simple<3,7> e(.in = in, .supply = supply, .reset_B = _reset_B);
+
+    fifo<3, 5> fifo_post(.in = e.out, .out = out, .supply = supply, .reset_B = _reset_B);
+
+
+}
+
+encoder1d_simple_test e;

test/unit_tests/encoder1d_7/test.prsim

@@ -0,0 +1,257 @@
+watchall
+
+system "echo '[] Set Reset 1'"
+
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 0
+set e.out.v 0
+set Reset 1
+
+cycle
+status X
+system "echo '[] Set Reset 0'"
+set Reset 0
+cycle
+status X
+
+
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 5 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 1
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 5
+assert e.in[5].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[5].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 6 spikes'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 1
+cycle
+assert-qdi-channel-valid "e.out" 3 6
+assert e.in[6].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.a 1
+set e.out.v 1
+cycle
+assert e.in[6].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+
+system "echo '[] Neuron 1 spikes'"
+set e.in[0].r 0
+set e.in[1].r 1
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+cycle
+assert-qdi-channel-valid "e.out" 3 1
+assert e.in[1].a 1
+
+system "echo '[] remove data and give ack'"
+set e.in[0].r 0
+set e.in[1].r 0
+set e.in[2].r 0
+set e.in[3].r 0
+set e.in[4].r 0
+set e.in[5].r 0
+set e.in[6].r 0
+
+set e.out.v 1
+set e.out.a 1
+cycle
+assert e.in[1].a 0
+assert-qdi-channel-neutral "e.out" 3
+set e.out.a 0
+set e.out.v 0
+

test/unit_tests/encoder1d_bd/test.act

@@ -0,0 +1,61 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+pint N = 7;
+pint Nc = std::ceil_log2(N);
+pint N_BUFFERS = 5;
+pint N_BD_DLY_CFG = 4;
+
+defproc _encoder1d_bd (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
+
+    bool _reset_B;
+    prs {
+       Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+    encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
+        .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+_encoder1d_bd c; 

test/unit_tests/encoder1d_bd/test.prsim

@@ -0,0 +1,82 @@
+watchall
+
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+set c.in[4].r 0
+set c.in[5].r 0
+set c.in[6].r 0
+
+set c.out.a 0
+
+set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set Reset 0
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 3
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+assert c.in[4].a 0
+assert c.in[5].a 0
+assert c.in[6].a 0
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 3 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 3
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 3 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 6
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+

test/unit_tests/encoder2D_8x8/test.act

@@ -0,0 +1,54 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc encoder2d_2x2 (a1of1 x[8]; a1of1 y[8]; avMx1of2<6> out){
+    encoder2d_simple<3, 3, 8, 8, 0> e(.inx=x, .iny=y, .out=out);
+
+    e.to_pd_x = e.inx;
+    e.to_pd_y = e.iny;
+
+
+
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    e.supply.vss = GND;
+    e.supply.vdd = Vdd;
+    e.reset_B = _reset_B;
+}
+
+encoder2d_2x2 e;

test/unit_tests/encoder2D_8x8/test.prsim

@@ -0,0 +1,238 @@
+watchall
+# mode run
+
+system "echo '[] Set Out Ack/Valid Low'"
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Setting Neuron Req Low'"
+
+set e.y[0].r 0
+set e.y[1].r 0
+set e.y[2].r 0
+set e.y[3].r 0
+set e.y[4].r 0
+set e.y[5].r 0
+set e.y[6].r 0
+set e.y[7].r 0
+
+set e.x[0].r 0
+set e.x[1].r 0
+set e.x[2].r 0
+set e.x[3].r 0
+set e.x[4].r 0
+set e.x[5].r 0
+set e.x[6].r 0
+set e.x[7].r 0
+set Reset 1
+
+
+cycle 
+mode run
+status X
+status 0
+set Reset 0
+cycle
+
+
+
+system "echo '[] Single Neuron Spikes (2,5), raise y[5].r'"
+
+set e.y[5].r 1
+# set e.x[2].r 1
+cycle
+
+assert e.y[5].a 1
+system "echo '[] Asserted y[5].a 1'"
+
+# assert e.e.Yarb.out.r 1
+# assert e.e.Xarb.out.r 0
+
+# assert e.e._x_v 0
+
+
+
+system "echo '[] Raise x[2].r'"
+# set e.y[5].r 1
+set e.x[2].r 1
+cycle
+assert e.x[2].a 1
+system "echo '[] Asserted x[2].a 1'"
+
+# assert e.e.Yarb.out.r 1
+# assert e.e.Xarb.out.r 1
+# assert e.e._x_v 1
+
+
+system "echo '[] Check Arbiter Acks'"
+
+# assert e.e._x_a_B 1
+
+assert e.y[0].a 0
+assert e.y[1].a 0
+assert e.y[2].a 0
+assert e.y[3].a 0
+assert e.y[4].a 0
+assert e.y[5].a 1
+assert e.y[6].a 0
+assert e.y[7].a 0
+# assert e.e.Yarb.out.a 1
+
+
+assert e.x[0].a 0
+assert e.x[1].a 0
+assert e.x[2].a 1
+assert e.x[3].a 0
+assert e.x[4].a 0
+assert e.x[5].a 0
+assert e.x[6].a 0
+assert e.x[7].a 0
+# assert e.e.Xarb.out.a 1
+
+assert-qdi-channel-valid "e.out" 6 42
+system "echo '[] Asserted output encoding valid 42'"
+set e.out.v 1
+
+system "echo '[] Finish Neuron Handshake'"
+
+set e.y[5].r 0
+set e.x[2].r 0
+cycle
+
+assert e.y[0].a 0
+assert e.y[1].a 0
+assert e.y[2].a 0
+assert e.y[3].a 0
+assert e.y[4].a 0
+assert e.y[5].a 0
+assert e.y[6].a 0
+assert e.y[7].a 0
+
+
+assert e.x[0].a 0
+assert e.x[1].a 0
+assert e.x[2].a 0
+assert e.x[3].a 0
+assert e.x[4].a 0
+assert e.x[5].a 0
+assert e.x[6].a 0
+assert e.x[7].a 0
+
+
+system "echo '[] Asserted all in acks 0'"
+
+set e.out.a 1
+cycle
+
+assert-qdi-channel-neutral "e.out" 6
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (2,5) Encoded'"
+
+
+
+
+
+
+
+
+system "echo '[] Single Neuron Spikes (5,2), raise y[2].r'"
+
+set e.y[2].r 1
+# set e.x[2].r 1
+cycle
+
+assert e.y[2].a 1
+system "echo '[] Asserted y[2].a 1'"
+
+# assert e.e.Yarb.out.r 1
+# assert e.e.Xarb.out.r 0
+
+# assert e.e._x_v 0
+
+
+
+system "echo '[] Raise x[5].r'"
+# set e.y[5].r 1
+set e.x[5].r 1
+cycle
+assert e.x[5].a 1
+system "echo '[] Asserted x[5].a 1'"
+
+# assert e.e.Yarb.out.r 1
+# assert e.e.Xarb.out.r 1
+# assert e.e._x_v 1
+
+
+system "echo '[] Check Arbiter Acks'"
+
+# assert e.e._x_a_B 1
+
+assert e.y[0].a 0
+assert e.y[1].a 0
+assert e.y[2].a 1
+assert e.y[3].a 0
+assert e.y[4].a 0
+assert e.y[5].a 0
+assert e.y[6].a 0
+assert e.y[7].a 0
+# assert e.e.Yarb.out.a 1
+
+
+assert e.x[0].a 0
+assert e.x[1].a 0
+assert e.x[2].a 0
+assert e.x[3].a 0
+assert e.x[4].a 0
+assert e.x[5].a 1
+assert e.x[6].a 0
+assert e.x[7].a 0
+# assert e.e.Xarb.out.a 1
+
+assert-qdi-channel-valid "e.out" 6 21
+system "echo '[] Asserted output encoding valid 21'"
+set e.out.v 1
+
+system "echo '[] Finish Neuron Handshake'"
+
+set e.y[2].r 0
+set e.x[5].r 0
+cycle
+
+assert e.y[0].a 0
+assert e.y[1].a 0
+assert e.y[2].a 0
+assert e.y[3].a 0
+assert e.y[4].a 0
+assert e.y[5].a 0
+assert e.y[6].a 0
+assert e.y[7].a 0
+
+
+assert e.x[0].a 0
+assert e.x[1].a 0
+assert e.x[2].a 0
+assert e.x[3].a 0
+assert e.x[4].a 0
+assert e.x[5].a 0
+assert e.x[6].a 0
+assert e.x[7].a 0
+
+
+system "echo '[] Asserted all in acks 0'"
+
+set e.out.a 1
+cycle
+
+assert-qdi-channel-neutral "e.out" 6
+
+set e.out.a 0
+set e.out.v 0
+cycle
+
+system "echo '[] Neuron (5,2) Encoded'"

test/unit_tests/encoder_7/test.act

@@ -0,0 +1,44 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc encoder_7 (bool? in[7]; Mx1of2<3> out){
+    dualrail_encoder<3,7> e(.in=in, .out=out);
+    e.supply.vss = GND;
+    e.supply.vdd = Vdd;
+
+}
+
+encoder_7 e;

test/unit_tests/encoder_7/test.prsim

@@ -0,0 +1,78 @@
+watchall
+
+system "echo '0'"
+
+set e.in[0] 0
+set e.in[1] 0
+set e.in[2] 0
+set e.in[3] 0
+set e.in[4] 0
+set e.in[5] 0
+set e.in[6] 0
+
+# set-bool-array "e.in" 7 0
+
+cycle
+mode run
+
+# assert t.out 0
+
+system "echo '[] setting input 0 high'"
+set Reset 0
+set e.in[0] 1
+cycle
+
+system "echo '[] removing inputs'"
+set e.in[0] 0
+cycle
+
+system "echo '[] setting input 4 high'"
+set e.in[4] 1
+cycle
+
+system "echo '[] removing inputs'"
+set e.in[4] 0
+cycle
+
+system "echo '[] setting input 6 high'"
+set e.in[6] 1
+cycle
+
+system "echo '[] removing inputs'"
+set e.in[6] 0
+cycle
+
+
+
+# system "echo '[] setting input 6 high'"
+# set e.in[4] 0
+# set e.in[6] 1
+# cycle
+
+
+# assert t.out 0
+
+# system "echo '[] setting all bits high'"
+# set t.in[3] 1
+# set t.in[4] 1
+
+# cycle
+# assert t.out 1
+
+
+# system "echo '[] setting some low'"
+# set t.in[0] 0
+# set t.in[1] 0
+
+# cycle 
+# assert t.out 0
+
+
+# system "echo '[] setting all low'"
+# set t.in[2] 0
+# set t.in[3] 0
+# set t.in[4] 0
+
+# cycle 
+# assert t.out 0
+

test/unit_tests/fifo-decoder_dly-neurons-encoder-fifo/test.act

@@ -0,0 +1,77 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[6]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    pint NxC,NyC,Nx,Ny;
+    NxC = 4;
+    NyC = 3;
+    Nx = 1<<NxC;
+    Ny = 1<<NyC;
+
+    fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+    decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg, 
+        .reset_B = _reset_B, .supply = supply);
+    and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .supply = supply);
+    // Pretend that each "synapse" immediately makes its one neuron "spike".
+    // that is, connect the output of each encoder target to the decoder input.
+    nrn_hs_2d_array<Nx,Ny> neuron_grid(.reset_B = _reset_B, .supply = supply);
+    (i:Nx*Ny:
+        // Connect the output bool to the input req of each neuron handshaker
+        // Leave ack dangling.
+        neuron_grid.in[i].r = _and_grid.out[i];
+    )
+
+    encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
+        .to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
+        .reset_B = _reset_B, .supply = supply);
+
+    fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_decoder_neurons_encoder_fifo e; 

test/unit_tests/fifo-decoder_dly-neurons-encoder-fifo/test.prsim

@@ -0,0 +1,101 @@
+watchall
+
+set e.out.a 0
+set e.out.v 0
+set-qdi-channel-neutral "e.in" 7
+set Reset 1
+
+set e.dly_cfg[0] 1
+set e.dly_cfg[1] 1
+set e.dly_cfg[2] 1
+set e.dly_cfg[3] 1
+set e.dly_cfg[4] 1
+set e.dly_cfg[5] 1
+
+cycle
+
+# assert e.decoder.outx[0] 0
+# assert e.neuron_grid.outx[0].r 0
+
+
+# assert e.encoder.pd_x[0].inv.y 1
+
+# assert e.encoder.pd_x[0].pull_downR.n1 1
+# assert e.encoder.pd_x[0].pull_downR.n2 1
+# assert e.encoder.pd_x[0].pull_downR.y 0
+
+# assert e.neuron_grid.neurons[0].pu_x.p1 1
+# assert e.neuron_grid.neurons[0].pu_x.p2 1
+# assert e.neuron_grid.neurons[0].pu_x.p3 1
+
+# assert e.encoder.Xarb.in[0].a 0
+
+
+
+mode run
+system "echo '[] Set reset 0'"
+system "echo '[] Asserting decoder req 0 0'"
+
+
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+
+
+
+
+

test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.act

@@ -0,0 +1,73 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    pint NxC,NyC,Nx,Ny;
+    NxC = 4;
+    NyC = 3;
+    Nx = 1<<NxC;
+    Ny = 1<<NyC;
+
+    fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+    decoder_2d_hs<NxC,NyC,Nx,Ny> decoder(.in = fifo_pre.out, .reset_B = _reset_B, .supply = supply);
+    // Pretend that each "synapse" immediately makes its one neuron "spike".
+    // that is, connect the output of each encoder target to the decoder input.
+    nrn_hs_2d_array<Nx,Ny> neuron_grid(.reset_B = _reset_B, .supply = supply);
+    (i:Nx*Ny:
+        neuron_grid.in[i].r = decoder.out[i].r;
+        neuron_grid.in[i].a = decoder.out[i].a;
+    )
+
+    encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
+        .to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
+        .reset_B = _reset_B, .supply = supply);
+    fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_decoder_neurons_encoder_fifo e; 

test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.prsim

@@ -0,0 +1,74 @@
+watchall
+
+set e.out.a 0
+set e.out.v 0
+set-qdi-channel-neutral "e.in" 7
+set Reset 1
+
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+
+
+
+
+

test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.act

@@ -0,0 +1,90 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[4], hs_en, ack_disable){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    pint NxC,NyC,Nx,Ny;
+    NxC = 4;
+    NyC = 3;
+    Nx = 1<<NxC;
+    Ny = 1<<NyC;
+
+    fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+    
+
+    decoder_2d_hybrid<NxC,NyC,Nx,Ny,4> decoder(.in = fifo_pre.out, .dly_cfg =dly_cfg,
+        .hs_en = hs_en, .ack_disable = ack_disable,
+        .reset_B = _reset_B, .supply = supply);
+    
+    // // Pretend that each "synapse" immediately makes its one neuron "spike".
+    // // that is, connect the output of each encoder target to the decoder input.
+    // and_grid<Nx, Ny> _and_grid(.inx = decoder.out_req_x, .iny = decoder.out_req_y, .supply = supply);
+
+    // // Attach line end pull ups of decoder
+    // decoder.to_pu = decoder.
+
+    // Dummy synapse handshake circuits, to be removed for innovus
+    decoder_2d_synapse_hs<Nx, Ny> _synapses(
+        .in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
+        .to_pu = decoder.to_pu,
+        .out_ackB_decoder = decoder.in_ackB_decoder,
+        .supply = supply);
+
+
+    nrn_hs_2d_array<Nx,Ny> neuron_grid(.in =_synapses.synapses,
+        .reset_B = _reset_B, .supply = supply);
+
+
+    encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
+        .to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
+        .reset_B = _reset_B, .supply = supply);
+    
+    fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_decoder_neurons_encoder_fifo e; 

test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.prsim

@@ -0,0 +1,149 @@
+watchall
+
+
+# Use handshaking at first
+set e.dly_cfg[0] 0
+set e.dly_cfg[1] 0
+set e.dly_cfg[2] 0
+set e.dly_cfg[3] 0
+set e.hs_en 1
+set e.ack_disable 0
+
+
+set e.out.a 0
+set e.out.v 0
+set-qdi-channel-neutral "e.in" 7
+set Reset 1
+
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+
+# Enable delays
+set e.dly_cfg[0] 1
+set e.dly_cfg[1] 1
+set e.dly_cfg[2] 1
+set e.dly_cfg[3] 1
+set e.hs_en 0
+cycle
+
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet WITH DELAYS'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+

test/unit_tests/fifo-register-fifo/test.act

@@ -0,0 +1,59 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_reg_fifo_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of2<8> out){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    fifo<9,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+
+    // Make a register array with 3 bit address (-> 8 registers), 
+    // each register holding 5 bits.
+    register_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
+        .reset_B = _reset_B, .supply = supply);
+
+    fifo<8,5> fifo_post(.in = reg.out, .out = out, .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_reg_fifo_3x5x8 b;

test/unit_tests/fifo-register-fifo/test.prsim

@@ -0,0 +1,199 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 9
+set b.out.a 0
+set b.out.v 0
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-qdi-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-qdi-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 01100=12 to reg0'"
+set-qdi-channel-valid "b.in" 9 352
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 12
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 12
+
+
+system "echo '[] Sending packet write 0s to reg1'"
+set-qdi-channel-valid "b.in" 9 257
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[1]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg2'"
+set-qdi-channel-valid "b.in" 9 258
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[2]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[2]" 5 0
+
+system "echo '[] Sending packet write 0s to reg3'"
+set-qdi-channel-valid "b.in" 9 259
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg4'"
+set-qdi-channel-valid "b.in" 9 260
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg5'"
+set-qdi-channel-valid "b.in" 9 261
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg6'"
+set-qdi-channel-valid "b.in" 9 262
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg7'"
+set-qdi-channel-valid "b.in" 9 263
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+assert-var-int "b.data[2]" 5 0
+assert-var-int "b.data[3]" 5 0
+assert-var-int "b.data[4]" 5 0
+assert-var-int "b.data[5]" 5 0
+assert-var-int "b.data[6]" 5 0
+assert-var-int "b.data[7]" 5 0
+
+
+system "echo '[] Reading register 0'"
+set-qdi-channel-valid "b.in" 9 0
+cycle
+assert-qdi-channel-valid "b.out" 8 96
+assert b.in.v 1
+assert b.in.a 1
+
+set b.out.a 1
+set b.out.v 1
+cycle
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert-qdi-channel-neutral "b.out" 8
+set b.out.a 0
+set b.out.v 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+
+
+system "echo '[] Reading register 1'"
+set-qdi-channel-valid "b.in" 9 1
+cycle
+assert-qdi-channel-valid "b.out" 8 1
+assert b.in.v 1
+assert b.in.a 1
+
+set b.out.a 1
+set b.out.v 1
+cycle
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert-qdi-channel-neutral "b.out" 8
+set b.out.a 0
+set b.out.v 0
+cycle
+assert b.in.a 0
+assert b.in.v 0